XBOX360 FAT Jasper FabB Retail RevA

March 21, 2023 | Author: Anonymous | Category: N/A

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Download XBOX360 FAT Jasper FabB Retail RevA...

Description

CR-1

:

@JASPER_LIB.JASPER(SCH_1):PAGE1

SCHEMATIC

R EV EV

PCBA NUMBER X8XXXXX-001

A

PAGE

PAGE

CONTENTS COVER PAGE CLOCK DIAGRAM RESET/ENABLE DIAGRAM CPU, CLOCKS + EEPROM + STRAPPING CPU, FS FSB CPU, FSB POWER + PLL POWER CPU, CORE POWER CPU, POWER CPU, DECOUPLING CPU, DE DEC COUPLING CPU, DE DEC COUPLING GPU, FS FSB GPU, VIDEO + PC PCIEX + E EE EPROM GPU, MEMORY CONTROLLER A + B GPU, MEMORY CONTROLLER C + D GPU, PLL POWER + F S SB B POWER GPU, CORE P PO OWER + MEM POWER GPU, DE DECOUPLING MEMORY, A (TOP) MEMORY, A MI MIRRORED (BOTTOM) MEMORY, B (TOP)

[35] [36] [37] [38] [39] [40] [41] [42] [43] [44] [45] [46] [47] [48] [49] [50] [51] [52] [53] [54] [55]

SB, FLASH + U US SB + S SP PI SB, ETHERNET + AU AUDIO + S SA ATA SB, STANDBY POWER + DEC DECOUPLE SB, MAIN POWER + D EC ECOUPLE SB OUT, ETHERNET (ICS PHY) SB O OU UT, ETHERNET (BCM PHY) SB OUT, AUDIO SB OUT, FLASH SB OU OUT, FAN + IR + B BU UTTON + TILT CONN, A AV VIP CONN, RJ45 + US USB COMBO CONN, GAME PORTS + MEMORY PORTS MISC, V_5P0 DUAL, DEBUG MAPPING CONN, ODD AND HDD CONN, ARGON + P PO OWER VREGS, INPUT + OU OUTPUT FI FILTERS VREGS, CPU CONTROLLER VREGS, GPU OUTPUT PH PHASE 1, 1,2 2,3 VREGS, GPU CONTROLLER VREGS, GPU OUTPUT PH PHASE 1, 1,2 2 VREGS, SWITCHED 1 1..8, 5.0V

23 2]] [[2 [24] [25] [26] [27] [28] [29] [30] [31] [32]

ME EM MO OR RY Y,, C B (MI M RP R)ORED (BOTTOM) M TIO MEMORY, C MIRRORED (BOTTOM) MEMORY, D (TOP) MEMORY, D MIRRORED (BOTTOM) HANA, CLOCKS + S ST TRAPPING HANA, VIDEO + F FA AN + J JT TAG CONN, H HD DMI HANA NA,, POWER + DE DEC COUPLING HANA NA,, POWER + DE DEC COUPLING POWER TRACE E EM MI CAPS

[[5 56 7]] [58] [59] [60] [61] [62] [63] [64] [65] [66]

V NS EAR REGR GT UO LR AT VR RE EG GS S,, L VIC UE LA SORS XDK, DEBUG CONN DEBUG B BO OARD, CPU + GPU B BR REAKOUT DEBUG BOARD, CPU CONN DEBUG BOARD, CPU C CO ONN + TERM DEBUG BOARD, CPU TERM DEBUG BOARD, SMP CONNECTORS DEBUG B BO OARD, GPU C CO ONN + TERM XDK, LEDS, DEBUG TITAN LABELS AND MOUNTING

3] [34

SB,

7] [68

G PN UAD VA ID BA BC OK AU RP D + IMPEDANCE PA

RU RULE LES: S: 1. 1.)) 2.) 2.) 3. 3.)) 4.) 4.) 5.) 5.) 6.) 6.) 7.) 7.) 8.) 8.) 9.) 9.) 10.) 10.) 12.) 12.) 13.) 13.) 14 14.) .) 15.) 15.)

(AP (APPL PLIED IED

+ S SM MM GPIO

+ J JT TAG

RETAIL REV A FAB B

CUPONS

JASPER PL PLEA EASE SE

BOM RELEASE

DATE

SIGNATURE

JASPER_FAB_B W ed ed J u ull

30 1 3 3:: 1 17 7: 0 05 5

2008

REFE REFER R TO THE XE XENO NON N DESI DESIGN GN

PB NUMBER NUM BER

XX/XX/06

DATE

SP SPEC EC

X80XXXX-00X

DR DRN N BY

MICRO MIC ROSO SOFT FT XBOX XBOX

CH CHK K BY

TITLE

ENGR APVD

DRAWING

PAGE PAGE]]

DA DATE

JASPER

WH WHEN EN PO POSS SSIB IBLE LE))

MSB TO TO LS LSB B IS T O OP P TO BOT BOTTOM WHEN WHEN POSS POSSIB IBLE LE:: INPU INPUTS TS ON LEFT LEFT,, OUTPU UTPUTS TS ON RIG RIGHT HT ORDE ORDER R OF PAGE PAGES= S=CH CHIP IP IN INTE TERF RFAC ACES ES,, TERM TERMINA INATI TION ON,, PO POWE WER, R, DEC DECOU OUPL PLIN ING G AVOI AVOID D US USIN ING G OFF OFF PA PAGE GE CONN CONNEC ECTO TORS RS FO FOR R ON PAGE PAGE CON CONNE NECT CTIO IONS NS LANE LANED D SI SIGN GNAL ALS S AR ARE E GROU GROUPED PED ON SY SYMB MBOL OLS S TRAN TRANSI SIMI MITT TTER ER NA NAME ME USED USED AS PR PREF EFIX IX WI WITH TH RX AND AND TX TX CONN CONNEC ECTI TION ONS S SUFF SUFFIX IX V_ IS USED USED FO FOR R V VOL OLTA TAGE GE RAIL RAIL SIG SIGNAL NAL NAME NAMES S SUFF SUFFIX IX _DP _DP AND AND _D _DN N ARE US USED ED F FO OR DI DIFF FFER ERIE IENT NTAL AL PAIR PAIRS S UN UNNA NAME MED D NET NETS S ARE ARE NAM NAMED ED WIT WITH H /2 TE TEXT XT SIZE SIZE SUFF SUFFIX IX _N FOR FOR ACTI ACTIVE VE LOW LOW O OR R N JUN JUNCT CTIO ION N SUFF SUFFIX IX _P FOR FOR P JUN JUNCT CTIO ION N SUFF SUFFIX IX _EN _EN FOR FOR E ENA NABL BLE E 'C 'CLK LK'' F OR OR CLO LOC CKS KS,, 'R 'RST ST'' FO OR R RES ESET ETS S PWRGD PWRGD FO FOR R PO POWER WER GO GOOD OD

[P [PAG AGE_ E_TI TIT TLE=C LE=COV OVER ER

BOM RELEASE XX/XX/06

CONTENTS

[1] [2] [3 [3]] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21]

P EX SM SC MIC

REV B

APVD APVD

SC SCH, H,

MICROSOFT

CONFIDENTIAL

PBA, PBA, PRO PROJEC JECT T H08580

JASP JASPER ER NAME NAM E

PAGE 1/83

REV A

CR-2

:

@JASPER_LIB.JASPER(SCH_1):PAGE2

RJ45/USB CONN

ENET PHY

AVIP CONN

*

FAN CONN

THIS

IS

OUT OF OF DA DATE *

POWER CONN

CLOCK CLO CK DIAGR DIAGRAM AM

ENET_CLK(25MHZ)

I2S_MCLK(12.288MHZ) I2S_BCLK(3.072MHZ)

AUDIO DAC

ANA_XTAL_IN(27MHZ)

GP GPU U VR

DEBUG CONN

ANA ANA BCKUP

SB DVD SATA CONN

GP GPU U VR CNTL

STBY_CLK(48MHZ) SATA_CLK_REF(25MHZ) SATA_CLK_DP/DN(100MHZ) PCIEX_CLK_DP/DN(100MHZ) AUD_CLK(24.576MHZ)

CPU_CLK_DP/DN(100MHZ) GPU_CLK_D GPU_ CLK_DP/DN P/DN

DVD PWR CONN

MC_CLK1_DP/DN(800MHZ) MC_CLK0_DP/DN(800MHZ)

ANA BCKUP

1P8

MEM CL CLAM AM C+D C+D

MD_CLK1_DP/DN(800MHZ) MD_CLK0_DP/DN(800MHZ)

GPU

CPU

CPU VR

     )      )      )      )      Z     Z     Z     Z      H     H     H     H      M     M     M     M      0     0     0     0      0     0     0     0      8      (      8      (      8      (      8      (      N     N     N     N      D      /      D      /      D      /      D      /      P     P     P     P      D     D     D     D _ _ _ _      1     0     1     0      K     K     K     K      L     L     L     L      C     C     C     C _ _ _ _

VR FLSH

HDD CONN

3P3

RISCWATCH CONN

PIX_CLK_OUT_DP/DN(100MHZ) (100MHZ) (100MHZ)

TI TITA TAN N CONN

     M      A     M      A     M      B     M      B

VR

MEM CLAM CLAM A+B

VMEM VMEM VR 5P0 5P0

MPORT MPORT VR

EFUS EFUSE E

JTAG JTAG

VR

CPU CPU VR CNTL

VR

GAME CONN IR

MEM CONN

EJECT SW

MEM CONN

BIND SW

ARGON CONN

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 0 05 5

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 2/83

REV A

CR-3

:

@JASPER_LIB.JASPER(SCH_1):PAGE3

AVIP CONN

RJ45/USB CONN

ENET PHY

ENET_RST_N

     N _      N      O _      R      W      P _      T      X      E

POWER CONN

FAN CONN

RESE RE SET/ T/EN ENAB ABLE LE AUD_CLAMP AUD_RST_N

AUDIO DAC

PSU_V12P0_EN

GP GPU U VR

HANA_CLK_OE HANA_RST_N

DVD SATA CONN

DIA DIAGRAM GRAM

HANA

VREG_GPU_EN_N

SMC_RST_N

     N _      T      S      R _      B      S

SB

VREG_GPU_PWRGD EXT_PWR_ON_N CPU_CHECKSTOP_N CPU_RST_N CPU_PWRGD GPU_RST_N

DVD PWR CONN

RISCWATCH CONN

GPU_RST_DONE

     N      E _

     D

     B      G      D      N _      E _      C      3      M     P      S      3 _      G      E      R      V

     R      G      W      P _      U      P      C _      G      E      R      V

HDD CONN

GP GPU U VR CNTL

MEM CL CLAM AM C+ C+D D

MEM_RST MEM_SCAN_EN MEM_SCAN_TOP_EN MEM_SCAN_BOT_EN

GPU

CPU

     N     N      E      N     E _ _      E     P _      T      N     O     O      B      T     A     T _ _      S     C     N      N      R     S _ _     A     A      C      M     M     C      S      S      E      E _ _      M     M     M     M      E     E      M     M

3P3 VR

DEBUG CONN

CPU VR

VREG_1P8_EN_N VREG_5P0_EN_N

CPU_PWRGD TI TITA TAN N CONN

MEM CLAM CLAM A+B VMEM VMEM VR 5P 5P0 0

EFUS EFUSE E

JTAG JTAG

VR

CPU CPU VR CNTL

VR

VREG_EFUSE_EN VREG_CPU_EN GAME CONN IR

EJECT SW

[P [PAG AGE_ E_TI TITL TLE= E=RE RESE SET/ T/EN ENAB ABLE LE

MEM CONN

MEM CONN

DI DIAG AGRA RAM] M]

BIND SW

ARGON CONN

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 0 05 5

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 3/83

REV A

CR-6

:

@JASPER_LIB.JASPER(SCH_1):PAGE6

CPU CPU,

FSB POWER + PLL

POWER

V_1P8

V_CPUPLL

V_GPUCORE U7D1

FB7R1

1

C7R1

1

2

1K

FB 603

0.2A 0.7DCR

1

2

1

C7R7

.1UF 10%

2 6.3V X5R

ST7R1 2

1

.1UF 10% 6.3V X5R 402

1

2

C7R116

.1UF 10% 6.3V X5R 402

FB6D1

1

2

C6D1

0

1

2

FB 603

.1UF 10% 6.3V X5R 402

402

1

1

CPU_VDDE

5% CH

C6D4 2.2UF 10%

V_CPU_CORE_HF_VDDA_PLL V_CPU_CORE_HF_GNDA_PLL

ST6D1 2

V_CPU_CORE_IF_VDDA_PLL V_CPU_CORE_IF_GNDA_PLL V_CPU_FSB_HF_VDDA_PLL V_CPU_FSB_HF_GNDA_PLL

FB6R1

2

VDD_IO VDDE VDDE_SEC

AG17 AF17

CORE_HF_VDDA_PLL CORE_HF_GNDA_PLL

AH17 AH16

CORE_IF_VDDA_PLL CORE_IF_GNDA_PLL

AD20 AE20

FSB_HF_VDDA_PLL FSB_HF_GNDA_PLL

AD18 AE18

FSB_IF_VDDA_PLL FSB_IF_GNDA_PLL

AH11 AG11

VDDA_RNG GNDA_RNG

603

SHORT

C6R2

AH4 A7 B7

2 6.3V X5R 1

1

VDD_FSB0 VDD_FSB1 VDD_FSB2 VDD_FSB3 VDD_FSB4 VDD_FSB5 VDD_FSB6 VDD_FSB7 VDD_FSB8

.1UF 10%

402

R7T2

V_CPU_FSB_IF_VDDA_PLL

1

2

1K

FB 603

0.2A 0.7DCR

V_CPU_FSB_IF_GNDA_PLL V_CPU_VDDA_RNG

1

.1UF 10% 6.3V X5R 402

2 ST6R1 2

1

V_CPU_GNDA_RNG

C6R4

IC

10

LOKI

6.3V 2 X5R

2

1K

4 of of

C7R114

V_EFUSE

SHORT

0.2A 0.7DCR

1

2.2UF 10% 6.3V X5R 603

2

402

C7R115

2.2UF 10% 6.3V X5R 603

VDD_FSB9 VDD_FSB10 VDD_FSB11 VDD_FSB12 VDD_FSB13 VDD_FSB14 VDD_FSB15 VDD_FSB16 VDD_FSB17 VDD_FSB18 VDD_FSB19 VDD_FSB20 VDD_FSB21 VDD_FSB22 VDD_FSB23 VDD_FSB24 VDD_FSB25 VDD_FSB26 VDD_FSB27 VDD_FSB28 VDD_FSB29 VDD_FSB30 VDD_FSB31 VDD_FSB32 VDD_FSB33 VDD_FSB34

AA25 AB24 AC25 AD24 AE25 AF24 AG25 AH24 B11 B15 B19 B23 B27 C24 D8 D12 D16 D20 D25 E24 F25 G24 H25 J24 K25 L24 M25 N24 P25 R24 T24 U25 V24 W25 Y24

SHORT

FB6R2

1

2

C6R3

1

2

1K

FB 603

0.2A 0.7DCR

1

.1UF 10% 6.3V X5R 402

2 ST6R2 2

1

C6R5 2.2UF 10% 6.3V X5R 603

X806937-001

SHORT

FB7D1

1

1K

C7D1

0.2A 0.7DCR

1UF 10% 16V EMPTY 603

2

FB 603

1

2 1

ST7D1 2

C7D2 2.2UF 10% 6.3V X5R 603

SHORT

[PA [PAGE_TIT _TITLE LE= =CPU CPU,

FSB POWER + PLL PLL

POWER] ER]

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 0 09 9

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 6/83

REV A

CR-7

:

@JASPER_LIB.JASPER(SCH_1):PAGE7

CP CPU, U, V_CPUCORE

V_CPUCORE

IC

U7D1 5 o off

V_CPUCORE

U7D1

10

CORE CORE POW POWER ER

6 o off

LOKI

10

V_CPUCORE

IC

V_CPUCORE

AA2 AA4 AA6 AA8 AA10 AA12 AA14 AA16 AA18 AA20 AA22 AB1 AB3 AB5 AB7 AB9 AB11 AB13 AB15 AB17 AB19 AB21 AB23 AC2 AC4 AC6 AC8 AC10 AC12 AC14 AC16 AC18 AC20 AC22 AD1

VDD0 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11

VDD48 VDD49 VDD50 VDD51 VDD52 VDD53 VDD54 VDD55 VDD56 VDD57 VDD58 VDD59

VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24 VDD25 VDD26 VDD27 VDD28 VDD29 VDD30 VDD31 VDD32 VDD33 VDD34

VDD60 VDD61 VDD62 VDD63 VDD64 VDD65 VDD66 VDD67 VDD68 VDD69 VDD70 VDD71 VDD72 VDD73 VDD74 VDD75 VDD76 VDD77 VDD78 VDD79 VDD80 VDD81 VDD82

AD3 AD5 AD7 AD9 AD11 AD13 AD15 AD17 AD19 AD21 AD23 AE1 AE4

VDD35 VDD36 VDD37 VDD38 VDD39 VDD40 VDD41 VDD42 VDD43 VDD44 VDD45 VDD46 VDD47

VDD83 VDD84 VDD85 VDD86 VDD87 VDD88 VDD89 VDD90 VDD91 VDD92 VDD93 VDD94 VDD95

AE6 AE8 AE10 AE12 AF4 AF7 AF10 AF13 AG3 AG6 AG9 AG12 G2 G4 G6 G8 G10 G12 G14 G16 G18 G20 G22 H1 H3 H5 H7 H9

H11 H13 H15 H17 H19 H21 H23 J2 J4 J6 J8 J10 J12 J14 J16 J18 J20 J22 K1 K3

K5 K7 K9

K11 K13 K15 K17 K19 K21 K23 L2 L4 L6 L8

L10 L12 L14 L16 L18 L20 L22 M1

M3 M5 M7

M9 M11 M13 M15 M17 M19 M21 M23 N2 N4 N6 N8 N10 N12 N14 N16 N18 N20 N22 P1

P3 P5

7 of of

10

LOKI

VDD96 VDD97 VDD98 VDD99 VDD100 VDD101 VDD102 VDD103 VDD104 VDD105 VDD106 VDD107

VDD143 VDD144 VDD145 VDD146 VDD147 VDD148 VDD149 VDD150 VDD151 VDD152 VDD153 VDD154

VDD108 VDD109 VDD110 VDD111 VDD112 VDD113 VDD114 VDD115 VDD116 VDD117 VDD118 VDD119 VDD120 VDD121 VDD122 VDD123 VDD124 VDD125 VDD126 VDD127 VDD128 VDD129 VDD130

VDD155 VDD156 VDD157 VDD158 VDD159 VDD160 VDD161 VDD162 VDD163 VDD164 VDD165 VDD166 VDD167 VDD168 VDD169 VDD170 VDD171 VDD172 VDD173 VDD174 VDD175 VDD176 VDD177

VDD131 VDD132 VDD133 VDD134 VDD135 VDD136 VDD137 VDD138 VDD139 VDD140 VDD141 VDD142

VDD178 VDD179 VDD180 VDD181 VDD182 VDD183 VDD184 VDD185 VDD186 VDD187 VDD188 VDD189

X806937-001

V_CPUVCS

IC

U7D1

LOKI P7

P9 P11 P13 P15 P17 P19 P21 P23 R2 R4 R6 R8 R10 R12 R14 R16 R18 R20 R22 T1

T3 T5 T7

T9 T11 T13 T15 T17 T19 T21 T23 U2 U4 U6

V9 V11 V13 V15 V17 V19 V21 V23 W2 W4 W6 W8 W10 W12 W14 W16 W18 W20 W22 Y1

Y3 Y5 Y7

Y9 Y11 Y13 Y15 Y17 Y19 Y21 Y23

VDD190 VDD191 VDD192 VDD193 VDD194 VDD195 VDD196 VDD197 VDD198 VDD199 VDD200 VDD201

VCS0 VCS1 VCS2 VCS3 VCS4 VCS5 VCS6 VCS7 VCS8 VCS9 VCS10 VCS11

VDD202 VDD203 VDD204 VDD205 VDD206 VDD207 VDD208 VDD209 VDD210 VDD211 VDD212 VDD213 VDD214 VDD215 VDD216 VDD217 VDD218 VDD219 VDD220

VCS12 VCS13 VCS14 VCS15

B1

B3 C1

C2 C3 D1

D3 D4 D5 E2 E4 E6 F1

F3 F5 F7

U8 U10 U12 U14 U16 U18 U20 U22 V1

V3 V5 V7

X806937-001

X806937-001

[PAG [PAGE_ E_TI TITL TLE= E=CP CPU, U,

CORE CORE POWE POWER] R]

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 0 09 9

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 7/83

REV A

CR-9

:

@JASPER_LIB.JASPER(SCH_1):PAGE9

CPU,, CPU

V_CPUCORE

1

C7T94

2

4.7UF 10% 6.3V EMPTY 805

1

C7T93

2

4.7UF 10% 6.3V EMPTY 805

1

C7T33

2

4.7UF 10% 6.3V X5R 805

1

C7R2

2

4.7UF 10% 6.3V X5R 805

1

C7E10

C7T32

2

4.7UF 10% 6.3V X5R 805

1

C7R26

2

4.7UF 10% 6.3V X5R 805

1

C7E9

2

4.7UF 10% 6.3V EMPTY 805

1

C7T1

2

4.7UF 10% 6.3V X5R 805

1

C7T6

2

4.7UF 10% 6.3V X5R 805

[P [PAG AGE_ E_TI TITL TLE= E=CP CPU, U,

DE DECO COUP UPLI LING NG]]

C7E6

2

1

C7D12

2

4.7UF 10% 6.3V X5R 805

1

C7D19

1

C7D3

2

4.7UF 10% 6.3V X5R 805

1

2

4.7UF 10% 6.3V EMPTY 805

1

C7E5

2

4.7UF 10% 6.3V X5R 805

1

C7D5

2

4.7UF 10% 6.3V EMPTY 805

C7R121

1

2

4.7UF 10% 6.3V EMPTY 805

1

C7R23

2

4.7UF 10% 6.3V X5R 805

1

C7R24

1

C7R3

2

4.7UF 10% 6.3V X5R 805

2

4.7UF 10% 6.3V X5R 805

1

C7E1

2

4.7UF 10% 6.3V X5R 805 C7R119

2

4.7UF 10% 6.3V EMPTY 805

C7R120

2

4.7UF 10% 6.3V EMPTY 805

1

1

4.7UF 10% 6.3V X5R 805

DEC DECOUP OUPLIN LING G

1

2

4.7UF 10% 6.3V EMPTY 805

1

C7R90

2

4.7UF 10% 6.3V X5R 805

1

C7E2

2

4.7UF 10% 6.3V X5R 805

1

C7T83

2

4.7UF 10% 6.3V X5R 805

1

C7D11

2

4.7UF 10% 6.3V X5R 805

1

C7T84

2

4.7UF 10% 6.3V X5R 805

1

C6T1

2

4.7UF 10% 6.3V X5R 805

1

C7R30

2

4.7UF 10% 6.3V X5R 805

1

C7R27

2

4.7UF 10% 6.3V X5R 805

1

C7D8

2

4.7UF 10% 6.3V X5R 805

1

C7D4

2

4.7UF 10% 6.3V X5R 805

1

C7D18

2

4.7UF 10% 6.3V EMPTY 805

1

C7D7

2

4.7UF 10% 6.3V X5R 805

1

C7R91

1

C6R7

2

4.7UF 10% 6.3V X5R 805

1

C6R10

2

4.7UF 10% 6.3V X5R 805

1

C7R28

2

4.7UF 10% 6.3V X5R 805

1

C7R29

2

4.7UF 10% 6.3V X5R 805

1

C7T4

2

4.7UF 10% 6.3V X5R 805

2

4.7UF 10% 6.3V X5R 805

1

C7T5

2

4.7UF 10% 6.3V X5R 805

1

C7R5

2

4.7UF 10% 6.3V X5R 805

1

C7R4

2

4.7UF 10% 6.3V X5R 805

1

C7R25

2

4.7UF 10% 6.3V X5R 805

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 0 09 9

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 9/83

REV A

CR-10

:

@JASPER_LIB.JASPER(SCH_1):PAGE10

CPU,, CPU

V_CPUCORE

1

C7R49

2

.1UF 10% 6.3V X5R 402

1

C7R44

2

.1UF 10% 6.3V X5R 402

1

C6R29

2

.1UF 10% 6.3V X5R 402

1

C6R28

2

.1UF 10% 6.3V X5R 402

1

C6R17

2

.1UF 10% 6.3V X5R 402

1

C7R76

2

.1UF 10% 6.3V X5R 402

1

C6R39

2

.1UF 10% 6.3V X5R 402

1

C6R42

2

.1UF 10% 6.3V X5R 402

1

C7R67

2

.1UF 10% 6.3V X5R 402

1

C7T3

2

.1UF 10% 6.3V X5R 402

[P [PAG AGE_ E_TI TITL TLE= E=CP CPU, U,

DE DECO COUP UPLI LING NG]]

1

C7T9

2

.1UF 10% 6.3V X5R 402

1

C7R22

2

.1UF 10% 6.3V X5R 402

1

C7R35

2

.1UF 10% 6.3V X5R 402

1

C7R34

2

.1UF 10% 6.3V X5R 402

1

C7R19

2

.1UF 10% 6.3V X5R 402

1

C7R43

2

.1UF 10% 6.3V X5R 402

1

C6R16

2

.1UF 10% 6.3V X5R 402

1

C6R19

2

.1UF 10% 6.3V X5R 402

1

C7R61

2

.1UF 10% 6.3V X5R 402

1

C6R35

2

.1UF 10% 6.3V X5R 402

1

C6R44

2

.1UF 10% 6.3V X5R 402

1

C6R32

2

.1UF 10% 6.3V X5R 402

C7R102

1

2

.1UF 10% 6.3V X5R 402

1

C7R81

2

.1UF 10% 6.3V X5R 402

1

C7R68

2

.1UF 10% 6.3V X5R 402

1

C7R69

2

.1UF 10% 6.3V X5R 402

1

C7R57

2

.1UF 10% 6.3V X5R 402

1

C6R20

2

.1UF 10% 6.3V X5R 402

1

C6R21

2

.1UF 10% 6.3V X5R 402

1

C6T26

2

.1UF 10% 6.3V X5R 402

DEC DECOUP OUPLIN LING G

1

C7R52

2

.1UF 10% 6.3V X5R 402

1

C7R51

2

.1UF 10% 6.3V X5R 402

1

C7R50

2

.1UF 10% 6.3V X5R 402

1

C6T6

2

.1UF 10% 6.3V X5R 402

1

C6R36

2

.1UF 10% 6.3V X5R 402

1

C6R23

2

.1UF 10% 6.3V X5R 402

1

C7R58

2

.1UF 10% 6.3V X5R 402

1

C7R59

2

.1UF 10% 6.3V X5R 402

1

C7R60

2

.1UF 10% 6.3V X5R 402

1

C7T2

2

.1UF 10% 6.3V X5R 402

1

C6T10

2

.1UF 10% 6.3V X5R 402

1

C7T22

2

.1UF 10% 6.3V X5R 402

1

C7T27

2

.1UF 10% 6.3V X5R 402

1

C7R48

2

.1UF 10% 6.3V X5R 402

1

C7T51

1

C7T21

2

.1UF 10% 6.3V X5R 402

1

C6T2

2

.1UF 10% 6.3V X5R 402

1

C7T10

2

.1UF 10% 6.3V X5R 402

C7R111

1

2

.1UF 10% 6.3V X5R 402

2

.1UF 10% 6.3V X5R 402

1

C7T37

2

.1UF 10% 6.3V X5R 402

1

C7R89

2

.1UF 10% 6.3V X5R 402

1

C6T25

2

.1UF 10% 6.3V X5R 402

1

C7R99

2

.1UF 10% 6.3V X5R 402

C7R100

1

2

.1UF 10% 6.3V X5R 402

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 0 09 9

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 10/83

REV A

CR-11

:

@JASPER_LIB.JASPER(SCH_1):PAGE11

CPU,, CPU

V_CPUCORE

DEC DECOUP OUPLIN LING G

V_CPUVCS

N:EMPTIES 1

C7R31

2

.1UF 10% 6.3V X5R 402

1

C7T54

2

.1UF 10% 6.3V X5R 402

1

C6T16

2

.1UF 10% 6.3V X5R 402

1

C7R56

2

.1UF 10% 6.3V X5R 402

1

C6R26

2

.1UF 10% 6.3V X5R 402

1

C6T9

2

.1UF 10% 6.3V X5R 402

1

C6T3

2

.1UF 10% 6.3V X5R 402

1

C7R21

2

.1UF 10% 6.3V X5R 402

1

C6R41

2

.1UF 10% 6.3V X5R 402

1

C6R13

2

.1UF 10% 6.3V X5R 402

[P [PAG AGE_ E_TI TITL TLE= E=CP CPU, U,

1

C7T25

2

.1UF 10% 6.3V X5R 402

1

C6T24

2

.1UF 10% 6.3V X5R 402

1

C6T13

2

.1UF 10% 6.3V X5R 402

1

C7R20

2

.1UF 10% 6.3V X5R 402

1

C7R42

2

.1UF 10% 6.3V X5R 402

1

C7R41

2

.1UF 10% 6.3V X5R 402

1

C7R40

2

.1UF 10% 6.3V X5R 402

1

C7R39

2

.1UF 10% 6.3V X5R 402

1

C6T21

2

.1UF 10% 6.3V X5R 402

1

C6R12

2

.1UF 10% 6.3V X5R 402

DE DECO COUP UPLI LING NG]]

1

C7T38

2

.1UF 10% 6.3V X5R 402

C7R110

1

2

.1UF 10% 6.3V X5R 402

1

C6T14

2

.1UF 10% 6.3V X5R 402

1

C7T28

2

.1UF 10% 6.3V X5R 402

1

C7R14

2

.1UF 10% 6.3V X5R 402

1

C7T49

2

.1UF 10% 6.3V X5R 402

1

C6T22

2

.1UF 10% 6.3V X5R 402

1

C7T41

2

.1UF 10% 6.3V X5R 402

1

C7R33

2

.1UF 10% 6.3V X5R 402

1

C7R32

2

.1UF 10% 6.3V X5R 402

1

C7T58

2

.1UF 10% 6.3V X5R 402

1

C6R24

2

.1UF 10% 6.3V X5R 402

1

C7T56

2

.1UF 10% 6.3V X5R 402

1

C7T50

2

.1UF 10% 6.3V X5R 402

C7R106

1

2

.1UF 10% 6.3V X5R 402

1

C7T11

2

.1UF 10% 6.3V X5R 402

1

C7T40

2

.1UF 10% 6.3V X5R 402

1

C7R75

2

.1UF 10% 6.3V X5R 402

1

C7T47

2

.1UF 10% 6.3V X5R 402

1

C7T46

2

.1UF 10% 6.3V X5R 402

1

C6T17

2

.1UF 10% 6.3V X5R 402

1

C7R95

2

.1UF 10% 6.3V X5R 402

1

C6T18

2

.1UF 10% 6.3V X5R 402

C7R101

1

2

.1UF 10% 6.3V X5R 402

1

C7T57

2

.1UF 10% 6.3V X5R 402

1

C7T55

2

.1UF 10% 6.3V X5R 402

1

C7R83

2

.1UF 10% 6.3V X5R 402

1

C7T39

2

.1UF 10% 6.3V X5R 402

1

C7T26

2

.1UF 10% 6.3V X5R 402

1

C7T48

2

.1UF 10% 6.3V X5R 402

1

C7R66

2

.1UF 10% 6.3V EMPTY 402

1

C6T4

2

.1UF 10% 6.3V EMPTY 402

1

C7T15

2

.1UF 10% 6.3V EMPTY 402

1

C7T24

2

.1UF 10% 6.3V EMPTY 402

1

C6T11

2

.1UF 10% 6.3V EMPTY 402

1

C7R74

2

.1UF 10% 6.3V EMPTY 402

1

C6R30

2

.1UF 10% 6.3V EMPTY 402

1

C7R82

2

.1UF 10% 6.3V EMPTY 402

1

C7T23

2

.1UF 10% 6.3V EMPTY 402

1

C7R65

2

.1UF 10% 6.3V EMPTY 402

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 1 10 0

1

C7T7

2

.1UF 10% 6.3V X5R 402

1

C7T14

2

.1UF 10% 6.3V X5R 402

1

C7T12

2

.1UF 10% 6.3V X5R 402

1

C7T13

1

C7T29

2

.1UF 10% 6.3V X5R 402

1

C7T30

2

.1UF 10% 6.3V X5R 402

1

C7T31

2

.1UF 10% 6.3V X5R 402

2

.1UF 10% 6.3V X5R 402

1

C7T8

2

.1UF 10% 6.3V X5R 402

1

C7T16

2

.1UF 10% 6.3V X5R 402

1

C7T17

2

.1UF 10% 6.3V X5R 402

1

C7T18

2

.1UF 10% 6.3V X5R 402

1

C7T19

2

.1UF 10% 6.3V X5R 402

1

C7T20

2

.1UF 10% 6.3V X5R 402

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 11/83

REV A

CR-16

:

@JASPER_LIB.JASPER(SCH_1):PAGE16

GPU,

PLL

POWER + FSB POWER

V_GPUCORE FB4D1 1

2

FB 603

120 0.2A 0.5 0.5 D CR

1

C4D6

1

2.2UF 10%

2 6.3V X5R

2

603

C4D5 .1UF 10% 6.3V X5R 402

1

2

C4D4

0.01UF 10% 16V X7R 402

V_GPUCORE V_GPUPCIE

U4D1

GP GPU U Y2 VERSI VERSION ON

FB4T1 1

2 V_PVDDA

FB 603

120 0.2A 0.5 0.5 D CR

1

C4T48

2.2UF 10% 6.3V X5R 603

2

1

2

C4T30 .1UF 10% 6.3V X5R 402

C4T37 0.01UF 10% 16V X7R 402

1

C5R7

2

.1UF 10% 6.3V X5R 402

V_PVDDA_MEM

FB4R1 1

0.5 0.5

120 0.2A D CR

2

V_PVDDA_ED

FB 603

1

2

C4R68

2.2UF 10% 6.3V X5R 603

1

2

C4R4 .1UF 10% 6.3V X5R 402

C4R6

0.01UF 10% 16V X7R 402

V_PVDDA_FSB

1

2

C4R8 .1UF 10% 6.3V X5R 402

A20 A21

PVDDA PVSSA

C27 C26

VDD_BSB1 VSS_BSB1

C25 C24

VDD_BSB0 VSS_BSB0

AG10 AG9

PVDDA_MEM PVSSA_MEM

A18 A19

PVDDA_ED PVSSA_ED

B25 B24

PVDDA_PEX PVSSA_PEX

G34 F34

PVDDA_FSB PVSSA_FSB

V_GPUPCIE

IC

8 OF 1 2 1 VDD_FSB24

AA27

VDD_FSB23 VDD_FSB22 VDD_FSB21 VDD_FSB20 VDD_FSB19 VDD_FSB18 VDD_FSB17 VDD_FSB16 VDD_FSB15 VDD_FSB14 VDD_FSB13 VDD_FSB12 VDD_FSB11 VDD_FSB10 VDD_FSB9 VDD_FSB8 VDD_FSB7 VDD_FSB6 VDD_FSB5 VDD_FSB4 VDD_FSB3 VDD_FSB2 VDD_FSB1

AB28 AB32 AC27 AD28 AD31 K28 K31 L27 M28 M32 N27 P28 P31 R28 R32 T27 U28 U31 V27 V30 W28 W32 Y28

VDD_FSB0

Y31

X02125-001

1

2

C4R5

C4R7

.1UF 10% 6.3V X5R 402

0.01UF 10% 16V X7R 402

C5R13

C5R15

10% 6.3V X5R 402

10% 16V X7R 402

FB5R1 1

120 0.2A 0.5 0.5 D CR

2

FB 603

1

C5R19

1

.1UF

2.2UF

2

[PAGE_T E_TITLE=GPU, PU,

10% 6.3V X5R 603

PLL

2

0.01UF

POWER + FSB POWER]

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 1 18 8

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 16/83

REV A

CR-18

:

@JASPER_LIB.JASPER(SCH_1):PAGE18

GPU, GPU,

DECO DECOUP UPLI LING NG

V_GPUCORE

V_GPUCORE

V_GPUCORE

N:EMPTIES 1

C4R20

2

.1UF 10% 6.3V X5R 402

1

C4R37

2

.1UF 10% 6.3V X5R 402

1

C4T15

2

.1UF 10% 6.3V X5R 402

1

C4R14

2

.1UF 10% 6.3V X5R 402

1

C4R39

2

.1UF 10% 6.3V X5R 402

1

C4R11

2

.1UF 10% 6.3V X5R 402

1

C4R17

2

.1UF 10% 6.3V X5R 402

1

C4R55

2

.1UF 10% 6.3V X5R 402

1

C4R47

2

.1UF 10% 6.3V X5R 402

1

C4T20

2

.1UF 10% 6.3V X5R

1

C4T25

2

.1UF 10% 6.3V X5R 402

1

C4T11

2

.1UF 10% 6.3V X5R 402

C4T3

1

2

C4R49

2

.1UF 10% 6.3V X5R 402

1

C4R18

2

.1UF 10% 6.3V X5R 402

[P [PAG AGE_ E_TI TITL TLE= E=GP GPU, U,

C4R36

1

C4R34

2

.1UF 10% 6.3V X5R 402

C4R42

2

.1UF 10% 6.3V X5R 402

1

C4T16

2

.1UF 10% 6.3V X5R 402

1

C4T1

2

1

C4R21

2

.1UF 10% 6.3V X5R 402

1

C4T26

2

.1UF 10% 6.3V X5R 402

1

C4T21

2

.1UF 10% 6.3V X5R 402

1

C4R46

2

.1UF 10% 6.3V X5R

1

2

.1UF 10% 6.3V X5R 402

DE DECO COUP UPLI LING NG]]

1

C4R41

C4R35

2

.1UF 10% 6.3V X5R 402

2

C4R67

1

.1UF 10% 6.3V X5R 402

1

C4R63

2

.1UF 10% 6.3V X5R 402

1

C4T2

2

1

C4R22

2

.1UF 10% 6.3V X5R 402

1

C4T23

2

.1UF 10% 6.3V X5R 402

1

C4R44

2

.1UF 10% 6.3V X5R 402

1

C4T24

2

.1UF 10% 6.3V X5R

1

2

.1UF 10% 6.3V X5R 402

1

C4T19

C4T18

2

.1UF 10% 6.3V X5R 402

1

C4R62

2

.1UF 10% 6.3V X5R 402

1

C4R43

2

.1UF 10% 6.3V X5R 402

1

C5R17

2

1

C5R16

1

2

C5R10

1

.1UF 10% 6.3V X5R 402

1

C5R12

2

.1UF 10% 6.3V X5R 402

1

C4R24

1

.1UF 10% 6.3V X5R 402

2

C4R54

2

.1UF 10% 6.3V X5R 402

C4R40

1

C5R8

C4R9

C4R59

C4T6

1

2

C5R14

1

C5R9

C4R57

2

2

1

1

2

2

2

.1UF 10% 6.3V X5R 402

2

C4T4

2

.1UF 10% 6.3V EMPTY 402

1

C4R58

2

C4T8

2

1

C5R4

2

C5R20

C6E1

1

4.7UF 10% 6.3V X5R 805

2

1

C5D3

1

4.7UF 10% 6.3V X5R 805

2

1

C5D4

1

4.7UF 10% 6.3V X5R 805

4.7UF 10% 6.3V X5R 805

2

1

C5D6

2

C4R29

1

10UF 20% 6.3V X5R 805

2

C4T17

1

10UF 20% 6.3V X5R 805 2

C4R30

1

10UF 20% 6.3V X5R 805

2

C4R69

1

10UF 20% 6.3V X5R 805

1

4.7UF 10% 6.3V X5R 805

4.7UF 10% 6.3V X5R

1

2

.1UF 10% 6.3V EMPTY 402

C5R2

2

2

2

C5R1

C5D5

1

4.7UF 10% 6.3V X5R 805

4.7UF 10% 6.3V X5R 805

1

4.7UF 10% 6.3V X5R 805

2

.1UF 10% 6.3V EMPTY 402

1

C5R5

1

805

C4R56

.1UF 10% 6.3V EMPTY 402

2

C6E2

C6R47

4.7UF 10% 6.3V X5R 805

4.7UF 10% 6.3V X5R 805

2

2

2

1

4.7UF 10% 6.3V X5R 805

2

2

C5D2

4.7UF 10% 6.3V X5R 805

402

.1UF 10% 6.3V X5R 402

1

2

.1UF 10% 6.3V EMPTY

2

.1UF 10% 6.3V X5R 402

1

.1UF 10% 6.3V EMPTY 402

.1UF 10% 6.3V X5R 402

1

C4T5

.1UF 10% 6.3V EMPTY 402

.1UF 10% 6.3V X5R 402

1

2

.1UF 10% 6.3V EMPTY 402

.1UF 10% 6.3V X5R

1

2

.1UF 10% 6.3V EMPTY 402

402

2

.1UF 10% 6.3V X5R 402

1

C4R13

.1UF 10% 6.3V X5R 402

402

2

.1UF 10% 6.3V X5R 402

1

C4R28

.1UF 10% 6.3V X5R 402

402

2

.1UF 10% 6.3V X5R 402

1

.1UF 10% 6.3V EMPTY 402

1

1

.1UF 10% 6.3V X5R 402

402

1

C4R16

C5R3

1

4.7UF 10% 6.3V X5R 805

2

C5R11

1

4.7UF 10% 6.3V X5R 805

2

C5R6

1

4.7UF 10% 6.3V X5R 805

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 1 18 8

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 18/83

REV A

CR-20

:

@JASPER_LIB.JASPER(SCH_1):PAGE20

CHIP CHIP Y SE SELE LECT CT RTIT = 1, MI MIRR RROR OR MEMOR EMORY PA PART ITIO ION N

V_MEM

1

R4U3

60.4

60.4

CH

CH 402

1%

14

402

1%

2

IC

U4U1 GDDR136 MF=1

MA_CLK1_DP

IN

14 13 14

J11 J10

MA_CLK1_DN

IN

MEM_RST MA_A

IN IN

MA_BA

IN

CLK_DP CLK_DN

V9

RESET

11

L9

10

K11

A7/A11 A8/A10 A3/A9 A10/A8 A11/A7 A2/A6 A1/A5 A0/A4 A9/A3 A6/A2 A5/A1 A4/A0

9 8

M4 K2

7

L4 K3

6 5 4

H2

3

M9

2

K10

1

H11

0 14

K4

K9

2

H3

1

G4

0

G9

RAS_N/BA2 BA0/BA1 BA1/BA0

IN IN IN IN IN

MA_CKE MA_WE_N MA_CAS_N MA_RAS_N MA_CS1_N

IN

MEM_SCAN_BOT_EN

A9

12

IN

MEM_SCAN_EN

V4

SCAN_EN

20

IN IN

MEM_A_VREF0 MEM_A_VREF1

H1

VREF1 VREF0

14 14 14 14 14 12

19

H9

WE_N/CKE CKE/WE_N CS_N/CAS_N BA2/RAS_N CAS_N/CS_N

H4 F9

H10 F4

MF

H12

V_MEM

V_MEM

DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24

T3 T2 R3 R2 M3 N2 M2

MA_DQ23 MA_DQ22 MA_DQ21 MA_DQ20 MA_DQ19 MA_DQ18 MA_DQ17 MA_DQ16

WDQS3 RDQS3 DM3

P2 P3 N3

MA_WDQS2 MA_RDQS2 MA_DM2

DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 WDQS2 RDQS2 DM2

T10 T11 R10 R11 M10 N11 L10 M11 P11 P10 N10

MA_DQ31 MA_DQ30 MA_DQ29 MA_DQ28 MA_DQ27 MA_DQ26 MA_DQ25 MA_DQ24 MA_WDQS3 MA_RDQS3 MA_DM3

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 WDQS1 RDQS1 DM1

G10 F11 F10 E11 C10 C11 B10 B11 D11 D10 E10

MA_DQ7 MA_DQ6 MA_DQ5 MA_DQ4 MA_DQ3 MA_DQ2 MA_DQ1 MA_DQ0 MA_WDQS0 MA_RDQS0 MA_DM0

DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0 DM0

G3 F2 F3 E2 C3 C2 B3 B2 D2 D3 E3

MA_DQ15 MA_DQ14 MA_DQ13 MA_DQ12 MA_DQ11 MA_DQ10 MA_DQ9 MA_DQ8 MA_WDQS1 MA_RDQS1 MA_DM1

ZQ

A4

L3

BI BI BI BI BI BI BI BI

19

14

19

14

19

V1

14

19

14

19

R12

14

19

14

19

R1

14

19

N12

IN

14 19

IN

14

OUT

R9 R4

N9 14

V12 N4

14

19

J9

14

19

J4

14

19

14

19

E12

14

19

E4

14

19

E1

14 14

E9

19

C12

19

C9 C4

14

IN

19

OUT

14

C1

14

IN

A12 A1

14

BI BI BI BI BI BI BI BI

19

V2

19

14

19

M12

14

19

14

19

14

19

14

19 14

IN

19

OUT 14

19

14

19

14

19

14

19

14

19

14

19

14 14

IN

OUT IN

M1

V11 F12 F1

A11 A2 14

14

IN

BI BI BI BI BI BI BI BI

19

14 14

K12

VSS VSS VSS VSS VSS

VDD VDD VDD

VSS VSS VSS

T1

P12 P9 P4 P1 L11 L2

G11 G2 D12 D9 D4 D1

B12 B9 B4 B1

V3 L12 L1

G12 G1

A10 V10 A3

NC NC

J3 J2

VSSA VSSA

J1

X801995-011

19 19 14 19

14

14

R3U1 1%

549

2

1%

CH 402

MEM_A_VREF0

CH 402

V_MEM MEM MEMORY ORY A,

OUT

C3U2

R4F2 1.27K

.22UF 10% 6.3V X5R 402

C4F2

.1UF 10% 6.3V X5R 402

[PAG [PAGE_ E_T TITLE ITLE=M =MEM EMOR ORY Y

BOT BOTTOM TOM,,

DEC DECOUP OUPLING LING

19 20

1

CH 402

VDD VDD VDD VDD VDD

VDDA VDDA

K1 J12

T12 T9 T4

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

243

R4F1

2

GDDR136 MF=1

1

1

1%

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

N1

BI BI BI BI BI BI BI BI

IC

U4U1

14

MA_ZQ_BOT

X801995-011

2

= 1 TTOM BO BOTT OM

1

R4U2

2

A,

FUNC FUNCTI TION ON

PART PARTIT ITIO ION N

A,

TO TOP] P]

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 2 21 1

C4U8

.22UF 10% 6.3V X5R 402

2008

C4U11 .22UF 10% 6.3V X5R 402

C4U6

.22UF 10% 6.3V X5R 402

MICROSOFT

CONFIDENTIAL

C3U1 .22UF 10% 6.3V X5R 402

C4U1 .22UF 10% 6.3V X5R 402

PRO PROJEC JECT T H08580

C4U5

.22UF 10% 6.3V X5R 402

NAME NAM E

C4U2

.22UF 10% 6.3V X5R 402

PAGE 20/83

REV A

CR-22

:

@JASPER_LIB.JASPER(SCH_1):PAGE22

ME MEM MCHIP OR ORY PA PART ION N CH IP Y SELE SELECT CT RTIT = 1,ITIO MI MIRR RROR OR

B,

FUNC FUNCTI TION ON

BO BOTT TTOM OM

= 1

V_MEM

1

1

R5U2

R5U1

60.4

60.4

CH 402

402

1%

2 14

IN

1%

CH

2

IC

U5U1 GDDR136 MF=1

MB_CLK1_DP

14 13 14

IN

MB_CLK1_DN

IN

MEM_RST MB_A

IN

J11 J10 V9 11 10

9 8 7

6 5 4 3

2 1

0 14

IN

MB_BA

H3 G4

2 1

0

G9 H9 H4 F9 H10 F4

IN IN IN IN IN

MB_CKE MB_WE_N MB_CAS_N MB_RAS_N MB_CS1_N

IN

MEM_SCAN_BOT_EN

12

IN

MEM_SCAN_EN

22

IN IN

MEM_B_VREF0 MEM_B_VREF1

14 14 14 14 14 12

21

L9 K11 M4 K2 L4 K3 H2 K4 M9 K10 H11 K9

A9

CLK_DP CLK_DN

RAS_N/BA2 BA0/BA1 BA1/BA0 WE_N/CKE CKE/WE_N CS_N/CAS_N BA2/RAS_N CAS_N/CS_N MF

V4

SCAN_EN

H1

VREF1 VREF0

H12

DQ26 DQ25 DQ24 WDQS3 RDQS3 DM3

MB_DQ23 MB_DQ22 MB_DQ21 MB_DQ20 MB_DQ19 MB_DQ18 MB_DQ17 MB_DQ16 MB_WDQS2 MB_RDQS2 MB_DM2

DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 WDQS2 RDQS2 DM2

T10 T11 R10 R11 M10 N11 L10 M11 P11 P10 N10

MB_DQ31 MB_DQ30 MB_DQ29 MB_DQ28 MB_DQ27 MB_DQ26 MB_DQ25 MB_DQ24 MB_WDQS3 MB_RDQS3 MB_DM3

DQ15 DQ14 DQ13 DQ12

G10 F11 F10 E11

MB_DQ7 MB_DQ6 MB_DQ5 MB_DQ4

RESET A7/A11 A8/A10 A3/A9 A10/A8 A11/A7 A2/A6 A1/A5 A0/A4 A9/A3 A6/A2 A5/A1 A4/A0

V_MEM

V_MEM T3 T2 R3 R2 M3 N2 L3 M2 P2 P3 N3

DQ31 DQ30 DQ29 DQ28 DQ27

DQ11 DQ10 DQ9 DQ8 WDQS1 RDQS1 DM1

C10 C11 B10 B11 D11 D10 E10

MB_DQ3 MB_DQ2 MB_DQ1 MB_DQ0 MB_WDQS0 MB_RDQS0 MB_DM0

DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0 DM0

G3 F2 F3 E2 C3 C2 B3 B2 D2 D3 E3

MB_DQ15 MB_DQ14 MB_DQ13 MB_DQ12 MB_DQ11 MB_DQ10 MB_DQ9 MB_DQ8 MB_WDQS1 MB_RDQS1 MB_DM1

ZQ

A4

BI BI BI BI BI

14

21

14

21

14

21

14

21

14

21

14

21

BI BI BI

14

21

14

21

BI BI BI BI BI BI BI BI

BI BI BI BI BI BI BI BI

BI BI BI BI BI BI BI BI

14

IN OUT IN

21

21

14

21

14

21

14

21

14 14

21 21

14

21

14

21 14

IN OUT IN

21

14

14 14

21

14

21

14

21

14

21

14 14

21 21

14

21

14

21 14

IN OUT IN

21

14

14 14

21

14

21

14

21

14

21

14

21

14 14 14

IN OUT IN

14

14 14

IC

U5U1

V1 R12 R9

VDDQ VDDQ VDDQ

R4 R1 N12 N9 V12 N4 N1 J9 J4 E12 E9 E4 E1 C12 C9 C4 C1 A12 A1

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

V2 M12 M1 V11 F12 F1 A11 A2

VDD VDD VDD VDD VDD VDD VDD VDD

K12 K1

VDDA VDDA

J12 J1

VSSA VSSA

21

GDDR136 MF=1 VSSQ

T12

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

T9 T4 T1 P12 P9 P4 P1 L11 L2 G11 G2 D12 D9 D4 D1 B12 B9 B4 B1

VSS VSS VSS VSS VSS VSS VSS VSS

V3 L12

NC NC

L1

G12 G1 A10 V10 A3 J3 J2

X801995-011

21 21 14 21

14

14

MB_ZQ_BOT

1 1

R4U1 243

X801995-011

R5F1

1%

549 1%

CH

CH

2

2

402

MEM_B_VREF0

OUT

402

V_MEM MEM MEMORY ORY B,

21 22

1

R5F2 1.27K

1% CH

2

402

[PAG [PAGE_ E_T TITL ITLE=ME E=MEMO MORY RY

C4U10

.22UF 10% 6.3V X5R 402

C5F1

.1UF 10% 6.3V X5R 402

PARI PARITI TION ON

B,

TOP] TOP]

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 2 23 3

2008

C5U4

.22UF 10% 6.3V X5R 402

C4U7

.22UF 10% 6.3V X5R 402

BOT BOTTOM TOM,,

C4U4

.22UF 10% 6.3V X5R 402

MICROSOFT

CONFIDENTIAL

DEC DECOUP OUPLING LING

C4U3

.22UF 10% 6.3V X5R 402

PRO PROJEC JECT T H08580

C5U1 .22UF 10% 6.3V X5R 402

NAME NAM E

C5U2

.22UF 10% 6.3V X5R 402

C5U3

.22UF 10% 6.3V X5R 402

PAGE 22/83

REV A

CR-29

:

@JASPER_LIB.JASPER(SCH_1):PAGE29

R2A11 0

5%

603

CH

44

NA SM CM2A1 EMPTY 28

28

IN IN

HDMI_TX2_DP

CMCHOKE

1

1

ESDB-MLP7 402

                                           1

X801560-001

EG2A2

R2A12 0

FTP FT3M2

1

EG2A1

FTP FT3M4

HDMI_TX2_DP_CM

1

HDMI_TX2_DN_CM

2 3

5% CH

603

             2

             2

HDMI_TX0_DP_CM

R2A13 HDMI_TX0_DN_CM

0

5%

HDMI_TXC_DP_CM

CH

28

IN IN

HDMI_TX1_DP HDMI_TX1_DN

1

CMCHOKE

16 17 18

ESDB-MLP7 402

ESDB-MLP7 402

                                           1

EG2A4

DIO

DIO

2

5%

CH

34

             2

34

44 28 28 44

IN

1%

402

2

IN

28

IN

HDMI_TX0_DP HDMI_TX0_DN

1

CMCHOKE

3

1

ESDB-MLP7 402

EG3M2

                                           1

BAV99 DIO

R3A11 0

                                           1

EG3A2

ESDB-MLP7 402

EG3A1

DIO

R3M7

2

HDMI_HPD

5%

OUT

28

CH

DIO

CH

2 EMPTY

PGB0010603 603

EG3M1

47K 5%

ESDB-MLP7 402

EG3M3

3

ESDB-MLP7 402

                                           1

R3M1

4

BAV99 DIO

                                           1

1

5 6

X801560-001

     H

FT2N6

10K 402

EMPTY

4

X806395-002

CR3M1

1

2

20

     P      H      I_      M      D

FTP

ME4 ME3 ME2 ME1

21

     N      I      P _      D

FT4N2

1

                                           1

IN

FTP

402

2

CH

NA SM CM3A1 EMPTY 28

1

CH

CR3M1

5%

23 22

2K

HDMI_DDC_CLK HDMI_DDC_DATA

R3A10 0

R3M6

1%

2K

EG2A3

19

R3M5 CH

             2

603

HDMI_CEC

1

1

R2A14

1

2

                                           1

0

DB3A1

V_5P0STBY

X801560-001

603

12 13 14 15

HDMI_TXC_DN_CM

3

4

TMDS_DATA1_SHD TMDS_DATA1_DN TMDS_DATA0_DP TMDS_DATA0_SHD TMDS_DATA0_DN TMDS_CLK_DP TMDS_CLK_SHD TMDS_CLK_DN CEC RESERVED SCL SDA DDC_CEC_GND 5VCC HOT_PLUG_DET

11

NA SM CM2A2 EMPTY 28

HDMI TMDS_DATA2_DP TMDS_DATA2_SHD TMDS_DATA2_DN TMDS_DATA1_DP

4 5 6 7 8 9 10

HDMI_TX1_DP_CM HDMI_TX1_DN_CM

603

HDR

J2A1

FTP FT3M3

1

DIO

DIO

.1UF 10% 6.3V X5R 402

FTP FT3M1

1

ESDB-MLP7 402

                                           1

C2A9

2

FTP FT2M5

1

3

4

1

FTP FT2M4

1

HDMI_TX2_DN

V_AVIP

FTP FT2M3

1

2

IN

FTP FT2M2

1

402              2

             2              2

DIO

5%

CH

603

             2

             2

R3A12 0

5%

CH

603

NA SM CM3A2 EMPTY 28

IN

HDMI_TXC_DP

1

28

IN

HDMI_TXC_DN

4

CMCHOKE

2

3                                            1

X801560-001

0

HDMI HDMI]]

ESDB-MLP7 402

EG3A3

DIO

DIO

5%

CH

             2

[PAG [PAGE_ E_TI TITL TLE= E=CO CONN NN,,

                                           1

EG3A4

R3A13 603

ESDB-MLP7 402

             2

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 3 30 0

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 29/83

REV A

CR-30

:

@JASPER_LIB.JASPER(SCH_1):PAGE30

HANA HANA,,

V_3P3STBY

POWE POWER R + DECO DECOUP UPLI LING NG

FB4N5

1

2

V_HANA_VAA_RTS33S

FB 603

120 0.2A D CR

0.5 C4N360.5

1

4.7UF 10% 6.3V X5R 805

C4N37

4.7UF 10% 6.3V X5R 805

2

C4N35 .1UF 10% 6.3V X5R 402

V_1P8STBY U4C2

IC

3 OF 4 HANA

V_3P3

D12 D11

FB4N8 1

C4N15

60 0.5A 0.1DCR

2

V_HANA_VAA_DAC33M

FB 603

1

4.7UF 10% 6.3V X5R 805

2

C4N24

C4N23

4.7UF 10% 6.3V X5R 805

.1UF 10% 6.3V X5R 402

1

2

C4N29 .1UF 10% 6.3V X5R 402

V_3P3STBY

V_3P3STBY R4N1

1

100 402

2

V_HANA_VAA_XTAL_33S

5% CH

1

2

C4N16

.1UF 10% 6.3V X5R 402

VAA_RTS33S AVSS_RTS33S

E9 D9 C9 D8

VAA_DAC33M3 VAA_DAC33M2 VAA_DAC33M1 AVSS_DAC33M1

C7 D7

VAA_DAC33M0 AVSS_DAC33M0

C6

VAA_POR33S

C10

VAA_FAN33S

R3

VAA_XTAL33S

N8 P8

VDDIO33S_STBY_PLL VSSIO33S_STBY_PLL

M6 N6

VDDIO33S_25M_PLL VSSIO33S_25M_PLL

P5 R5

2

C4N25

4.7UF 10% 6.3V X5R 805

1

2

C4N8

4.7UF 10% 6.3V X5R 805

VAA_GP_PLL AVSS_GP_PLL VAA_100M_PLL_A AVSS_100M_PLL_A1 AVSS_100M_PLL_A0 VAA_100M_PLL_D AVSS_100M_PLL_D

2

.1UF 10% 6.3V X5R 402

N15 P15 R15 R12 P12 N7 M7

VDDC_25M_PLL VSSC_25M_PLL

N5 M5

VDDC_AUD_PLL VSSC_AUD_PLL

N4 P4

V_1P8STBY

E7

1

D6

VDDIO18S_100M_PLL5 VDDIO18S_100M_PLL4 VDDIO18S_100M_PLL3

N14 N13 P11

VDDIO18S_100M_PLL2 VSSIO18S_100M_PLL2

M10 N12

VDDIO18S_100M_PLL1 VSSIO18S_100M_PLL1

N9 N11

VDDIO18S_100M_PLL0 VSSIO18S_100M_PLL0

M9 N10

VDDIO18S_PIX_PLL VSSIO18S_PIX_PLL

L13 L12

1

C3C6

2

4.7UF 10% 6.3V X5R 805

2

C4P13

4.7UF 10% 6.3V X5R 805

1

2

C3N3

4.7UF 10% 6.3V X5R 805

V_1P8STBY

1

C4N18

R7 P7

X802478-003

V_3P3STBY

1

M12 M13

VDDC_STBY_PLL VSSC_STBY_PLL

VDD_DAC18S VAA_POR18S

VDDIO33S_AUD_PLL VSSIO33S_AUD_PLL

V_3P3STBY

1

VAA_VID_PLL AVSS_VID_PLL

1

2

C4N19

.1UF 10% 6.3V X5R 402

[PAG [PAGE_ E_TI TITL TLE= E=HA HANA NA,,

1

2

C4N20

.1UF 10% 6.3V X5R 402

1

2

C4N28

.1UF 10% 6.3V X5R 402

1

2

C4P8

.1UF 10% 6.3V X5R 402

1

2

C4N42 .1UF 10% 6.3V X5R 402

POWE POWER R + DECO DECOUP UPLI LING NG]]

2

C4N31

.1UF 10% 6.3V X5R 402

1

C4N17

1

.1UF 10%

2 6.3V X5R 402

2

C4P5 .1UF 10% 6.3V X5R 402

1

C4N34 .1UF 10%

6.3V 2 X5R 402

1

C4P6

1

.1UF 10%

2 6.3V X5R 402

2

C4N27

.1UF 10% 6.3V X5R 402

1

2

C4P11 .1UF 10% 6.3V X5R 402

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 3 30 0

1

2

C4P1 .1UF 10% 6.3V X5R 402

2008

1

2

C4P9

.1UF 10% 6.3V X5R 402

1

C4N26 .1UF 10%

2 6.3V X5R 402

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 30/83

REV A

CR-31

:

@JASPER_LIB.JASPER(SCH_1):PAGE31

HANA HANA,,

PO POWE WER R + DECO DECOUP UPLI LING NG

V_3P3STBY U4C2

4

o off

4

IC

V_1P8STBY

HANA E13 J4 J3 C3

V_3P3STBY

FB4N6 1

C4N3 4.7UF 10% 6.3V X5R 805

120 0.5A 0.2DCR

V_HANA_VDDIO_33S_AVCC

2

FB 603

F4 E4 F3 G4 G3 C2

1

2

C4N6 4.7UF 10% 6.3V X5R 805

1

C4N9 .1UF 10% 6.3V X5R 402

1

C4N10 .1UF

10% 6.3V X5R 402

2

2

C4N14 .1UF

10% 6.3V X5R 402

1

C4N13 .1UF 10%

2 6.3V X5R 402

G2 A1 E1 J1

E2 E3 J2

V_3P3STBY

1

2

G1 C1

C4N5

.1UF 10% 6.3V X5R 402

VSSIO_33S_AVSS8 VSSIO_33S_AVSS7 VSSIO_33S_AVSS6 VDDIO_33S_AVCC5 VDDIO_33S_AVCC4 VDDIO_33S_AVCC3 VDDIO_33S_AVCC2 VDDIO_33S_AVCC1 VDDIO_33S_AVCC0 VSSIO_33S_AVSS5 VSSIO_33S_AVSS4 VSSIO_33S_AVSS3 VSSIO_33S_AVSS2 VSSIO_33S_AVSS1 VSSIO_33S_AVSS0

H3

VDDIO_33S_PVDD1

D3

VDDIO_33S_PVCC0

H4 D4

VSSIO_33S_PVSS1 VSSIO_33S_PVSS0

C4N12

.1UF 10% 6.3V X5R 402

VDD33S3 VDD33S2 VDD33S1 VDD33S0

V_3P3STBY

FB4N7 1

C4N4

4.7UF 10% 6.3V X5R 805

120 0.2A 0.5 0.5 D CR

V_HANA_VDDIO_33S_PVCC0

2

FB 603

1

2

C4N7

4.7UF 10% 6.3V X5R 805

C4N11

.1UF 10% 6.3V X5R 402

FB4P1 VDD18S21 VDD18S20 VDD18S19 VDD18S18 VDD18S17 VDD18S16 VDD18S15 VDD18S14 VDD18S13 VDD18S12 VDD18S11 VDD18S10 VDD18S9 VDD18S8 VDD18S7 VDD18S6 VDD18S5 VDD18S4 VDD18S3 VDD18S2 VDD18S1 VDD18S0 VSS35 VSS34 VSS33 VSS32 VSS31 VSS30 VSS29 VSS28 VSS27 VSS26 VSS25 VSS24 VSS23 VSS22 VSS21 VSS20 VSS19 VSS18 VSS17 VSS16 VSS15 VSS14 VSS13 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 VSS0

L11 K11 G11 J10 H10 J9 H9 M8 L8 K8 G8

1

V_HANA_VDD18S

1

2

C4P4

.1UF 10% 6.3V X5R 402

1

FB 603

120 0.5A 0.2DCR

C4P3

2

1

4.7UF 10% 6.3V X5R 805

2

2

C3P1 4.7UF 10% 6.3V X5R 805

F8 L7

K7

G7 F7 J6 H6 J5 H5 E5 D5

1

C4N32 .1UF 10%

6.3V 2 X5R 402

1

C4N30 .1UF 10%

6.3V 2 X5R 402

1

C4N41 .1UF 10%

6.3V 2 X5R 402

1

C4N33 .1UF 10%

6.3V 2 X5R 402

1

C4N22 .1UF 10%

6.3V 2 X5R 402

1

C4P7 .1UF 10%

6.3V 2 X5R 402

1

C4N21 .1UF 10%

6.3V 2 X5R 402

J13 H13 G13 F13 D13 K12 M11 J11 H11 L10 K10 G10 F10 E10 L9 K9 G9 F9 J8 H8 E8 J7 H7

L6 K6 G6 F6 E6 L5 K5 G5 F5 C5 L4 C4 R1

X802478-003

[PAG [PAGE_ E_TI TITL TLE= E=HA HANA NA,,

PO POWE WER R + DE DECO COUP UPLI LING NG]]

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 3 30 0

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 31/83

REV A

CR-32

:

@JASPER_LIB.JASPER(SCH_1):PAGE32

POWER POW ER TR TRACE ACE DECO DECOUPLI UPLING NG V_12P0

V_12P0

1

C7G2

2

1

C4N40

2

1

10% 0.01UF 16V X7R 402

1

C9F2

C3N2

2

0.01UF 10% 16V X7R 402

10% 0.01UF 16V X7R 402

1

V_5P0STBY

C1N12

2

0.01UF 10% 16V X7R 402

2

1

10% 0.01UF 16V X7R 402

C1C7

2

0.01UF 10% 16V X7R 402

V_5P0DUAL

V_3P3STBY

1

C7B1

2

.1UF 10% 6.3V X5R 402

1

C6B1

2

1

C2F2

2

1

C2G1

C4A1

C3G3

1

2

1

C1C8

2

.1UF 10% 6.3V X5R 402

2

.1UF 10% 6.3V X5R 402

.1UF 10% 6.3V X5R 402

1

.1UF 10% 6.3V X5R 402

.1UF 10% 6.3V X5R 402

55

1

C7G16

2

.1UF 10% 6.3V X5R 402

2

1

.1UF 10% 6.3V X5R 402

C1F1

IN

V_VREG_V1P8V5P0

1

C4F13

2

0.01UF 10% 16V X7R 402

1

C5G1

2

10% 0.01UF 16V X7R 402

2

.1UF 10% 6.3V X5R 402

V_5P0 1

C9E2

2

1

0.01UF 10% 16V X7R 402 1

1

C9C7

2

0.01UF 10% 16V X7R 402 1

C1C15

0.01UF 10% 16V X7R 402

C7N1

2

10% 0.01UF 16V X7R 402

C3U3

C2T4

2

1

C5G3

2

1

.1UF 10% 6.3V X5R 402

C1B2

2

.1UF 10% 6.3V X5R

1

C6N1

C1C1

2

402 2

.1UF 10% 6.3V X5R 402

1

C1N13

1

2

.1UF 10% 6.3V X5R 402

2

2

C1D10

2

.1UF 10% 6.3V X5R 402

1

C1G1

2

.1UF 10% 6.3V X5R 402

C1B3

2

.1UF 10% 6.3V X5R 402

1

C1F2

2

.1UF 10% 6.3V X5R 402

C5N1

C4N1

C5N2

2

C3N1

2

.1UF 10% 6.3V X5R 402

C7N2

2

.1UF 10% 6.3V X5R 402

2

0.01UF 10% 16V X7R 402

1

2

.1UF 10% 6.3V X5R 402

1

1

C9N1

.1UF 10% 6.3V X5R 402

1 1

1

0.01UF 10% 16V X7R 402

2

.1UF 10% 6.3V X5R

402 1

C1C12

1 1

V_1P8 1

2

.1UF 10% 6.3V X5R 402

C5G5

.1UF 10% 6.3V X5R 402

2

.1UF 10% 6.3V X5R 402

1

1

.1UF 10% 6.3V X5R 402

1

2

C5V1

C1D8

.1UF 10% 6.3V X5R 402

2

10% 0.01UF 16V X7R 402

[PAG [PAGE_ E_TI TITL TLE= E=PO POW WER

TRAC TRACE E EMI EMI

CA CAPS PS]]

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 3 30 0

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 32/83

REV A

CR-35

:

@JASPER_LIB.JASPER(SCH_1):PAGE35

SB,

FLASH U2C1

58 58 58

42 42

SPI_CLK SPI_MOSI SPI_SS_N

IN IN IN

FLSH_DATA

BI

7

6 5

FLSH_WP_N

OUT

4 3

V_3P3STBY

2

2

42

IN

R1P7

2.2K 402

FLSH_READY

1

1

0

5%

FT2P22 FT2P23

FTP FTP

1 1

USBPORTA3_DP USBPORTA3_DN

FT2P20 FT2P21

FTP FTP

1 1

USBPORTA2_DP USBPORTA2_DN

SPI_CLK SPI_MOSI SPI_SS_N*

Y2 AA2 Y3

FLSH_DATA7 FLSH_DATA6 FLSH_DATA5

AA3 AB3 Y4 AA4 AB4

FLSH_DATA4 FLSH_DATA3 FLSH_DATA2 FLSH_DATA1 FLSH_DATA0

W18 Y18 AA17 AB17

46 46

BI BI

GAMEPORT2_DP GAMEPORT2_DN

46

BI

GAMEPORT1_DP GAMEPORT1_DN

46

BI

W16 Y16

AA15 AB15 W12

      S       A       I       B       R _       B       S       U _       B       S

3

o off

SB VE VERSI RSION

U3 Y5 AA5

Y1 V1

CH

+ USB + SPI

IC

6 106 SPI_MISO

AB5

R1R1

2

SPI_MISO_R

33

402

1

SPI_MISO

W1

FLSH_CLE

OUT

42

FLSH_CE_N*

V3

FLSH_CE_N

OUT

42

FLSH_RE_N*

V2

FLSH_RE_N

OUT

42

FLSH_WE_N*

W3

FLSH_WE_N

OUT

42

FLSH_ALE

W2

FLSH_ALE

OUT

42

FLSH_CLE

FLSH_WP_N* FLSH_READY

USBA_D3_DP USBA_D3_DN

USBB_D4_DP USBB_D4_DN

Y10 W10

ARGONPORT_DP ARGONPORT_DN

BI BI

USBA_D2_DP USBA_D2_DN

USBB_D3_DP USBB_D3_DN

Y8 W8

MEMPORT1_DP MEMPORT1_DN

BI BI

46 46

USBA_D1_DP USBA_D1_DN

USBB_D2_DP USBB_D2_DN

AB7 AA7

EXPPORT_DP EXPPORT_DN

BI BI

45 45

USBA_D0_DP

USBB_D1_DP

AB9 AA9

MEMPORT2_DP MEMPORT2_DN

BI

46

USBA_D0_DN

USBB_D1_DN

AB11 AA11

MEMPORT3_DP MEMPORT3_DN

BI BI BI

46

USB_RBIAS

USBB_D0_DP USBB_D0_DN

OUT

5% CH

58

49 49

62 62

X02047-012

1

1

2

[PAGE_TITLE=SB,

FLASH

R2P14

C2P40 .1UF 10% 6.3V EMPTY 402

+ USB USB + S P PII]

113

1% CH

2

402

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 3 32 2

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 35/83

REV A

CR-36

:

@JASPER_LIB.JASPER(SCH_1):PAGE36

SB,

40

39

IN

R1B9

MII_TX_CLK 33

39

IN

+ SATA

MII_TX_CLK_R

U2C1

R1B10

MII_RX_CLK

+ AUDIO

5% CH

402

40

ETHERNET

33

MII_RX_CLK_R

5%

B3 C3

CH

402

IN IN IN IN

MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0

D1

IN IN

MII_RXDV MII_RXER

C2

39

40 39 40 39 40 39

IN IN BI

MII_COL MII_CRS MII_MDIO

B5

40 40 40 40

39

40 40

39

27

39 39 39

D2 D3 C1

B2

A5 E1

o off

MII_TX_CLK MII_RX_CLK MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0 MII_RXDV MII_RXER

R1C3

MII_MDC_CLK_OUT_R

IC

6

33

402

106 MII_MDC_CLK_OUT

MII_MDC_CLK_OUT

A8

E2

MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0

C5 A4 B4 C4

MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0

MII_TXEN

A3

MII_TXEN

OUT OUT OUT OUT

39 40 39 40 39 40 39 40

OUT

39 40

MII_COL MII_CRS MII_MDIO

AUD_CLK

R2B11 47

R2B14 I2S_MCLK_OUT I2S_BCLK_OUT I2S_SD I2S_WS SPDIF

C7

I2S_MCLK_R

B8

I2S_BCLK_R

A7

I2S_SD_R

B7

I2S_WS_R

C6

SPDIF_R

IN IN

HDD_RX_DP HDD_RX_DN

47

47

48 48

IN IN

ODD_RX_DP ODD_RX_DN

R2 P2

HDD_TX_DP HDD_TX_DN

OUT OUT

48 48

SATA0_RX_DP SATA0_RX_DN

SATA0_TX_DP SATA0_TX_DN

N1

M3

ODD_TX_DP ODD_TX_DN

OUT OUT

48 48

U2

SATA_RBIAS

P4 L3

SATA_RBIAS

5% CH

2

R1C8

C1C9

.1UF 10% 6.3V X5R 402

X02047-012

374

1

CH

1

402

1

10K 402

[PAGE AGE_TITLE=SB,

ETHERNET + AUD AUDIO

+ SA SAT TA]

CH

OUT

41

OUT

28 41

I2S_SD

OUT

28 41

I2S_WS

OUT

28 41

OUT

28

5% CH

R2B15 2

1

I2S_MCLK I2S_BCLK

5%

SB_SPDIF_OUT

5% CH

R2N12 2

10K 402

5% CH

R2N11

2

5% CH

R2N10 2

10K 402

1%

2

1

10K 402

1

1

M1

402

47 402

SATA1_TX_DP SATA1_TX_DN

R2B13

R2B12

SATA1_RX_DP SATA1_RX_DN

N4

402

5% CH

402

402

48 48

39 40

OUT

5% CH

47

AUD_CLK

IN

4

SB VERSION

5% CH

R1B3

2

5%

CH

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 3 33 3

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 36/83

REV A

CR-37

:

@JASPER_LIB.JASPER(SCH_1):PAGE37

SB SB,,

ST STAN ANDB DBY Y PO POWE WER R + DECO DECOUP UPLI LING NG 5

U2C1

of of

FB2P4

1

120 0.2A 0.5 0.5 D CR

C2R5

4.7UF 10% 6.3V X5R 805

2

V_AVDD_USB

FB 603

V_AVSS_USB

1

C2P47

2.2UF 10% 6.3V X5R 603

2 ST2P3

1

2

1

2

C2P43

V_CMPAVDD18_USB

.1UF 10% 6.3V X5R 402

V_CMPAVSS18_USB V_VDD18_USB

SHORT

0.5 0.5

120 0.2A D CR

FB 603

1

2 ST2P2

1

Y13 W13

CMPAVDD18_USB CMPAVSS18_USB VDD18_USB VDD18_USB VDD18_USB VDD18_USB VDD18_USB VDD18_USB VDD18_USB VDD18_USB VDD18_USB VDD18_USB

Y6 W6 V6

2

2

1

C2P46

2.2UF 10% 6.3V X5R 603

2

C2P42

.1UF 10% 6.3V X5R 402

V_CMPAVSS33_USB V_VDD33_USB

SHORT

AVDD_USB AVSS_USB

V13 V12 V11 V10 V9 V8 V7

FB2P3 1

AB13 AA13

Y14 W14

CMPAVDD33_USB CMPAVSS33_USB

V17 V16 V15 V14

VDD33_USB VDD33_USB VDD33_USB VDD33_USB

FB2R1

1

1

C2R3

2

FB 603

120 0.5A 0.2DCR

1

4.7UF 10% 6.3V X5R 805

C2P45

10UF 20% 6.3V X5R 805

2

1

2

C2P41

.1UF 10% 6.3V X5R 402

1

2

C2P2 .1UF 10% 6.3V X5R 402

1

2

C2P3 .1UF 10% 6.3V X5R 402

V_3P3STBY 37

FB2P5

1

C2R6

0.5 0.5

FB 603

1

2 1

VDD33_AUX VDD33_AUX VDD33_AUX VDD33_AUX VDD33_AUX VDD33_AUX VDD33_AUX VDD33_AUX VDD33_AUX VDD33_AUX VDD33_AUX VDD33_AUX VDD33_AUX VDD33_AUX VDD33_AUX VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB

J18 H18 G18 J15 H15 R14 H14 R12 P12 R9

V19 D19 V18 F18 E18 E17 D17 E16 E15

S B B AL AL L LS S V1 18 8 AN D V V1 1 9 AR E I N T HE HE LO LOWE WER R RIGHT RIGHT HA HAND ND OF TH THE E CHIP CHIP THE THEY Y HAV HAVE E BEE BEEN N ISOL ISOLATE ATED D FOR BET BETTER TER POW POWER ER ROUTING ROUTING V_CMPAVDD33_USB

37

IN

V_3P3STBY

W5 V5 U5 W4 V4 U4

Y19 W19 AB18 AA18 Y17 W17 AB16 AA16 Y15 W15 AB14 AA14 AB12 AA12 Y11 W11 AB10 AA10

V_1P8STBY

1

Y9

2

W9

AB8 AA8

C2P38

.1UF 10% 6.3V X5R 402

C2P37 .1UF 10% 6.3V X5R 402

C2P23

.1UF 10% 6.3V X5R 402

C2P24

.1UF 10% 6.3V X5R 402

Y7 W7

AB6 AA6

X02047-012

V_3P3STBY

2

120 0.2A D CR

4.7UF 10% 6.3V X5R 805

V_CMPAVDD33_USB

OUT

V_1P8STBY

IC

106 VDD18_AUX VDD18_AUX VDD18_AUX VDD18_AUX VDD18_AUX VDD18_AUX VDD18_AUX VDD18_AUX VDD18_AUX VDD18_AUX

V_1P8STBY

2

6

SB VERSI VERSION

ST2P4

2

C2P48

2.2UF 10% 6.3V X5R 603

1

2

C2P44

.1UF 10% 6.3V X5R 402

1

2

C2P6

C2N1

.1UF 10% 6.3V X5R 402

.1UF 10% 6.3V X5R 402

C2P5

.1UF 10% 6.3V X5R 402

SHORT

FB2P1 1

C2P8

120 0.2A 0.5 D CR

4.7UF 10% 6.3V X5R 805

[P [PAG AGE_ E_TI TITL TLE= E=SB SB,,

2

FB 603

1

2

C2P34

2.2UF 10% 6.3V X5R 603

1

2

C2P35

.1UF 10% 6.3V X5R 402

ST STAN ANDB DBY Y PO POWE WER R + DECO DECOUP UPLI LING NG]]

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 3 33 3

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 37/83

REV A

CR-39

:

@JASPER_LIB.JASPER(SCH_1):PAGE39

N: N:

123 123.8 .8 OH OHM M TE TERM RMINA INATIO TION N REQUI REQUIRE RED D FO FOR R IC ICS S 100 OH OHM M TE TERM RMINA INATI TION ON RE REQUI QUIRE RED D FO FOR R BROADCO BROADCOM M ENET_RX_DP

40

BI

45

1 39

R1A4

V_ENET

IN

61.9 1%

1

R1B7

2

5% CH 402

1

CH 402

1K

27

ENET_CLK

IN

2 IC

U1B2

47

33

IN

36 36

10K 5%

36

CH

40 40 40 40

36

402

1

40 40 40

36

R1C1

36 36 36

40

MII_MDC_CLK_OUT

36

IN

2

V_ENET

R1B11

1

36 36

1% CH

1.5K

MII_RX_CLK MII_RXDV MII_RXER

OUT OUT OUT OUT

MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0

IN IN IN IN

36 39

OUT OUT OUT

OUT IN

36

IN

46

ENET_REF_CLK_OUT

ENET_RST_N 2

36

1

36

36 36

40 40

30 31 37 38

TXCLK TXEN

MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0

42

TXD TXD TXD TXD

41 40

39

MII_COL MII_CRS ENET_AMDIX_EN

R1N4

100 402 39

IN

V_ENET

2

R1N1

9.53K 402

RXD RXD RXD RXD

MII_TX_CLK MII_TXEN

48 45

VDD VDD VDD VDD VDD VDD VDD VDD

33 14

MDC MDIO

43 44

COL CRS

10

AMDIX_EN

20 19

2

2

R1A3

1%

CH

CH 402

13

ENET_RX_DN

BI

40 45

16

ENET_TX_DP

BI

40 45

15

8 6 4

1

R1A1 61.9

3

ENET_P2LI_R

1

21

1

17

11 5 2

1

ENET_TX_DP_R

CH

1

R1M2

ENET_LINK_N

CH

2

10K 5%

402

402

ETHER ETHERNET NET

I S F OR OR OU OU T TP P UT OF CO CONN NNEC ECTIO TION N

40 45

2

R1B5

R1N5

1K

10K 5%

5%

CH

CH

CH

402

402

402

2

0

OUT

1

1

CH 402

R1B4

2

R1N6

10K 5%

1

2

     D      R      4      P _      T      E      N      E

     D      T      3      P _      T      E      N      E

     L      C      1      P _      T      E      N      E

36

25

1%

45

OUT

1

9

R1N7

10/ 1 10 00 PI N IND INDICA ICATIO TION N

402

1

CH 402

12

2

ENET_10_100_OUT

5% CH 603 ENET_TX_DN_R

1

R1A2

61.9

EMPTY FOR BROADCO BROADCOM M ST STUF UFF F FO FOR R ICS ICS

AMD AMDIX_ IX_EN EN HAS INTERNA INTERNAL L PULLUP PULLUP AU AUTO TO MDIX MDIX IS ON B BY Y DE DEFA FAULT ULT

2K

1%

1

1%

45

TP_BP TP_BN

2

R1N3

1.58K

40

OUT

2

X800188-002

ENET_RX_DN_R

1

61.9

ENET_ACT_N

100TCSR 10TCSR

DB1N3

R1N2

             2

TP_AP TP_AN

VSS VSS VSS VSS VSS VSS VSS

2

2

1%

EMPTY 402

18

ENET_10BIAS

1% CH

332

10K 5% CH 402

10K 5%

ENET_100BIAS

5% CH 603

7

P4RD P3TD P2LI P1CL P0AC

1

5% EMPTY

1

27 26

STU STUFF FF FOR BROADCOM EMPT EMPTY Y FO FOR R ICS R1B13

                   1

24 22

10/100

OUT OUT

2

RXCLK RXDV RXER

29

MII_MDIO

BI

34 32 35 28

402

40

RESET_N*

0

45

OUT

R1B6

REF_IN REF_OUT

23

R1M1 ENET_POAC_R

1

ICS1893BF

DB1N4

ENET_RX_DP_R

1%

2

CH 402

ENET_TX_DN

SP SPEE EED D

BI

40

45

ADDRESS="0 ADDRESS="00001 0001""

V_3P3 FB1B1

1

60 0.5A 1

C1A5

100UF 20% 16V

ELEC 2 RDL

[P [PA AGE_ E_T TITLE=SB

OUT,

V_ENET

2

0.1DCR 603

2 1

C1B1

10UF 20% 6.3V X5R 805

ETH ETHERN ERNET (IC (ICS

C1N1

.1UF 10% 6.3V X5R 402

PHY)]

C1N4 .1UF 10% 6.3V X5R 402

C1N5 .1UF 10% 6.3V X5R 402

C1N3 .1UF 10% 6.3V X5R 402

C1N9

.1UF 10% 6.3V X5R 402

C1N11 .1UF 10% 6.3V X5R 402

C1N2

.1UF 10% 6.3V X5R 402

OUT

39 4 0

45

C1N10 .1UF 10% 6.3V X5R 402

DRAWING JASPER_FAB_B Wed J Ju ul 30 1 13 3: 1 17 7: 3 33 3

20 00 08

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 39/83

REV A

CR-40

:

@JASPER_LIB.JASPER(SCH_1):PAGE40

BD BDCM CM PHY PHY V_1P8 FB1N1 2

1

2

27

DB1N1 IN

V_ENET

33

1

R1B12

4.7K 5% EMPTY

39

OUT

39

36

39

36

39

36

39

36 36

2 402 36

36

MII_RXD0

36

39 39

39 36 36 36 36

36 36

40

U1B1

ENET_REF_CLK2_OUT

36

39

36

39

RESET_N

OUT OUT OUT

MII_RX_CLK MII_RXDV MII_RXER

20

RXC RX_DV/TEST0 RX_ER/TEST1

OUT OUT OUT

MII_RXD3

15 16 17 18

OUT IN

MII_RXD2 MII_RXD1

23 24

TXC TX_EN

28

TXD3 TXD2 TXD1 TXD0

26 25 14 13

OUT OUT

29

MII_COL MII_CRS

30

31

32

ENET_AVDD

ET ETHE HERN RNET ET (BDC (BDCM M

PH PHY) Y)]]

EMPTY

RXD2/F100 RXD1/ANEN RXD0/PHYAD0

MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0

27

40

.1UF 10% 6.3V EMPTY 402

OVDD2 OVDD1

RXD3/ISOLATE

MII_TX_CLK MII_TXEN

2

OU OUT, T,

19 21

2

OUT

C1N14

BCM5241

10

1

[PAG [PAGE_ E_TI TITL TLE= E=SB SB

2

1

XTALI2 XTALO2

ENET_RST_N

MII_MDC_CLK_OUT MII_MDIO

IN

BI

IN

1

805

IN

IN IN IN IN

36

39

C1N7

6.3V 2 EMPTY

4.7UF 10% 6.3V EMPTY 805

1

39

1

10UF 20%

C1N8

ENET_CLK

IN

ENET_AVDD

1

EMPTY 603

60 0.5A 0.1DCR

MDC_CLK_OUT MDIO

22

V_ENET

9

IN

39

7

IN

ENET_AVDD

AVDD LINK# ACT#

12

11 3

OUT OUT

39 45

39 45

TDP TDN

4

ENET_RX_DP ENET_RX_DN

OUT OUT

RDP RDN

6 5

ENET_TX_DP ENET_TX_DN

OUT OUT

RDAC

8

GND

40

ENET_LINK_N ENET_ACT_N

39 45

39 45 39 45 39 45

     C      A      D      R _      T      E      N      E

33

COL/ENERGYDET CRS/LOWPWR0 1

REGVDDIN REGVDDOUT

R1N8 1.27K

C1N6

.1UF 10% 6.3V EMPTY 402

1%

X801554-002

LCC32

EMPTY

2

402

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 3 34 4

MICROSOFT 2008

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 40/83

REV A

CR-41

:

@JASPER_LIB.JASPER(SCH_1):PAGE41

V_12P0

AUDIO

V_3P3 R2B1

1 0

1

R2B6

1 0

603

FTP

FT2N1

2

C2A7

2

4.7UF 10% 16V X5R 1206

AUD_VDD

5%

CH

1

2

C2B11

4.7UF 10% 6.3V X5R 805

1

C2B5

2

10UF

FB2B2

1

AUD_CLAMP_R

1K

2

0.7DCR 603

0.2A

2

R2B5

0.1UF 10% 25V X7R 603

1

1

5% CH

402

AUD_AC_R

C2B7

10K 5% CH

.1UF 10% 6.3V X5R 402

                                           1

1

PGB0010603

402

2

603 EG2B2 X801161-001 EMPTY

IC

U2B1

1K

2

20% 16V TANT 1206

AUD_VAA

5% CH

603

FTP FT2M1

R2B3

2

C2B10

1

1

C2B3 470PF 5% 50V X7R 402

XDAC

36

IN IN IN IN

36

FT2N2 33

IN

FTP

36

1

36

I2S_MCLK I2S_BCLK I2S_SD I2S_WS

             2

14

DVDD

13

MCLK BCLK SD WS

4 3

2 5

AUD_RST_N

NC PDN DVREF

12

11

AUD_DCAP

1

R2N3 1K

5% CH

2

402

C2B1

10UF 20% 6.3V X5R 805

C2B6

.1UF 10% 6.3V X5R 402

1

AVDD

9

VOUTR VOUTL

6

AUD_VOUTR

10

AUD_VOUTL

AVREF

8

AGND

AUD_R_OUT

OUT

44

AUD_L_OUT

OUT

44

AUD_ACAP

7

C2B4 .1UF 10% 6.3V X5R 402

DGND

X02238-003

C2B8

10UF 20% 6.3V X5R 805

                                           1

PGB0010603 603 EG2B1 X801161-001 EMPTY

2

R2B4 10K 5%

2

CH              2

1

402 1

470PF C2B2 5% 50V X7R 402

AUDIO

C2B9 10UF 1 2

AUD_AC_L

20% 16V TANT 1206

R2B2

2 1K

402

FTP

FT2P1

1

1

FB2B1 AUD_CLAMP_L

5% CH

CR2M2 MBT3904

34

AUD_CLAMP

IN

2

3

AUD_CLAMP_C

Q2N1

1

V_3P3STBY 1

MMBT3906 XSTR

R2N23 2

4.7K 402

5% CH

R2N2

2 1K

402

1

AUD_CLAMP_B2

1

1K

0.2A

3

2

0.7DCR 603

6 2

5

AUD_CLAMP_B3

R2N1

2 1K

5% CH

4

1

402

XSTR

1

5% CH

AUD_CLAMP_B1

1

R2N22 1K

5% CH

2

[PAG [PAGE E_T _TIT ITLE LE=S =SB B

OUT OUT,

AUDIO UDIO]]

402

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 3 34 4

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 41/83

REV A

CR-42

:

@JASPER_LIB.JASPER(SCH_1):PAGE42

XSB SOUTHBRIDG BRIDGE E FLSH_DATA0 0 1

     1      A      T      A      D 0 _      H 1      S      L      F

8MB

16MB

32MB

64MB

N: N:

PSB SOUTHBRIDGE BRIDGE

RET RETAIL AIL=16M =16MB B XDK XDK=64 =64MB MB

FLSH_ DA DATA[ 1 1::0 ] 0X0 0X1 0X2 0X3

FLASH CONFI G GU UR A AT TI O ON N 0.5KB, 16KB BLOCKS, 16MB 0.5KB, 16KB BLOCKS, 16MB 2KB, 12 128KB BLOCKS, V VA ARIOUS SIZES 4KB, 25 256KB BLOCKS, V VA ARIOUS SIZES

RETAIL XDK

V_3P3STBY

1

1

FT1R3 FT1R4 FT1R5 FT2R3 FT2R4 FT2R5 FT2R6 FT2R7 35

IN

1 1 1 1 1 1 1 1

FLSH_DATA

2

10K 5% EMPTY 402

1

R2D6

R2D7

FTP FTP FTP FTP FTP FTP FTP FTP

2

10K 5% CH 402

1

R1E2 10K 5%

2

CH

402

2

1

C2E6

4.7UF 10% 6.3V X5R 805

2

1

C2E5

.1UF 10% 6.3V X5R 402

2

N: N:

C2R11 .1UF 10% 6.3V X5R 402

ST STUFF UFFED ED AT CONFIG CONFIG LE LEVE VEL L UP UPDA DATE TE TO RECEN RECENT T PA PART RT NO NO# #

IC

U2E1 NAND FLASH RDY

1

37 FTP

FT1T1

12

7

44

6 5 4

43

3 1

32 31 30

0

29

42 41

2

35 35

10K 5% CH

402

2

10K 5% EMPTY 402

1

R2D4

R2D5

R2D8

2

1

1

1

10K 5% CH

2

402

1

2

10K 5% CH 402

1

R2D1

R2D3

2

10K 5% CH 402

1

R1D4 10K 5%

2

1

R1D3 10K 5%

CH

CH

402

402

2

35

R1D2

2

10K 5% CH 402

35 35 35

IN IN IN IN IN IN

FLSH_CE_N FLSH_RE_N FLSH_WE_N FLSH_WP_N FLSH_ALE FLSH_CLE

9 8 18 19

17 16

6 36 13

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

VCC1 VCC0 DATA DATA DATA DATA DATA DATA DATA DATA CE_N* RE_N* WE_N* WP_N* ALE CLE VSS/NC VSS1 VSS0

X802184-001

[PAG [PAGE_ E_TI TITL TLE= E=SB SB

OUT, OUT,

FL FLAS ASH] H]

FLSH_READY

7 38

FLSH_NC38

R2D2

2

48

0

47

402

OUT

35

1

5% EMPTY

46 45 40 39 35 34 33

28 27

26 25 24 23 22 21

20 15 14

11 10

5 4 3

2 1

TSOP

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 3 35 5

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 42/83

REV A

CR-43

:

@JASPER_LIB.JASPER(SCH_1):PAGE43

V_3P3STBY BIN BINDIN DING G

BUTTON BUTTON

FAN CONTRO CONTROL L 1

TH

V_12P0 R5V3

SWITCH

SW5G1 THR

2

4

1

3

2

10K 5% CH 402

R5V2

2

BINDSW_N_R

10K 402

1

OUT

34

FAN1_Q1_C

IN

FAN1_OUT

2

R1G4

SW1G1 THR

2

1

10K 5% CH 402

3

MMBT2222 XSTR

     E _      1      Q _      1      N      A      F

2 1

SWITCH

MJD210 XSTR

3

Q3M2

1

V_3P3STBY

TH

Q3M1

1

3

CH

28

BUT BUTTON TON

1

1% CH 2

BINDSW_N

5%

X02246-002

ODD EJECT EJECT

R3M9

2 5.11K 402

2700PF C4P14 10% 50V X7R 402

1

J3A2 1X3HDR

2

1

3

2

100 5%

R1G3

2

EJECTSW_N_R

10K 402

1

EJECTSW_N

34 48

OUT

5%

CH

X02246-002

     R _      K      B      D      F _      1      N      A      F

1

402

1UF 10% 16V X7R 603

1

30.1K

1%

R4P2

1

2

402

FAN1_FDBK

1% CH

R2G2

10K 5% CH 402

R2G3

2 10K 402

1

TILTSW_N

OUT

5%

43

SWIT SWITCH CH,,

34

1

TILTSW_N_R

1

V_3P3STBY

V_IR

X815684-001 EMPTY

TILT

X800550-004

MODU MODULE LE

CO COMU MUS S

SW2G5

2

2

1%

402

CH

SM SW2G2 SM

R2V1

11K

CH

2

IR TILT TILT

28

R3A2 N: X8 X800 0055 5500-00 003 3 HOLD HOLDS S ALL ALL TH THRE REE E TILT TILT SWIT SWITCH CHES ES TM TMEC EC ONLY ONLY HA HAS S 3 PI PINS NS WHI WHICH CH RE REQU QUIRE IRES S A DIF DIFFE FERE RENT NT UN UNIQU IQUE E PA PART RT NU NUMB MBER ER TO HO HOLD LD TH THE E SY SYMB MBOL OL NAME NAME N: BO BOM M MU MUST ST C CAL ALL L OUT OUT X8 X800 0055 5500-00 003 3 WI WITH TH QTY QTY 1 AN AND D LIS LIST T AL ALL L TH THRE REE E RE REF F DES. FA FACT CTORY ORY CHO CHOOS OSES ES FROM FROM THE THERE RE

1

SOLI SOLICO CO

OUT

1

V_3P3STBY

SW SWITC ITCH, H,

CONN

CH

2

2

2 3

C3A9

R3A7

5.11K 402

TIL TILT T

1

V_FAN1

R3M8 CH

4

D3A1 1N4148 SOT23 DIO

1

49.9 402

C2V1

2

4.7UF 10% 6.3V X5R 805

SM IC

U1G1

1

2

1%

CH

2

C2V2

R2N7

.1UF 10% 6.3V X5R 402

10K 5% CH

1

402

IR

TILT

SWITCH, SWITCH,

X815685-001 EMPTY

SW2G4 1

TILT

[PAG [PAGE_ E_TI TITL TLE= E=CO CONN NN,,

SIGNAL SIGNALQUE QUEST ST

VCC DATA GND ME2 ME1

3 1

IR_DATA

2 5 4

OUT

34

X803473-002

2 SM

FA FAN N + IN INFR FRAR ARED ED

+ SWIT SWITC CHES] HES]

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 3 35 5

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 43/83

REV A

CR-44

28

:

@JASPER_LIB.JASPER(SCH_1):PAGE44

1

VID_DACA_DP

IN

      9       O       I      3       9       6       D       V       3       A       T       B       O       S

             6

      2       A       3       R       C

V_3P3

.27UH 0.45A NA

1

R3A4

1

75 1%

                                           1

OUT

1

2

1.1A 0.21DCR

C3A3

75PF 5% 50V NPO 402

28

IN

1

VID_DACB_DP

C2A6

      S       3       9       2       9       T       V       O       I      O       A       D       S       B

      9       O       I      3       9       6       D       V       3       A       T

                   3

      2       A       3       R       C

V_3P3

.27UH 0.45A NA

1

      B       O       S

R3A3 75

1

62PF 5%

             5

C3A2 44

44

44

VID_DACC_DP

IN

V_3P3

.27UH 0.45A NA

      9       O       3       I       9       6       D       V       3       A 1       T       B       O       S

             6

      1       A       3       R       C

R3A6 75

1

                                           1

CH 402

2

1

62PF 5% 50V NPO 402

2

                   1

44

OUT

      8       A       2       R

IND 1210

C3A4

1%

             2

VID_DACC_OUT

2

44

      H       %       1       C

44

      K       2       2       0       8       4              2 .       1

C3A1

75PF 5% 50V NPO 402

33

33

1

WSS_CNTL1

IN

5.36K 402

WSS_CNTL0

IN

1

4.75K 402

R2A6

VID_DACD_DP

IN

1% CH

4

                   3

V_3P3

      1       A       3       R       C              5

      9 1       O       I      3       9       6       D       V       3       A       T       B       O       S

R3A9 75

2

CH 402

1

.27UH 0.45A NA

                   1

IND 1210

2

C3A7

1%

2

44

OUT

62PF 5% 50V NPO 402

1

             4

IN

R3M3 2

1

VID_VSYNC_OUT_R

49.9 402

1% CH

33

44

SCART_RGB

IN

1

             5

             4

28

2

IN

R3M2 2

1

49.9 402       9       O       I       9       D       V       A       B

             6

V_3P3STBY

      2       M       3

1% CH

B

N/A

PB

PB

B

CVBS(COMP)

CVBS

N/A

CVBS

CVBS

VID_DACB_OUT VID_DACB_RET

IN

VID_DACC_OUT VID_DACC_RET

IN

VID_DACD_OUT

IN

VID_HSYNC_OUT

11 9

VID_HSYNC_OUT VID_HSYNC_RET

IN

VID_VSYNC_OUT

12 10

VID_VSYNC_OUT VID_VSYNC_RET

25

SPDIF

7

VID_DACD_OUT VID_DACD_RET

5

AUD_R_OUT AUD_R_RET

41

IN

AUD_L_OUT

16 14

AUD_L_OUT AUD_L_RET

R2A5

2 1K

402       H       %

      2       1       0       0       3       4

      2       K       0       0       1       4

1

WSS_CNTL_OUT

5%

2 1

1

VID_HSYNC_OUT

                   1

OUT

      H       %       5       C

      0       1       M       2       R              2

      2       K       0       0       4 1

HDMI_DDC_CLK HDMI_DDC_DATA

28 24 20

AV_MODE2 AV_MODE1 AV_MODE0

OUT

58 34 44

BI

28 34 29 28 34 29

BI

OUT OUT OUT

34 44 34 44 34 44

34 33 32

31

MTGB MTGA

TH

V_3P3STBY

44 44 44 44

IN IN IN IN

EXT_PWR_ON_N AV_MODE2 AV_MODE1 AV_MODE0

1

R2M9 2

402

5% CH

2

1

2

2

C2M4

0.01UF 10% 16V X7R 402

10K 5% CH 402

C2A3

470PF 5% 50V X7R 402

1

R2M6

R2A1

58

1

1

1

3

44

23

18

SHIELD SHIELD SHIELD SHIELD

     T      U      O _      B      G      R _      T      R      A      C      S

MMBT3906 XSTR

CH

EXT_PWR_ON_N

26 22

GND GND GND

X806743-001

75PF 5% 50V NPO 402

Q2N3

1

AV_MODE2 AV_MODE1 AV_MODE0

30 21

WSS_CNTL SCART_RGB

19

C2A8

2

SCART_RGB_R

5%

17

DDC_CLK DDC_DATA

CH

      4       5      C       A       2       R

                   1

CONNECTOR

EXT_PWR_ON

15 13

XSTR

      H       %       1       C

CONN

8 6

AUD_R_OUT

             2

R2N19

10K 402

VID_HSYNC_OUT_R

N/A

CVBS(COMP)

VID_DACC_OUT

33

      9       O       3       I       9       6       D       V       3       A       T       B       O       S

C D

IN

SCART_RGB_OUT_R

      2       M       3       R       C

R

IN

WSS_CNTL_OUT_R

                   3

V_3P3STBY

G

R

VID_DACA_OUT VID_DACA_RET

75PF 5% 50V NPO 402

OUT

G

PR

3 1

C3A8

VID_VSYNC_OUT

Y

PR

4 2

V_3P3

28

Y

C(CHROMA)

41

2

      9       A       2       R

VID_DACD_OUT

Y(LUMA)

VID_DACA_OUT

2

             2

28

N/A

VID_DACB_OUT

6

3

MBT3904

WSS_CNTL_E

L3A4 2 1

VGA

N/A

XENON AVIP V_AVIP V_AVIP_RET

WSS_CNTL_B

CR2A1 5

R2A7

44

2

1% CH

SCART

HDTV

A

IN

402

L3A1 2 1

SDTV

B

J3A1

29 27

V_12P0

28

470PF 5% 50V X7R 402

                                           1

50V 2 NPO

402

             4

             2

75PF 5%

50V 2 NPO

C2A1

C2M5

4.7UF 10% 6.3V X5R 805

V_3P3 1

ADVANCED

      1       A       2       D

44

OUT

IND 1210

C3A5

1% CH

402

2

VID_DACB_OUT

STANDARD

                   3

402

L3A2 2

1

2 22PF 5%

IN

THRMSTR 1206

V_AVIP

HANA_SPDIF_OUT 1

29

DAC RT2M1 2 1

2 50V NPO 28

OUT

V_5P0

44

IND 1210

C3A6

2

402

2

VID_DACA_OUT

62PF 5% 50V NPO 402

CH

             2

L3A3 2

2

1

10K 5% CH 402

C2M3

470PF 5%

2 50V X7R

LAY LAYOUT OUT:PLA :PLACE CE

402

1

R2M4

2

1

10K 5% CH 402

C2M2

R2N20

2

1

470PF 5%

2 50V X7R 402

2

10K 5% CH 402

C2N3

470PF 5% 50V X7R 402

CLO CLOSE SE TO CON CONNECT NECTOR OR EMI EMI CAPS CAPS

      R       C              2

[PA [PAGE_ E_T TITLE ITLE=[ =[C CONN,

AVIP VIP]

                                           1

DRAWING JASPER_FABA We ed d Ju ull 30 1 3 3:: 1 17 7 ::3 37

MICROSOFT 2008

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 44/83

REV A

CR-45

:

@JASPER_LIB.JASPER(SCH_1):PAGE45

V_5P0DUAL RT1B1 45

2

V_EXPPORT

IN

L1B1 35

35

BI BI

EXPPORT_DN

1

EXPPORT_DP

4

THRMSTR 1206

5%

220UF 20% 10V

2 1

C1A3

470PF 5% 50V X7R 402

2 1

1

C1M2

4.7UF 10% 6.3V X5R 805

OUT

45

FTP FT1N2

1

NA SM EMPTY

BAV99 SOT23S DIO

2

EXPPORT_DN_CM

3

EXPPORT_DP_CM

D1A1

X801560-001

2

PGB0010603 603

                                           1

R1B1

                                           1

EG1A2

3

0

C2A4

ELEC 2 RDL

3

CH

CMCHOKE

603

1

2

R1B2 0

603

V_EXPPORT

1

1.1A 0.21DCR

D1A2

EG1A1 EMPTY

EMPTY

1

PGB0010603 603

5%

CH

BAV99 SOT23S DIO

             2

             2

J1A1

CONN

XENON RJ45/ RJ45/USB USB

IN

ARGON_NTX D1B1

V_EXPPORT

45

2

5% 470PF 50V X7R 402

1

39

40

1

IN

V_ENET

39 39

BAV99 SOT23S DIO 39

VBUS DD+ GND

16

OMNI

C1A4

2

IN 3

12 13 14 15

0

402

0

402

1

ENET_LINK_N

2

IN IN

ENET_POAC_R

3

11

ENET_TX_CT

10 7

XFMER2_P XFMER2_C XFMER2_N

9 6 5

XFMER1_P XFMER1_C XFMER1_N

8

CAP

ENET_ACT_N

39

2

40

39

IN

ENET_TX_DP

5% EMPTY

40

39

IN

ENET_TX_DN

2

40

39

IN

ENET_RX_DP

5% EMPTY

40

39

IN

ENET_RX_DN

R1A5

1

ENET_P2LI_R

40

R1M3

1

IN IN

4

ENET_RX_CT

C1M1 .1UF 10% 6.3V X5R 402

C1A2

.1UF 10% 6.3V X5R 402

20 19 18 21 17

COMBO

LED_LEFT_A LED_LEFT_C LED_RIGHT_A LED_RIGHT_C

EMI4 EMI3 EMI2 EMI1 ME1

X806148-001

[PAGE_TI _TITLE=CON CONN,

RJ45

+ U US SB COMBO]

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 3 37 7

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 45/83

REV A

CR-46

:

@JASPER_LIB.JASPER(SCH_1):PAGE46

V_MPORT

V_5P0DUAL

RT2G1

RT8G1 1

1.1A 0.21DCR

V_GAMEPORT2

THRMSTR 2 1206

1

1

C9G5 4.7UF 10% 6.3V X5R 805

2

2

C9G2

220UF 20% 10V ELEC RDL

1

470PF 5% 50V X7R 402

PGB0010603 603

35

35

BI BI

GAMEPORT2_DP

2

1

NA SM EMPTY

                                           1

35

BI

MEMPORT2_DP

4

CMCHOKE

MEMPORT2_DN_CM

2

2

GAMEPORT2_DP_CM

2 3

4

GAMEPORT1_DN_CM

5 6

GAMEPORT1_DP_CM

7

10

V_GAMEPORT1

1

1

2

11

2

C9G3

220UF 20% 10V ELEC RDL

C9G4

12

470PF 5% 50V X7R 402

1

XENON MU

4 5 6

V_MEMPORT1

0

L2G1 35

35

BI

MEMPORT1_DN

1

BI

MEMPORT1_DP

4

C2G2

220UF 20% 10V 1

C3V5

2

470PF 5% 50V X7R 1 402

8 9

10

C2G3

4.7UF 10% 6.3V X5R 805

14 13 12

CH

15 16 17 18

NA SM EMPTY

CMCHOKE

EMI4 EMI3 EMI2 EMI1

11

5%

603

EMI1 EMI2

2

2 ELEC RDL

R3G4

GND VBUS DD+ GND

7

1

VBUS DD+ GND

X800245-003

3

             2

VBUS DD+ GND

ME1 ME2

GND VBUS DD+ GND

2              2

2

MEMPORT1_DN_CM

3

MEMPORT1_DP_CM

ME4 ME3 ME2 ME1 MTGA MTGB MTGC X800059-001

X801560-001                                            1

D9V2

R9V2 0

603

3

5% CH

35

BI

GAMEPORT1_DN

4

CMCHOKE

3

603 1

             2

2                                            1

BI

GAMEPORT1_DP

1

2

5% CH 1206

PGB0010603 603

X801560-001

EMPTY D9V1 2

603

[P [PAG AGE_ E_TI TITL TLE= E=CO CONN NN,,

EG2G1 DIO

DIO

5%

CH

             2

             2

5% CH

2

1

2

V_MPORT

1206

C1U2 1.0UF 10% 16V X7R 805

IC

U1F2 NCP1117

3

IN

1

ADJUST/GND

OUT

2

1 1

X800499-001

2

C1F6

0.1UF 10% 25V X7R 603

1

FTP FT1V1

C1F4

100UF 20% 16V

ELEC 2 RDL

1

R9V1 0

TH

0

V_5P0_MEMPORT

             2

3

PGB0010603 603

R1F10

0

EG9V1

35

                                           1

1

R1F9

EMPTY BAV99 SOT23S DIO

0

PGB0010603 603

EG9V2

1

EMPTY

L9V1

R2G5

V_5P0                                            1

NA SM

PGB0010603 603

EG3G1

V_5P0DUAL 2

CONN

J4G2 1

5% CH

603

XENON GAME CONN

9

4.7UF 10% 6.3V X5R 805

TH CONN

J9G1

8

C9G6

PGB0010603 603

                                           1

R4G4

1

RT8G2 THRMSTR 1206 2

PGB0010603 603

DIO

BAV99

V_5P0DUAL

MEMPORT2_DP_CM

                                           1

EG4G1

GAMEPORT2_DN_CM

1

SOT23S DIO

1

3

EG4G2

5%

1.1A 0.21DCR

1

0

CH

2

MEMPORT2_DN

DIO

3

BI

EG9G1

2

0

C5G6

4.7UF 10% 6.3V X5R 805

1

PGB0010603 603

             2

D9G1

X801560-001

603

35

EMPTY

2

R9G1

2

2

470PF 5% 50V X7R 402

EMPTY

X801560-001

BAV99 SOT23S DIO

3

1

220UF 20% 10V ELEC RDL

C4V6

3

5%

1

1

C5G4

NA SM

CH

CMCHOKE

4

GAMEPORT2_DN

1

5% CH

L4G1

             2

D9G2

L9G1

FB 603

R4G5 0

603

EMPTY

R9G2 2

V_MEMPORT2

1

120 0.5A 0.2DCR

THRMSTR 1206

2

V_5P0DUAL

0

C9G1

EG9G2

603

2

1

1.1A 0.21DCR

                                           1

1

FB5G1

2

2

5%

CH

BAV99 SOT23S DIO

MEMO MEMORY RY PO PORT RTS S + GA GAME ME PORT PORTS] S]

DRAWING JASPER_FAB_B Wed J u ull 30 1 3 3::1 7 7::3 8

20 0 08 8

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 46/83

REV A

CR-47

:

@JASPER_LIB.JASPER(SCH_1):PAGE47

XDK BOA BOARD RD MAP MAPPIN PING G DEBUG BOARD MAPPING MAPPING

59

IN

1 1 1

CPU_DBGSEL_XDK N:CON ONNE NECT CT TO CPU DEB DEBUG UG OUT

FTP FT6U11 FTP FT6U9 FTP FT6U10

N:CO N:CONN NNEC ECT T TO CPU DEBUG DEBUG OUT

DBG_CPU_LINKTRAINED DBG_CPU_SECURE_SYS DBG_CPU_PLL_LOCK

52 53 54

1 1

DBG_CPU_POST_OUT0 DBG_CPU_POST_OUT1 DBG_CPU_POST_OUT2 DBG_CPU_POST_OUT3 DBG_CPU_POST_OUT4 DBG_CPU_POST_OUT5 DBG_CPU_POST_OUT6 DBG_CPU_POST_OUT7

56 57

58 59 60 61

62 63

1 1

DBG_CPU_TST_CLK

55

CPU_ CPU_DB DBGS GSEL EL_D _DEB EBUG UG

IN

1 1 1 1 1 1 1 1

0

1

2

3

3

4 5 6

4 5 6

DB6E1 DB6E2 DB6E3

7

7

8 9

8 9

DB6E4

10

10

FTP FT6U8 FTP FT6U2 FTP FT6U3 FTP FT6U4 FTP FT6U5 FTP FT6U6 FTP FT6U7 FTP FT6U1

11

11

12

12

13

13

14

14

15

15

16

16

17

18

19

20

19 20

21

21

22 23 24 25 26

22 23

27

27

28 29

28

30

V_12P0

1

1

40 41

42 43 44 45 46

42 43

47

47

48 49 50

48

1%

51

51

CH 1206

52 53 54

52

55 56

56

57

57

58 59 60

58

61

61

62 63 64 65 66

62

67

67

68 69

68

35 36

R1R2

2

R1R3

10K 5% CH 402

2 10K 402

VREG_V5P0_SEL_C

R1R5

10K 5% CH 402

2

2

3

1

4

VREG_V5P0_SEL_PGATE

CH

2

CR1D1

34

IN

FT1R1

FTP

1

1

4.7K 402

R1D6

2

1 VREG_V5P0_SEL_B1

VREG_V5P0_SEL_B2

5% CH

37 38

IC

SI4501DY

D D D D

V_5P0

C1R3 .22UF 10% 6.3V X5R 402

2 1

2

XSTR

V_5P0DUAL

S2 G2

VREG_V5P0_SEL_NGATE

5%

MBT3904

VREG_V5P0_SEL

C1D11

U1R1

1

5 8 7

R1G1

5%

1%

CH

CH 1206

2

CH

402

20

2

     2      C _      R      E      D      E      E      L      B

     1      C _      R      E      D      E      E      L      B

5%

R1V2

20

402

2

X801132-002 4.7K R1D5

1

R1G2 1K

G1 S1

FTP FT1R2

1

1

1

6

3

Q1G2

1

VREG_5P0_SEL

VREG_5P0_SEL NGATE/PGATE

V_5P0DUAL 27

HIGH LOW

[PAGE_T _TIITLE=[MISC,

V_5P0STBY

LOW

IN

SMC_RST_N

2 10K 402

R1V1

1

BLEEDER_B

Q1V1

1

MMBT2222 XSTR

5% CH

MMBT2222 XSTR

2

V_5P0

HIGH

V_5 V_5P0

2

3

DU DUA AL,

DEB DEBUG MAPPING ING]

29

41

34

220UF 20% 10V ELEC RDL

26

39

33

1

25

40

V_5P0STBY

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 3 38 8

2008

OUT

24

30 31 32 33 34 35 36 37 38 39

32

CPU_ CPU_DB DBG_ G_TE TERM RM

17

18

31

V_5P0STBY

0

1

2

44 45 46

49 50

53 54 55

59 60

63 64 65 66

69

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 47/83

REV A

CR-48

:

@JASPER_LIB.JASPER(SCH_1):PAGE48

V_5P0 D1E4 2 3 36

HDD_TX_DP

IN

C1E4

1

2 1

0.01UF 10% 16V X7R 402

BAV99 SOT23S DIO

HDD_TX_DP_C

HD HDD D SATA SATA AND AND PO POWE WER R

HDD_TX_DN_C

36

HDD_TX_DN

IN

D1E3

C1E3

1

2

J1E1

2

10% 0.01UF 16V X7R 402

1

3

2 3

1

4 5 6

BAV99 SOT23S DIO

7

8 9

V_5P0

10

D1E2 2

                                           1

36

OUT

1

C1E2

2

BAV99 SOT23S DIO

HDD_RX_DN_C

36

OUT

HDD_RX_DP

1

                                           1

PGB0010603 603

EMPTY

RT1U1

2

36

IN

2

GND GND GND V_HDD V_HDD V_HDD V_XPOD EMI1 EMI2 ME1 ME2

2 2

1

1.5A 0.11DCR

3

V_HDD

THRMSTR 1812

1

1

2

C1E5

100UF 20% 16V ELEC RDL

X800351-002

C1T4

C1T5

ODD POWE POWER R DECOU DECOUPLING PLING

ODD_TX_DP_C

TH

470PF 5% 50V X7R 402

RT1R1 1

1.1A 0.21DCR

V_XPOD

THRMSTR 1206

C1T1

V_3P3

V_3P3

C1T2

470PF 5% 50V X7R 402

1UF 10% 16V X7R 603

V_3P3

V_12P0

C1T3

1UF 10% 16V X7R 603

1UF 10% 16V X7R 603

2

0.01UF 10% 16V X7R 402

XENON HDD CONN

MTGA MTGB

V_5P0

V_5P0DUAL

15 16 17 18

ODD ODD SAT SATA A C1C6

12 13 14

             2

             2

BAV99 SOT23S DIO

1

11

PGB0010603 603

EG1E1

EMPTY

EMPTY

D1E1

0.01UF 10% 16V X7R 402

ODD_TX_DP

                                           1

EG1E2

             2

             2

HDD_RX_DP_C

C1E1

PGB0010603 603

EG1E3

EMPTY

1

10% 0.01UF 16V X7R 402

                                           1

EG1E4

3

HDD_RX_DN

PGB0010603 603

CONN

GND D+ DGND DD+ GND

ODD POWER POWER AND CONTRO CONTROL L CR1D2

CR1D3 2

36

IN

ODD_TX_DN

1

C1C5

2

J1C1 SATA

ODD_TX_DN_C

1

C1C10 100UF 20% 16V ELEC RDL

9

0.01UF 10% 16V X7R 402

1

2

2

C1C14 1UF 10% 16V X7R 603

C1C13 0.1UF 10% 25V X7R 603

1

2

C1C11

100UF 20% 16V ELEC RDL

C1D6

1UF 10% 16V X7R 603

C1R1

.1UF 10% 6.3V X5R 402

36

OUT

ODD_RX_DN

1

2

ODD_RX_DN_C

0.01UF 10% 16V X7R 402

36

OUT

ODD_RX_DP

1

C1C3

2

34

4 5 6

V_5P0

7

OUT

TRAY_STATUS

1

R1R4

100 402

2

CONN ODD_RX_DP_C

TRAY_STATUS_R

5%

2

C1D9

100UF 20% 16V ELEC RDL

C1D4 1UF 10% 16V X7R 603

C1D1

1UF 10% 16V X7R 603

C1D3

BAV99 SOT23S EMPTY

CH

V_3P3

1

1

BAV99 SOT23S EMPTY

J1D1

V_5P0

8

0.01UF 10% 16V X7R 402

[PAGE_T E_TITLE=CONN CONN,,

3 1

3

C1C4

2

3

1 3

4 6 8 10 12

V_12P0

.1UF 10% 6.3V X5R 402

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 3 38 8

2008

IN IN

43 34

7

9 11

CONN

ODD + HD HDD] D]

EJECTSW_N TRAY_OPEN

5

MICROSOFT

CONFIDENTIAL

1

2

PRO PROJEC JECT T H08580

C1R4 75PF 5% 50V NPO 402

NAME NAM E

PAGE 48/83

REV A

CR-49

:

@JASPER_LIB.JASPER(SCH_1):PAGE49

V_3P3STBY

V_12P0

1

1

2

C6G5

100UF 20% 16V ELEC RDL

2 1

FTP

C6G2 470PF 5% 50V X7R 402

1

2

DB8M1 DB8M2 DB8M3

1

1

1

C9B1

1500UF 20% 16V ALUM RDL

1

FT9N1

1

C9A1

1

C9A5

0.1UF 10%

25V 2 X7R

0.1UF 10% 25V X7R 603

2

603

1

C9A6

0.1UF 10% 25V X7R 603

2

C9A2

0.1UF 10% 25V X7R 603

2

J9A1

3

GND GND GND

4 5 6

V12P0 V12P0 V12P0

2

R6G7

1

2

2 34

0

5% CH

603

IN

PSU_V12P0_EN

R8A1

NA SM L6G1 35

BI

35

BI

R8A2

1

7 PSU_V12P0_EN_R

100 402

1

5%

1

CH

10K 5%

4

CMCHOKE

3

ARGONPORT_DP

1

2

2

1

C8A1 .1UF 10% 6.3V X5R 402

2

CH

EMPTY

ARGONPORT_DN

402

2

PSU_EN

C8A2

470PF 5% 50V EMPTY 402

X801560-001

1

2

R6G8

1 0

603

2

1

C6G3

470PF 5% 50V EMPTY 402

2

C6G4

1

470PF 5% 50V EMPTY 402

ARGON_DN_CM ARGON_DP_CM

2 3

4 5 6

5% CH

USE USE LC NE NETW TWOR ORK K FOR FOR US USB B 1. 1.1 1 US USE E USB USB CH CHOK OKE E FO FOR R USB USB 2.0

R3N7

2 34

IN

PWRSW_N

2 10K 402

R3N6

CH

34

BI BI

PWRSW_N_R

2 1

C6V15

470PF 5% 50V X7R 402

1

C6V11

470PF 5% 50V X7R 402

2 1

1

V_5P0STBY

2 RDL

MTGA MTGB

DB8N1

1

NTX

13

ARGON_DATA ARGON_CLK 2

1

5%

34

XENON RF CONN

9

12

10K 5% CH 402

FTP FT8N1

1

C5B7

100UF 20% 16V ELEC

C8B1

2

100UF 20% 16V ELEC RDL

TH

X815566-001

1

C9A4

470PF 5%

50V 2 X7R 402

EMI1 EMI2 ME1 ME2

V_5P0STBY

V_12P0

1

1

X800095-001

C6V10

470PF 5% 50V X7R 402

2.2K 5%

2.2K 5%

CH

CH

402

2

V_12P0

R7B2

R8B5

2

     1      C _      0      P      2      1      V _      R      E      D      E      E      L      B

402

2 549 402

     2      C _      0      P      2      1      V _      R      E      D      E      E      L      B

R8N1

1

CH

3

R8A4

27

IN

2 2.2K 402

ARGO ARGON N + PO POWE WER R SUPP SUPPLY LY]]

BLEEDER_V12P0_B1

CH

R8A3

BCP51 XSTR

BLEEDER_V12P0_LOAD

MMBT2222 XSTR

2

1

1

1

R7N3

R7N1

R7N4

R7N2

CH 805

CH 805

CH 805

CH

10 1%

Q8B4 2

Q8B5

1

2

10 1%

10 1%

10 1%

2

2

805

MMBT2222 XSTR

5%

2.2K 402

ANA_V12P0_PWRGD

1

Q8N1 2 4

1

1

2

3 1

BLEEDER_V12P0_B2

1%

3

[P [PAG AGE_ E_TI TITL TLE= E=CO CONN NN,,

ME1 ME2

12

1

11

EMI1 EMI2 EMI3 EMI4

11

SPARE C_DATA C_CLK GND

10

1

VSB5P0

9

CONN

8

7

V_3P3STBY

VCC DD+ GND

8 10 13 14

TH

J6G1

CONN XENON PWR

1

2

1

5%

CH

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 3 39 9

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 49/83

REV A

CR-50

:

@JASPER_LIB.JASPER(SCH_1):PAGE50

4

IN

CPU_VREG_APS5

4

IN

CPU_VREG_APS4

IN

CPU_VREG_APS3

IN

CPU_VREG_APS2

IN

CPU_VREG_APS1

IN

CPU_VREG_APS0

4

4

4

4

R7E3 0

5

5% 0

R7E5 0

402

R7E2 0

4 5% CH

402

5%

3

402

5%

2

5% CH

1K

402

10K 5% CH

2

0

5% CH

402

1

R7T4

R7T6

1

R7E6

CH

1

1

R7E4

CH

0

402

V_GPUCORE

R7E1

CH

402

2

5

10K 5% EMPTY 402

1

1

R7T8

2

4

10K 5% EMPTY 402

2

10K 5% EMPTY 402

10K 5% EMPTY 402

2

2

3

N: N: N: N:

1

R7T5

R7T7

R7T9

2

10K 5% CH 402

WATERNOSE=0 WATERNOSE=011100=1. 11100=1.1625V 1625V DD DD1. 1.0 0 RE REQU QUIR IRES ES VI VID0 D0 RC DD 2. 2. 0 N O ST U UF FF RC LOKI= LOKI=1000 100001=1 01=1.05V .05V

0

1

OUT

VREG_CPU_VID

R7T13

2

1

1

1

10K 5% EMPTY 402

R7T11

2

10K 5% CH 402

1

1

R7T15

R7T14

R7T12

CH

CH

CH

10K 5%

2

402

10K 5%

2

402

R7T16

10K 5%

402

2

2

10K 5% EMPTY 402

N:GPU

V_12P0 V_12P0

N:CPU

1 1

2

C9B2 4.7UF 10% 16V X5R 1206

IN INPU PUT T

FIL FILTE TER R

V_VREG_CPU

IND

TH

C9C4

C9E3

C9C1

1500UF 20% 16V ALUM RDL

1500UF 20% 16V ALUM RDL

C9D2

1500UF 20% 16V ALUM RDL

1500UF 20% 16V ALUM RDL

1

C9B4

4.7UF 10% 16V EMPTY 1206

2

1

2

1

2

C8C2

820UF 20% 6.3V EMPTY RDL

1

2

C8E3

820UF 20% 6.3V ALUM RDL

1

2

C8E1

820UF 20% 6.3V ALUM RDL

1

2

C8F1

820UF 20% 6.3V ALUM RDL

1

2

C8E2

820UF 20% 6.3V ALUM RDL

1

2

C8D1

820UF 20% 6.3V ALUM RDL

INPU INPUT T

FIL FILTE TER R

1

2

C8B2

1 1.6UH 10A NA

2

4.7UF 10% 16V X5R 1206

1

1

C6B3

1500UF 20% 16V ALUM RDL

2

DB8P2

2

1

C7B3

1500UF 20% 16V ALUM RDL

2

C8B4

4.7UF 10% 16V X5R 1206

1

2

C6B5

4.7UF 10% 16V X5R 1206

1

1

C6N2

2

4.7UF 10% 16V X5R 1206

2

C7B4

4.7UF 10% 16V X5R 1206

1

53

54

C7N3

4.7UF 10% 16V X5R 1206

2

V_GPUCORE N:GPU N:GPU

FTP FT7T9

C8C1

820UF 20% 6.3V EMPTY RDL

+ OUT OUTPU PUT T FILT FILTER ERS] S]

OUT

V_VREG_GPU

IND

TH

DB8P1

1

2

1

C8D4 820UF 20% 6.3V ALUM RDL

2 1

[PAG [PAGE_ E_TI TITL TLE= E=VR VREG EGS, S,

1

2

1

OUT OUTPUT PUT FILTER FILTER

51 52

4.7UF 10% 16V EMPTY 1206

1

V_CPUCORE

OUT

C9C3

1

N:CPU N:CPU

INPU INPUT T

L8B1

L9B1 2

1.6UH 10A NA

51

1

FTP

C7C2

820UF 20% 6.3V ALUM RDL

1

2

C7C1

820UF 20% 6.3V ALUM RDL

1

OUT OUTPUT PUT FIL FILTER TER

1

2

1

C6C3

820UF 20% 6.3V ALUM RDL

2

C7C3

820UF 20% 6.3V ALUM RDL

1

2

FTP FT5R2

C6C2 820UF 20% 6.3V ALUM RDL

1

2

C6C1

820UF 20% 6.3V ALUM RDL

1

2

C5C8

820UF 20% 2.5V EMPTY 8X8

1

2

C5C9

820UF 20% 2.5V EMPTY 8X8

FT7U4

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 4 40 0

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 50/83

REV A

CR-51

:

@JASPER_LIB.JASPER(SCH_1):PAGE51

V_5P0

50

R8G1

1 10

R8G1 R8V10 C8U4

V_VREG_CPU

IN

3190A EMPTY STUFF STUFF

1

2

R8U5

1%

603

3188 STUFF EMPTY EMPTY

1K 1%

CH

CH

50 34

R8V10

2

V_VREG_CPU

IN

VREG_CPU_EN

IN

1

10

1%

805

EMPTY

VREG_CPU_RAMPADJ_R

FTP

1

IN

1UF 10% 16V X7R 603

R8F7

10K 5% CH

2

52

IN

IN

4.7UF 10% 16V X5R 1206

2

1

C8G6 4.7UF 10% 16V X5R 1206

2

1

R8U3

1

294K 1%

402

2

2

C8U4 .1UF 10% 6.3V

1

402 X5R

402

0

VREG_CPU_RAMPADJ

R8V7

VREG_CPU_PHASE2 0

5% DB8U4

0

2

2

R8V2

R8V1

47.5K CH

CH

603

603

1%

1

R8V4

47.5K

EMPTY 603

47.5K

1%

1

1%

1

RAMPADJ

1

RT8F1 2

VREG_CPU_PHASE3_R

21

22 23

VREG_CPU_CSCOMP

THRMSTR 603

PWRGD

EN

CSCOMP

17

CSSUM

16

TEMP SENSOR

8

R8V3

1

2

1%

35.7K 603

CH

2

1

R8V5 76.8K 1%

2

CH

603

1

C8V1

360PF 10% 50V NPO 603

SW4 SW3 SW2 SW1

18

1

FTP

FT8U1

20

VREG_CPU_PHASE2_R VREG_CPU_PHASE1_R

NA 100K

     U _      P      C _      G      E      R      V

1

1

TP

CH

     R _      P      M      O      C      S      C

2

VREG_CPU_SW4

5%

603

VCC

14

CH

R8V9

VREG_CPU_PHASE1

ADP3190A

28

11

9

COMP

7

FBRTN

6

PWM4 PWM3 PWM2 PWM1

24 25 26

DELAY

1

2 3 4 5

27

VREG_CPU_VID

5 4 2 1

CH

VREG_CPU_FBRTN

0

VREG_CPU_PWM3 VREG_CPU_PWM2 VREG_CPU_PWM1

OUT OUT OUT

12

603

52 52 52

VREG_CPU_DRV_EN

RT

13

GND

19

OUT

52

VREG_CPU_DELAY

1

2

2

2

2

VREG_CPU_RT

422K ST7T1

2

5% CH

402

R8U2

2

R8F8

1

0

1%

8200PF 10% 16V

50

IN

3

15

ILIMIT

CSREF FB

10

VID5 VID4 VID3 VID2 VID1 VID0

X806818-001

C8U3

2

34

OUT

IC

U8U1

5% EMPTY

FTP FT2P16

VREG_CPU_PWRGD

R8V6

VREG_CPU_PHASE3

603 52

C8G5

CH

603 52

1

C8V15

1

FT2P17

2

VREG_CPU_VCC

402

R8U1

C8U1

.047UF 10% 16V X7R 603

1

R8U4

1%

324K

240K 5%

CH

CH

603

1

2 1

402

C8U2

1000PF 10% 50V EMPTY 402

CH

1

1

402

SHORT

2

VREG_CPU_CSSUM

V_CPUCORE

1

LAY LAYOUT OUT:AT :ATTAC TACH H TO CLOSEST CLOSEST INDUCTOR 1

ST8F1 2

FT8U2

R8G3 2

1

VREG_CPU_CSREF

10

SHORT

402

1% CH

2

VREG_V_CPUCORE_S

R8U13

ST7T2

1 2

SHORT

5% EMPTY

2 0

402

2

C8U7

1

R8U10

[P [PAG AGE_ E_TI TITL TLE= E=VR VREG EGS, S,

TAR TARGET GET FSW FSW=233 =233KHZ KHZ

1000PF 10% 50V X7R 402

VREG_CPU_FB

C8U8

2 1

1% CH

N:

C8G1

10% 0.1UF 25V EMPTY 603

1

1

1000PF 10% 50V X7R 402

VREG_CPU_CSREF_R

1

1

FTP

C8U10

2

1.33K 603

1

C8U6

2

VREG_CPU_COMP_R

330PF 5% 50V X7R 402

CP CPU U CO CONT NTRO ROLL LLER ER]]

1

R8U11

24.3K 402

2

22PF 5% 50V NPO 402

VREG_CPU_COMP

1% CH

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 4 42 2

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 51/83

REV A

CR-52

:

@JASPER_LIB.JASPER(SCH_1):PAGE52

50

50

IN

R9P2

1

V_VREG_CPU

D9C1 1N4148

2

1

VREG_CPU3_VCC

3

EMPTY

1

C9P4 1.0UF 10%

IN

VREG_CPU_DRV_EN

VREG_CPU_PWM3

IN

R9P1

1

805

U9P1 4 2 3 6

3

C9P3

2

D

2.2 805

EMPTY

MOS DRIVER VCC BST IN DRVH SW OD_N* PGND DRVL

2

S

G

2

2

1

NTD60N02R DPAK

1

1

G

EMPTY

S

EMPTY

2

2

C9D3

4.7UF 10% 16V X5R 1206

1

2

C9D1

4.7UF 10% 16V EMPTY 1206

VREG_CPU_PHASE3

5% 16V EMPTY 805

OUT

V_CPUCORE 1

EMPTY TH

1

3 D

Q9C1

D

0.6UH 30A NA

R9C1

3

2.2

Q8C1

1%

EMPTY 805 NTD85N02R DPAK

1 G

S

2

1 G

EMPTY

2

NTD85N02R DPAK

S

2

EMPTY

VREG_CPU_SW3_R

1

R9T2

1

2.2 805

D9E1 1N4148

2 1

2

51

1

VREG_CPU2_VCC

1% CH

3

2

VREG_CPU_BST2

1

1.0UF 10% 16V X7R 805

R9T1

1

3

6

MOS DRIVER VCC BST IN DRVH

3

2

D

2

VREG_CPU_BST2_R

C9T1

1

1

2

3

Q9E1 NTD60N02R DPAK

G

S

2

5% 16V X7R 805

0.015UF

CH

1

8

Q9D4

D

NTD60N02R DPAK

1

G

FET

S

1

2

EMPTY

2

C9D4

4.7UF 10% 16V EMPTY 1206

1

2

C9E1 4.7UF 10% 16V X5R 1206

VREG_CPU_PHASE2

2

VREG_CPU_DRVH2

IND

1

5      2      G      B _      U      P      C _      G      E      R      V

X801233-001

3 D

L8E1

D

1

S

2

OUT

G

S

2

1

0.6UH 30A NA

1%

2

EMPTY 805

FET

VREG_CPU_SW2_R

1

R9U2

1

D9F1 1N4148

2

1

VREG_CPU1_VCC

VREG_CPU_BST1

3

1

2

SOT23 DIO

C9U3

1.0UF 10% 16V

U9U1

IN

VREG_CPU_PWM1

R9U1

1

805 X7R

51

1

1%

CH

4 2 3

6

MOS DRIVER VCC BST IN DRVH OD_N* SW PGND DRVL X801233-001

2.2 805

IC

C9U2

2 2

3 D

0.01UF 10% 50V X7R 805

2

1% CH

VREG_CPU_BST1_R

1

C9U1

2

1 G

0.015UF

5% 16V X7R 805

3

Q9F1 NTD60N02R DPAK

S

2

FET

Q9F4

D

NTD60N02R DPAK

1 G

S

EMPTY

2

1

2

C9F4

4.7UF 10% 16V X5R 1206

1

C9F1

4.7UF 10% 1206

2

VREG_CPU_DRVH1

7

TH

Q9F2 NTD85N02R DPAK

1

S

2

R9F1

3

3

FET

D

G

S

2

1

0.6UH 30A NA

2.2

Q8F1

1%

NTD85N02R DPAK

1

2

EMPTY 805 VREG_CPU_SW1_R

FET 1

2

CPU CPU O OUT UTPU PUT T PHASE PHASE 1,2, 1,2,3] 3]

51

L8F1

IND 1

D

OUT

VREG_CPU_PHASE1

5      1      G      B _      U      P      C _      G      E      R      V

C9E4

4700PF 10% 50V EMPTY 603

16V 2 EMPTY

1

8

G

[PAG [PAGE_ E_TI TITL TLE= E=VR VREG EGS, S,

51

2.2

Q9D3 NTD85N02R DPAK

1

FET

TH

R9E1

3

Q9E3 NTD85N02R DPAK

G

2.2 805

C9C5

4700PF 10% 50V EMPTY 603

7

SW DRVL

OD_N* PGND

1%

2.2 805

IC

U9T1 4 2

C9T2

10% 0.01UF 50V X7R 805

SOT23 DIO

C9T3

VREG_CPU_PWM2

IN

51

L8D1

2

VREG_CPU_DRVH3

     3      G      B _      U      P      C _      G      E      R      V

X801233-001

Q9D1

D

0.015UF

EMPTY

1

8 7 5

C9P2

1

VREG_CPU_BST3_R

1%

3

Q9D2 NTD60N02R DPAK

0.01UF 10% 50V EMPTY 805

SOT23 EMPTY

16V 2 EMPTY

51

1

1%

2.2 805

51

V_VREG_CPU

IN

VREG_CPU_BST3

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 4 42 2

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

C9F3

4700PF 10% 50V EMPTY 603

NAME NAM E

PAGE 52/83

REV A

CR-53

:

@JASPER_LIB.JASPER(SCH_1):PAGE53

50

V_VREG_GPU

IN

V_GPUCORE

1

ST5R2

1

R8N7 2.2

2

1%

1

SHORT

R8C9

0 61

2 2

1

NA 10K

VREG_GPU_VFB_R

2

R8P7

1.1K 402

R8P9

2

1.21K 402

THRMSTR 603

FT8P2

FTP

FT8P1

FTP

1

1

2

CH 805

2

R8P4

2

5.11K 402

1.150V 1 .1 25 V 1 .1 50 V 1 ..1 15 50 0V 1 .1 25 V 1. XX XXXV

B13 RHEA G UN GA

ANY ANY AN Y

VID VI D V IID D

1.150V 1.150V 1 .0 75 V

1

1

C8N3 1.0UF 10% 16V X7R 805

2

1.0UF 10% 16V X7R 805

1

53

2

IN

1

R8P1

1

VREG_GPU_COMP_C

30

5VSB

7

VFFB

VCCH

VREG_GPU_VFB

1

VFB

VREG_GPU_VDRP

2

VDRP

2

2

.047UF 10% 16V X7R 603

1

6800PF 10% 50V X7R 603 1

R8P5

2

V_GPUCORE

10

VREG_GPU_CS1

6 4

VREG_GPU_CSREF

5

CSREF

VREG_GPU_ROSC

9

ROSC

28 27

1

C8N4

0.01UF 10% 16V X7R 402

5%

OUT

R8B8

1

ILIM 5VREF

15

20

13 12

VREG_GPU_ILIM

29

GH2 GL2

19

GH1 GL1

22 24

COVC

CH

1

R8B2

2

2 1

17

LGND

3

GND2 GND1

23

1

R8B4

2

18

1

2

1% CH

7.5K 603

2 6.19K

[P [PAG AGE_ E_TI TITL TLE= E=VR VREG EGS, S,

1

1%

V_5P0STBY

CH 402

1

X800631-001

10K 5%

402

FTP

FT2P6

R9B1

1

VREG_GPU_EN_N 1

FET

     R _      N _      N      E _      U      P      G _      G      E      R      V

R5N1

IN

Q8B3

2N7002 2 SOT23

1

34

10K 402

VREG_GPU_PWRGD

C8P4 0.1UF 10% 25V X7R 603

1 VREG_GPU_GH2_R

R8N5

1

2

1A CH

CH

0

2 5% CH

2

2

470PF 5% 50V X7R 402

1

R8N3

1 0

805

1A CH

VREG_GPU_GL1_R

2

2

R8N4

1

1%

0

CH

805

OUT

34

VREG_GPU_GH2

OUT

54

VREG_GPU_GL2

OUT

54

VREG_GPU_GH1

OUT

54

VREG_GPU_GL1

OUT

54

FTP FT2P3

1A CH

805 VREG_GPU_GH1_R

750K

C8B7

R8N6

1

1

R8B3 1

3

R8C1

C9C2

0.1UF 10% 25V X7R 603

1

C8B8

0.1UF 10% 25V X7R 603

D8B1 MMSZ18 SOD123 DIO

2

2

1%

2K 402

SHORT

1

C8N1

0.1UF 10% 25V X7R 603

53

0

2

805

2

805 VREG_GPU_CSREF_R

C9B3

1

5%

VREG_GPU_GL2_R

2

53

0.1UF 10% 25V X7R 603

62

OUT

0.1UF 10% 25V X7R 603

2

2

R8N2

C8P3

1

V_GPUCORE

ST8C1

54

1% CH

7.5K 603

1

OUT

VREG_GPU_NPNC

1

5% EMPTY

402

VREG_GPU_5VREF

PGD

VREG_GPU_PHASE1

1

VREG_GPU_VCCH

31

NSEN

2

R8B10 2 0

8

CS2 CS1

2

5% EMPTY

402 1

C8B3

0.1UF 10% 25V BAV99 X7R 603 SOT23S DIO

CH

R8B9

1

2

3

2

VREG_GPU_VID0

11

21

CPGD

61

14

CBOUT

OUT

VREG_GPU_PHASE1_C

5%

402

61

D8B2 1N4148 SOT23 DIO

3

CH

402

61

D8B3 1

1

2

CH

1

R8P6

2

VREG_GPU_PHASE1

CH 603

2

2

IN

VREG_GPU_SEN VREG_GPU_CS2

VREG_GPU_CPGD

1

1% CH

7.5K 603

0

COMP

1%

1

IN

VCCL

32

R8C7 35.7K

SHORT

VREG_GPU_PHASE2

26

VREG_GPU_COMP

2

ST5R1 2

R8B7

1

0

VREG_GPU_VFFB

7.5K 1% 603 CH C8N5

C9P1

VREG_GPU_VID3

2

5% EMPTY

402

61

VREG_GPU_VID1

VREG_GPU_5VREF

1

R8B1

1 0

NCP5331 VCCL2 VCCL1

VID4 VID3 VID2 VID1 VID0

1% CH

4.02K 402

6800PF 10% 50V X7R 603

2

R8P3

2

VREG_GPU_COMP_R

VREG_GPU_VID4

OUT

IC

U8N1 16

CH

C8P2

2

C8P1

V_VREG_GPU

IN

0

25

1000PF 10% 50V EMPTY 402 1

0=10000 0=10000 0 0= =1 00 11

50 61

OUT

C8B9

VREG_GPU_VCCL

1

53

VOLTAGE

VID 0=10000 V IID D --1 1 =1 00 01 V IID D 0 =1 00 00 V I D 0= 0= 10 0 00 00 V IID D --1 1 =1 00 01 V ID ? ?= = 01 110

1%

1%

54

VID

ANY SEC I FX HY HYNI NIX X AN Y AN Y

VREG_GPU_VID2

1

1% CH

MEM

1%

2

402 VREG_V1P8_FB1_R

1

R4G8 549

THE THESE SE ARE THE VOLTAGES NEE NEEDED DED FOR VARIOUS MEMORIES. CONSULT WITH WITH MEM TEAM FOR USAG USAGE. E.

C3V8 .22UF 10% 6.3V X5R 402

AND V5P0]

R4G6

1%

CH

CH

2

2

V_MEM

CH

JASPER

R3V3

IN

820UF 20% 4V EMPTY RDL

FET

1%

CH

34

C2F1

OUT

R4V5

243

5% EMPTY 402

1

2

2

1

2

NTD60N02R DPAK

1

18.2K 402

FR FREQ EQ PIN 3: 0 3 00 KHZ 1 600KHZ

1

0

ST3G1

D

55

1

ST2F1 SHORT

3

CH

5% EMPTY

1

1

1.7UH 13.8A

     1      S      S _      8      P      1      V _      G      E      R      V

1

FTP

VREG_V1P8_SW1_S

SHORT

1% CH

     1      P      M      O      C _      8      P      1      V _      G      E      R      V

5%

R4V2

SHORT

TRK1 EN1

FT2U1

FET 2

ST2F2

1

1

X807026-001

10K 402

S

2

VREG_V1P8_CSL1_R

      3       3

1

DB3F1

NTD60N02R DPAK

1

VREG_V5P0_VMEM_PWRGD

34

2

1UF 10% 16V X7R 603

Q3F1

D

470NF 10% 10V X7R 603

G

             4

2

1% CH

402

1

VREG_V1P8_DL1

PGND2

220PF 5% 50V NPO 402

VREG_V5P0_FB2

18

DL2

15

G

7.5K 402

DL1

16

     2      P      M      O      C _      0      P      5      V _      G      E      R      V

VREG_V5P0_COMP2_R

VREG_V1P8_CSL1

VREG_V5P0_DL2

1

C4V12

20

CSL2

CH 402

1

CSL1

14

1%

1%

VREG_V1P8_SW1

VREG_V5P0_CSL2

VREG_V5P0_CSL2_R

1.82K

VREG_V1P8_DH1

21

SW2

2

R4V6

22

SW1

DH2

13

357

     C _      2      B 2      F _      0      P      5      V _      G      E 1      R      V

DH1

12

VREG_V5P0_SW2

NTD60N02R DPAK 1

VREG_V1P8_BST1

VREG_V5P0_DH2

Q6F2 FET

D

23

BST2

3

820UF 20% 6.3V ALUM RDL

BST1

11

TH

C7F3

27

VREG_V5P0_BST2

2

SHORT

LDOSD

ADP1823

C3V7

2

IC

P   I       N   V

VREG

4

1.7UH 13.8A

     R _      2      B      F _      0      P      5      V _      G      E      R      V

1

R4V11 5% EMPTY 402

2

ST6F2

      1       2       8      7

U4V1

29

G

VREG_V5P0_SW2_S

C3V6

1500UF 20% 16V

3

1

1UF 10% 16V X7R 603

2

2

1

R4V9

2

C7F1

2 ALUM RDL

V_MEM C4V8

470NF 10% 10V X7R 603

DPAK 1

SHORT

1

C4V15

0.1UF 10% 25V X7R 603

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 4 46 6

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

CH

2

402

PAGE 55/83

REV A

CR-56

:

@JASPER_LIB.JASPER(SCH_1):PAGE56

U6T2

V_3P3 V_5P0

V_5P0 1 IC

U1F1 34

IN

VREG_3P3_EN

2

1

NCP5662 TAB

IN

1

6

1.27K

1

C1U1

1.0UF 10% 16V X7R 805

1

2

R1F7 1K

EN

1K

2

1

2

R1U2 475

2 TYPE F IIX XE ED D ADJ

1

EMPTY 402

FTP FT5N1

PART # X 80 79 6 64 4 --0 00 01 1

R1U1 E MP TY

R1U2 E MP TY

X807089-001

1. 27K

475

1

1

C5B1

0.1UF 10% 25V X7R 603

2

2

C5B2

FTP

FT7T8

100UF 20% 16V ELEC RDL

402

1

2

R4C31

1

CH

0

402

603

D5N1 DIO SOD123 VREG_1P8STBY_D1 1

MBR130L

1

D5N2 DIO SOD123 MBR130L

D5B1 DIO SMA

2

2

1 S1A VREG_1P8STBY_D2

R5B3 1

1206

4

1

VREG_1P8STBY_IN

IN

1

ADJUST/GND

C5N3

1.0UF 10% 16V X7R 805

1

R5B1

549 1%

2

V_GPUCORE

2

EMPTY 402

VREG_1P8STBY_ADJ

R4P13

2

3

VREG_GPUPCIE_IN

5%

1

C5B6 0.1UF 10% 25V X7R 603

CH

C4C6

ADJUST/GND

100UF 20% 16V ELEC RDL

R4C31

R4P14

U5C1

B 13L GU GUNG NGA A

E MP TY S TUF UFF F

ST UF F E MP TY

EM PT Y S TUFF

S TU TU FF E MP TY

1

NCP1117

3

IN

1

ADJUST/GND

1

1

2

OUT

4

1

1

R3C21

549

X800501-001 SOT223 1.2V

2

2

2

V_ _S S BP CI E 1.87V 1.80V

R 3C 22 499 549

2

R2C3

C2C6

.1UF 10% 6.3V X5R 402

243 1%

CH

2

402

1

2

R5P2

R5C9

EMPTY

CH

R5C4

805

2

VREG_CPUPLL_IN

FTP

FT5R1

1

1%

2

402

402

     R _      X      E      I      C      P _      G      E      R      V

5% EMPTY 402

1

2 1A

EMPTY

C5C5

4.7UF 10% 6.3V X5R 805

V_CPUPLL

U6R1

0

FTP FT2P26

R6C1 0

805

IC

N:

NCP1117

3

IN

1

ADJUST/GND

TA TARG RGET

IS

1.8V 1.8V 1

2

OUT

FTP

1A

EMPTY

C6P1

1.0UF 10%

16V 2 X7R

R6R3

R6R1

549

X800501-001 SOT223 1.8V

1

1%

1%

CH

2

805

402

2

1

2

R6R2

C6R1

.1UF 10% 6.3V X5R 402

CH 402

     R _      L      L      P      U      P      C _      G      E      R      V

VREG_CPUPLL_ADJUST

CH 402 1

FT7R3

1

1

4

OUT/TAB

     R _      X      E      P _      D      D      V _      G      E      R      V

1

1 1

0

.1UF 10%

1

VREG_VDD_PEX_ADJ

1

C5P1

1%

1%

CH

402

1.25 1.25V V

R5P1

2 6.3V EMPTY

1A CH

1

OUT/TAB

IS

1K 1%

1

R5C6 0

V_SBPCIE

R3C22

C2C5

1.0UF 10% 16V X7R 805

OUT/TAB

TA TARG RGET 1

4

2 1

IC

U3P1

N:

2

OUT

2

R4P13

2

5% CH

V_GPUPCIE

X800501-001 SOT223 1.2V

1.0UF 10% 16V X7R 805

GPU

1

402

1UF 10% 16V EMPTY 603

1UF 10% 16V X7R 603

2

NCP1117

V_3P3

C5B4

2

C7T99

C7T98

4

2.9V

FTP FT7T6

EMPTY

IN

1

805

R5B2

1

1

FTP FT5N2

0

V_3P3

2

5% CH

U5C1

V_1P8

2

R4P14 0

402

1

X818397-001 DPAK 1.8V

5

GND

1

2 1

VOUT

SC70

PLACEHOLDERS OUT



VREG_PCIEX_ADJUST

V_1P8STBY

3

ENABLE

TH HII S I S A CT U UA A LL Y A 3 .3 .3 V P ART NC NCP6 P612 12 FAMI FAMILY LY.. NE NEED ED TO MAKE MAKE NEW SY SYMB MBOL OL

XSTR

1

SET SET TO 1.816V 816V

IC

NCP1117

VIN

3

X810988- 002

603

1

5%

U5B2

2

6

2

2 -

V_EFUSE IC

1

2

SE ET T TO 1 1.. 8 8V V

USING USING U5B2 U5B2 AS AN ADJU ADJUSTAB STABLE LE R 5B 1 = 54 549 9 OHM R 5B 2 = 22 221 1 OHM

CH

1

1

IF

4

2.9V

NC 3

5% EMPTY

603

-

2

X803461-001

1UF 10% 16V X7R 603

VREG_EFUSE_EN_C2

5%

10K 5%

USI USI N NG G U5B 2 A S A FI FI X XE ED R5 R5B1 B1 = EMPT PTY Y R5 B2 = 0 O HM

5

GND

CH

0

IF

VOUT

V_3P3

1

2

NCP502D

VREG_EFUSE_EN_R

V_5P0STBY

2

2

C7T100

R6T1

1

V_5P0

1

ENABLE

NC

10K 5% CH 402

5

R6T4

2

VREG_EFUSE_EN

IN

3

U6T1

MBT3904

1K

ADJUST/GND

10K 5% CH 402

     1      C _      N      E _      E      S      U      F      E _      G      E      R      V

VREG_V3P3_ADJ

VIN

R6T3

R7T10

CR6T1

2

OUT

X800499-001 DPAK 3.3V

1.0UF 10% 16V X7R 805

EMPTY 402

2

VREG_3P3_EN_R

V_3P3STBY

C5B3

5

100UF 20% 16V

1

IC

NCP1117

IN

4

ADJ

C1F3

ELEC 2 RDL

EMPTY LP2980

1

1

1

5% CH

V_5P0STBY U5B1

O UT

2

FTP FT1U1

1%

R1F8

402

3

X807964-001

1

2

GND

5% CH 402

2

1

3

1

1%

1

C1F5

0.1UF 10% 25V X7R 603

R1U1

V_5P0

243 1%

1

CH

2

402

2

C7P1 4.7UF 10% 6.3V X5R 805

C3C1 4.7UF 10%

6.3V 2 X5R 805

[PA [PAGE_TITL TITLE E=[VRE [VREG GS,

LINE INEAR

VREG REGS]

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 4 46 6

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 56/83

REV A

CR-57

:

@JASPER_LIB.JASPER(SCH_1):PAGE57

VCS REG REGULA ULATOR TOR

V_5P0

R7G23 0

805 1A

2

1

CH DB8U1

4

1

IN

2 1

V_CPUCORE

R7T19

DB8U2

0

2

TP

5% EMPTY 402

2

1

1

R8U8

R8U9

5% EMPTY 402

5%

V_12P0 2

V_CPUCORE

2

VREG_VCS_SS_SD_N

1

3

VREG_VCS_LTO

1

1

Q7F1

EMPTY 2N7002 SOT23

2

2

C7U5

4700PF 10% 50V X7R 603

1

DB8F4

C7U6 .1UF 10% 6.3V X5R 402

R7U4

2

5%

EMPTY

C8U9

             2

.1UF 10% 6.3V X5R 402

2

MMBT2222 EMPTY

VREG_VCS_CPUCORE_R

1UF 10% 16V X7R 603

1UF 10% 16V X7R 603

1

11

NC2

12

COMP

R7U6

FB

      D       N       G

4 9

VREG_VCS_HDRV

LDRV

6

VREG_VCS_LDRV

PGND

8

HDRV

X811812-001

0

               7

             5

      4       1

S WI TC TC H

S TU FF E MP TY

1

VREG_VCS_COMP_C

1

C7G5

0.1UF 10% 25V X7R 603

EMPTY TH

10A NA

1

C7F5 4.7UF 10% 16V

1206 2 X5R

C7U8

2

F RE Q

2

GATE1

1

SRC1

DRN1

TH

7 8

DRN1

1

L8F2

2

VREG_VCS_VOUT_L

FTP FT7U3

1

1.7UH 13.8A

4

1

SO-8

C7F4

820UF 20% 6.3V ALUM RDL

2 1

C7T103

4.7UF 10% 6.3V X5R 805

2 1

C7T102

4.7UF 10% 6.3V X5R 805

MBR0520L SOD123 EMPTY

DB7U1

VREG_VCS_NC1 1

4 00 KHZ 20 200K 0KH HZ

DB8U3

R7U7

1

VREG_VCS_FB

VREG_VCS_COMP

10K 402

2

1

47PF 5%

C7U11

220PF

R8U6

2.67K 402

2

2

1%

EMPTY

5%

50V NPO 402

50V EMPTY 402

1

R8U14 2

VREG_VCS_FB_R

1

1%

0

CH

402

VREG_VCS_FB_COMP

1

C8U5

2 5% EMPTY

2

ST7D2

1

SHORT

2

2700PF 10% 50V EMPTY 402

1

R7U8 4.02K

R8U12

1%

CH

2

5 6

DRN0

CR7V2

1

C7U7

1

2

                                           1

3300PF 10% 50V EMPTY 402

1

1

C7V2

0.1UF 10% 25V X7R 603

2

VREG_VCS_NC

1

R 7U 6

2

V_CPUVCS

DRN0

SRC0

X807111-001

             2

R7U5

2

C7G4

4.7UF 10% 16V X5R 1206

IND

                   1

15K 1% 402 EMPTY

1

2

FET

GATE0

3

      1       C       C       N       N SSOP

402 EMPTY 5%

2

1

C7G3

4.7UF 10% 16V X5R 1206

IRF8915PBF

U7F1

IC

      C       V

IR3638

SS

1

1

Q7U1

1

1K

1

VREG_VCS_RT

TP

3

402

2

      0       1

      C       C       V

NC0 VP

13

TP

                   1

             4

U7U2 3 VREG_VCS_VP

DB7U2

2

1

5% EMPTY 402

R7F9 10K 5% EMPTY 402

C8F2

2

0

CH

402

1

C7U9

C8G4

4.7UF 10% 16V X5R 1206

L7G1 2

1.6UH

R8U7

0

0

             2

VREG_VCS_VREF

1

1

V_VREG_VCS

V_12P0

TP

CPU_SRVID

402

GAI GAIN=2 N=20% WITH R7U7=10K, OUTPUT = CPU_SRVID D(1+GA (1+GAIN)

33.2K

1%

R8U R8U12= 12=49. 49.9K 9K

CH

402

2

VREG_VCS_COMP_R 1

2

C7U10 0.01UF 10% 16V X7R 402

DRAWING JASPER_FAB_B Wed J Ju ul 30 1 13 3: 1 17 7: 4 47 7

20 00 08

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 57/83

REV A

CR-58

:

@JASPER_LIB.JASPER(SCH_1):PAGE58

XD XDK, K,

J1D2 2X5HDR_10 35 35

OUT IN

SPI_SS_N SPI_MISO

2 4 6 8

1 3

SPI_MOSI SPI_CLK

V_5P0STBY

35

OUT OUT

5

DEBU DEBUG G CONNEC CONNECTO TORS RS

KER_DBG_RXD

35

33

OUT

7

9

C1D7

HDR

V_5P0STBY

.1UF 10% 6.3V X5R 402

R2P18 2

1

100 402

SMC_RST_N

IN

J9A2

27

1X2HDR

5% CH

1

2

V_3P3STBY SM HDR      N _      K      D      X _      T      S      R _      C      M      S

J2B1 2X7HDR_14

V_3P3 33

KER_DBG_TXD SMC_DBG_TXD SMC_DBG_EN

IN IN

34 34

OUT

2 4 6 8 10 12

SMB_CLK_R

1

2

27

34

BI

SMB_CLK

1

100 402

.1UF 10% 6.3V X5R 402

1UF 10% 16V X7R 603

1 3

7

9 11 13

R2N14 2

1

SMB_DATA_R

HDR

R2N13 2

.1UF 10% 6.3V X5R 402

C2B15

5

C1R2

.1UF 10% 6.3V X5R 402

C2B12

C9A3

100 402

5% CH

1

R3B3

EXT_PWR_ON_DBG

1K

402

5%

SMB_DATA

BI

27 34

V_12P0 2

EXT_PWR_ON_N

OUT

5%

4 4 5 8 34

CH

CH

1

V_5P0STBY

D8B4

2

GREEN SM LED

1

1

2

C3B8

CPU_CHECKSTOP_N_LED

R8B6

C3B9

.1UF 10% 6.3V X5R 402

1UF 10% 16V X7R 603

2K

1%

2

CH 402

CPU_CHECKSTOP_N_LED_B

CPU_CHECKSTOP_N_LED_C

3

R8A5

1 1K

402

2

Q8B6

1

5% CH

2

MMBT2222 XSTR

V_3P3STBY 2

V_1P8

V_1P8

R2P19 10K 5% CH

2

2

R8C3

1

4

R8C2

2

CPU_RST_V1P1_N

IN

1K

59 59 59 59

OUT OUT IN OUT

402

CPU_TMS CPU_TRST_N CPU_TDO CPU_TDI FT7R7

FTP

1

10K 5% EMPTY 402

2

R8C4

1

10K 5% EMPTY 402

2

R8C5

1

10K 5% EMPTY 402

R8C6

1

1

10K 5% EMPTY 402

2

.1UF 10% 6.3V X5R 402

1

1

CH

CPU_RST_N_2_R

2 4 6 8

1 CPU_CHECKSTOP_N_R

R8C8

1

3

0

5

402

7

10

9

2

402

SMC_CPU_CHKSTOP_DETECT BI

R8P8

C8P5

J8C1 2X5HDR

5%

1

2

10K SMC_CPU_CHKSTOP_DETECT_B 5% 3 EMPTY 1 R3N8 2 Q2P1 1 402 MMBT2222 1K 5% XSTR 402 CH 2

CPU_CHECKSTOP_N

IN

59

OUT OUT

59 44

34

5% CH

CPU_TCLK EXT_PWR_ON_N

58 34

HDR

1

C7D23 .1UF 10%

2 6.3V X5R 402

[PA [PAGE_T GE_TIT ITLE LE=X =XDK DK..

DEB DEBUG CONN CONN]]

DRAWING JASPER_FAB_B Wed J Ju ul 30 1 13 3: 1 17 7: 4 48 8

20 00 08

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 58/83

REV A

CR-59

:

@JASPER_LIB.JASPER(SCH_1):PAGE59

U4D1

V_GPUCORE

IC

7 OF 1 2 GP GPU U Y2 VERSI VERSION ON

DEBU DEBUG G BO BOAR ARD, D,

CPU CPU + GP GPU U DEBU DEBUG G BR BREA EAKO KOUT UT]] U7D1

1

TBCLK1 TBCLK0

58 58 58 58

G30 F32

IN IN IN IN

CPU_TCLK CPU_TDI CPU_TMS CPU_TRST_N

TCLK TDI TMS TRST_B

2 TB15 TB14 TB13 TB12 TB11 TB10 TB9 TB8 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0

D28 H29 E29 H30 C30 B30 A30 G31 B31 A31 B32 A32 F33 E33 D33 E34

C6T35 .1UF 10% 6.3V X5R 402

1

2

C7T90 .1UF 10% 6.3V X5R 402

1

2

C6T36 .1UF 10% 6.3V X5R 402

1

2

C7T91 .1UF 10% 6.3V X5R 402

V_GPUCORE

1

2

C6T12

.1UF 10% 6.3V X5R 402

1

2

C6T34 .1UF 10% 6.3V X5R 402

1

2

C7T92

.1UF 10% 6.3V X5R 402

1

2

TDO CHECKSTOP_B DEBUG_CLKOUT_DP DEBUG_CLKOUT_DN DEBUG_OUT0 DEBUG_OUT1 DEBUG_OUT2 DEBUG_OUT3 DEBUG_OUT4 DEBUG_OUT5 DEBUG_OUT6 DEBUG_OUT7 DEBUG_OUT8 DEBUG_OUT9 DEBUG_OUT10 DEBUG_OUT11 DEBUG_OUT12 DEBUG_OUT13 DEBUG_OUT14 DEBUG_OUT15 DEBUG_OUT16 DEBUG_OUT17 DEBUG_OUT18 DEBUG_OUT19 DEBUG_OUT20 DEBUG_OUT21 DEBUG_OUT22 DEBUG_OUT23 DEBUG_OUT24 DEBUG_OUT25 DEBUG_OUT26 DEBUG_OUT27 DEBUG_OUT28 DEBUG_OUT29 DEBUG_OUT30 DEBUG_OUT31 DEBUG_OUT32 DEBUG_OUT33 DEBUG_OUT34 DEBUG_OUT35 DEBUG_OUT36 DEBUG_OUT37 DEBUG_OUT38 DEBUG_OUT39 DEBUG_OUT40 DEBUG_OUT41 DEBUG_OUT42 DEBUG_OUT43 DEBUG_OUT44 DEBUG_OUT45 DEBUG_OUT46 DEBUG_OUT47 DEBUG_OUT48 DEBUG_OUT49 DEBUG_OUT50 DEBUG_OUT51 DEBUG_OUT52 DEBUG_OUT53 DEBUG_OUT54 DEBUG_OUT55 DEBUG_OUT56

V_GPUCORE

1

IC

3 O F 10 10 LOKI

AF5 AH6 AH2 AH5

C6T31

.1UF 10% 6.3V X5R 402

X02125-001

DEBUG_OUT57 DEBUG_OUT58 DEBUG_OUT59 DEBUG_OUT60 DEBUG_OUT61 DEBUG_OUT62 DEBUG_OUT63 DEBUG_OUT64 DEBUG_OUT65 DEBUG_OUT66 DEBUG_OUT67 DEBUG_OUT68 DEBUG_OUT69

CPU_TDO CPU_CHECKSTOP_N

AG5 AG1 D23 C23 F9 C8 E8

0

D7

3

B8 A8 F11 D9 C9 F13 A9 E10

4 5 6

C10 B10 E12 D11 A10 C11 A11 C12 F15 B12 E14 D13 C13 A12 C14 D15 C15 B14 E16 A13 A14 C16 B16 A15 A16 A17 D17 C17 F17 A18 B18 A19 C18 C19 D19 E18 C20 C21 E20 F19 A20 B26 B20 A21 A22 A26 B22 A24 A27 A23 A28 A25 F21 D21 B24 C22 E22 F23

12 13 14

1

2

OUT OUT

58 58

CPU_DBG_CLK_DP OUT CPU_DBG_CLK_DN OUT CPU_DBGSEL_XDK

OUT

47

N:CPU_DBGSEL_DEBUG N:CPU_DBGSEL_XDK

7

8 9 10

11

15 16

17 18 19 20 21 22 23 24 25 26 27 28 29

30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

X806937-001

[PAG [PAGE_ E_TI TITL TLE= E=DE DEBU BUG G

BO BOAR ARD, D,

CPU CPU + GPU GPU DE DEBU BUG G BR BREA EAKO KOUT UT]]

DRAWING JASPER_FABA We d Ju l 30 1 3 3:: 1 17 7: 4 49 9

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 59/83

REV A

CR-60

:

@JASPER_LIB.JASPER(SCH_1):PAGE67

IN INTE TELL LLIG IGEN ENT T

SE SERI RIAL AL

NUMB NUMBER ER TAR TARGE GET. T.

LB7G1 LABEL                                            1

1375X250_TARGET X801181-001

MIDDLE MIDDLE EDGE

EAS EAST T

EMPTY

EMPTY

EMPTY

GND=1,2,3,4,5,6,7,8 EDGE

GND=1,2,3,4,5,6,7,8 CTR

GND=1,2,3,4,5,6,7,8 EDGE

MTG1G1 MTG_HOLE 9 NC9

MTG9B1 MTG_HOLE 9 NC9

MTG5B1 MTG_HOLE 9 NC9

EMPTY

EMPTY

EMPTY

GND=1,2,3,4,5,6,7,8

GND=1,2,3,4,5,6,7,8

GND=1,2,3,4,5,6,7,8

HEAT HEAT SINK SINK STD MTG8C1 MTG_HOLE 9 NC9

MOUNTIN MOUNTING G HOLES HOLES STD MTG6E1 MTG_HOLE 9 NC9

EMPTY

EMPTY

GND=1,2,3,4,5,6,7,8

GND=1,2,3,4,5,6,7,8

STD MTG3C1 MTG_HOLE 9 NC9

STD MTG3E1 MTG_HOLE 9 NC9

EMPTY

EMPTY

GND=1,2,3,4,5,6,7,8

GND=1,2,3,4,5,6,7,8

STD MTG6C1 MTG_HOLE 9 NC9

STD MTG8E1 MTG_HOLE 9 NC9

EMPTY

EMPTY

GND=1,2,3,4,5,6,7,8

GND=1,2,3,4,5,6,7,8

STD MTG5C1 MTG_HOLE 9 NC9

STD MTG5E1 MTG_HOLE 9 NC9

EMPTY

GND=1,2,3,4,5,6,7,8

AND MO MOUN UNTI TING NG,,

PCI

PCB MOUNTING MOUNTING HOLE HOLES S EDGE MTG9G1 MTG_HOLE 9 NC9

CTR MTG5G1 MTG_HOLE 9 NC9

MTG1B1 MTG_HOLE 9 NC9

[PA [PAGE_TITL TITLE E=LABELS

PCB MOUNTIN MOUNTING G HOLES HOLES

SWIZ] IZ]

EMPTY

GND=1,2,3,4,5,6,7,8

DRAWING JASPER_FAB_B We d Ju l 30 1 3 3:: 1 17 7: 5 50 0

2008

MICROSOFT

CONFIDENTIAL

PRO PROJEC JECT T H08580

NAME NAM E

PAGE 67/83

REV A

XBOX360 FAT Jasper FabB Retail RevA

Short Description

Description

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