Xbox 360 Trinity Schematic
September 5, 2022 | Author: Anonymous | Category: N/A
Short Description
Download Xbox 360 Trinity Schematic...
Description
CR-1 : @TRINITY_LIB.TRINITY(SCH_1):PAGE1
8
7
PAGE D
C
B
A
[1] [2] [3] [4]
6
CONTENTS COVER GCPU, GCPU, GCPU,
5
3
CONTENTS
PAGE
PAGE SETUP DEBUG BUS VIDEO + PCIEX PCIEX
4
[35] [36] [37] [38]
INFRARED+SWITCHES+ACCELEROMETER+AUDIBLE INFRARED+SWITCHES+ACCELEROMETER+AUDIBLE F/B CONN, FAN CONN, AVIP CONN, RJ45 USB AUX COMBO + BORON + PWR
[5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29]
GCPU, EEPROM GCPU, PLL PWR+ +JTAG FSB PWR GCPU, PWR GCPU, PWR GCPU, DECOUPLING GCPU, DECOUPLING GCPU, DECOUPLING GCPU, MEMORY MEMORY CONTROLLER CONTROLLER A + B GCPU, MEMORY MEMORY CONTROLLER CONTROLLER C + D MEMORY PARTITION A, TOP MEMORY PARTITION A, BOTTOM MEMORY PARTITION B, TOP MEMORY PARTITION B, BOTTOM MEMORY PARTITION C, TOP MEMORY PARTITION C, BOTTOM MEMORY PARTITION D, TOP MEMORY PARTITION D, BOTTOM HANA, CLOCKS CLOCKS + STRAPING + JTAG HANA, VIDEO + FAN + AUDIO HANA, POWER + DECOUPLING DECOUPLING HANA, POWER + DECOUPLING DECOUPLING PSB, PCIEX + SMM GPIO GPIO + JTAG JTAG PSB, SMC PSB, FLASH + USB + SPI PSB, ETHERNET ETHERNET + AUDIO + SATA
[39] [40] [41] [42] [43] [44] [45] [46] [47] [48] [49] [50] [51] [52] [53] [54] [55] [56] [57] [58] [59] [60] [61] [62] [63]
CONN, USB + MEM PORTS + TOSLINK + WAVEPORT WAVEPORT CONN, HDMI CONN, ODD + HDD VREGS, BLEEDERS VREGS, INPUT INPUT + OUTPUT FILTERS VREGS, CPU CONTROLLER VREGS, CPU OUTPUT PHASE 1 & 2 VREGS, V5P0DUAL VREGS, V5P0 VREGS, V3P3 VREGS, VEDRAM VREGS, VMEM VREGS, VCS VREGS, 1P8+GPUPCIE+SBPCIE+CPUPLL+EFUSE 1P8+GPUPCIE+SBPCIE+CPUPLL+EFUSE VREGS, STANDBY SWITCHERS BOARD, DECOUPLING MARGIN, VMEM + VEDRAM VEDRAM MARGIN, V3P3 + V5P0 V5P0 MARGIN, VREFS + VCS MARGIN, VGPUPCIE+VSBPCIE+VCPUPLL+V12P0+TEMP VGPUPCIE+VSBPCIE+VCPUPLL+V12P0+TEMP XDK, DEBUG CONN XDK, DEBUG TITAN DEBUG BOARD, SPYDER CONN LABELS & MOUNTING POWER DIAGRAM
[30] [31] [32] [33] [34]
PSB, STANDBY STANDB Y POWER + DECOUPLING DECOUPLIN PSB, MAIN MAIN POWER + DECOUPLING DECO UPLING G SB OUT, ETHERNET SB OUT, AUDIO SB OUT, FLASH
[64] [65] [66] [67]
CLOCK DIAGRAM DIAGRAM RESET REFERENCE TABLES DOC TRACKING
2
1
TRINITY
D
REV 1.01
FAB G RETAIL
C
B
RULES: (APPLIED WHEN POSSIBLE) 1.) MSB TO LSB IS TOP TO BOTTOM 2.) WHEN POSSIBLE: INPUTS ON LEFT, OUTPUTS ON RIGHT 3.) ORDER OF PAGES=CHIP INTERFACES, TERMINATION, POWER, DECOUPLING 4.) AVOID USING OFF PAGE CONNECTORS FOR ON PAGE CONNECTIONS 5.) LANED SIGNALS ARE GROUPED ON SYMBOLS 6.) TRANSIMITTER NAME USED AS PREFIX WITH RX AND TX CONNECTIONS 7.) SUFFIX V_ IS USED FOR VOLTAGE RAIL SIGNAL NAMES 8.) SUFFIX _DP AND _DN ARE USED FOR DIFFERIENTAL PAIRS 9.) UNNAMED NETS ARE NAMED WITH /2 TEXT SIZE 10.) SUFFIX _N FOR ACTIVE LOW OR N JUNCTION 12.) SUFFIX _P FOR P JUNCTION 13.) SUFFIX _EN FOR ENABLE 14.) 'CLK' FOR CLOCKS, 'RST' FOR RESETS 15.) PWRGD FOR POWER GOOD 16.) REV AND FAB ARE SET USING CUSTOM CUSTOM VARIABLES. TOOLS>OPTIONS>VARIABLES TOOLS>OPTIONS>VARIABLES
A
[PAGE_TITLE=COVER PAGE] 8
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DRAWING Wed Feb 10 16:23:24 2010
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4
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MICROSOFT CONFIDENTIAL
2
PROJECT NAME TRINITY_XDK
PAGE 1/81
FAB G
1
REV 1.01
CR-2 : @TRINITY_LIB.TRINITY(SCH_1):PAGE2
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2
1
GCPU SETUP 27
R4D4 2 1
CPU_RST_N
IN
FT4R2 FTP
1
FT5R18 FTP
1
1
CPU_CLK_DP
IN
U5E1
B
FT4T2 FTP
1
R4D1 2 1
P2
CPU_CLK_DP
E5
CPU_CHECKSTOP_N
OUT
60
C24 B24 A24 C23 B23 A23
CPU_VREG_APS6 CPU_VREG_APS5 CPU_VREG_APS4 CPU_VREG_APS3 CPU_VREG_APS2 CPU_VREG_APS1
OUT OUT OUT OUT OUT OUT
43 43 43 43 43 43
0 OH M 5 % CH 402
IN
CPU_CLK_DN
IN
CPU_CLK_DN_R2
R4D2 2 1 0 OHM 402
C
562 OHM 1% 2 CH 402
T5
14 OF 17 IC GCPU VERSION 1 HARD_RESET_B CHECKSTOP_B POWER_GOOD
D5
CPU_CLK_DP_R2
IN
1 R4T5
D
402
5%
WHEN V_CPUPLL=1.83V SET VGATE=1.20V ACTUAL=1.202V
60
CPU_PWRGD
IN
603
V_CPUPLL
OUT
2 KOHM 1%
603
V 2 50 EMPTY
22
CPU_RST_V1P1_N 1 R4D5 2 CH
50 V 2 EMPTY
C4T1PF 1 360
22
1% CH
360 PF 5%
D 27
C5R11
1.27 KOHM 402
VID6 VID5 VID4 VID3 VID2 VID1
5% CH P1
CPU_DBG_RST_EN
INTERNAL PULLDN
GPU_DBG_RST_EN
INTERNAL PULLDN
CPU_CLK_DN
1 1 1 1 1 1
OUT OUT
CPU_DBG_RST_EN GPU_DBG_RST_EN
P5 R5
CPU_DBG_RST_EN GPU_DBG_RST_EN
OUT OUT
EDRAM_PSRO_DOUT CPU_PSRO0_OUT
N6 G7
PSRO_DOUT PSRO0_OUT
FTP FTP FTP FTP
C
FT7P8 FT7P7 FT7P6 FT7P5
FTP FT7P4 FTP FT7P3
N: IF V_CPUPLL CHANGES VGATE RESISTORS SHOULD BE ADJUSTED
CPU_VGATE
V6
OUT OUT
RESISTOR0_DP RESISTOR0_DN
L7 M7
OUT
CPU_EXT_CLK_EN
PULSE_LIMIT_BYPASS
J6
V_GATE
F8
PLL_BYPASS
CPU_LIMIT_BYPASS
OUT
CPU_PLL_BYPASS
OUT
CPU_SRVID VREG_EFUSE_EN
OUT OUT
CORE_HF_BGR_PLL
OUT
B
1 R4T6
1.07 KOHM 1%
2 CH
402
F7 J7 E7
CPU_TINIT
RESISTOR0_DP RESISTOR0_DN
SRVID EFU_POWERON
A3 C1
EXT_CLK_EN TI_39_TINIT TE CORE_HF_BGR_PLL
M6
1 R5R1
200 OHM 5% 2 CH 402
51 52
X818336-001
BGA_2
6 LAYER ONLY SIGNALS
A
CORE_HF_BGR_PLL
6 LAYER ONLY; TP ONLY
CPU_LIMIT_BYPASS
6 LAYER ONLY; TP ONLY, INTERNAL PULLDN
CPU_PLL_BYPASS
6 LAYER ONLY; TP ONLY, INTERNAL PULLDN
CPU_CORE_HF_CLKOUT_DN
6 LAYER ONLY; TP ONLY
CPU_CORE_HF_CLKOUT_DP
6 LAYER ONLY; TP ONLY
CPU_EXT_CLK_EN
6 LAYER ONLY; TP ONLY, INTERNAL PULLDN
CPU_DLL_SNIF_OUT
6 LAYER ONLY; TP ONLY
CPU_VDDS0_DP
[PAGE_TITLE=GCPU SETUP] 8
7
6
A
6 LAYER ONLY
CPU_VDDS0_DN
6 LAYER ONLY
CPU_VDDS1_DP
6 LAYER ONLY
CPU_VDDS1_DN
6 LAYER ONLY
RESISTOR0_DP
6 LAYER ONLY
RESISTOR0_DN
6 LAYER ONLY
EDRAM_PSRO_DOUT
6 LAYER ONLY
5
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MICROSOFT CONFIDENTIAL
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FAB G
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REV 1.01
CR-3 : @TRINITY_LIB.TRINITY(SCH_1):PAGE3
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1
GCPU, DEBUG BUS D
D
FT5T2 FTP
OUT
CPU_DLL_SNIF_OUT
W6
OUT OUT
CPU_DBG_TBCLK1 CPU_DBG_TBCLK0
B5 A4
FT5P1 FTP FT5P2 FTP
1 1 B27 H6 J4 K7 L4 AJ30 AP26 AP7
C
15 of 17
U5E1
1CPU_DLL_SNIF_OUT_TP
IC
GCPU VERSION 1 TB15_GPUCLK1 DLL_SNIF_OUT TB14_GPUCLK0 TB13_CPUCLK1 TBCLK1 TB12_CPUCLK0 TBCLK0 TB11_GPU_HB TB10_RESET2 TB9_RESET1 TB8_RESET0 TB7_POST_OUT7 SPARE7 TB6_POST_OUT6 SPARE6 TB5_POST_OUT5 SPARE5 TB4_POST_OUT4 SPARE4 TB3_POST_OUT3 SPARE3 TB2_POST_OUT2 SPARE2 TB1_POST_OUT1 SPARE1 TB0_POST_OUT0 SPARE0
10 9 8 7 6 5 4 3 2 1 0
F6 G6 G5 F5 H5
POST_IN4 POST_IN3 POST_IN2 POST_IN1 POST_IN0 X818336-001
CPU_DBG
B9 D7 E8 D6 D9 C8 A8 D8 C5 A5 B6 C6 A6 C7 A7 B8
FTP FTP FTP FTP FTP
4 3 2 1 0
4
3
2
1
R4R5 1
R4R3 1
R4R8 1
R4R6 1 R4R13
5% 2 EMPTY 402
5% 2 EMPTY 402
5% 2 EMPTY 402
200 OHM
200 OHM
200 OHM
C
0
5% 2 EMPTY 402
200 OHM
1 1 1 1 1
3
ALL POST IN'S HAVE INTERNAL PULLUPS POST_IN
BGA_2
FT4R6 FT4R4 FT4R8 FT4R7 FT4R9
OUT
200 OHM
1
5% 2 EMPTY 402
4 3 2 1 0
B
B
3
IN
CPU_DBG
CPU_DBG15_GPUCLK1_TP CPU_DBG14_GPUCLK0_TP CPU_DBG13_CPUCLK1_TP CPU_DBG12_CPUCLK0_TP CPU_DBG11_GPU_HB_TP CPU_DBG10_RST2 10 CPU_DBG9_RST1 9 CPU_DBG8_RST0 8 CPU_DBG7_POST7 7 CPU_DBG6_POST6 6 CPU_DBG5_POST5 5 CPU_DBG4_POST4 4 CPU_DBG3_POST3 3 CPU_DBG2_POST2 2 CPU_DBG1_POST1 1 CPU_DBG0_POST0 0
A
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FTP FTP FTP FTP FTP FTP FTP FTP FTP FTP FTP FTP FTP FTP FTP FTP
[PAGE_TITLE=GCPU, DEBUG BUS] 8
7
FT5R9 FT5R12 FT5R13 FT5R11 FT5R16 FT5R15 FT5R10 FT5R14 FT5R1 FT5R2 FT5R3 FT5R4 FT5R5 FT5R6 FT5R7 FT5R8
A
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CR-4 : @TRINITY_LIB.TRINITY(SCH_1):PAGE4
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1
GCPU, VIDEO + PCIEX D
22
IN OUT
22
IN OUT
0 OHM 402
R4E2 1 2
GPU_CLK_DN
0 OHM 402
D
C4E1 0.1 UF 10% 6.3 V X5R 402 1 2
5% CH
GPU_CLK_DP_C
1
5% CH
5 OF 17
U5E1
2
GPU_CLK_DN_R2
R2
R1
NB_CLK_DP
NB_CLK_DN
IN
GPU_RST_N
D2
RST_IN_N*
IN IN IN IN
PEX_SB_GPU_L1_DP PEX_SB_GPU_L1_DN PEX_SB_GPU_L0_DP PEX_SB_GPU_L0_DN
T2 T1 V2 V1
PEX_RX1_DP PEX_RX1_DN PEX_RX0_DP PEX_RX0_DN
22 22
IN IN
HANA_PIX_CLK_2X_DP HANA_PIX_CLK_2X_DN
N1 N2
PIX_CLK_IN_DP PIX_CLK_IN_DN
V3
PEX_RCAL
PEX_RCAL
4.99 KOHM 1%
402
GPU_TEMP_P 1
P4
NB_THERMD_P
P3
NB_THERMD_N
V4
ED_THERMD_P
C4C2
100 PF 5%
23
GPU_TEMP_N
IN
EDRAM_TEMP_P
50 V 2 EMPTY 402
1
B
23 61 23
OUT
EDRAM_TEMP_N
IN
CPU_TEMP_P
PEX_TX1_DP
U2
PEX_TX0_DN
1 CH
OUT
U6
PEX_TX0_DP
2 R5T1
23 61
RST_DONE
PEX_TX1_DN
26 26 26 26
IN
1
U1
2
1
C4C6
100 PF 5% 50 V EMPTY 402
V5
ED_THERMD_N
M5
CPU_THERMD_P
L5
CPU_THERMD_N
W2
W1
FTP FT3R16
GPU_RST_DONE 1 C5E2 2
PEX_GPU_SB_L1_DP_C
PEX_GPU_SB_L1_DN_C
PEX_GPU_SB_L1_DP
F2 F1 F3 G2
14 13 12 11
G1 H3 H2 H1 J1 K3 K2 K1 L2 L1 M3
10 9 8 7 6 5 4 3 2 1 0
VSYNC_OUT HSYNC_OUT
M1 M2
26
OUT
26
PEX_GPU_SB_L0_DP
OUT
26
0.1 UF 10% 6.3 V X5R C5E3 402 1 2
PEX_GPU_SB_L0_DN
OUT
26
OUT
23
PIX_DATA
OUT
23
GPU_VSYNC_OUT GPU_HSYNC_OUT
OUT OUT
23 23
OUT OUT OUT
14 15 16 17 18 19 20 21 14 15 16 17 18 19 20 21 14 16 18 20
1
C5E4
0.1 UF 10% 6.3 V X5R 402
PIX_DATA14 PIX_DATA13 PIX_DATA12 PIX_DATA11 PIX_DATA10 PIX_DATA9 PIX_DATA8 PIX_DATA7 PIX_DATA6 PIX_DATA5 PIX_DATA4 PIX_DATA3 PIX_DATA2 PIX_DATA1 PIX_DATA0
OUT
0.1 UF 10% 6.3 V X5R 2 402
PEX_GPU_SB_L0_DN_C
J2
27
PEX_GPU_SB_L1_DN
PEX_GPU_SB_L0_DP_C
PIX_CLK_OUT
OUT
0.1 UF 10% 6.3 V X5R C5E1 402 1 2
402
1
27
23
IC
GCPU VERSION 1 GPU_CLK_DP_R2
C4E2 0.1 UF 10% 6.3 V X5R
GPU_CLK_DN_C FT3R17 FTP
C
R4E1 1 2
GPU_CLK_DP
GPU_PIX_CLK_1X
C
B
C4C7
100 PF 5%
23 61
OUT
CPU_TEMP_N
50 V 2 EMPTY 402
MEM_CALA MEM_CALB
2 R6T3
240 OHM 1% 1 CH 402
2 R6T6
240 OHM 1%
W27 AG18
MEM_CALA MEM_CALB
MEM_RST MEM_SCAN_EN MEM_SCAN_OEN_A MEM_SCAN_OEN_B
X818336-001
MEM_RST MEM_SCAN_EN MEM_SCAN_TOP_EN
AD27 AB33 AF7 AE7
BGA_2
1 CH
1 R7T7
1 R7R6
2 R6F6
2 R7E2
2 CH
2 CH
1 CH
1 CH
1 KOHM 5% 402
402
1 KOHM 5% 402
1 KOHM 5%
IC
U5U2
A
5 VCC MEM_SCAN_BOT_EN_N
C5T36 R5U6 1
1 KOHM 5% CH 402 2
[PAGE_TITLE=GCPU, VIDEO + PCIEX] 8
7
5
4
A
74LVC1G06
2 A 1 DNU
Y
4 MEM_SCAN_BOT_EN
OUT
15 17 19 21
3 GND X801851-001
DRAWING Wed Feb 10 16:23:24 2010
6
402
V_MEM
VIDEO DECOUPLING V_MEM
0.1 UF 10% 6.3 V X5R 402
1 KOHM 5%
402
3
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PAGE 4/81
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CR-5 : @TRINITY_LIB.TRINITY(SCH_1):PAGE5
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GCPU, EEPROM + JTAG D
D
V_MEM FT4P8 FT4P6 FT4P5 FT4P4 FT4P7 60 60 60 60 60
C
60
FTP FTP FTP FTP FTP
1 1 1 1 1
CPU_TCLK CPU_TDO CPU_TDI CPU_TMS CPU_TRST_N
OUT
CPU_TRST_N_R
C2 B1 B2 B4 A2
V_MEM
60 60
OUT OUT
1
GPU_TRST_N GPU_TRST_ED_N FT4P1 FTP
CPU_TCLK CPU_TDO CPU_TDI CPU_TMS CPU_TRST_B
R4P9 1 2 5% 0 OHM CH 402
FT4P2 FTP
100 OHM 5%
IC
17 of 17
1 EMPTY 402
GCPU VERSION 1
OUT OUT OUT OUT OUT
V_MEM
2 R4R2 U5E1
V_MEM
1 R4C8
1 R4C5
2 EMPTY
2 EMPTY
100 OHM 5% 402
1
E3
GPU_SROM_EN
SROM_SCLK
D3
GPU_SROM_SCLK
SROM_SI
E1
GPU_SROM_SO
V_MEM
2 R4R12
V_MEM
10 KOHM 5% 1 CH 402
200 OHM 5% 2 EMPTY 402
R4R11 1 2
1 KO KO HM HM 5 % 402 CH SROM_CS
D1
GPU_SROM_CS
R4R7 1 2
1 KO KO HM HM 5 % CH 402
SCK
5
SDI
7 1 3
HOLD_N* CS_N* WP_N*
VCC
8
SDO
2
1 C4R4
GND
4
6.3 V 2 X5R
0.1 UF 10% 402
X800552-001
402
2
AT25020A
6
1 KOHM 5% CH 402
1 R4C3
C
EMPTY
U4R2
R4R9 1 2
100 OHM 5%
1
B
1
SROM_EN
DB4R1 TP
R6 U5
C4C8
SROM_SO
GPU_TRST_B GPU_TRST_ED_B
1 R4R10
10 KOHM 5%
X818336-001
0.01 UF 10% 16 V EMPTY 402
E2
BGA_2
GPU_SROM_CLK_R GPU_SROM_SO_R GPU_SROM_CS_N_R GPU_SROM_WP_N GPU_SROM_SI
2 EMPTY 402
IN IN IN IN OUT
60 60 60 60 60
B
A
A
[PAGE_TITLE=GCPU, [PAGE_TITLE=GC PU, EEPROM + JTAG] 8
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CR-6 : @TRINITY_LIB.TRINITY(SCH_1):PAGE6
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6
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GCPU, PLL POWER + FSB POWER V_GPUPCIE
V_CPUEDRAM
V_CPUPLL
V_EFUSE
16 of 17
U5E1
IC
GCPU VERSION 1
D
E4
VDDE
CORE_HF_CLKOUT_DP CORE_HF_CLKOUT_DN
OUT OUT
CPU_VDDS1_DP CPU_VDDS1_DN
H25 J26
VDDS1_DP VDDS1_DN
OUT OUT
CPU_VDDS0_DP CPU_VDDS0_DN
P7 N7
VDDS0_DP VDDS0_DN
V_CPU_PVDDA_MEM
D4
PVDDA_MEM
V_CPU_PVSSA_MEM
C4
PVSSA_MEM
V_CPU_PVDDA_PEX
U3
PVDDA_PEX
V_CPU_PVSSA_PEX
U4
PVSSA_PEX
V_CPU_PVDDA_HS
C3
PVDDA_HS
B3
PVSSA_HS
V_CPU_PVDDA_ED
W5
PVDDA_ED
V_CPU_PVSSA_ED
W4
PVSSA_ED
V_CPU_VDDA_RNG
N4
VDDA_RNG
V_CPU_GNDA_RNG
N3
GNDA_RNG
V_CPU_CORE_HF_VDDA_PLL
J5
CORE_HF_VDDA_PLL
V_CPU_CORE_HF_GNDA_PLL
K5
CORE_HF_GNDA_PLL
V_GPU_VDDA_PLL
G4
GPU_VDDA_PLL
V_GPU_GNDA_PLL
H4
GPU_GNDA_PLL
R3
VDD_VTT
1FB5R12 FB 0.2A 603 0.5 DCR 1
L6 K6
CPU_CORE_HF_CLKOUT_DP CPU_CORE_HF_CLKOUT_DN
OUT OUT
D
1 C5R14 ST5R1
2
2
10 UF 20% 6.3 V X5R 805
SHORT
FB5T2 1 0.2A 0.5 DCR
2 FB 603
1 C5T9 1
C
ST5T1
22
10 UF 20% 6.3 V X5R 805
C
SHORT
FB5R2 1
2 FB 603
0.2A 0.5 DCR
1 C5R17 10 UF 20% 6.3 V
ST5R2 1
2 X5R 2
V_CPU_PVSSA_HS
805
SHORT
FB5T3 1
2 FB 603
0.2A 0.5 DCR
1
1 ST5T2
2
2
C5T13
4.7 UF 10% 6.3 V X5R 805
SHORT
B
1
0.2A 0.5 DCR
2 FB 603 1
ST5R5
1
DB5R5
FB5R5
C5R54 1 10 UF 2
2
20% 6.3 V X5R 805
B
SHORT
FB5R4
1
2
0.2A 0.5 DCR
1 10 C5R42 UF
FB 6 03 1
ST5R4
20% 6.3 V
2
2 X5R 805
SHORT
FB5R3 1 0.2A 0.5 DCR
2 FB 603
1
C5R31
10 UF 20%
1
ST5R3
V 2 6.3 X5R
2
805
SHORT
A
A
FB5T1 1 0.2A 0.5 DCR
2 FB 603
7
6
C5T4
4.7 UF 10%
6.3 V 2 X5R
[PAGE_TITLE=GCPU, PLL POWER + FSB POWER] 8
R4
V_CPU_VDD_VTTA
1
805
5
1
C5T6
0.1 UF 10%
6.3 V 2 X5R 402
4
VDD_VTTA X818336-001
BGA_2
DRAWING Wed Feb 10 16:23:24 2010
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GCPU, POWER D
D
V_CPUVCS
V_CPUVCS
V_MEM
V_MEM 8 OF 17
U5E1 U5E1
C
6 OF 17
V_CS28 V_CS27 V_CS26 V_CS25 V_CS24 V_CS23 V_CS22 V_CS21
X818336-001
B
IC
GCPU VERSION 1
A11 A9 B10 C11 C9 D10 E11 E9
R7 T6 U7 W7 Y11 Y10 Y8 Y6 Y4 Y2 Y1 AA11 AA10 AA9 AA8 AA7 AA6 AA5 AA4 AA3 AA2 AA1 AB10 AB8
A
GCPU VERSION 1 F10 G11 G9 H10 H8 J9 K10 K8 L9 M10 M8 N9 P10
A33 B34 C31 C29 C27 D32 D30 D28 D25 E31 E26 F32 F28
V_MEM111 V_MEM110 V_MEM109 V_MEM108 V_MEM107 V_MEM106 V_MEM105 V_MEM104 V_MEM103 V_MEM102 V_MEM101 V_MEM100 V_MEM99
V_MEM56 V_MEM55 V_MEM54 V_MEM53 V_MEM52 V_MEM51 V_MEM50 V_MEM49 V_MEM48 V_MEM47 V_MEM46 V_MEM45 V_MEM44
AG23 AG20 AG17 AG15 AG13 AG10 AG7 AG4 AH32 AH29 AH27 AH24 AH19
V_CS7 V_CS6 V_CS5 V_CS4 V_CS3 V_CS2 V_CS1 V_CS0
P8 R9 T10 T8 U9 V10 V8 W9
G31 G29 G27 G25 H32 H28 H26 J32 J29 K27 L31 L28 M30 M27 N29 P31 P29 R27 T32 T28 V31 V27 W32 W29 Y27
V_MEM98 V_MEM97 V_MEM96 V_MEM95 V_MEM94 V_MEM93 V_MEM92 V_MEM91 V_MEM90 V_MEM89 V_MEM88 V_MEM87 V_MEM86 V_MEM85 V_MEM84 V_MEM83 V_MEM82 V_MEM81 V_MEM80 V_MEM79 V_MEM78 V_MEM77 V_MEM76 V_MEM75 V_MEM74
V_MEM43 V_MEM42 V_MEM41 V_MEM40 V_MEM39 V_MEM38 V_MEM37 V_MEM36 V_MEM35 V_MEM34 V_MEM33 V_MEM32 V_MEM31 V_MEM30 V_MEM29 V_MEM28 V_MEM27 V_MEM26 V_MEM25 V_MEM24 V_MEM23 V_MEM22 V_MEM21 V_MEM20 V_MEM19
AH14 AH9 AH8 AH6 AH3 AJ31 AJ28 AJ26 AJ22 AJ21 AJ16 AJ12 AJ11 AJ7 AJ4 AK32 AK23 AK13 AK3 AL31 AL29 AL27 AL24 AL21 AL17
AA31 AA28 AB30 AB27 AC29 AD31 AD29 AE8 AE4 AF32 AF28 AF27 AF6 AF3 AG31 AG28 AG25
V_MEM73 V_MEM72 V_MEM71 V_MEM70 V_MEM69 V_MEM68 V_MEM67 V_MEM66 V_MEM65 V_MEM64 V_MEM63 V_MEM62 V_MEM61 V_MEM60 V_MEM59 V_MEM58 V_MEM57
V_MEM18 V_MEM17 V_MEM16 V_MEM15 V_MEM14 V_MEM13 V_MEM12 V_MEM11 V_MEM10 V_MEM9 V_MEM8 V_MEM7 V_MEM6 V_MEM5 V_MEM4 V_MEM3 V_MEM2 V_MEM1 V_MEM0
AL14 AL11 AL8 AL6 AL4 AM34 AM30 AM28 AM26 AM19 AM16 AM9 AM7 AM5 AM3 AN33 AN1 AP34 AP2
BGA_2
V_CPUEDRAM U5E1
7 OF 17
IC
GCPU VERSION 1 V_EDRAM47 V_EDRAM23 V_EDRAM46 V_EDRAM22 V_EDRAM45 V_EDRAM21 V_EDRAM44 V_EDRAM20 V_EDRAM43 V_EDRAM19 V_EDRAM42 V_EDRAM18
AB6 AB4 AB2 AC11 AC10 AC9
V_EDRAM41 V_EDRAM40 V_EDRAM39 V_EDRAM38 V_EDRAM37 V_EDRAM36 V_EDRAM35 V_EDRAM34 V_EDRAM33 V_EDRAM32 V_EDRAM31 V_EDRAM30 V_EDRAM29 V_EDRAM28 V_EDRAM27 V_EDRAM26 V_EDRAM25 V_EDRAM24
AC8 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AD11 AD10 AD8 AD6 AD4 AD2 AD1 AE11 AE9 AF10
X818336-001
V_EDRAM17 V_EDRAM16 V_EDRAM15 V_EDRAM14 V_EDRAM13 V_EDRAM12 V_EDRAM11 V_EDRAM10 V_EDRAM9 V_EDRAM8 V_EDRAM7 V_EDRAM6 V_EDRAM5 V_EDRAM4 V_EDRAM3 V_EDRAM2 V_EDRAM1 V_EDRAM0
V_CPUCORE U5E1
V_CS20 V_CS19 V_CS18 V_CS17 V_CS16 V_CS15 V_CS14 V_CS13 V_CS12 V_CS11 V_CS10 V_CS9 V_CS8
V_CPUEDRAM
V_CPUCORE
IC
GCPU VERSION 1 VDD_CORE91 VDD_CORE45 VDD_CORE90 VDD_CORE44 VDD_CORE89 VDD_CORE43 VDD_CORE88 VDD_CORE42 VDD_CORE87 VDD_CORE41 VDD_CORE86 VDD_CORE40 VDD_CORE85 VDD_CORE39 VDD_CORE84 VDD_CORE38 VDD_CORE83 VDD_CORE37 VDD_CORE82 VDD_CORE36 VDD_CORE81 VDD_CORE35 VDD_CORE80 VDD_CORE34 VDD_CORE79 VDD_CORE33 VDD_CORE78 VDD_CORE32 VDD_CORE77 VDD_CORE31 VDD_CORE76 VDD_CORE30 VDD_CORE75 VDD_CORE29 VDD_CORE74 VDD_CORE28 VDD_CORE73 VDD_CORE27 VDD_CORE72 VDD_CORE26 VDD_CORE71 VDD_CORE25 VDD_CORE70 VDD_CORE24 VDD_CORE69 VDD_CORE23 VDD_CORE68 VDD_CORE22 VDD_CORE67 VDD_CORE21 VDD_CORE66 VDD_CORE20 VDD_CORE65 VDD_CORE19 VDD_CORE64 VDD_CORE18 VDD_CORE63 VDD_CORE17 VDD_CORE62 VDD_CORE16 VDD_CORE61 VDD_CORE15 VDD_CORE60 VDD_CORE14 VDD_CORE59 VDD_CORE13 VDD_CORE58 VDD_CORE12 VDD_CORE57 VDD_CORE11 VDD_CORE56 VDD_CORE10 VDD_CORE55 VDD_CORE9 VDD_CORE54 VDD_CORE8 VDD_CORE53 VDD_CORE7 VDD_CORE52 VDD_CORE6 VDD_CORE51 VDD_CORE5 VDD_CORE50 VDD_CORE4 VDD_CORE49 VDD_CORE3 VDD_CORE48 VDD_CORE2 VDD_CORE47 VDD_CORE1 VDD_CORE46 VDD_CORE0
R23 R21 R19 R17 R15 R13 R11 T26 T24 T22 T20 T18 T16 T14 T12 U25 U23 U21 U19 U17 U15 U13 U11 V26 V24 V22 V20 V18 V16 V14 V12 W25 W23 W21 W19 W17 W15 W13 W11 Y26 Y24 Y22 Y20 Y18 Y16 Y14
X818336-001
V_CPUCORE
V_CPUCORE U5E1
IC Y12 AA25 AA23 AA21 AA19 AA17 AA15 AA13 AB26 AB24 AB22 AB20 AB18 AB16 AB14 AB12 AC25 AC23 AC21 AC19 AC17 AC15 AC13 AD26 AD24 AD22 AD20 AD18 AD16 AD14 AD12 AE25 AE23 AE21 AE19 AE17 AE15 AE13 AF26 AF24 AF22 AF20 AF18 AF16 AF14 AF12
10 OF 17
IC
A21 A19 A17 A15 A13 B22 B20 B18 B16 B14 B12 C21 C19 C17
GCPU VERSION 1 VDD_CORE143 VDD_CORE189 VDD_CORE142 VDD_CORE188 VDD_CORE141 VDD_CORE187 VDD_CORE140 VDD_CORE186 VDD_CORE185 VDD_CORE139 VDD_CORE184 VDD_CORE138 VDD_CORE137 VDD_CORE183 VDD_CORE136 VDD_CORE182 VDD_CORE135 VDD_CORE181 VDD_CORE134 VDD_CORE180 VDD_CORE133 VDD_CORE179 VDD_CORE132 VDD_CORE178 VDD_CORE131 VDD_CORE177 VDD_CORE130 VDD_CORE176
H16 H14 H12 J25 J23 J21 J19 J17 J15 J13 J11 K26 K24 K22
C15 C13 D24 D22 D20 D18 D16 D14 D12 E23 E21 E19 E17 E15 E13 F24 F22 F20 F18 F16 F14 F12 G23 G21 G19
VDD_CORE175 VDD_CORE174 VDD_CORE173 VDD_CORE172 VDD_CORE171 VDD_CORE170 VDD_CORE169 VDD_CORE168 VDD_CORE167 VDD_CORE166 VDD_CORE165 VDD_CORE164 VDD_CORE163 VDD_CORE162 VDD_CORE161 VDD_CORE160 VDD_CORE159 VDD_CORE158 VDD_CORE157 VDD_CORE156 VDD_CORE155 VDD_CORE154 VDD_CORE153 VDD_CORE152 VDD_CORE151
VDD_CORE129 VDD_CORE128 VDD_CORE127 VDD_CORE126 VDD_CORE125 VDD_CORE124 VDD_CORE123 VDD_CORE122 VDD_CORE121 VDD_CORE120 VDD_CORE119 VDD_CORE118 VDD_CORE117 VDD_CORE116 VDD_CORE115 VDD_CORE114 VDD_CORE113 VDD_CORE112 VDD_CORE111 VDD_CORE110 VDD_CORE109 VDD_CORE108 VDD_CORE107 VDD_CORE106 VDD_CORE105
K20 K18 K16 K14 K12 L25 L23 L21 L19 L17 L15 L13 L11 M26 M24 M22 M20 M18 M16 M14 M12 N25 N23 N21 N19
G17 G15 G13 H24 H22 H20 H18
VDD_CORE150 VDD_CORE149 VDD_CORE148 VDD_CORE147 VDD_CORE146 VDD_CORE145 VDD_CORE144
VDD_CORE104 VDD_CORE103 VDD_CORE102 VDD_CORE101 VDD_CORE100 VDD_CORE99 VDD_CORE98 VDD_CORE97 VDD_CORE96 VDD_CORE95 VDD_CORE94 VDD_CORE93 VDD_CORE92
N17 N15 N13 N11 P26 P24 P22 P20 P18 P16 P14 P12 R25
BGA_2
X818336-001
C
B
BGA_2
A
BGA_2 X818336-001
BGA_2
[PAGE_TITLE=GCPU, POWER] 8
9 OF 17
7
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GCPU, POWER D
U5E1
11 OF 17
C
B
D
IC
GCPU VERSION 1
U5E1 AF15 AF13 AF11
Y3 AA32
VSS130 VSS129
VSS65 VSS64 VSS63
AA27 AA26 AA24 AA22 AA20 AA18 AA16 AA14 AA12 AB25 AB23 AB21 AB19 AB17 AB15 AB13 AB11 AB9 AB7 AB5 AB3 AB1 AC31 AC27 AC26
V VS SS S1 12 28 7 VSS126 VSS125 VSS124 VSS123 VSS122 VSS121 VSS120 VSS119 VSS118 VSS117 VSS116 VSS115 VSS114 VSS113 VSS112 VSS111 VSS110 VSS109 VSS108 VSS107 VSS106 VSS105 VSS104
V VS SS S6 62 1 VSS60 VSS59 VSS58 VSS57 VSS56 VSS55 VSS54 VSS53 VSS52 VSS51 VSS50 VSS49 VSS48 VSS47 VSS46 VSS45 VSS44 VSS43 VSS42 VSS41 VSS40 VSS39 VSS38
AF9 AF8 AF4 AG32 AG29 AG27 AG26 AG24 AG22 AG21 AG19 AG16 AG14 AG12 AG11 AG9 AG8 AG6 AG3 AH31 AH28 AH7 AH4 AJ32 AJ29
AC24 AC22 AC20 AC18 AC16 AC14 AC12 AD32 AD25 AD23 AD21 AD19 AD17 AD15 AD13 AD9 AD7 AD5 AD3 AE29 AE27 AE26 AE24 AE22 AE20
VS SS S1 10 02 3 V VSS101 VSS100 VSS99 VSS98 VSS97 VSS96 VSS95 VSS94 VSS93 VSS92 VSS91 VSS90 VSS89 VSS88 VSS87 VSS86 VSS85 VSS84 VSS83 VSS82 VSS81 VSS80 VSS79
V VS SS S3 37 6 VSS35 VSS34 VSS33 VSS32 VSS31 VSS30 VSS29 VSS28 VSS27 VSS26 VSS25 VSS24 VSS23 VSS22 VSS21 VSS20 VSS19 VSS18 VSS17 VSS16 VSS15 VSS14 VSS13
AJ27 AJ25 AJ20 AJ17 AJ15 AJ10 AJ8 AJ6 AJ3 AK31 AK18 AK4 AL32 AL30 AL28 AL26 AL22 AL19 AL16 AL12 AL9 AL7 AL5 AL3 AM33
AE18 AE16 AE14 AE12 AE10 AE6 AE3 AF31 AF25 AF23 AF21 AF19 AF17
VSS78 VSS77 VSS76 VSS75 VSS74 VSS73 VSS72 VSS71 VSS70 VSS69 VSS68 VSS67 VSS66
VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 VSS0
AM31 AM29 AM27 AM24 AM21 AM14 AM11 AM8 AM6 AM4 AN34 AP33 AP1
X818336-001
BGA_2
K29 K25 K23 K21 K19 K17 K15 K13 K11 K9 K4 L32 L27 L26 L24 L22 L20 L18 L16 L14 L12 L10 L8 L3 M25 M23 M21 M19 M17 M15 M13 M11 M9 M4 N31 N27 N26 N24 N22 N20 N18 N16 N14 N12 N10 N8 N5 P32 P27 P25 P23 P21 P19 P17 P15 P13 P11 P9 P6 R29 R26 R24 R22 R20 R18
12 OF 17
IC
GCPU VERSION 1 VSS260 VSS259 VSS258 VSS257 VSS256 VSS255 VSS254 VSS253 VSS252 VSS251 VSS250 VSS249 VSS248 VSS247 VSS246 VSS245 VSS244 VSS243 VSS242 VSS241 VSS240 VSS239 VSS238 VSS237 VSS236 VSS235 VSS234 VSS233 VSS232 VSS231 VSS230 VSS229 VSS228 VSS227 VSS226 VSS225 VSS224 VSS223 VSS222 VSS221 VSS220 VSS219 VSS218 VSS217 VSS216 VSS215 VSS214 VSS213 VSS212 VSS211 VSS210 VSS209 VSS208 VSS207 VSS206 VSS205 VSS204 VSS203 VSS202 VSS201 VSS200 VSS199 VSS198 VSS197 VSS196 X818336-001
VSS195 VSS194 VSS193 VSS192 VSS191 VSS190 VSS189 VSS188 VSS187 VSS186 VSS185 VSS184 VSS183 VSS182 VSS181 VSS180 VSS179 VSS178 VSS177 VSS176 VSS175 VSS174 VSS173 VSS172 VSS171 VSS170 VSS169 VSS168 VSS167 VSS166 VSS165 VSS164 VSS163 VSS162 VSS161 VSS160 VSS159 VSS158 VSS157 VSS156 VSS155 VSS154 VSS153 VSS152 VSS151 VSS150 VSS149 VSS148 VSS147 VSS146 VSS145 VSS144 VSS143 VSS142 VSS141 VSS140 VSS139 VSS138 VSS137 VSS136 VSS135 VSS134 VSS133 VSS132 VSS131
R16 R14 R12 R10 R8 T31 T27 T25 T23 T21 T19 T17 T15 T13 T11 T9 T7 T4 T3 U30 U27 U26 U24 U22 U20 U18 U16 U14 U12 U10 U8 V29 V25 V23 V21 V19 V17 V15 V13 V11 V9 V7 W31 W26 W24 W22 W20 W18 W16 W14 W12 W10 W8 W3 Y29 Y25 Y23 Y21 Y19 Y17 Y15 Y13 Y9 Y7 Y5
U5E1
13 OF 17
IC
A34 A22 A20 A18 A16 A14 A12 A10 B33 B21 B19 B17 B15 B13 B11 B7 C28 C25 C22 C20 C18 C16 C14 C12
VSS354 GCPU VERSION 1 VSS318 VSS353 VSS317 VSS352 VSS316 VSS315 VSS351 VSS314 VSS350 VSS313 VSS349 VSS312 VSS348 VSS311 VSS347 VSS310 VSS346 VSS309 VSS345 VSS344 VSS308 VSS343 VSS307 VSS342 VSS306 VSS341 VSS305 VSS340 VSS304 VSS339 VSS303 VSS338 VSS302 VSS337 VSS301 VSS336 VSS300 VSS335 VSS299 VSS334 VSS298 VSS333 VSS297 VSS332 VSS296 VSS331 VSS295
E24 E22 E20 E18 E16 E14 E12 E10 E6 F31 F29 F27 F23 F21 F19 F17 F15 F13 F11 F9 F4 G32 G28 G24
C10 D31 D29 D27 D23 D21 D19 D17 D15 D13 D11 E32
VSS330 VSS329 VSS328 VSS327 VSS326 VSS325 VSS324 VSS323 VSS322 VSS321 VSS320 VSS319
VSS294 VSS293 VSS292 VSS291 VSS290 VSS289 VSS288 VSS287 VSS286 VSS285 VSS284 VSS283 VSS282 VSS281 VSS280 VSS279 VSS278 VSS277 VSS276 VSS275 VSS274 VSS273 VSS272 VSS271 VSS270
G22 G20 G18 G16 G14 G12 G10 G8 G3 H31 H29 H27 H23 H21 H19 H17 H15 H13 H11 H9 H7 J31 J27 J24 J22
VSS269 VSS268 VSS267 VSS266 VSS265 VSS264 VSS263 VSS261
J20 J18 J16 J14 J12 J10 J8 J3
X818336-001
C
B
BGA_2
BGA_2
A
A
[PAGE_TITLE=GCPU, POWER]
DRAWING Wed Feb 10 16:23:25 2010
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GCPU, DECOUPLING V_CPUCORE
V_CPUVCS
V_CPUEDRAM
D
D 2
C5D13 1 2
4.7 6.3 UF 10% V X5R 805
4.7 6.3 UF 10% V X5R 805
1
C6R4
C5R15 1 2 4.7 UF 10% 6.3 V X5R 805
1
C
C6R3
2
4.7 UF 10% 6.3 V X5R 805 C5R10 1 2 4.7 UF 10% 6.3 V X5R 805
C5D12 1 2 4.7 UF 10% 6.3 V X5R 805 1
B
C6R2
2
4.7 UF 10% 6.3 V X5R 805 C5R12 1 2 4.7 UF 10% 6.3 V X5R 805
1
C5D3
2
4.7 UF 10% 6.3 V X5R 805
1
C5D8
2
4.7 UF 10% 6.3 V X5R 805
1
C5R6
2
4.7 UF 10% 6.3 V X5R 805
1
C5R5
2
4.7 UF 10% 6.3 V X5R 805
1
C5D2
2
4.7 UF 10% 6.3 V X5R 805
C5R8
2
1
C6D3
2
4.7 UF 10% 6.3 V X5R 805 1
C5R7
2
4.7 UF 10% 6.3 V X5R 805
1
C6R6
2
4.7 UF 10% 6.3 V X5R 805 1
C6D4
2
4.7 UF 10% 6.3 V X5R 805
1
C6R1
2
4.7 UF 10% 6.3 V X5R 805
1
C5R9
2
4.7 6.3 UF 10% V X5R 805
1
C5D7
2
4.7 UF 10% 6.3 V X5R 805
C5R43 1 2
1
C5D5
2
4.7 UF 10% 6.3 V X5R 805
1
C5D9
2
4.7 UF 10% 6.3 V X5R 805 C5R18 1 2 4.7 UF 10% 6.3 V X5R 805
1
C6R5
2
4.7 UF 10% 6.3 V X5R 805
C5R13 1 2 4.7 UF 10% 6.3 V X5R 805
C5T27 1 2 0.1 UF 10% 6.3 V X5R 402
1C5T20 2
2
C5T33 1 2
C5T25 1 2
4.7 UF 10% 6.3 V X5R 805
0.1 UF 10% 6.3 V X5R 402
1
C5R2
2
4.7 UF 10% 6.3 V X5R 805
C6T22 1 2
C5T21 1 2
4.7 UF 10% 6.3 V X5R 805
0.1 UF 10% 6.3 V X5R 402
2
0.1 UF 10% 6.3 V X5R 402
C5T34 1 2
C5R50 1 2 0.1 UF 10% 6.3 V X5R 402
C5T43 1 2
0.1 UF 10% 6.3 V X5R 402
1
C5T7
4.7 UF 10% 6.3 V X5R 805
4.7 UF 10% 6.3 V X5R 805
4.7 UF 10% 6.3 V X5R 805
C6D6
2
4.7 UF 10% 6.3 V X5R 805
C5T22 1 2
0.1 UF 10% 6.3 V X5R 402
1
1
C5E7
0.1 UF 10% 6.3 V X5R 402
4.7 UF 10% 6.3 V X5R 805
1C5D11 2
2
0.1 UF 10% 6.3 V X5R 402
4.7 UF 10% 6.3 V X5R 805
4.7 UF 10% 6.3 V X5R 805
C6D2
C5T31 1 2
C5T23 1 2
1 C6R7 2
1
C5E5
0.1 UF 10% 6.3 V X5R 402
4.7 UF 10% 6.3 V X5R 805
4.7 UF 10% 6.3 V X5R 805
C5R58 1 2 0.1 UF 10% 6.3 V X5R 402
1
C5T35 1 2
1C5R16 2
2
2
4.7 UF 10% 6.3 V X5R 805
4.7 UF 10% 6.3 V X5R 805
C5D10 1 2
C5R3
C5E6
C5T24 1 2
2
1
C5R35 1 2 0.1 6.3 UF 10% V X5R 402
1
0.1 UF 10% 6.3 V X5R 402
C5D6
4.7 UF 10% 6.3 V X5R 805
C6D1
C5T32 1 2 0.1 UF 10% 6.3 V X5R 402
2
4.7 6.3 UF 10% V X5R 805
2
1
1 C6D5 2
1
C5T26 1 2 0.1 6.3 UF 10% V X5R 402
4.7 UF 10% 6.3 V X5R 805
4.7 UF 10% 6.3 V X5R 805
4.7 UF 10% 6.3 V X5R 805
A
C5D14 1 2 4.7 UF 10% 6.3 V X5R 805
1
4.7 6.3 UF 10% V X5R 805
1
C5E8
1
C5T1
1
C5D1
2
4.7 6.3 UF 10% V X5R 805
1
C5R4
2
4.7 UF 10% 6.3 V X5R 805
1
C5D4
2
4.7 UF 10% 6.3 V X5R 805
1
C5R1
C
2
4.7 UF 10% 6.3 V X5R 805
2
0.1 UF 10% 6.3 V X5R 402
B
2
4.7 UF 10% 6.3 V X5R 805
1 C5E9 2
4.7 UF 10% 6.3 V X5R 805
1
C4T3
2
4.7 UF 10% 6.3 V X5R 805
1
C4T4
2
A
4.7 UF 10% 6.3 V X5R 805
C6T23 1 2 4.7 6.3 UF 10% V X5R 805
[PAGE_TITLE=GCPU, DECOUPLING]
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GCPU, DECOUPLING V_CPUCORE
D
D C5T12 1 2
C5R26 1 2
0.1 UF 10% 6.3 X5RV 402
0.1 UF 10% 6.3 X5RV 402
C5R33 1 2
C6R25 1 2
C6T11 1 2
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402
C5R39 1 2 0.1 UF 10% 6.3 V X5R 402
C
C5R40 1 2 0.1 UF 10% 6.3 V X5R 402
1
C6T7
2
0.1 UF 10% 6.3 V X5R 402
B
C5R61 1 2 0.1 UF 10% 6.3 V X5R 402 C6T20 1 2 0.1 UF 10% 6.3 V X5R 402
C6R42 1 2 0.1 UF 10% 6.3 V X5R 402 C5R37 1 2 0.1 UF 10% 6.3 V X5R 402 C6R37 1 2 0.1 UF 10% 6.3 V X5R 402
1
C5T8
2
0.1 UF 10% 6.3 V X5R 402 C6R45 1 2 0.1 UF 10% 6.3 V X5R 402 C5R49 1 2 0.1 UF 10% 6.3 V X5R 402 C6R33 1 2 0.1 UF 10% 6.3 V X5R 402
C6R36 1 2 0.1 UF 10% 6.3 X5RV 402 C5R63 1 2 0.1 UF 10% 6.3 V X5R 402 C5R28 1 2 0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402 C5R27 1 2 0.1 UF 10% 6.3 V X5R 402
C5R32 1 2
C5R57 1 2
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402
C5R64 1 2
C6R15 1 2
C5R55 1 2
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402
C6R31 1 2 0.1 UF 10% 6.3 V X5R 402 C6R38 1 2 0.1 UF 10% 6.3 V X5R 402 C6R43 1 2 0.1 UF 10% 6.3 V X5R 402
1
C6T6
2
0.1 UF 10% 6.3 V X5R 402 C6R28 1 2 0.1 UF 10% 6.3 V X5R 402 C5R36 1 2 0.1 UF 10% 6.3 V X5R 402 C5T11 1 2 0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402 C5R46 1 2 0.1 UF 10% 6.3 V X5R 402 C5R45 1 2 0.1 UF 10% 6.3 V X5R 402 C6T14 1 2 0.1 UF 10% 6.3 V X5R 402
1
C6T8
2
C5R62 1 2 0.1 UF 10% 6.3 V X5R 402
C6R21 1 2
C5R51 1 2
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402
C6R20 1 2
C6R18 1 2
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402
C6R44 1 2 0.1 UF 10% 6.3 V X5R 402
C
C5R59 1 2
C5R38 1 2
0.1 UF 10% 6.3 V X5R 402
[PAGE_TITLE=GCPU, DECOUPLING]
C5R60 1 2 0.1 UF 10% 6.3 V X5R 402
C5T10 1 2 0.1 UF 10% 6.3 X5RV 402
0.1 UF 10% 6.3 V X5R 402 C6T12 1 2
A
C5T17 1 2 0.1 UF 10% 6.3 X5RV 402
B
C6R17 1 2 0.1 UF 10% 6.3 V X5R 402
DRAWING Wed Feb 10 16:23:25 2010
A
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6
5
4
3
2
3
2
1
CR-11 : @TRINITY_LIB.TRINITY(SCH_1):PAGE11
8
5
4
1
GCPU, DECOUPLING V_CPUCORE
D
D C5R25 1 2 0.1 UF 10% 6.3 V X5R 402 C6T15 1 2 0.1 UF 10% 6.3 V X5R 402
C
C5R30 1 2 0.1 UF 10% 6.3 V X5R 402
C6R34 1 2 0.1 UF 10% 6.3 V X5R 402
2
C5R52 1 2
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402
1
C6T3
2
C5T14 1 2
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402
1
C6T5
C5R21 1 2 0.1 UF 10% 6.3 V X5R 402
C6R19 1 2
C6R35 1 2
C5T15 1 2
C5T16 1 2
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R
402
402
C6T18 1 2
C5R53 1 2
C6R22 1 2
C5T28 1 2
C6T19 1 2
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402
1
C6R9
2
C5T30 1 2 0.1 UF 10% 6.3 V X5R 402
C5R44 1 2 0.1 UF 10% 6.3 V X5R 402
C5R41 1 2 0.1 UF 10% 6.3 V X5R 402
C6T25 1 2 0.1 UF 10% 6.3 V X5R 402
1
C6T9
2
0.1 UF 10% 6.3 V X5R 402
1
C5T3
2
0.1 UF 10% 6.3 V X5R
C6R13 1 2 0.1 UF 10% 6.3 V X5R 402 C5R34 1 2 0.1 UF 10% 6.3 V X5R 402
C6R10 1 2
C5T29 1 2
C5R47 1 2
C6R24 1 2
C6R12 1 2
C6R14 1 2
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402
C5R20 1 2 0.1 UF 10% 6.3 V X5R 402
C5R24 1 2 0.1 UF 10% 6.3 V X5R 402
C5R48 1 2 0.1 UF 10% 6.3 V X5R 402
1
C6T2
2
0.1 UF 10% 6.3 V X5R 402
C5R19 1 2
C5R56 1 2
C6R26 1 2
C6T16 1 2
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402
C5R22 1 2 0.1 UF 10% 6.3 V X5R 402
2
C6R32 1 2
C5T18 1 2
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402
1
C6T4
C5R23 1 2
C5R29 1 2
C6R29 1 2
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402
C6R30 1 2 0.1 UF 10% 6.3 V X5R 402
1
C5T2
2
0.1 UF 10% 6.3 V X5R 402 C6T17 1 2 0.1 UF 10% 6.3 V X5R 402 C6R40 1 2 0.1 UF 10% 6.3 V X5R 402
C
402
0.1 UF 10% 6.3 V X5R 402
[PAGE_TITLE=GCPU, DECOUPLING]
C6R8
C5T19 1 2
0.1 UF 10% 6.3 V X5R 402
A
C6R39 1 2 0.1 UF 10% 6.3 V X5R 402
1
0.1 UF 10% 6.3 V X5R 402
B
2
0.1 UF 10% 6.3 V X5R 402
1
C5T5
B
2
0.1 UF 10% 6.3 V X5R 402 C6T13 1 2 0.1 UF 10% 6.3 V X5R 402 C6T24 1 2 0.1 UF 10% 6.3 V X5R 402
C6R41 1 2
A
0.1 UF 10% 6.3 V X5R 402
DRAWING Wed Feb 10 16:23:25 2010
MICROSOFT CONFIDENTIAL
PROJECT NAME TRINITY_XDK
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GPU, MEMORY CONTROLLER 0 PARTITION A & B U5E1
D
C
B
4 OF 17
15 14 15 14 15 14 15 14
BI OUT IN OUT
15 14 15 14 15 14 15 14 15 14 15 14 15 14 15 14 15 14 15 14 15 14
BI BI BI BI BI BI BI BI OUT IN OUT
MA_DQ23 MA_DQ22 MA_DQ21 MA_DQ20 MA_DQ19 MA_DQ18 MA_DQ17 MA_DQ16 MA_WDQS2 MA_RDQS2 MA_DM2
Y34 Y33 Y32 AA33 W33 AB31 V34 AB32 AA34 Y31 W34
MA_DQ23 MA_DQ22 MA_DQ21 MA_DQ20 MA_DQ19 MA_DQ18 MA_DQ17 MA_DQ16 MA_WDQS2 MA_RDQS2 MA_DM2
15 14 15 14 15 14 15 14 12 15 14 15 14 15 14 15 14 15 14 12 15 14 15 14
BI BI BI BI BI BI BI BI OUT IN OUT
MA_DQ15 MA_DQ14 MA_DQ13 MA_DQ12 MA_DQ11 MA_DQ10 MA_DQ9 MA_DQ8 MA_WDQS1 MA_RDQS1 MA_DM1
W28 R30 W30 R28 V28 T29 U29 U28 T30 V30 V32
MA_DQ15 MA_DQ14 MA_DQ13 MA_DQ12 MA_DQ11 MA_DQ10 MA_DQ9 MA_DQ8 MA_WDQS1 MA_RDQS1 MA_DM1
15 14 15 14 15 14 15 14 12 15 14 15 14 15 14 15 14 15 14 12 15 14 15 14
BI BI BI BI BI BI BI BI OUT IN OUT
MA_DQ7 MA_DQ6 MA_DQ5 MA_DQ4 MA_DQ3 MA_DQ2 MA_DQ1 MA_DQ0 MA_WDQS0 MA_RDQS0 MA_DM0
Y30 AD28 Y28 AD30 AB28 AC30 AB29 AC28 AC32 AA29 AA30
MA_DQ7 MA_DQ6 MA_DQ5 MA_DQ4 MA_DQ3 MA_DQ2 MA_DQ1 MA_DQ0 MA_WDQS0 MA_RDQS0 MA_DM0
AB34
MA_VREF0
14 14 14 14 14 14
BI BI BI BI BI BI
T34 T33 U31 R33 U33 R32 V33 R31 R34 U32 U34
U5E1
IC
GCPU VERSION 1
MA_DQ31 MA_DQ30 MA_DQ29 MA_DQ28 MA_DQ27 MA_DQ26 MA_DQ25 MA_DQ24 MA_WDQS3 MA_RDQS3 MA_DM3
15 15 15 15 15 15
BI OUT IN OUT
H33 G34 H34 F34 K31 D34 K32 C34 E34 J33 J34
MB_DQ25 MB_DQ24 MB_WDQS3 MB_RDQS3 MB_DM3
16 16 16 16 16 16 16 16 16 16 16
BI BI BI BI BI BI BI BI OUT IN OUT
MB_DQ23 MB_DQ22 MB_DQ21 MB_DQ20 MB_DQ19 MB_DQ18 MB_DQ17 MB_DQ16 MB_WDQS2 MB_RDQS2 MB_DM2
M32 M34 M31 M33 K33 N34 K34 P33 N33 L34 L33
MB_DQ23 MB_DQ22 MB_DQ21 MB_DQ20 MB_DQ19 MB_DQ18 MB_DQ17 MB_DQ16 MB_WDQS2 MB_RDQS2 MB_DM2
17 17 17 17 16 17 17 17 17 17 16 17 17
16 16 16 12 16 16 16 16 12 16 16
BI BI BI BI BI BI BI BI OUT IN OUT
MB_DQ15 MB_DQ14 MB_DQ13 MB_DQ12 MB_DQ11 MB_DQ10 MB_DQ9 MB_DQ8 MB_WDQS1 MB_RDQS1 MB_DM1
J28 C33 J30 D33 F33 E33 G30 F30 E30 G33 H30
MB_DQ15 MB_DQ14 MB_DQ13 MB_DQ12 MB_DQ11 MB_DQ10 MB_DQ9 MB_DQ8 MB_WDQS1 MB_RDQS1 MB_DM1
17 17 17 17 16 17 17 17 17 17 16 17 17
16 16 16 12 16 16 16 16 12 16 16
BI BI BI BI BI BI BI BI OUT IN OUT
MB_DQ7 MB_DQ6 MB_DQ5 MB_DQ4 MB_DQ3 MB_DQ2 MB_DQ1 MB_DQ0 MB_WDQS0 MB_RDQS0 MB_DM0
K30 P28 K28 P30 M28 N30 M29 N28 N32 L29 L30
MB_DQ7 MB_DQ6 MB_DQ5 MB_DQ4 MB_DQ3 MB_DQ2 MB_DQ1 MB_DQ0 MB_WDQS0 MB_RDQS0 MB_DM0
P34
MB_VREF0
17 17 17 17 17 17
16 16 16 16 16 16
BI BI BI BI BI BI
MA_DQ25 MA_DQ24 MA_WDQS3 MA_RDQS3 MA_DM3
17 17 17 17
16 16 16 16
17 17 17 17 17 17 17 17 17 17 17
X818336-001
MA_CLK1_DP MA_CLK1_DN MA_CLK0_DP MA_CLK0_DN
AE28 AE30 AC33 AC34
MA_A12 MA_A11 MA_A10 MA_A9 MA_A8 MA_A7 MA_A6 MA_A5 MA_A4 MA_A3 MA_A2 MA_A1 MA_A0
AL33 AH34 AL34 AG34 AD33 AF34 AE33 AD34 AF33 AG33 AH33 AK33 AJ34
11 10 9 8 7 6 5 4 3 2 1 0
MA_BA2 MA_BA1 MA_BA0
AE34 AE32 AK34
2 1 0
MA_CKE MA_WE_N* MA_CAS_N* MA_RAS_N* MA_CS1_N* MA_CS0_N*
AJ33 AF29 AG30 AH30 AF30 AE31
15 14 12
MA_CLK1_DP MA_CLK1_DN MA_CLK0_DP MA_CLK0_DN
OUT OUT OUT OUT
15 15 14 14
MA_A
OUT
14 15
MA_BA
MA_CKE MA_WE_N MA_CAS_N MA_RAS_N MA_CS1_N MA_CS0_N
15 14 12
OUT OUT OUT OUT OUT OUT
OUT
MA_WDQS1
BI
MA_DQ12
14 14 14 14 14 14
15 15 15 15 15
R6T8 1 2
4.75 KOHM 402
BGA_2
14 15
OUT
3 OF 17
1% CH
IC
GCPU VERSION 1
MB_DQ31 MB_DQ30 MB_DQ29 MB_DQ28 MB_DQ27 MB_DQ26 MB_DQ25 MB_DQ24 MB_WDQS3 MB_RDQS3 MB_DM3
MA_DQ31 MA_DQ30 MA_DQ29 MA_DQ28 MA_DQ27 MA_DQ26
D
MB_DQ31 MB_DQ30 MB_DQ29 MB_DQ28 MB_DQ27 MB_DQ26
B32 A32 B31 A31
MB_CLK1_DP MB_CLK1_DN MB_CLK0_DP MB_CLK0_DN MB_A12 MB_A11 MB_A10 MB_A9 MB_A8 MB_A7 MB_A6 MB_A5 MB_A4 MB_A3 MB_A2 MB_A1 MB_A0
C30 F25 A25 E29 B30 B29 A30 C32 A29 E25 G26 B25 F26
11 10 9 8 7 6 5 4 3 2 1 0
MB_BA2 MB_BA1 MB_BA0
E28 B28 E27
2 1 0
MB_CKE MB_WE_N* MB_CAS_N* MB_RAS_N* MB_CS1_N* MB_CS0_N*
A27 B26 C26 D26 A28 A26
15 14 12 15 14 12
BI
MA_DQ4
X818336-001
BGA_2
OUT
1R6T72
4 .7 .7 5 K OH OH M 402
MA_WDQS0
17 16 12
17 16 12
1% CH
V_MEM 17 16 12
1 R6T5
549 OHM 1%
2 EMPTY 402
1 R6T2
V_MEM
549 OHM 1%
MEMORY CONTROLLER A, DECOUPLING
1 R6T4 NEED NEW VREF RESISTORS
1.27 KOHM 1%
2 EMPTY 402
C6T27
0.1 UF 10% 6.3 V X5R 402
C6T10
0.1 UF 10% 6.3 V X5R 402
C6T32
0.1 UF 10% 6.3 V X5R 402
C6T29
0.1 UF 10% 6.3 V X5R 402
17 17 16 16
MB_A
OUT
16 17
C
MB_BA
OUT
16 17
MB_CKE MB_WE_N MB_CAS_N MB_RAS_N MB_CS1_N MB_CS0_N
OUT OUT OUT OUT OUT OUT
16 16 16 16 16 16
17 17 17 17 17
OUT
MB_WDQS1
BI
MB_DQ12
R6R2 1 2
4.75 KOHM 402
BI
MB_DQ4
OUT
MB_WDQS0
1% CH
R6R1 1 2
4.75 KOHM 402
1% CH
V_MEM MEMORY CONTROLLER B, DECOUPLING
2 EMPTY MB_VREF0
MA_VREF0
OUT OUT OUT OUT
B
17 16 12
V_MEM
MB_CLK1_DP MB_CLK1_DN MB_CLK0_DP MB_CLK0_DN
402
1 R6T1
1.27 KOHM 1%
2 EMPTY 402
C6R27
0.1 UF 10% 6.3 V X5R 402
C6R11
0.1 UF 10% 6.3 V X5R 402
C6R16
0.1 UF 10% 6.3 V X5R 402
C6T30
C6R23
0.1 UF 10% 6.3 V X5R 402
4.7 UF 10% 6.3 V X5R 805
C6R46
0.1 UF 10% 6.3 V X5R 402
A
A TO CHANGE GPU VREF, CHANGE THESE RESISTORS TO MATCH THE TABLE R6T4, R6T1, R5T3, R5T4 MEM VREF 70% 72% 73% 74%
RESISTOR VALUE 1.27KOHM 1.40KOHM 1.47KOHM 1.54KOHM
THESE ARE THE GPU VREFS NEEDED FOR VARIOUS MEMORIES. CONSULT WITH MEM TEAM FOR USAGE.
[PAGE_TITLE=GPU, MEMORY CONTROLLER CONTROLLER A + B]
N: GPU VREF SET INTERNALLY BY DEFAULT. EXTERNAL RESISTOR DIVIDER USED TO MANUALLY SET GPU VREF VOLTAGE.
DRAWING Wed Feb 10 16:23:26 2010
MICROSOFT CONFIDENTIAL
PROJECT NAME TRINITY_XDK
PAGE 12/81
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GPU, MEMORY CONTROLLER 1 PARTITION C & D U5E1
D
C
B
2 OF 17
U5E1
IC
GCPU VERSION 1
21 21 20 20 21 20 21 20
AM23 AL23 AP23 AP24 AP22 AN25 AN21 AP25 AN24 AN23 AN22
MD_DQ24 MD_WDQS3 MD_RDQS3 MD_DM3
21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20
BI BI BI BI BI BI BI BI OUT IN OUT
MD_DQ23 MD_DQ22 MD_DQ21 MD_DQ20 MD_DQ19 MD_DQ18 MD_DQ17 MD_DQ16 MD_WDQS2 MD_RDQS2 MD_DM2
AN19 AP19 AN20 AL18 AL20 AP18 AP21 AN18 AM18 AP20 AM20
MD_DQ23 MD_DQ22 MD_DQ21 MD_DQ20 MD_DQ19 MD_DQ18 MD_DQ17 MD_DQ16 MD_WDQS2 MD_RDQS2 MD_DM2
MD_DQ15 MD_DQ14 MD_DQ13 MD_DQ12 MD_DQ11 MD_DQ10 MD_DQ9 MD_DQ8 MD_WDQS1 MD_RDQS1 MD_DM1
AJ19 AH23 AK19 AJ23 AK21 AK22 AH21 AM22 AH22 AK20 AH20
MD_DQ15 MD_DQ14 MD_DQ13 MD_DQ12 MD_DQ11 MD_DQ10 MD_DQ9 MD_DQ8
21 20 21 13 20 21 20
BI BI BI BI BI BI BI BI OUT IN OUT
21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20
BI BI BI BI BI BI BI BI OUT IN OUT
MD_DQ7 MD_DQ6 MD_DQ5 MD_DQ4 MD_DQ3 MD_DQ2 MD_DQ1 MD_DQ0 MD_WDQS0 MD_RDQS0 MD_DM0
AH18 AJ14 AJ18 AK14 AM17 AK15 AK16 AH16 AH15 AK17 AH17
MD_DQ7 MD_DQ6 MD_DQ5 MD_DQ4 MD_DQ3 MD_DQ2 MD_DQ1 MD_DQ0 MD_WDQS0 MD_RDQS0 MD_DM0
AN17
MD_VREF0
MC_DQ31 MC_DQ30 MC_DQ29 MC_DQ28 MC_DQ27 MC_DQ26 MC_DQ25
21 21 21 21 21 21 21
19 18 18 19 19 18 19 18
AP15 AM15 AN15 AL15 AL13 AN16 AM13 AP17 AP16 AN14 AP14
MC_DQ24 MC_WDQS3 MC_RDQS3 MC_DM3
19 19 19 19 19 19 19 19 19 19 19
18 18 18 18 18 18 18 18 18 18 18
BI BI BI BI BI BI BI BI OUT IN OUT
MC_DQ23 MC_DQ22 MC_DQ21 MC_DQ20 MC_DQ19 MC_DQ18 MC_DQ17 MC_DQ16 MC_WDQS2 MC_RDQS2 MC_DM2
AP11 AL10 AN11 AM10 AN13 AN10 AP13 AN9 AP10 AP12 AN12
MC_DQ23 MC_DQ22 MC_DQ21 MC_DQ20 MC_DQ19 MC_DQ18 MC_DQ17 MC_DQ16 MC_WDQS2 MC_RDQS2 MC_DM2
19 19 19 19 18 19 19 19 19
18 18 18 13 18 18 18 18
MC_DQ15 MC_DQ14 MC_DQ13 MC_DQ12 MC_DQ11 MC_DQ10 MC_DQ9 MC_DQ8 MC_WDQS1 MC_RDQS1 MC_DM1
AJ9 AJ13 AK9 AH13 AK11 AK12 AH11 AM12 AH12 AK10 AH10
MC_DQ15 MC_DQ14 MC_DQ13 MC_DQ12 MC_DQ11 MC_DQ10 MC_DQ9 MC_DQ8
19 18 19 13 18 19 18
BI BI BI BI BI BI BI BI OUT IN OUT
19 19 19 19 18 19 19 19 19 19 18 19 19
BI BI BI BI BI BI BI BI OUT IN OUT
MC_DQ7 MC_DQ6 MC_DQ5 MC_DQ4 MC_DQ3 MC_DQ2 MC_DQ1 MC_DQ0 MC_WDQS0 MC_RDQS0 MC_DM0
AN8 AN2 AK8 AN3 AN6 AK5 AK6 AN5 AN4 AK7 AN7
MC_DQ7 MC_DQ6 MC_DQ5 MC_DQ4 MC_DQ3 MC_DQ2 MC_DQ1 MC_DQ0 MC_WDQS0 MC_RDQS0 MC_DM0
AE5
MC_VREF0
18 18 18 13 18 18 18 18 13 18 18
MC_WDQS1 MC_RDQS1 MC_DM1
AP9 AP8 AP6 AP5
MC_CLK1_DP MC_CLK1_DN MC_CLK0_DP MC_CLK0_DN MC_A12 MC_A11 MC_A10 MC_A9 MC_A8 MC_A7 MC_A6 MC_A5 MC_A4 MC_A3 MC_A2 MC_A1 MC_A0
AE1 AH1 AE2 AJ2 AP4 AK1 AL1 AP3 AK2 AJ1 AH2 AF1 AG2
MC_BA2 MC_BA1 MC_BA0
AL2 AM1 AF2
MC_CKE MC_WE_N* MC_CAS_N* MC_RAS_N* MC_CS1_N* MC_CS0_N*
AG1 AH5 AG5 AF5 AJ5 AM2
11 10 9 8 7 6 5 4 3 2 1 0
BGA_2
OUT OUT OUT OUT
19 19 18 18
MC_A
OUT
18 19
MC_BA
2 1 0
OUT
MC_CKE MC_WE_N MC_CAS_N MC_RAS_N MC_CS1_N MC_CS0_N
19 18 13
X818336-001
MC_CLK1_DP MC_CLK1_DN MC_CLK0_DP MC_CLK0_DN
19 18 13
19 18 13
OUT OUT OUT OUT OUT OUT
OUT
MC_WDQS1
BI
MC_DQ12
19 19 19 19 19
1% CH
20 20 20 20 20 20 20
20 20 20 13 20 20 20 20
IC
MD_DQ31 MD_DQ30 MD_DQ29 MD_DQ28 MD_DQ27 MD_DQ26 MD_DQ25
D
MD_CLK1_DP MD_CLK1_DN MD_CLK0_DP MD_CLK0_DN
AJ24 AK24 AL25 AM25
MD_A12 MD_A11 MD_A10 MD_A9 MD_A8 MD_A7 MD_A6 MD_A5 MD_A4 MD_A3 MD_A2 MD_A1 MD_A0
AK30 AN31 AN32 AK26 AK25 AN26 AH26 AH25 AN27 AP32 AN29 AM32 AN30
MD_BA2 MD_BA1 MD_BA0
AK27 AN28 AK29
MD_CKE MD_WE_N* MD_CAS_N* MD_RAS_N* MD_CS1_N* MD_CS0_N*
AP30 AP28 AP29 AP31 AK28 AP27
MD_WDQS1 MD_RDQS1 MD_DM1
X818336-001
R5T6 1 2
MC_DQ4
MC_VREF0
NEED TO VREF RESISTOR VALUES
549 OHM 1% 1 EMPTY 402
2 EMPTY
6.3 V 2 X5R
1.27 KOHM 1% 402
C5U2
4.7 UF 10% 805
C5T37
0.1 UF 10%
V 2 6.3 X5R
1
C5T41
0.1 UF 10%
V 2 6.3 X5R
402
402
549 OHM 1% 2 EMPTY 402
1
C6T28
0.1 UF 10%
6.3 V 2 X5R 402
1
TO CHANGE GPU VREF, CHANGE THESE RESISTORS TO MATCH THE TABLE R6T4, R6T1, R5T3, R5T4 GPU MEM VREF 70% 72% 73% 74%
RESISTOR VALUE 1.27KOHM 1.40KOHM 1.47KOHM 1.54KOHM
THESE ARE THE GPU VREFS NEEDED FOR VARIOUS MEMORIES. CONSULT WITH MEM TEAM FOR USAGE.
0.1 UF 10%
V 2 6.3 X5R
1
0.1 UF 10%
V 2 6.3 X5R
402
[PAGE_TITLE=[GPU, MEMORY CONTROLLER CONTROLLER C + D]
402
1
C6T33
0.1 UF 10%
V 2 6.3 X5R 402
OUT
20 21
MD_CKE MD_WE_N MD_CAS_N MD_RAS_N MD_CS1_N MD_CS0_N
OUT OUT OUT OUT OUT OUT
20 20 20 20 20 20
OUT
MD_WDQS1
BI
MD_DQ12
21 21 21 21 21
B
R6T9 1 2
4 .7 .7 5 K OH OH M 402
1% CH
C5T48
1
1
C5T39
0.1 UF 10% 6.3 V X5R 402
2
1
C6T31
0.1 UF 10% 6.3 V X5R 402
2
1
C5T38
0.1 UF 10%
6.3 V 2 X5R 402
MD_VREF0
0.1 UF 10%
6.3 V 2 X5R 402
1 R5T4
1.27 KOHM 1%
2 EMPTY
1
402
C5T46
MD_BA
C5T49
A C5T50
20 21
C
0.1 UF 10% 6.3 V X5R 402
2
2 1
OUT
MEMORY CONTROLLER D, DECOUPLING
MEMORY CONTROLLER C, DECOUPLING 1
MD_A
V_MEM 1 R5T5
1
21 21 20 20
V_MEM
V_MEM
1 R5T3
OUT OUT OUT OUT
BGA_2
CH 1%
MC_WDQS0
OUT
MD_CLK1_DP MD_CLK1_DN MD_CLK0_DP MD_CLK0_DN
2 1 0
21 20 13
1 2 R5T2
11 10 9 8 7 6 5 4 3 2 1 0
21 20 13
BI
19 18 13
18 18 18 18 18 18
21 21 21 21 20 21 21 21 21
R5T7 1 2
4.75 KOHM 402
4.75 KOHM 402
V_MEM
18 19
1 OF 17
MD_DQ31 MD_DQ30 MD_DQ29 MD_DQ28 MD_DQ27 MD_DQ26 MD_DQ25 MD_DQ24 MD_WDQS3 MD_RDQS3 MD_DM3
MC_DQ31 MC_DQ30 MC_DQ29 MC_DQ28 MC_DQ27 MC_DQ26 MC_DQ25 MC_DQ24 MC_WDQS3 MC_RDQS3 MC_DM3
18 18 18 18 18 18 18
GCPU VERSION 1
BI BI BI BI BI BI BI BI OUT IN OUT
BI BI BI BI BI BI BI BI OUT IN OUT
19 19 19 19 19 19 19
C6T26
0.1 UF 10% 6.3 V X5R 402
1 2
C5T42
0.1 UF 10% 6.3 V X5R 402
1 2
C5T45
0.1 UF 10% 6.3 V X5R 402
1
C5T44
0.1 UF 10%
V 2 6.3 X5R
A
402
C5T47
0.1 UF 10%
V 2 6.3 X5R 402
N: GPU VREF SET INTERNALLY BY DEFAULT. EXTERNAL RESISTOR DIVIDER USED TO MANUALLY SET GPU VREF VOLTAGE.
DRAWING Wed Feb 10 16:23:26 2010
MICROSOFT CONFIDENTIAL
PROJECT NAME TRINITY_XDK
PAGE 13/81
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REV 1.01
8
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MEMORY PARTITION A, TOP CHIP SELECT = 0, MIRROR FUNCTION = 0 V_MEM
D
D 1 R7E5
60.4 OHM 1% 2 CH 402
1 R7E4
60.4 OHM 1% 2 CH 402
V_MEM IC
U7E1 12 12 4
IN IN IN
MA_CLK0_DP MA_CLK0_DN MEM_RST
12
IN
MA_A
C
B
J11 J10 V9
11 10 9 8 7 6 5 4 3 2 1 0
J2 L4 K2 M9 K11 L9 K10 H11 K9 M4 K3 H2 K4
2 1 0
H10 G9 G4
12
IN
MA_BA
12 12 12 12 12 12 4
IN IN IN IN IN IN IN
MA_CKE MA_WE_N MA_CAS_N MA_RAS_N MA_CS0_N MA_CS1_N MEM_SCAN_TOP_EN
H4 H9 F4 H3 F9 J3 A9
4
IN
MEM_SCAN_EN
V4
14 15
IN IN
MEM_A_VREF1 MEM_A_VREF0
H1 H12
GDDR136 (1Gbit) MF=0
CLK_DP CLK_DN RESET
A12(1Gbit only, dual-load) A11/A7 A10/A8 A9/A3 A8/A10 A7/A11 A6/A2 A5/A1 A4/A0 A3/A9 A2/A6 A1/A5 A0/A4 BA2/RAS_N BA1/BA0 BA0/BA1 CKE/WE_N WE_N/CKE CAS_N/CS_N RAS_N/BA2 CS_N/CAS_N CS1_N (1Gbit only, single-load) MF SCAN_EN VREF1 VREF0
U7E1
DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 WDQS3 RDQS3 DM3
T3 T2 R3 R2 M3 N2 L3 M2 P2 P3 N3
MA_DQ31 MA_DQ30 MA_DQ29 MA_DQ28 MA_DQ27 MA_DQ26 MA_DQ25 MA_DQ24 MA_WDQS3 MA_RDQS3 MA_DM3
BI BI BI BI BI BI BI BI IN OUT IN
12 15 12 15 12 15 12 15 12 15 12 15 12 15 12 15 12 15 12 12
DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 WDQS2 RDQS2
T10 T11 R10 R11 M10 N11 L10 M11 P11 P10 N10
MA_DQ23 MA_DQ22 MA_DQ21 MA_DQ20 MA_DQ19 MA_DQ18 MA_DQ17 MA_DQ16 MA_WDQS2 MA_RDQS2 MA_DM2
12 15 12 15 12 15 12 15 12 15 12 15 12 15 12 15 12 15 12
DM2 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 WDQS1 RDQS1 DM1
G10 F11 F10 E11 C10 C11 B10 B11 D11 D10 E10
MA_DQ15 MA_DQ14 MA_DQ13 MA_DQ12 MA_DQ11 MA_DQ10 MA_DQ9 MA_DQ8 MA_WDQS1 MA_RDQS1 MA_DM1
BI BI BI BI BI BI BI BI IN OUT IN BI BI BI BI BI BI BI BI IN OUT IN
12 12 15 12 15 12 15 12 15 12 15 12 15 12 15 12 15 12 15 12 12
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0 DM0
G3 F2 F3 E2 C3 C2 B3 B2 D2 D3 E3
MA_DQ7 MA_DQ6 MA_DQ5 MA_DQ4 MA_DQ3 MA_DQ2 MA_DQ1 MA_DQ0 MA_WDQS0 MA_RDQS0 MA_DM0
BI BI BI BI BI BI BI BI IN OUT IN
12 15 12 15 12 15 12 15 12 15 12 15 12 15 12 15 12 15 12 12
ZQ
A4
V1 R12 R9 R4 R1 N12 N9 V12 N4 N1 J9 J4 E12 E9 E4 E1 C12 C9 C4 C1 A12 A1
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
V2 M12 M1 V11 F12 F1 A11 A2
VDD VDD VDD VDD VDD VDD VDD VDD
K12 K1
VDDA VDDA
J12 J1
VSSA VSSA
IC
GDDR136 (1Gbit) MF=0 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
T12 T9 T4 T1 P12 P9 P4 P1 L11 L2 G11 G2 D12 D9 D4 D1 B12 B9 B4 B1
VSS VSS VSS VSS VSS VSS VSS VSS
V3 L12 L1 G12 G1 A10 V10 A3
C
B
X802980-019
MX_CS1_N CONNECTED TO J3 TO SUPPORT 1G RAM CONFIGS.
MA_ZQ_TOP
1 R7E8
V_MEM
243 OHM 1%
X802980-019
2 CH
402
1 R7T5
PARTITION A DECOUPLING V_MEM
549 OHM 1%
2 EMPTY 402
MEM_A_VREF1
14 15
1 R7T4
A
1.27 KOHM 1% 2 EMPTY 402
1 2
C7T7
0.1 UF 10% 6.3 V X5R 402
V_MEM MEMORY A, TOP, DECOUPLING
OUT
C7E8
4.7 UF 10% 6.3 V X5R 805
C7E14 0.1 UF 10% 6.3 V X5R 402
C7E11 0.1 UF 10% 6.3 V X5R 402
C7E6
0.1 UF 10% 6.3 V X5R 402
C7E5
0.1 UF 10% 6.3 V X5R 402
C7E13 0.1 UF 10% 6.3 V X5R 402
C7E10 0.1 UF 10% 6.3 V X5R 402
C7E4
0.1 UF 10% 6.3 V X5R 402
C7E7
0.1 UF 10% 6.3 V X5R 402
TO CHANGE MEM VREF, CHANGE THESE RESISTORS TO MATCH THE TABLE R7T4, R7E7, R7R4, R7D5, R5U4, R5F2, R6U4, R6F2 MEM VREF 69% 70% 72%
RESISTOR VALUE 1.21KOHM 1.27KOHM 1.40KOHM
THESE ARE THE MEM VREFS NEEDED FOR VARIOUS MEMORIES. CONSULT WITH MEM TEAM FOR USAGE.
[PAGE_TITLE=MEMORY [PAGE_TITLE=MEMOR Y PARTITION A, TOP]
DRAWING Wed Feb 10 16:23:26 2010
MICROSOFT CONFIDENTIAL
PROJECT NAME TRINITY_XDK
PAGE 14/81
FAB G
REV 1.01
A
8
7
6
5
7
6
5
4
3
2
3
2
1
CR-15 : @TRINITY_LIB.TRINITY(SCH_1):PAGE15
8
4
1
MEMORY PARTITION A, BOTTOM
V_MEM
CHIP SELECT = 1, MIRROR FUNCTION = 1
D
D 1 R7T3
1 R7T2
2 CH
2 CH
60.4 OHM 1%
60.4 OHM 1%
12 12 4
IN IN IN
12
IN
MA_CLK1_DP MA_CLK1_DN MEM_RST
J11 J10 V9
MA_A
C
B
12
IN
MA_BA
12 12 12 12 12
IN IN IN IN IN
MA_CKE MA_WE_N MA_CAS_N MA_RAS_N MA_CS1_N
4
IN
MEM_SCAN_BOT_EN
U7T1
402
402
11 10 9 8 7 6 5 4 3 2
J2 L9 K11 M4 K2 L4 K3 H2 K4 M9 K10
1 0
H11 K9
2 1 0
H3 G4 G9 H9 H4 F9 H10 F4 J3 A9
4
IN
MEM_SCAN_EN
V4
15 14
IN IN
MEM_A_VREF0 MEM_A_VREF1
H1 H12
GDDR136 (1Gbit) MF=1
CLK_DP CLK_DN RESET
A12(1Gbit only, dual-load) A7/A11 A8/A10 A3/A9 A10/A8 A11/A7 A2/A6 A1/A5 A0/A4 A9/A3 A6/A2 A5/A1 A4/A0 RAS_N/BA2 BA0/BA1 BA1/BA0 WE_N/CKE CKE/WE_N CS_N/CAS_N BA2/RAS_N CAS_N/CS_N CS1_N (1Gbit only, single-load) MF SCAN_EN VREF1 VREF0
T3 T2 R3 R2 M3 N2 L3 M2 P2 P3 N3
MA_DQ23 MA_DQ22 MA_DQ21 MA_DQ20 MA_DQ19 MA_DQ18 MA_DQ17 MA_DQ16 MA_WDQS2 MA_RDQS2 MA_DM2
BI BI BI BI BI BI BI BI IN OUT IN
12 14 12 14 12 14 12 14 12 14 12 14 12 14 12 14 12 14 12 12
DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 WDQS2 RDQS2 DM2
T10 T11 R10 R11 M10 N11 L10 M11 P11 P10 N10
MA_DQ31 MA_DQ30 MA_DQ29 MA_DQ28 MA_DQ27 MA_DQ26 MA_DQ25 MA_DQ24 MA_WDQS3 MA_RDQS3 MA_DM3
BI BI BI BI BI BI BI BI IN OUT IN
12 14 12 14 12 14 12 14 12 14 12 14 12 14 12 14 12 14 12 12
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 WDQS1 RDQS1 DM1
G10 F11 F10 E11 C10 C11 B10 B11 D11 D10 E10
MA_DQ7 MA_DQ6 MA_DQ5 MA_DQ4 MA_DQ3 MA_DQ2 MA_DQ1 MA_DQ0 MA_WDQS0 MA_RDQS0 MA_DM0
BI BI BI BI BI BI BI BI IN OUT IN
12 14 12 14 12 14 12 14 12 14 12 14 12 14 12 14 12 14 12 12
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0 DM0
G3 F2 F3 E2 C3 C2 B3 B2 D2 D3 E3
MA_DQ15 MA_DQ14 MA_DQ13 MA_DQ12 MA_DQ11 MA_DQ10 MA_DQ9 MA_DQ8 MA_WDQS1 MA_RDQS1 MA_DM1
BI BI BI BI BI BI BI BI IN OUT IN
12 14 12 14 12 14 12 14 12 14 12 14 12 14 12 14 12 14 12 12
ZQ
A4
X802980-019
V_MEM
V_MEM
EMPTY DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 WDQS3 RDQS3 DM3
EMPTY
U7T1 V1 R12 R9 R4 R1 N12 N9 V12 N4 N1 J9 J4 E12 E9 E4 E1 C12 C9 C4 C1 A12 A1
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
V2 M12 M1 V11 F12 F1 A11 A2
VDD VDD VDD VDD VDD VDD VDD VDD
K12 K1
VDDA VDDA
J12 J1
VSSA VSSA
GDDR136 (1Gbit) MF=1
VSSQ VSSQ
T12 T9 T4 T1 P12 P9 P4 P1 L11 L2 G11 G2 D12 D9 D4 D1 B12 B9 B4 B1
VSS VSS VSS VSS VSS VSS VSS VSS
V3 L12 L1 G12 G1 A10 V10 A3
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
VDDQ VDDQ
C
B
X802980-019
MA_ZQ_BOT
1 R7T6
243 OHM 1%
2 CH
402
1 R7E6
V_MEM
549 OHM 1%
2 EMPTY 402
MEM_A_VREF0
MEMORY A, BOTTOM, DECOUPLING OUT
14 15
1 R7E7
1.27 KOHM 1%
A
2 EMPTY 402
C7T12 C7E9
0.1 UF 10% 6.3 V X5R 402
[PAGE_TITLE=MEMORY [PAGE_TITLE=MEMOR Y PARTITION A, BOTTOM]
0.1 UF 10% 6.3 V X5R 402
C7T9
0.1 UF 10% 6.3 V X5R 402
DRAWING Wed Feb 10 16:23:26 2010
C7T5
0.1 UF 10% 6.3 V X5R 402
C7T4
0.1 UF 10% 6.3 V X5R 402
MICROSOFT CONFIDENTIAL
C7T11 0.1 UF 10% 6.3 V X5R 402
C7T8
0.1 UF 10% 6.3 V X5R 402
PROJECT NAME TRINITY_XDK
C7T3
0.1 UF 10% 6.3 V X5R 402
PAGE 15/81
C7T6
0.1 UF 10% 6.3 V X5R 402
FAB G
REV 1.01
A
8
7
6
5
7
6
5
4
3
2
3
2
1
CR-16 : @TRINITY_LIB.TRINITY(SCH_1):PAGE16
8
4
1
MEMORY PARTITION B, TOP CHIP SELECT = 0, MIRROR FUNCTION = 0
V_MEM
D
D
1 R7D3
C
B
12 12 4
IN IN IN
MB_CLK0_DP MB_CLK0_DN MEM_RST
12
IN
MB_A
V_MEM
1 R7D2
60.4 OHM 1% CH 2 402 U7D1
60.4 OHM 1% CH 2 402
J11 J10 V9
11 10 9 8 7 6 5 4 3 2 1 0
J2 L4 K2 M9 K11 L9 K10 H11 K9 M4 K3 H2 K4
2 1 0
H10 G9 G4
12
IN
MB_BA
12 12 12 12 12 12 4
IN IN IN IN IN IN IN
MB_CKE MB_WE_N MB_CAS_N MB_RAS_N MB_CS0_N MB_CS1_N MEM_SCAN_TOP_EN
H4 H9 F4 H3 F9 J3 A9
4
IN
MEM_SCAN_EN
V4
16 17
IN IN
MEM_B_VREF1 MEM_B_VREF0
H1 H12
U7D1 IC GDDR136 (1Gbit) MF=0
CLK_DP CLK_DN RESET
A12(1Gbit only, dual-load) A11/A7 A10/A8 A9/A3 A8/A10 A7/A11 A6/A2 A5/A1 A4/A0 A3/A9 A2/A6 A1/A5 A0/A4 BA2/RAS_N BA1/BA0 BA0/BA1 CKE/WE_N WE_N/CKE CAS_N/CS_N RAS_N/BA2 CS_N/CAS_N CS1_N (1Gbit only, single-load) MF SCAN_EN VREF1 VREF0
T3 T2 R3 R2 M3 N2 L3 M2 P2 P3 N3
MB_DQ31 MB_DQ30 MB_DQ29 MB_DQ28 MB_DQ27 MB_DQ26 MB_DQ25 MB_DQ24 MB_WDQS3 MB_RDQS3 MB_DM3
BI BI BI BI BI BI BI BI IN OUT IN
MB_DQ23 MB_DQ22 MB_DQ21 MB_DQ20 MB_DQ19 MB_DQ18 MB_DQ17 MB_DQ16
WDQS2 RDQS2 DM2
T10 T11 R10 R11 M10 N11 L10 M11 P11 P10 N10
MB_RDQS2 MB_WDQS2 MB_DM2
BI BI BI BI BI BI BI BI IN OUT IN
12 12 17 12
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 WDQS1 RDQS1 DM1
G10 F11 F10 E11 C10 C11 B10 B11 D11 D10 E10
MB_DQ15 MB_DQ14 MB_DQ13 MB_DQ12 MB_DQ11 MB_DQ10 MB_DQ9 MB_DQ8 MB_WDQS1 MB_RDQS1 MB_DM1
BI BI BI BI BI BI BI BI IN OUT IN
12 17 12 17 12 17 12 17 12 17 12 17 12 17 12 17 12 17 12 12
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0 DM0
G3 F2 F3 E2 C3 C2 B3 B2 D2 D3 E3
MB_DQ7 MB_DQ6 MB_DQ5 MB_DQ4 MB_DQ3 MB_DQ2 MB_DQ1 MB_DQ0 MB_WDQS0 MB_RDQS0 MB_DM0
BI BI BI BI BI BI BI BI IN OUT IN
ZQ
A4
DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 WDQS3 RDQS3 DM3 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16
12 17 12 17 12 17 12 17 12 17 12 17 12 17 12 17 12 17 12 12 12 12 12 12 12 12 12 12
12 12 12 12 12 12 12 12 12
17 17 17 17 17 17 17 17
V1 R12 R9 R4 R1 N12 N9 V12 N4 N1 J9 J4 E12 E9 E4 E1 C12 C9 C4 C1 A12 A1
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
V2 M12 M1 V11 F12 F1 A11 A2
VDD VDD VDD VDD VDD VDD VDD VDD
K12 K1
VDDA VDDA
J12 J1
VSSA VSSA
17 17 17 17 17 17 17 17
IC
GDDR136 (1Gbit) MF=0 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
T12 T9 T4 T1 P12 P9 P4 P1 L11 L2 G11 G2 D12 D9 D4 D1 B12 B9 B4 B1
VSS VSS VSS VSS VSS VSS VSS VSS
V3 L12 L1 G12 G1 A10 V10 A3
C
B
X802980-019
17 12 12
MB_ZQ_TOP
1 R7E1
V_MEM X802980-019
243 OHM 1%
2 CH
402
1 R7R2
PARTITION B DECOUPLING
549 OHM 1%
2 EMPTY 402
MEM_B_VREF1
OUT
16 17
V_MEM 1 R7R4
A
1.27 KOHM 1% 2 EMPTY 402
V_MEM MEMORY B, TOP, DECOUPLING
C7R6
0.1 UF 10% 6.3 V X5R 402
[PAGE_TITLE=MEMORY [PAGE_TITLE=MEMOR Y PARITION B, TOP]
1 2
C7D11 4.7 UF 10% 6.3 V X5R 805
A C7D13 0.1 UF 10% 6.3 V X5R 402
C7D9
0.1 UF 10% 6.3 V X5R 402
DRAWING Wed Feb 10 16:23:27 2010
C7E3
0.1 UF 10% 6.3 V X5R 402
C7E2
0.1 UF 10% 6.3 V X5R 402
MICROSOFT CONFIDENTIAL
C7D14 0.1 UF 10% 6.3 V X5R 402
C7D10 0.1 UF 10% 6.3 V X5R 402
PROJECT NAME TRINITY_XDK
C7D7
0.1 UF 10% 6.3 V X5R 402
PAGE 16/81
C7D8
0.1 UF 10% 6.3 V X5R 402
FAB G
REV 1.01
8
7
6
5
7
6
5
4
3
2
3
2
1
CR-17 : @TRINITY_LIB.TRINITY(SCH_1):PAGE17
8
4
1
MEMORY PARTITION B, BOTTOM CHIP SELECT = 1, MIRROR FUNCTION = 1
D
D V_MEM
1 R7R1
1 R7R3
2 CH
2 CH
60.4 OHM 1%
12 12 4
C
B
12
IN IN IN
IN
402
MB_CLK1_DP MB_CLK1_DN MEM_RST
60.4 OHM 1% J11 J10 V9
MB_A
12
IN
MB_BA
12 12 12 12 12
IN IN IN IN IN
MB_CKE MB_WE_N MB_CAS_N MB_RAS_N MB_CS1_N
4
IN
MEM_SCAN_BOT_EN
U7R1
EMPTY
402
11 10 9 8 7 6 5
J2 L9 K11 M4 K2 L4 K3 H2
4 3 2 1 0
K4 M9 K10 H11 K9
2 1 0
H3 G4 G9 H9 H4 F9 H10 F4 J3 A9
4
IN
MEM_SCAN_EN
V4
17 16
IN IN
MEM_B_VREF0 MEM_B_VREF1
H1 H12
GDDR136 (1Gbit) MF=1
CLK_DP CLK_DN RESET
A12(1Gbit only, dual-load) A7/A11 A8/A10 A3/A9 A10/A8 A11/A7 A2/A6 A1/A5 A0/A4 A9/A3 A6/A2 A5/A1 A4/A0 RAS_N/BA2 BA0/BA1 BA1/BA0 WE_N/CKE CKE/WE_N CS_N/CAS_N BA2/RAS_N CAS_N/CS_N CS1_N (1Gbit only, single-load) MF SCAN_EN VREF1 VREF0
V_MEM
V_MEM
DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 WDQS3 RDQS3 DM3
T3 T2 R3 R2 M3 N2 L3 M2 P2 P3 N3
MB_DQ23 MB_DQ22 MB_DQ21 MB_DQ20 MB_DQ19 MB_DQ18 MB_DQ17 MB_DQ16 MB_WDQS2 MB_RDQS2 MB_DM2
BI BI BI BI BI BI BI BI IN OUT IN
12 16 12 16 12 16 12 16 12 16 12 16 12 16 12 16 12 16 12 12
DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 WDQS2 RDQS2 DM2
T10 T11 R10 R11 M10 N11 L10 M11
BI BI BI BI BI BI BI
P11 P10 N10
MB_DQ31 MB_DQ30 MB_DQ29 MB_DQ28 MB_DQ27 MB_DQ26 MB_DQ25 MB_DQ24 MB_WDQS3 MB_RDQS3 MB_DM3
BI IN OUT IN
12 16 12 16 12 16 12 16 12 16 12 16 12 16 12 16 12 16 12 12
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 WDQS1 RDQS1 DM1
G10 F11 F10 E11 C10 C11 B10 B11 D11 D10 E10
MB_DQ7 MB_DQ6 MB_DQ5 MB_DQ4 MB_DQ3 MB_DQ2 MB_DQ1 MB_DQ0 MB_WDQS0 MB_RDQS0 MB_DM0
BI BI BI BI BI BI BI BI IN OUT IN
12 16 12 16 12 16 12 16 12 16 12 16 12 16 12 16 12 16 12 12
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0 DM0
G3 F2 F3 E2 C3 C2 B3 B2 D2
MB_DQ15 MB_DQ14 MB_DQ13 MB_DQ12 MB_DQ11 MB_DQ10 MB_DQ9 MB_DQ8 MB_WDQS1 MB_RDQS1 MB_DM1
BI BI BI BI BI BI BI BI
12 16 12 16 12 16 12 16 12 16 12 16 12 16 12 16 12 16 12 12
ZQ
A4
D3 E3
OUT IN IN
U7R1 V1 R12 R9 R4 R1 N12 N9 V12 N4 N1 J9 J4 E12 E9 E4 E1 C12
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
C9 C4 C1 A12 A1
VDDQ VDDQ VDDQ VDDQ VDDQ
V2 M12 M1 V11 F12 F1 A11 A2
VDD VDD VDD VDD VDD VDD VDD VDD
K12 K1
VDDA VDDA
J12 J1
VSSA VSSA
EMPTY GDDR136 (1Gbit) MF=1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
T12 T9 T4 T1 P12 P9 P4 P1 L11 L2 G11 G2 D12 D9 D4
VSSQ VSSQ VSSQ VSSQ VSSQ
D1 B12 B9 B4 B1
VSS VSS VSS VSS VSS VSS VSS VSS
V3 L12 L1 G12 G1 A10 V10 A3
C
B
X802980-019
MB_ZQ_BOT
1 R7T1
243 OHM 1%
X802980-019
2 CH
1 R7D4
402
549 OHM 1%
V_MEM
2 EMPTY 402
MEM_B_VREF0
OUT
1 R7D5
A
1.27 KOHM 1%
2 EMPTY 402
MEMORY B, BOTTOM, DECOUPLING
16 17
C7D12 0.1 UF 10% 6.3 V X5R 402
[PAGE_TITLE=MEMORY [PAGE_TITLE=MEMOR Y PARITION B, BOTTOM]
C7R7
0.1 UF 10% 6.3 V X5R 402
C7R4
0.1 UF 10% 6.3 V X5R 402
DRAWING Wed Feb 10 16:23:27 2010
C7T2
0.1 UF 10% 6.3 V X5R 402
C7T1
0.1 UF 10% 6.3 V X5R 402
MICROSOFT CONFIDENTIAL
C7R8
0.1 UF 10% 6.3 V X5R 402
C7R5
0.1 UF 10% 6.3 V X5R 402
PROJECT NAME TRINITY_XDK
C7R2
0.1 UF 10% 6.3 V X5R 402
PAGE 17/81
C7R3
0.1 UF 10% 6.3 V X5R 402
FAB G
REV 1.01
A
8
7
6
5
7
6
5
4
3
2
3
2
1
CR-18 : @TRINITY_LIB.TRINITY(SCH_1):PAGE18
8
4
1
MEMORY PARTITION C, TOP CHIP SELECT = 0, MIRROR FUNCTION = 0 V_MEM
D
D 1 R5F4
1 R5F3
CH 2 402
CH 2 402
60.4 OHM 1%
C
B
13 13 4
IN IN IN
MC_CLK0_DP MC_CLK0_DN MEM_RST
13
IN
MC_A
V_MEM
60.4 OHM 1% U5F1
J11 J10 V9
11 10 9 8 7 6 5 4 3 2 1 0
J2 L4 K2 M9 K11 L9 K10 H11 K9 M4 K3 H2 K4
2 1 0
H10 G9 G4
13
IN
MC_BA
13 13 13 13 13 13 4
IN IN IN IN IN IN IN
MC_CKE MC_WE_N MC_CAS_N MC_RAS_N MC_CS0_N MC_CS1_N MEM_SCAN_TOP_EN
H4 H9 F4 H3 F9 J3 A9
4
IN
MEM_SCAN_EN
V4
18 19
IN IN
MEM_C_VREF1 MEM_C_VREF0
H1 H12
U5F1
IC GDDR136 (1Gbit) MF=0
CLK_DP CLK_DN RESET
A12(1Gbit only, dual-load) A11/A7 A10/A8 A9/A3 A8/A10 A7/A11 A6/A2 A5/A1 A4/A0 A3/A9 A2/A6 A1/A5 A0/A4 BA2/RAS_N BA1/BA0 BA0/BA1 CKE/WE_N WE_N/CKE CAS_N/CS_N RAS_N/BA2 CS_N/CAS_N CS1_N (1Gbit only, single-load) MF SCAN_EN VREF1 VREF0
DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 WDQS3 RDQS3 DM3
T3 T2 R3 R2 M3 N2 L3 M2 P2 P3 N3
MC_DQ31 MC_DQ30 MC_DQ29 MC_DQ28 MC_DQ27 MC_DQ26 MC_DQ25 MC_DQ24 MC_WDQS3 MC_RDQS3 MC_DM3
BI BI BI BI BI BI BI BI IN OUT IN
13 19 13 19 13 19 13 19 13 19 13 19 13 19 13 19 13 19 13 13
DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 WDQS2 RDQS2 DM2
T10 T11 R10 R11 M10 N11 L10 M11 P11 P10 N10
BI BI BI BI BI BI BI BI IN OUT IN
13 19 13 19 13 19 13 19 13 19 13 19 13 19 13 19 13 19 13 13
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 WDQS1 RDQS1 DM1
G10 F11 F10 E11 C10 C11 B10 B11 D11 D10 E10
MC_DQ23 MC_DQ22 MC_DQ21 MC_DQ20 MC_DQ19 MC_DQ18 MC_DQ17 MC_DQ16 MC_WDQS2 MC_RDQS2 MC_DM2 MC_DQ15 MC_DQ14 MC_DQ13 MC_DQ12 MC_DQ11 MC_DQ10 MC_DQ9 MC_DQ8 MC_WDQS1 MC_RDQS1 MC_DM1
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0 DM0
G3 F2 F3 E2 C3 C2 B3 B2 D2 D3 E3
MC_DQ7 MC_DQ6 MC_DQ5 MC_DQ4 MC_DQ3 MC_DQ2 MC_DQ1 MC_DQ0 MC_WDQS0 MC_RDQS0 MC_DM0
BI BI BI BI BI BI BI BI IN OUT
ZQ
A4
BI BI BI BI BI BI BI BI IN OUT IN
13 13 13 13 13 13 13 13 13 19 13
19 19 19 19 19 19 19 19 13
V1 R12 R9 R4 R1 N12 N9 V12 N4 N1 J9 J4 E12 E9 E4 E1 C12 C9 C4 C1 A12 A1
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
V2 M12 M1 V11 F12 F1 A11 A2
VDD VDD VDD VDD VDD VDD VDD VDD
K12 K1
VDDA VDDA
J12 J1
VSSA VSSA
13 19 13 19 13 19 13 19 13 19 13 19 13 19 13 19 13 19 13 13
IC
GDDR136 (1Gbit) MF=0 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
T12 T9 T4 T1 P12 P9 P4 P1 L11 L2 G11 G2 D12 D9 D4 D1 B12 B9 B4 B1
VSS VSS VSS VSS VSS VSS VSS VSS
V3 L12 L1 G12 G1 A10 V10 A3
C
B
X802980-019
IN
MC_ZQ_TOP
1 R5F5
243 OHM 1% 2 CH 402
X802980-019
V_MEM 1 R5U5
549 OHM 1%
2 EMPTY 402
1 R5U4
A
1.27 KOHM 1% 2 EMPTY 402
MEM_C_VREF1
OUT
18 19
C5U9
0.1 UF 10% 6.3 V X5R 402
MC_CLK0 STITCHING CAP V_MEM
PARTITION C DECOUPLING V_MEM
MEMORY C, TOP, DECOUPLING 1 2
C5U1
0.1 UF 10% 6.3 V X5R 402
1
C5F10
4.7 UF 10%
6.3 V 2 X5R 805
[PAGE_TITLE=MEMORY [PAGE_TITLE=MEMOR Y PARTITION C, TOP]
V_MEM
C6F10
C6F8
C6F4
C6F1
0.1 UF 10% 6.3 V X5R
402
402
402
402
0.1 UF 10% 6.3 V X5R
0.1 UF 10% 6.3 V X5R
DRAWING Wed Feb 10 16:23:27 2010
0.1 UF 10% 6.3 V X5R
MICROSOFT CONFIDENTIAL
C6F2
A
0.1 UF 10% 6.3 V X5R
C6F5
0.1 UF 10% 6.3 V X5R
C6F7
0.1 UF 10% 6.3 V X5R
0.1 UF 10% 6.3 V X5R
402
402
402
402
PROJECT NAME TRINITY_XDK
PAGE 18/81
C6F9
FAB G
REV 1.01
8
7
6
5
7
6
5
4
3
2
3
2
1
CR-19 : @TRINITY_LIB.TRINITY(SCH_1):PAGE19
8
4
1
MEMORY PARTITION C, BOTTOM CHIP SELECT = 1, MIRROR FUNCTION = 1 V_MEM
D
D 1 R5U3
1 R5U2
2 CH
2 CH
60.4 OHM 1%
60.4 OHM 1%
402
13 13 4
C
B
13
IN IN IN
IN
402
MC_CLK1_DP MC_CLK1_DN MEM_RST
U5U1 J11 J10 V9
MC_A
11 10 9 8 7 6 5 4
J2 L9 K11 M4 K2 L4 K3 H2 K4
3 2 1 0
M9 K10 H11 K9
13
IN
MC_BA
13 13 13 13 13
IN IN IN IN IN
MC_CKE MC_WE_N MC_CAS_N MC_RAS_N MC_CS1_N
4
IN
MEM_SCAN_BOT_EN
4
IN
MEM_SCAN_EN
V4
19 18
IN IN
MEM_C_VREF0 MEM_C_VREF1
H1 H12
2 1 0
H3 G4 G9 H9 H4 F9 H10 F4 J3 A9
EMPTY GDDR136 (1Gbit) MF=1
CLK_DP CLK_DN RESET
A12(1Gbit only, dual-load) A7/A11 A8/A10 A3/A9 A10/A8 A11/A7 A2/A6 A1/A5 A0/A4 A9/A3 A6/A2 A5/A1 A4/A0 RAS_N/BA2 BA0/BA1 BA1/BA0 WE_N/CKE CKE/WE_N CS_N/CAS_N BA2/RAS_N CAS_N/CS_N CS1_N (1Gbit only, single-load) MF SCAN_EN VREF1 VREF0
V_MEM
DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 WDQS3 RDQS3 DM3
T3 T2 R3 R2 M3 N2 L3 M2 P2 P3 N3
MC_DQ23 MC_DQ22 MC_DQ21 MC_DQ20 MC_DQ19 MC_DQ18 MC_DQ17 MC_DQ16 MC_WDQS2 MC_RDQS2 MC_DM2
BI BI BI BI BI BI BI BI IN OUT IN
DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 WDQS2
T10 T11 R10 R11 M10 N11 L10 M11 P11
MC_DQ31 MC_DQ30 MC_DQ29 MC_DQ28 MC_DQ27 MC_DQ26 MC_DQ25 MC_DQ24 MC_WDQS3
RDQS2 DM2
P10 N10
MC_RDQS3 MC_DM3
BI BI BI BI BI BI BI BI IN OUT IN
18 13 13
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 WDQS1 RDQS1 DM1
G10 F11 F10 E11 C10 C11 B10 B11 D11 D10 E10
MC_DQ7 MC_DQ6 MC_DQ5 MC_DQ4 MC_DQ3 MC_DQ2 MC_DQ1 MC_DQ0 MC_WDQS0 MC_RDQS0 MC_DM0
BI BI BI BI BI BI BI BI IN OUT IN
13 18 13 18 13 18 13 18 13 18 13 18 13 18 13 18 13 18 13 13
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0
G3 F2 F3 E2 C3 C2 B3 B2 D2 D3
MC_DQ15 MC_DQ14 MC_DQ13 MC_DQ12 MC_DQ11 MC_DQ10 MC_DQ9 MC_DQ8 MC_WDQS1 MC_RDQS1
13 18 13 18 13 18 13 18 13 18 13 18 13 18 13 18 13 18 13
DM0 ZQ
E3 A4
BI BI BI BI BI BI BI BI IN OUT IN
MC_DM1
13 13 13 13 13 13 13 13 13
V1 R12 R9 R4 R1 N12 N9 V12 N4 N1 J9 J4 E12 E9 E4 E1 C12 C9 C4
18 18 18 18 18 18 18 18
X802980-019
1 R5F1
VDD VDD VDD VDD VDD VDD VDD VDD
K12 K1
VDDA VDDA
J12 J1
VSSA VSSA
VSSQ VSSQ VSSQ VSS VSS VSS VSS VSS VSS VSS VSS
T12 T9 T4 T1 P12 P9 P4 P1 L11 L2 G11 G2 D12 D9 D4 D1 B12
C
B9 B4 B1 V3 L12 L1 G12 G1 A10 V10 A3
B
13
243 OHM 1%
2 CH
V_MEM MEMORY C, BOTTOM, DECOUPLING
MEM_C_VREF0
OUT
18 19
C6U9
1 R5F2
A
VDDQ VDDQ VDDQ
V2 M12 M1 V11 F12 F1 A11 A2
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
X802980-019
549 OHM 1%
1.27 KOHM 1% 2 EMPTY 402
C1 A12 A1
GDDR136 (1Gbit) MF=1
MC_ZQ_BOT
402
402
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
1 R5U1
V_MEM
2 EMPTY
EMPTY
U5U1
13 18 13 18 13 18 13 18 13 18 13 18 13 18 13 18 13 18 13 13
C5F1
0.1 UF 10% 6.3 V X5R 402
[PAGE_TITLE=MEMORY [PAGE_TITLE=MEMOR Y PARITION C, BOTTOM]
0.1 UF 10% 6.3 V X5R 402
C6U6
0.1 UF 10% 6.3 V X5R 402
DRAWING Wed Feb 10 16:23:27 2010
C6U3
0.1 UF 10% 6.3 V X5R 402
C6U1
0.1 UF 10% 6.3 V X5R 402
MICROSOFT CONFIDENTIAL
C6U2
0.1 UF 10% 6.3 V X5R 402
C6U4
0.1 UF 10% 6.3 V X5R 402
PROJECT NAME TRINITY_XDK
C6U5
0.1 UF 10% 6.3 V X5R 402
PAGE 19/81
C6U8
0.1 UF 10% 6.3 V X5R 402
FAB G
REV 1.01
A
8
7
6
5
7
6
5
4
3
2
3
2
1
CR-20 : @TRINITY_LIB.TRINITY(SCH_1):PAGE20
8
CHIP SELECT = 0, MIRROR FUNCTION = 0
1 R6F4
1 R6F3
2 CH
2 CH
60.4 OHM 1%
D
60.4 OHM 1%
V_MEM
402
402
IN IN IN
MD_CLK0_DP MD_CLK0_DN MEM_RST
13
IN
MD_A
J11 J10 V9
C
B
11 10 9 8 7 6 5 4 3 2 1 0
J2 L4 K2 M9 K11 L9 K10 H11 K9 M4 K3 H2 K4
2 1 0
H10 G9 G4
13
IN
MD_BA
13 13 13 13 13 13 4
IN IN IN IN IN IN IN
MD_CKE MD_WE_N MD_CAS_N MD_RAS_N MD_CS0_N MD_CS1_N MEM_SCAN_TOP_EN
H4 H9 F4 H3 F9 J3 A9
4
IN
MEM_SCAN_EN
V4
IN IN
MEM_D_VREF1 MEM_D_VREF0
H1 H12
20 21
IC
U6F1 IC
U6F1 13 13 4
1
MEMORY PARTITION D, TOP
V_MEM
D
4
CLK_DP CLK_DN RESET
GDDR136 (1Gbit) MF=0
A12(1Gbit only, dual-load) A11/A7 A10/A8 A9/A3 A8/A10 A7/A11 A6/A2 A5/A1 A4/A0 A3/A9 A2/A6 A1/A5 A0/A4 BA2/RAS_N BA1/BA0 BA0/BA1 CKE/WE_N WE_N/CKE CAS_N/CS_N RAS_N/BA2 CS_N/CAS_N CS1_N (1Gbit only, single-load) MF SCAN_EN VREF1 VREF0
GDDR136 (1Gbit)
DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 WDQS3 RDQS3 DM3
T3 T2 R3 R2 M3 N2 L3 M2 P2 P3 N3
MD_DQ31 MD_DQ30 MD_DQ29 MD_DQ28 MD_DQ27 MD_DQ26 MD_DQ25 MD_DQ24 MD_WDQS3 MD_RDQS3 MD_DM3
BI BI BI BI BI BI BI BI IN OUT IN
13 21 13 21 13 21 13 21 13 21 13 21 13 21 13 21 13 21 13 13
DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 WDQS2 RDQS2 DM2
T10 T11 R10 R11 M10 N11 L10 M11 P11 P10 N10
MD_DQ23 MD_DQ22 MD_DQ21 MD_DQ20 MD_DQ19 MD_DQ18 MD_DQ17 MD_DQ16 MD_WDQS2 MD_RDQS2 MD_DM2
BI BI BI BI BI BI BI BI IN OUT IN
13 21 13 21 13 21 13 21 13 21 13 21 13 21 13 21 13 21 13 13
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 WDQS1 RDQS1 DM1
G10 F11 F10 E11 C10 C11 B10 B11 D11 D10 E10
MD_DQ15 MD_DQ14 MD_DQ13 MD_DQ12 MD_DQ11 MD_DQ10 MD_DQ9 MD_DQ8 MD_WDQS1 MD_RDQS1 MD_DM1
BI BI BI BI BI BI BI BI IN OUT IN
13 21 13 21 13 21 13 21 13 21 13 21 13 21 13 21 13 21 13 13
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0 DM0
G3 F2 F3 E2 C3 C2 B3 B2 D2 D3 E3
MD_DQ7 MD_DQ6 MD_DQ5 MD_DQ4 MD_DQ3 MD_DQ2 MD_DQ1 MD_DQ0 MD_WDQS0 MD_RDQS0 MD_DM0
BI BI BI BI BI BI BI BI IN OUT IN
13 21 13 21 13 21 13 21 13 21 13 21 13 21 13 21 13 21 13 13
ZQ
A4
V1 R12 R9 R4 R1 N12 N9 V12 N4 N1 J9 J4 E12 E9 E4 E1 C12 C9 C4 C1 A12 A1
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
V2 M12 M1 V11 F12 F1 A11 A2 K12 K1
VDDA VDDA
J12 J1
VSSA VSSA
MF=0 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
T12 T9 T4 T1 P12 P9 P4 P1 L11 L2 G11 G2 D12 D9 D4 D1 B12 B9 B4 B1
VDD VDD
VSS VSS
V3 L12
VDD VDD VDD VDD VDD VDD
VSS VSS VSS VSS VSS VSS
L1 G12 G1 A10 V10 A3
C
X802980-019
B
MD_ZQ_TOP
1 R6F5 X802980-019
V_MEM
243 OHM 1%
2 CH
402
1 R6U5
549 OHM 1%
2 EMPTY 402
1 R6U4
A
1.27 KOHM 1% 2 EMPTY 402
MEM_D_VREF1
OUT
20 21
C6U7
0.1 UF 10% 6.3 V X5R 402
PARTITION D DECOUPLING V_MEM
MEMORY D, TOP, DECOUPLING 1
A
C6F11
4.7 UF 10%
V 2 6.3 X5R 805
[PAGE_TITLE=MEMORY [PAGE_TITLE=MEMOR Y PARTITION D, TOP]
V_MEM
C5F9
0.1 UF 10% 6.3 V X5R 402
C5F7
0.1 UF 10% 6.3 V X5R 402
DRAWING Wed Feb 10 16:23:28 2010
C5F4
0.1 UF 10% 6.3 V X5R 402
C5F3
0.1 UF 10% 6.3 V X5R 402
MICROSOFT CONFIDENTIAL
C5F2
0.1 UF 10% 6.3 V X5R 402
C5F5
0.1 UF 10% 6.3 V X5R 402
PROJECT NAME TRINITY_XDK
C5F6
C5F8
0.1 UF 10% 6.3 V X5R 402
PAGE 20/81
0.1 UF 10% 6.3 V X5R 402
FAB G
REV 1.01
8
7
6
5
7
6
5
4
3
2
3
2
1
CR-21 : @TRINITY_LIB.TRINITY(SCH_1):PAGE21
8
4
1
MEMORY PARTITION D, BOTTOM CHIP SELECT = 1, MIRROR FUNCTION = 1 V_MEM
D
D
1 R6U2
1 R6U3
2 CH
2 CH 402
60.4 OHM 1%
60.4 OHM 1% 402
13 13 4
C
B
13
IN IN IN
IN
MD_CLK1_DP MD_CLK1_DN MEM_RST
MD_A
11 10 9 8 7 6 5 4 3 2 1 0
J2 L9 K11 M4 K2 L4 K3 H2 K4 M9 K10 H11 K9
13
IN
MD_BA
13 13 13 13 13
IN IN IN IN IN
MD_CKE MD_WE_N MD_CAS_N MD_RAS_N MD_CS1_N
4
IN
MEM_SCAN_BOT_EN
IN
MEM_SCAN_EN
V4
IN IN
MEM_D_VREF0 MEM_D_VREF1
H1 H12
4 21 20
2 1 0
EMPTY
U6U1
J11 J10 V9
H3 G4 G9 H9 H4 F9 H10 F4 J3 A9
GDDR136 (1Gbit) MF=1
CLK_DP CLK_DN RESET
A12(1Gbit only, dual-load) A7/A11 A8/A10 A3/A9 A10/A8 A11/A7 A2/A6 A1/A5 A0/A4 A9/A3 A6/A2 A5/A1 A4/A0 RAS_N/BA2 BA0/BA1 BA1/BA0 WE_N/CKE CKE/WE_N CS_N/CAS_N BA2/RAS_N CAS_N/CS_N CS1_N (1Gbit only, single-load) MF SCAN_EN VREF1 VREF0
DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 WDQS3 RDQS3 DM3
T3 T2 R3 R2 M3 N2 L3 M2 P2 P3 N3
MD_DQ23 MD_DQ22 MD_DQ21 MD_DQ20 MD_DQ19 MD_DQ18 MD_DQ17 MD_DQ16 MD_WDQS2 MD_RDQS2 MD_DM2
BI BI BI BI BI BI BI BI IN OUT IN
13 20 13 20 13 20 13 20 13 20 13 20 13 20 13 20 13 20 13 13
DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 WDQS2 RDQS2 DM2
T10 T11 R10 R11 M10 N11 L10 M11 P11 P10 N10
BI BI BI BI BI BI BI BI IN OUT IN
13 20 13 20 13 20 13 20 13 20 13 20 13 20 13 20 13 20 13 13
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 WDQS1 RDQS1 DM1
G10 F11 F10 E11 C10 C11 B10 B11 D11 D10 E10
MD_DQ31 MD_DQ30 MD_DQ29 MD_DQ28 MD_DQ27 MD_DQ26 MD_DQ25 MD_DQ24 MD_WDQS3 MD_RDQS3 MD_DM3 MD_DQ7 MD_DQ6 MD_DQ5 MD_DQ4 MD_DQ3 MD_DQ2 MD_DQ1 MD_DQ0 MD_WDQS0 MD_RDQS0 MD_DM0
BI BI BI BI BI BI BI BI IN OUT IN
13 20 13 20 13 20 13 20 13 20 13 20 13 20 13 20 13 20 13 13
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0 DM0
G3 F2 F3 E2 C3 C2 B3 B2 D2 D3 E3
MD_DQ15 MD_DQ14 MD_DQ13 MD_DQ12 MD_DQ11 MD_DQ10 MD_DQ9 MD_DQ8 MD_WDQS1 MD_RDQS1 MD_DM1
BI BI BI BI BI BI BI BI IN OUT
13 20 13 20 13 20 13 20 13 20 13 20 13 20 13 20 13 20 13 13
ZQ
A4
V_MEM EMPTY
U6U1 V1 R12 R9 R4 R1 N12 N9 V12 N4 N1 J9 J4 E12 E9 E4 E1 C12 C9 C4 C1 A12 A1
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
V2 M12 M1 V11 F12 F1 A11 A2
VDD VDD VDD VDD VDD VDD VDD VDD
K12 K1
VDDA VDDA
J12 J1
VSSA VSSA
GDDR136 (1Gbit) MF=1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
T12 T9 T4 T1 P12 P9 P4 P1 L11 L2 G11 G2 D12 D9 D4 D1 B12 B9 B4 B1
VSS VSS VSS VSS VSS VSS VSS VSS
V3 L12 L1 G12 G1 A10 V10 A3
C
B
X802980-019
IN
MD_ZQ_BOT
1 R6U1
V_MEM
243 OHM 1% 2 CH 402
X802980-019
1 R6F1
549 OHM 1%
2 EMPTY 402
1 R6F2
1.27 KOHM 1%
A
2 EMPTY 402
MEM_D_VREF0
OUT
20 21
V_MEM
C6F3
0.1 UF 10% 6.3 V X5R 402
V_MEM
MEMORY D, BOTTOM, DECOUPLING
C5U12 0.1 UF 10% 6.3 V X5R 402
C6U10 0.1 UF 10% 6.3 V X5R 402
[PAGE_TITLE=MEMORY [PAGE_TITLE=MEMOR Y PARTITION D, BOTTOM]
C6F6
0.1 UF 10% 6.3 V X5R 402
C7E12 0.1 UF 10% 6.3 V X5R 402
C7T10 0.1 UF 10% 6.3 V X5R 402
C7E1
0.1 UF 10% 6.3 V X5R 402
MEMORY D, BOTTOM, DECOUPLING C7D15 0.1 UF 10% 6.3 V X5R 402
C7R9
0.1 UF 10% 6.3 V X5R 402
A
C5U8
C5U5
C5U4
C5U3
C5U6
C5U7
C5U11
C5U10
402
402
402
402
402
402
402
402
0.1 UF 10% 6.3 V X5R
0.1 UF 10% 6.3 V X5R
DRAWING Wed Feb 10 16:23:28 2010
0.1 UF 10% 6.3 V X5R
0.1 UF 10% 6.3 V X5R
MICROSOFT CONFIDENTIAL
0.1 UF 10% 6.3 V X5R
0.1 UF 10% 6.3 V X5R
PROJECT NAME TRINITY_XDK
0.1 UF 10% 6.3 V X5R
PAGE 21/81
0.1 UF 10% 6.3 V X5R
FAB G
REV 1.01
8
7
6
7
6
5
4
3
2
1
CR-22 : @TRINITY_LIB.TRINITY(SCH_1):PAGE22
8
5
R4B16 1 2 1 MOHM 5% CH 402
27
R3B3
10 KOHM 5% CH 402
2
SM XTAL
2 V_3P3STBY 1
2
C3B6
22 PF 5% 50 V NPO 402
C3B5
FT3P1 FTP
22 PF 5% 50 V NPO 402
1
1
27
IN
2
2
470 PF 5% 50 V EMPTY 402
R3B11 2 1 2
10 KOHM 5% EMPTY 1 402
1 K KO OHM 402
5% CH
1 HANA_V_12P0_DET
B6 M2 E12
V_12P0_DET CORE_RST_N* POR_BYPASS
HANA_XTAL_OUT
P2 R2
HANA_XTAL_VSS_CAP
P3
XTAL_VSS_CAP
HANA_XTAL_BYPASS
M4
XTAL_BYPASS
ANA_CLK_OE_R
R3P1 2 1 475 OHM 402 475 OHM 402
B
BI IN
60 60 60 60 60
IN OUT IN IN OUT
HANA_TCLK HANA_TDO HANA_TDI HANA_TMS HANA_TRST
FT3P7 FTP FT3P6 FTP FT3P5 FTP FT3P8 FTP FT3P9 FTP
1 1 1 1 1
SMC_HDMI_HPD ANA_V12P0_PWRGD SMC_RST_N
1 OF 4
CH 2 402 V_RST_OK V_12P0_OK SMC_RST_N*
E11 D10 M3
XTAL_IN XTAL_OUT
1% CH
HANA_CLK_DRV_RSET2 HANA_CLK_DRV_RSET1
N3 K13 R11
ANA_CLK_OE CLK_DRV_RSET2 CLK_DRV_RSET1
33 OHM 5% CH 402
69.8 OHM 1% CH 402
1% CH
N1 P1
G12 F11 J12 F12 H12
FTP FT3R1
R3C4 1 2
FTP FT3R3
CPU_CLK_DP_R
NB_CLK_DP NB_CLK_DN
R13 P13
GPU_CLK_DP_R
PCIEX_CLK_DP PCIEX_CLK_DN
R10 P10
PCIEX_CLK_DP_R
SATA_CLK_DP SATA_CLK_DN
R9 P9
SATA_CLK_DP_R
SATA_CLK_REF
R6
SATA_CLK_REF_R
M15 M14
HANA_PIX_CLK_2X_DP_R
ENET_CLK
P6
ENET_CLK_R
STBY_CLK
R8
STBY_CLK_R
AUD_CLK
R4
AUD_CLK_R
AV_CLK
N2
HANA_AV_CLK
0011 110 R/W HEX WRITE 0011 110 0 0X3C READ 0011 110 1 0X3D
OUT OUT
GPU_CLK_DN_R
49.9 OHM 1% CH 402
R3C2 1 2
R3C1 1 2
33 OHM 5% CH 402
49.9 OHM 1% CH 402
R3B21 1 2
SATA_CLK_DN_R
R3B19
R3B18
1 5% 2 33 OHM CH 402
2 49.9 1 OHM 1% CH 402
1
1
1
FTP FT2R3
1
FTP FT2P2
SATA_CLK_REF
OUT 1
R3C12 1 2
R3C14 1 2
33 OHM 5% CH 402
69.8 OHM 1% CH 402
C3B9
R3C13 1 2
3 3 O HM HM 5 %
69.8 OHM 1%
402
CH
402
26 26
26
10 PF 5%
B
50 V 2 EMPTY 402
1
FTP FT3P3
HANA_PIX_CLK_2X_DP HANA_PIX_CLK_2X_DN R3C11 1 2
C
FTP FT2R4
OUT OUT
33 OHM 5% CH 402
26 26
FTP FT3R10
49.9 OHM 1% CH 402
33 OHM 5% CH 402
R3B14 1 2
FTP FT3N1
OUT OUT
SATA_CLK_DP SATA_CLK_DN R3B16 1 2
R3B17 1 2 1
FTP FT3R11
49.9 OHM 1% CH 402
33 OHM 5% CH 402
HANA_PIX_CLK_2X_DN_R
1
PCIEX_CLK_DP PCIEX_CLK_DN R3B20 1 2
PCIEX_CLK_DN_R
10 KOHM 5% CH 2 402
0111 000 R/W HEX WRITE 0111 000 0 0X70 READ 0111 000 1 0X71
4 4
CPU_CLK_DN_R
R3N5 1
X802478-003
GPU_CLK_DP GPU_CLK_DN R3C7 1 2
R3C3 1 2
SMB_DATA SMB_CLK
I2C ADDRESS 0011 100 R/W HEX WRITE 0011 100 0 0X38 READ 0011 100 1 0X39
D
49.9 OHM 1% CH 402
33 OHM 5% CH 402
R14 P14
2 2
R3C8 1 2
33 OHM 5% CH 402
10 KOHM 5%
SMC_RST_N_R
OUT OUT
69.8 OHM 1% CH 402
33 OHM 5% CH 402
1 CH
TCK TDO TDI TMS TRST
CPU_CLK_DP CPU_CLK_DN R3C9 1 2
R3C5 1 2
27 27 42 27 42 59
2 R3R15
CPU_CLK_DP CPU_CLK_DN
PIX_CLK_OUT_DP PIX_CLK_OUT_DN
1 R3C10 1 2
FTP FT3P2
OUT OUT OUT 1 1
1 KOHM 5%
IC
HANA
2R3N81
41 27 59 27 59 55
1
1% CH
1 R3R16 U3B2
1
ANA_CLK_OE
SMB_DATA SMB_CLK
78 7 OH M 402
C4B2
HANA_XTAL_IN
R3B10
2 R3C6 1 2
402
1 KOHM 5% 1 EMPTY 402
C
1
HANA_POR_BYPASS
2 R3N7
FT3R13 FTP
3
R4B6 1 2
HANA_V_12P0_DET_R
787 OHM 1% 402 CH
ANA_RST_N
IN
Y3B1 27 MHZ
1
R4B7 1 2
11 KOHM 1% 402 CH 1 FT3R14 FTP
R3B9 1 2
D
4
HANA, CLOCKS + STRAPPING
V_12P0
OUT OUT 1
4 4
FTP FT3P4
CH
R3B13 1 2
ENET_CLK
OUT
33 OHM 5% CH 402
1
C3B8
1
10 PF 5%
32
FTP FT2R5
50 V 2 EMPTY 402
R3B15 1 2
STBY_CLK
33 OHM 5% CH 402
1 2
A
R3B12 1 2 33 OHM 5% CH 402
OUT C3B10 10 PF 5% 50 V EMPTY 402
1
FTP FT3N2
1
FTP FT2R1
AUD_CLK
OUT
27
A 29
1 C3B7
10 PF 5%
50 V 2 EMPTY 402
[PAGE TITLE=HANA, CLOCKS + STRAPING, JTAG]
DRAWING Wed Feb 10 16:23:28 2010
MICROSOFT CONFIDENTIAL
PROJECT NAME TRINITY_XDK
PAGE 22/81
FAB G
REV 1.01
8
7
6
5
7
6
5
4
3
2
3
2
1
CR-23 : @TRINITY_LIB.TRINITY(SCH_1):PAGE23
8
4
1
HANA, VIDEO + FAN + AUDIO U3B2
2 OF 4 HANA
D
4 4
IN IN
V_1P8 V_1P8STB STBY Y 1 2
4 4
GPU_PIX_CLK_1X PIX_DATA STBY_CLK STITCH V_3 V_3P3S P3STBY TBY V_1P8STBY
C3T18 0.1 UF 10% 6.3 V X5R 402
IN IN
1 2
V_3P3STBY 1
C3T16
0.1 UF 10% 6.3 V X5R 402
SATA_CLK_REF STITCH V_1P8 V_3P3
2
1
C3T8
0.1 UF 10% 6.3 V X5R 402
2
C2R8
0.1 UF 10% 6.3 V X5R 402
G14
PIX_CLK_IN
14 13 12 11 10
C14 C15 D14 D15 E14
PIX_DATA14 PIX_DATA13 PIX_DATA12 PIX_DATA11 PIX_DATA10
9 8 7 6 5 4 3 2 1 0
E15 F14 F15 G15 H14 H15 J14 J15 K14 K15
PIX_DATA9 PIX_DATA8 PIX_DATA7 PIX_DATA6 PIX_DATA5 PIX_DATA4 PIX_DATA3 PIX_DATA2 PIX_DATA1 PIX_DATA0
L14 L15
HSYNC_IN VSYNC_IN
C8
DAC_RSET
GPU_HSYNC_OUT GPU_VSYNC_OUT HANA_DAC_RSET
IC
VID_INT DAC_D_OUT_DP DAC_D_OUT_DN DAC_C_OUT_DP DAC_C_OUT_DN DAC_B_OUT_DP DAC_B_OUT_DN DAC_A_OUT_DP DAC_A_OUT_DN
L3 A7 B7 A8 B8 A9 B9 A10 B10
29 29 29
IN IN IN IN
HDMI_HPD SB_SPDIF_OUT I2S_BCLK I2S_WS
M1 K1 K2 L2 K4 K3
I2S_SD3 I2S_SD2 I2S_SD1
29
IN
I2S_SD
L1
2 R3B4
2 R3N4
1 R4B12
1 R4B9
1 R4B8
2 CH
2 CH
2 CH
2 CH
37.4 OHM 1%
402
37.4 OHM 1%
402
37.4 OHM 1%
402
2 R3N3
37
VID_DACB_DP
OUT
37
VID_DACA_DP
OUT
37
37.4 OHM 1%
BOARD TEMP SENSOR 23
BRD_TEMP_P
IN
Q4G1 2
V_3P3STBY
HSYNC_OUT VSYNC_OUT
B5 A5
TMDS_EXT_SWING
A2
TMDS_TXC_DP
B1
TMDS_TXC_DN
B2
BRD_TEMP_N
OUT
C VID_HSYNC_OUT_R VID_VSYNC_OUT_R HDMI_TXC_DP R3B8 2 C3B4 1 HDMI_TXC_DP_R 2 1
HDMI_EXT_SWING
0.1 UF 10% 6.3 V X5R 402 HDMI_TXC_DN
2
H1
TMDS_TX2_DN
H2
C3B1
1
R3B5 2 1
HDMI_TX2_DP_R
301 OHM OHM 1% 0 .1 .1 UF UF 1 0% 0% CH 603 6.3 V X5R 402 HDMI_TX2_DN
HDMI_TX1_DP TMDS_TX1_DP
F1
TMDS_TX1_DN
F2
C3B2
1
R3B6 2 1
HDMI_TX1_DP_R
HANA_OP2_DP
27
61 4
61 4
IN IN IN
SMC_PWM0
R4C1 2 1
GPU_TEMP_N
C11 A11
HANA_OP2_DN
IN
C12
FAN_OP1_DP
205 KOHM 1% CH 402
CPU_TEMP_N
23
0.1 UF 10% 6.3 V X5R 402 HDMI_TX1_DN
2 2
ST3C5 SHORT ST3C2
1
1
A
61 4
IN
EDRAM_TEMP_N
2
0.22 UF 10%
36
IN
FAN1_FDBK
B12
FAN_OP1_DN
A15
TEMP_N
402
BND_GAP_CAP
1
SHORT 38 23
23
IN
IN
BRD_TEMP_N
2
ST3C3
FT4N2 FTP
1
1 DB3P1 2
C4B3
0.01 UF
CAL_TEMP_N
2
SHORT ST3C1
D1 D2
1 1 FT4N1 FTP
1
16 10%V X7R 402
1 TEMP_RSET
A6 A14
BND_GAP_CAP TEMP_RSET
R4C2 1
11 KOHM 1% CH 2 402
SHORT
[PAGE TITLE=HANA, VIDEO + FAN + AUDIO]
X802478-003
FAN_OUT2
0.1 UF 10% 6.3 V X5R 402 HDMI_TX0_DN
FAN_OUT1
HANA_SPDIF_OUT HDMI_DDC_CLK HDMI_DDC_DATA
B4 B3 A3 B11 A12
40
OUT
40
OUT
40
OUT
40
OUT
40
B
2R3B71
HDMI_TX0_DP_R
1 1 SPDIF_OUT DDC_SCK DDC_SDA
40
OUT
301 OHM OHM 1% CH 603
FAN_OP1_DP
SHORT ST3C4
TMDS_TX0_DP TMDS_TX0_DN
C4P2
V 2 6.3 X5R
1
2 C3B3 1
FAN_OP2_DP FAN_OP2_DN
OUT
40
301 OHM 1% CH 603
HDMI_TX0_DP 10 KOHM 5% 2 CH 402
OUT OUT OUT
37 37
301 OHM 1% CH 603
HDMI_TX2_DP TMDS_TX2_DP
EMPTY 1
3 23 38
2
1 R4B15
D
402
I2S_SD0
10 KOHM 10 KOHM 10 KOHM 5% 5% 5% 1 CH 1 CH 1 CH 402 402 402
B
1 R4B13
SPDIF_IN I2S_SCK I2S_WS I2S_SD3 I2S_SD2 I2S_SD1
OUT
VID_DACA_DN
422 OHM 1% 1 CH 402
HDMI_HPD
37
VID_DACC_DP VID_DACB_DN
2 R3B2
A4
26
OUT
VID_DACC_DN
787 OHM 1% 2 CH 402
40
OUT
VID_DACD_DP VID_DACD_DN
1 R4B10
C
ANA_VID_INT
HANA_OP2_OUT
R4B14 1 2 HANA_OP2_DN
0 OHM 402
5% CH
FAN1_OUT
1 1
DB4N4 DB4N6 DB4N5 DB4N7
OUT BI BI
37 39 27 37 40 55 27 37 40 55
OUT
23
1 C4C1
OUT
36
V 2 50 EMPTY
OUT CUSTOM THERMAL CALIBRATION PADS LOCATION MUST REMAIN LOCKED
40
100 PF 5%
A
402
CAL_TEMP_N
OUT
23
B15
CPU_TEMP_P
OUT
4 61
GPU_TEMP_P EDRAM_TEMP_P
OUT OUT
4 61
TEMP0_P
B13 A13
TEMPCAL_P
B14
BRD_TEMP_P
OUT FAB G
23 38
TEMP3_P
C13
TEMP2_P TEMP1_P
CAL_TEMP_P
DRAWING
MICROSOFT
PROJECT NAME TRINITY_XDK
PAGE 23/81
4 61
REV 1.01
Wed Feb 10 16:23:28 2010
8
7
6
5
7
6
5
4
CONFIDENTIAL
3
2
3
2
1
CR-24 : @TRINITY_LIB.TRINITY(SCH_1):PAGE24
8
4
1
HANA, POWER + DECOUPLING D
D
V_1P8STBY
V_3P3STBY 3 OF 4
U3B2
V_3P3STBY
HANA
FB3N4 1
C3N37
4.7 UF 10% 6.3 V X5R 805
2 FB 603
0.2A 0.5 DCR
D12 D11
V_HANA_VAA_RTS33S
1
C3N36
4.7 UF 10%
V 2 6.3 X5R 805
VAA_VID_PLL AVSS_VID_PLL
VAA_RTS33S AVSS_RTS33S
C3N38
VAA_GP_PLL AVSS_GP_PLL
0.1 UF 10% 6.3 V X5R 402
VAA_100M_PLL_A AVSS_100M_PLL_A1 AVSS_100M_PLL_A0
V_3P3
C
VAA_100M_PLL_D AVSS_100M_PLL_D
FB3N3 1
C3N13
4.7 UF 10% 6.3 V X5R 805
2 FB 603
0.5A 0.1DCR
V_HANA_VAA_DAC33M
1
C3N23
4.7 UF 10%
V 2 6.3 X5R 805
C3N20
0.1 UF 10% 6.3 V X5R 402
1
C3N27
0.1 UF 10%
V 2 6.3 X5R 402
E9 D9 C9 D8
VAA_DAC33M3 VAA_DAC33M2 VAA_DAC33M1 AVSS_DAC33M1
C7
VAA_DAC33M0
D7 C6
AVSS_DAC33M0
C10
R3N6 1 2
R3
V_HANA_VAA_XTAL_33S
100 OHM 5% CH 402
1 2
N8 P8
C3N17
0.1 UF 10% 6.3 V X5R 402
M6 N6 P5 R5
M12 M13 R7 P7 N15 P15 R15 R12 P12
VDDC_STBY_PLL VSSC_STBY_PLL
N7 M7
VDDC_25M_PLL VSSC_25M_PLL
N5 M5
VDDC_AUD_PLL VSSC_AUD_PLL
N4 P4
VDD_DAC18S VAA_POR18S
E7 D6
VAA_POR33S VAA_FAN33S
VDDIO18S_100M_PLL5 VDDIO18S_100M_PLL4 VDDIO18S_100M_PLL3
N14 N13 P11
VDDIO18S_100M_PLL2 VSSIO18S_100M_PLL2
M10 N12
VDDIO18S_100M_PLL1 VDDIO33S_STBY_PLL VSSIO18S_100M_PLL1 VSSIO33S_STBY_PLL VDDIO18S_100M_PLL0 VSSIO18S_100M_PLL0 VDDIO33S_25M_PLL VSSIO33S_25M_PLL VDDIO18S_PIX_PLL VSSIO18S_PIX_PLL VDDIO33S_AUD_PLL VSSIO33S_AUD_PLL
N9 N11
V_3P3STBY
B
IC
VAA_XTAL33S
C
B
M9 N10 L13 L12
X802478-003
V_3P3STBY
A
1 2
C3N22
4.7 UF 10% 6.3 V X5R 805
1 2
C3N5
4.7 UF 10% 6.3 V X5R 805
1 2
C3C2
4.7 UF 10% 6.3 V X5R 805
V_1P8STBY
V_3P3STBY
V_1P8STBY
1 2
C3C1
4.7 UF 10% 6.3 V X5R 805
1 2
C3N34
4.7 UF 10% 6.3 V X5R 805
1 2
C3N15
0.1 UF 10% 6.3 V X5R 402
1 2
[PAGE TITLE=HANA, POWER + DECOUPLING]
C3N16
0.1 UF 10% 6.3 V X5R 402
1 2
C3N21
0.1 UF 10% 6.3 V X5R 402
1 2
C3N26
0.1 UF 10% 6.3 V X5R 402
1 2
C3P5
0.1 UF 10% 6.3 V X5R 402
1 2
C3N24
0.1 UF 10% 6.3 V X5R 402
1 2
C3N32
0.1 UF 10% 6.3 V X5R 402
1 2
C3N14
0.1 UF 10% 6.3 V X5R 402
1 2
C3P2
0.1 UF 10% 6.3 V X5R 402
1 2
C3N28
0.1 UF 10% 6.3 V X5R 402
1 2
C3P6
0.1 UF 10% 6.3 V X5R 402
1 2
DRAWING Wed Feb 10 16:23:29 2010
C3N25
0.1 UF 10% 6.3 V X5R 402
1 2
C3P7
0.1 UF 10% 6.3 V X5R 402
MICROSOFT
1 2
C3P8
0.1 UF 10% 6.3 V X5R 402
1 2
C3P9
0.1 UF 10% 6.3 V X5R 402
PROJECT NAME TRINITY_XDK
1 2
A
C3N35 0.1 UF 10% 6.3 V X5R 402
PAGE 24/81
FAB G
REV 1.01
CONFIDENTIAL
8
7
6
5
7
6
5
4
3
2
3
2
1
CR-25 : @TRINITY_LIB.TRINITY(SCH_1):PAGE25
8
4
1
HANA, POWER + DECOUPLING D
D
V_3P3STBY U3B2
4 of 4
IC
V_1P8STBY
HANA E13 J4 J3 C3
V_3P3STBY FB3N1 1
C3N1
4.7 UF 10% 6.3 V X5R 805
C
2 FB 0.5 603 0.2DCR
V_HANA_VDDIO_33S_AVCC
1
C3N3
4.7 UF 10%
V 2 6.3 X5R 805
C3N6
0.1 UF 10% 6.3 V X5R 402
1
C3N7
0.1 UF 10%
6.3 V 2 X5R 402
1
C3N11
0.1 UF 10%
V 2 6.3 X5R 402
1
C3N10 0.1 UF 10%
V 2 6.3 X5R 402
V_3P3STBY
F4 E4 F3 G4 G3 C2 G1 C1 G2
VSSIO_33S_AVSS8 VSSIO_33S_AVSS7 VSSIO_33S_AVSS6 VDDIO_33S_AVCC5 VDDIO_33S_AVCC4 VDDIO_33S_AVCC3 VDDIO_33S_AVCC2 VDDIO_33S_AVCC1 VDDIO_33S_AVCC0
A1 E1 J1 E2 E3 J2
VSSIO_33S_AVSS5 VSSIO_33S_AVSS4 VSSIO_33S_AVSS3 VSSIO_33S_AVSS2 VSSIO_33S_AVSS1 VSSIO_33S_AVSS0
H3
1 2
C3N8
C3N12
10% 0.1 UF 6.3 V X5R 402
10% 0.1 UF 6.3 V X5R 402
VDD33S3 VDD33S2 VDD33S1 VDD33S0
FB3N2 1
C3N2
4.7 UF 10% 6.3 V X5R 805
2 FB 0.2A 603 0.5 DCR
V_HANA_VDDIO_33S_PVCC0
1
C3N4
4.7 UF 10%
V 2 6.3 X5R 805
C3N9
0.1 UF 10% 6.3 V X5R 402
L11 K11 G11 J10 H10 J9 H9 M8 L8 K8 G8 F8 L7 K7 G7 F7 J6 H6 J5 H5 E5 D5
VSS35 VSS34 VSS33 VSS32 VSS31 VSS30 VSS29 VSS28 VSS27 VSS26 VSS25 VSS24 VSS23 VSS22 VSS21 VSS20 VSS19 VSS18 VSS17 VSS16 VSS15 VSS14 VSS13 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 VSS0
J13 H13 G13 F13 D13 K12 M11 J11 H11 L10 K10 G10 F10 E10 L9 K9 G9 F9 J8 H8 E8 J7 H7 L6 K6 G6 F6 E6 L5 K5 G5 F5 C5 L4 C4 R1
VDDIO_33S_PVDD1
V_3P3STBY
B
FB3P1 VDD18S21 VDD18S20 VDD18S19 VDD18S18 VDD18S17 VDD18S16 VDD18S15 VDD18S14 VDD18S13 VDD18S12 VDD18S11 VDD18S10 VDD18S9 VDD18S8 VDD18S7 VDD18S6 VDD18S5 VDD18S4 VDD18S3 VDD18S2 VDD18S1 VDD18S0
D3
VDDIO_33S_PVCC0
H4 D4
VSSIO_33S_PVSS1 VSSIO_33S_PVSS0
1
V_HANA_VDD18S
1 2
1
C3N33
0.1 UF 10%
V 2 6.3 X5R 402
1
C3P1
0.1 UF 10% 6.3 V X5R 402
C3N30
0.1 UF 10%
V 2 6.3 X5R 402
1
1 2
C3P3
C3N29
402
2 FB 603
1
1
C3N31
0.1 UF 10%
6.3 V 2 X5R 402
C3P4
4.7 UF 10%
4.7 UF 10% 6.3 V X5R 805
0.1 UF 10%
V 2 6.3 X5R
0.5 0.2DCR
6.3 V 2 X5R 805
1
C3N19 0.1 UF 10%
V 2 6.3 X5R 402
1
C3N39
0.1 UF 10%
6.3 V 2 X5R 402
1
C3N18
C
0.1 UF 10%
6.3 V 2 X5R 402
B
X802478-003
A
A
[PAGE TITLE=HANA, POWER + DECOUPLING]
DRAWING Wed Feb 10 16:23:29 2010
MICROSOFT
PROJECT NAME TRINITY_XDK
PAGE 25/81
FAB G
REV 1.01
CONFIDENTIAL
8
7
6
5
7
6
5
4
3
2
3
2
1
CR-26 : @TRINITY_LIB.TRINITY(SCH_1):PAGE26
8
U3D1
1 of 6
IC
PSB VERSION A0
D
2 R3T4
2 R3R14 2 R2R19
1 EMPTY
1 EMPTY 1 EMPTY
1 KOHM 5% 402
1 KOHM 5%
1 KOHM 5%
402
22 22
IN IN
22
IN
K1 J1
SATA_CLK_DP SATA_CLK_DN
SATA_CLK_REF
H3
SATA_CLK_REF
H4
SATA_CLK_SEL
SATA_CLK_SEL
402
DB2R8 TP
1
ECB_CLK_BYP
DB3T1 TP
1
HBEDB_CLK_BYP
DB3R2 TP
1
A6 B6
HBEDB_CLK_SEL XUSB_CLK_BYP XUSB_CLK_SEL
2 R2R23 1 KOHM 5%
1 CH
402
2
C3R14 0.1 UF 10% 6.3 V X5R 402
1 R3R24
1
124 OHM 1% 2 CH 402
2
499 OHM 1% 2 CH 402
0.1 UF 10% 6.3 V X5R 402
PCIEX_CLK_DN PCIEX_CLK_DP
L22 L21
PEX_CLK_DP PEX_CLK_DN
PEX_GPU_SB_L1_DP PEX_GPU_SB_L1_DN
P22 N22
PEX_RX1_DP PEX_RX1_DN
4 4
IN IN
PEX_GPU_SB_L0_DP PEX_GPU_SB_L0_DN
T21 R21
PEX_RX0_DP PEX_RX0_DN
PEX_RBIAS0
K20 K19
PEX_RBIAS1 PEX_RBIAS0
59
IN
KER_DBG_RXD
D15
UART0_RXD
1 R3R7
1 R3R8
10 KOHM 10 KOHM 10 KOHM 10 KOHM 10 KOHM 10 KOHM 10 KOHM 10 KOHM 5% 5% 5% 5% 5% 5% 5% 5% 2 EMPTY 2 EMPTY 2 EMPTY 2 CH 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY 402 402 402 402 402 402 402 402
B
1
2
3
5
11
1 R2D15 1 R2D16 1 R2D17 1 R2D18 1 R2D14 1 R3D5 1 KOHM 5% 2 CH 402
1 KOHM 5% 2 CH 402
1 KOHM 5% 2 CH 402
1 KOHM 5% 2 EMPTY 402
1 KOHM 5% 2 CH 402
1 KOHM 5% 2 EMPTY 402
15
14
1 R3D3
1 KOHM 5% 2 EMPTY 402
111 110 101 100 011 010 001
GPIO =
26
OUT
SB_GPIO
R3D7 1 2 0 OHM 402
5% CH
10 KOHM 5% 2 CH 402
AUD_SPI_MISO
1 R3D8
IN
35
10 KOHM 5%
2 EMPTY
IN OUT IN IN OUT
PEX_TX0_DP
1
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4
1 1 1 1
GPIO3 GPIO2 GPIO1 GPIO0
1 KOHM 5% 2 EMPTY 402
60 60 60 60 60
SB_TCLK SB_TDO SB_TDI SB_TMS SB_TRST
W20 V22 V21 W22 W21
PEX_SB_GPU_L1_DP
4
OUT
M20
1
PEX_SB_GPU_L1_DN_C
C3D2
D
2
PEX_SB_GPU_L1_DN
OUT
4
R19
1
PEX_SB_GPU_L0_DP_C
C3E3
2
PEX_SB_GPU_L0_DP
OUT
4
P19
1
PEX_SB_GPU_L0_DN_C
C3E2
2
PEX_SB_GPU_L0_DN
OUT
4
D14
R2C9 2 1
KER_DBG_TXD_R
KER_DBG_TXD
OUT
59
4 7 O HM HM 5 % CH 402
26
FT3T5 FTP FT3T4 FTP FT3T6 FTP FT3T7 FTP FT3T8 FTP
2
0.1 UF 10% 6.3 X5RV 402
UART0_TXD
1 R3D4
V_3P3STBY 1 R3G19
C3E1
0.1 UF 10% 6.3 V X5R 402
XENON ZEPHYR A ZEPHYR B ZEPHYR C FALCON JASPER TRINITY
BI
PEX_TX1_DN
PEX_TX0_DN
0 LESS THEN 1GB SYSTEM FLASH 1, 1GB SYSTEM FLASH
SB_GPIO
1
PEX_SB_GPU_L1_DP_C
0.1 UF 10% 6.3 V X5R 402
GPIO = 0 ENABLE DEBUG OUTPUT 1 DISABLE DEBUG OUTPUT GPIO =
0
XUSB_CLK_BYP XUSB_CLK_SEL
IN IN
V_3P3 1 R2R21 1 R2R22 1 R2R24 1 R2R25 1 R2R20 1 R3R9
HBEDB_CLK_BYP HBEDB_CLK_SEL
B15 C15
IN IN
1 R3R22
C3R9
ECB_CLK_BYP ECB_CLK_SEL
4 4
N20
0.1 UF 10% 6.3 V X5R 402
U20 V20
22 22
PEX_RBIAS1
1
PEX_TX1_DP
SATA_CLK_DP SATA_CLK_DN
ECB_CLK_SEL
C
1
SB, PCIEX + SMM GPIO + JTAG
V_3P3
V_1P8
4
D10 D11 D12
SB_GPIO_RESERVED31
D13 C8 D9 C9 B9 A9 C10 B10 A10 C11 B11 A11 C12 B12 A12 C13 B13 A13 C14 B14 A14 E3 F1 F2 F3
SB_GPIO_RESERVED28 SB_GPIO_RESERVED27
SB_GPIO_RESERVED30 SB_GPIO_RESERVED29
SB_GPIO_RESERVED26 SB_GPIO_RESERVED25 SB_GPIO_RESERVED24 SB_GPIO_RESERVED23 SB_GPIO_RESERVED22 SB_GPIO_RESERVED21 SB_GPIO_RESERVED20 SB_GPIO_RESERVED19 SB_GPIO_RESERVED18 SB_GPIO_RESERVED17 SB_GPIO_RESERVED16
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DB2R13 DB3R5 DB3R4 DB3R3 DB2R11 DB2R14 DB2R12 DB2R9 DB2R6 DB2R4 DB2R2 DB2R10 DB2R7 DB2R5 DB2R3 DB3R1
15 14
SCART_RGB AUD_RST_N
OUT OUT
37 33
ANA_VID_INT WSS_CNTL0 WSS_CNTL1 PCIEX_INT SB_GPIO_RESERVED6
IN OUT OUT OUT OUT
23 37 37 26 26
ENET_RST_N
OUT
SB_GPIO
1 1
TCK TDO TDI TMS TRST
B SATA_CLK V_3P3 STITCH V_3P3 5
32
2
2
C2C7
0.1 UF 10%
C2B3
0.1 UF 10%
6.3 V 1 X5R
TP DB2R15 TP DB2R16
1
26
BI
11
3 2 1 0
G1 G2 G3 G4
C
6.3 V 1 X5R
402
402
FTP FT2R2
402
X817692-001
V_3P3STBY
V_3P3STBY
A 26
IN
SB_GPIO_RESERVED6
R2R26 1 2 0 OHM 402
5% 2 CH 402
AUD_SPI_CLK
5% 1 R2E9 10 KOHM CH 5% 2 EMPTY 402
V_3P3STBY
OUT
35 26
IN
PCIEX_INT
R2D19 1 2
5% CH 2 402
AUD_SPI_MOSI
0 OH M 5 % 1 R2E8 CH 402 10 KOHM 5% 2 EMPTY 402
V_3P3STBY
R2G4 1 10 KOHM
R3G20 1 10 KOHM
R3G18 1 10 KOHM
OUT
35 26
IN
R2G3 SB_GPIO 1 2
5% CH 2 402
AUD_RDY_BSBY
0 OH M 5 % 1 R2G5 10 KOHM CH 402 5% 2 EMPTY 402
DRAWING
R2G21 1 10 KOHM
A
5%
OUT
35 26
IN
SB_GPIO
MICROSOFT
R3D10 1 2
CH 2 402
AUD_SSB
0 OHM 5% 1 R3D9 CH 402 10 KOHM 5% 2 EMPTY 402
PROJECT NAME TRINITY_XDK
PAGE 26/81
OUT
FAB G
REV 1.01
35
[PAGE_TITLE SB, PCIEX + SMM GPIO + JTAG] 8
Wed Feb 10 16:23:29 2010
7
6
5
7
6
5
4
CONFIDENTIAL
3
2
3
2
1
CR-27 : @TRINITY_LIB.TRINITY(SCH_1):PAGE27
8
4
1
SB, SMC 2 of 6
U3D1
IC
SB VERSION 106 22
D
22
IN
STBY_CLK
Y12
IN
SMC_RST_N
C17 1 UF 10% 16 V X5R 603
27
IN
1 SB_RST_N
27
IN
SB_MAIN_PWRGD
FT3R15 FTP
59
41 41
SMC_DBG_EN
IN
OUT
TRAY_OPEN
IN
TRAY_STATUS
R3R6 2 1
TRAY_OPEN_R
33 OHM 5% CH 402
R2C5 2 1
SB_RST_N*
G19
MAIN_PWR_OK
D16
SMC_UART1_RXD
C16
SMC_DBG
A18
SMC_P4_GPIO7
B18
SMC_P4_GPIO6
C18
SMC_P4_GPIO5
D18
SMC_P4_GPIO4
IN
50
BI
VREG_VMEM_PWRGD_CPU_TRST_N_R
55 40 37 23
BI
HDMI_DDC_DATA
A19
SMC_P4_GPIO3
60
BI
SMC_CPU_CHKSTOP_DETECT
B19
SMC_P4_GPIO2
60 59 37
FT3R4 FTP
10 KOHM 5% CH 402
FT3R6 FTP 59 55 41 22
BI
SMB_DATA
BI
SMB_CLK FT3R5 FTP
IN
AV_MODE2
37
IN
AV_MODE1
37 55 40 37 23
R3R3 2 1 10 KOHM 402
5% CH
R3R4 2 1
IN
AV_MODE0
BI
HDMI_DDC_CLK
10 KOHM 402
IN
VREG_V5P0_PWRGD
22
IN
48
IN
SMC_HDMI_HPD VREG_V3P3_PWRGD
47
V_3P3STBY
SMC_P2_GPIO7 SMC_P2_GPIO6 SMC_P2_GPIO5 SMC_P2_GPIO4 SMC_P2_GPIO3 SMC_P2_GPIO2 SMC_P2_GPIO1 SMC_P2_GPIO0
E22 E21 E20 E19 F22 F21 F20 F19
PWRSW_N VREG_V3P3_EN ANA_V12P0_PWRGD VREG_VEDRAM_PWRGD ANA_RST_N VREG_VEDRAM_EN PSU_V12P0_EN ANA_CLK_OE
SMC_P1_GPIO7 SMC_P1_GPIO6 SMC_P1_GPIO5 SMC_P1_GPIO4 SMC_P1_GPIO3 SMC_P1_GPIO2 SMC_P1_GPIO1 SMC_P1_GPIO0
Y21 Y22 AA20 AA21 AB20 Y20 AA19 AB19
VREG_CPU_EN VREG_CPUCORE_VCS_PWRGD VREG_V5P0_EN VREG_V5P0_SEL VREG_VMEM_EN BINDSW_N TILTSW_N EJECTSW_N
SMC_P0_GPIO7
J20
R3M1 2 1 1 0 K OH M 402
5% CH
R3R19 2 1
GPU_RST_DONE_R
SMC_P4_GPIO1
A20
SMC_P4_GPIO0
AV_MODE2_R
B20
SMC_P3_GPIO7
AV_MODE1_R
B21
SMC_P3_GPIO6
AV_MODE0_R
5% CH
1 FT4R10 FTP
FT3R9 FTP
1
C20
SMC_P3_GPIO5
C22
SMC_P3_GPIO4
C21
SMC_P3_GPIO3
D22
SMC_P3_GPIO2
D21
SMC_P3_GPIO1
D20
SMC_P3_GPIO0
SMC_P0_GPIO6
H21
DB2G3
OUT
A
35
IN
1
IR_DATA
59
IN OUT IN IN OUT OUT OUT OUT
38 48 22 49 22 49 38 42 22
OUT IN OUT OUT OUT IN IN IN
SMC_P0_GPIO5
H19
1 R3R21 2
SMC_P0_GPIO4
D
44 44 51 47 46 50 38 35 38
C
10 KOHM 5% CH 402
1 R3D2
TP DB3R7 TP DB3R6
1 1
EN_TEST1_N EN_TEST0_N
A16
SMC_IR_IN
G22 G21
ENTEST1_N* ENTEST0_N*
1
4
OUT
2
SB_MAIN_PWRGD
B FTP FT3R12
OUT
27
SB_RST_N
OUT
27
BORONFPM_DATA BORONFPM_CLK
BI BI OUT OUT
4 2
OUT OUT
36 23
1 KOHM 5% CH 402
V_1P8STBY 1 R3T2
1 R3T3
CH 2 402
CH 2 402
100 KOHM 5%
IN
10 KOHM 5% CH 2 402
H20
1% CH
2 KOHM 1% 2 EMPTY 402
GPU_RST_DONE 1 R3R20
R3R23 2 1
SB_MAIN_PWRGD_R
2 402
DBG_LED0
FT2V1 FTP
OUT
CPU_RST_N
N: DBG_LED0 PULLDOWN = SMC PRODUCTION MODE 1 R3D1 DBG_LED0 PULLUP = SMC DEVELOPMENT MODE 2 KOHM 1
SMC_DBG_TXD
47 OHM 5% CH 402
1 KO KO HM HM 5 % CH 402
1.27 KOHM 1% CH 2 402 C19
1
37
R2C1 1 2
SMC_DBG_TXD_R
1 R3R17
1.27 KOHM 1% CH 2 402
1
55 41 22 59
B16
V_3P3STBY
1
1 R3R18
B
G20
EXT_PWR_ON_N
EXT_PWR_ON_R
SMC_UART1_TXD
SMC_RST_N*
C3R2
V_3P3STBY
C
STBY_CLK
100 KOHM 5%
SMC_P0_GPIO3 SMC_P0_GPIO2
J19 J22
SMC_P0_GPIO1 SMC_P0_GPIO0
J21 H22
GPU_RST_N CPU_PWRGD
SMC_PWM1 SMC_PWM0
A17 B17
SMC_PWM1 SMC_PWM0
38 38
A
X817692-001
DRAWING
MICROSOFT
PROJECT NAME TRINITY XDK
PAGE 27/81
FAB G
REV 1.01
[PAGE_TITLE SB, SMC] 8
Wed Feb 10 16:23:29 2010
7
6
5
7
6
5
4
CONFIDENTIAL
3
2
3
2
1
CR-28 : @TRINITY_LIB.TRINITY(SCH_1):PAGE28
8
4
1
SB, FLASH + USB + SPI D
D
N: ALL PORTS ARE DIFFERENTIAL USB PAIRS ON THIS PAGE
U3D1 59 59 59
34
IN IN IN BI
SPI_CLK SPI_MOSI SPI_SS_N FLSH_DATA
7 6 5 4 3 2 1 0
3 of 6
U3 Y5 AA5
PSB VERSION A0 SPI_CLK SPI_MOSI SPI_SS_N*
Y2 AA2 Y3 AA3 AB3 Y4 AA4 AB4
FLSH_DATA7 FLSH_DATA6 FLSH_DATA5 FLSH_DATA4 FLSH_DATA3 FLSH_DATA2 FLSH_DATA1 FLSH_DATA0
IC SPI_MISO
AB5
SPI_MISO_R
2R2C81
SPI_MISO
OUT
59
33 OHM 5% CH 402
FLSH_CLE
W1
FLSH_CLE
OUT
34
FLSH_CE_N*
V3
FLSH_CE_N
OUT
34
FLSH_RE_N*
V2
FLSH_RE_N
OUT
34
FLSH_WE_N*
W3
FLSH_WE_N
OUT
34
FLSH_ALE
W2
FLSH_ALE
OUT
34
C
C 34
OUT
FLSH_WP_N
Y1
FLSH_WP_N*
V_3P3STBY
2 R2T1
2.2 KOHM 5% 1 CH 402 34
IN
FLSH_READY
39 39
BI BI
39 39
V1
FLSH_READY
EXPPORT_PORT2_DP EXPPORT_PORT2_DN
W18 Y18
USBA_D3_DP USBA_D3_DN
BI BI
EXPPORT_PORT1_DP EXPPORT_PORT1_DN
AA17 AB17
USBA_D2_DP USBA_D2_DN
BI BI BI BI
EXPPORT_RJ45_DP EXPPORT_RJ45_DN
W16 Y16
USBA_D1_DP
AA15 AB15
USBA_D1_DN USBA_D0_DP USBA_D0_DN
USBB_D4_DP USBB_D4_DN
Y10 W10
MUPORT_DP MUPORT_DN
BI BI
41 41
USBB_D3_DP USBB_D3_DN
Y8 W8
BORONFPMPORT_DP BORONFPMPORT_DN
BI BI
38 38
USBB_D2_DP USBB_D2_DN
AB7 AA7
WAVEPORT_DP WAVEPORT_DN
BI BI
39 39
USBB_D1_DP USBB_D1_DN
AB9 AA9
GAMEPORT1_DP GAMEPORT1_DN
BI BI
39 39
USBB_D0_DP USBB_D0_DN
AB11 AA11
GAMEPORT2_DP GAMEPORT2_DN
BI BI
39 39
B
B
38 38 39 39
EXPPORT_PORT3_DP EXPPORT_PORT3_DN
SB_USB_RBIAS
1 2
A
W12
USB_RBIAS
C2T13 0.1 UF 1 R2T2 113 OHM 10% 1% 6.3 V EMPTY 2 CH 402 402
A
X817692-001
DRAWING
MICROSOFT
PROJECT NAME TRINITY XDK
PAGE 28/81
FAB G
REV 1.01
[PAGE_TITLE [PAGE_TITLE SB, SB, FLASH FLASH ++ USB USB ++ SPI] SPI] 8
Wed Feb 10 16:23:29 2010
7
6
5
7
6
5
4
CONFIDENTIAL
3
2
3
2
1
CR-29 : @TRINITY_LIB.TRINITY(SCH_1):PAGE29
8
4
1
SB, ETHERNET + AUDIO + SATA D
D U3D1 32
33 OHM 5% CH 402
R2D7 1 2
MII_TX_CLK_R
B3
MII_RX_CLK_R
C3
MII_RX_CLK
MII_TX_CLK
IN IN IN IN IN
MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0
D1 D2 D3 C1
MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0
32 32
IN IN
MII_RXDV MII_RXER
C2 B2
MII_RXDV MII_RXER
IN IN BI
MII_COL MII_CRS MII_MDIO
B5 A5 E1
MII_COL MII_CRS MII_MDIO
IN
AUD_CLK
A8
AUD_CLK
32 32 32
4 of 6
IC
PSB VERSION A0 MII_MDC_CLK_OUT
E2
R2D13 1 2
MII_MDC_CLK_OUT_R
MII_MDC_CLK_OUT
OUT
32
33 OHM 5% CH 402
32 32 32 32
22
B
1R2D82
MII_RX_CLK
32
C
IN
MII_TX_CLK
33 OHM 5% CH 402
41 41
IN IN
HDD_RX_DP HDD_RX_DN
N4 P4
SATA1_RX_DP SATA1_RX_DN
41 41
IN IN
ODD_RX_DP ODD_RX_DN
L3 M3
SATA0_RX_DP SATA0_RX_DN
MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0
C5 A4 B4 C4
MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0
OUT OUT OUT OUT
32 32 32 32
MII_TXEN
A3
MII_TXEN
OUT
32
C
R2D9 1 2
I2S_MCLK_OUT
C7
I2S_MCLK_R
I2S_BCLK_OUT
B8
I2S_BCLK_R
I2S_SD
A7
I2S_SD_R
47 OHM 5% CH 402
R2D11 1 2
R2D10 1 2
47 OHM 5% CH 402
47 OHM 5% CH 402
R2D5 1 2
I2S_WS
B7
I2S_WS_R
SPDIF
C6
SPDIF_R
R2D12 1 2
1 R2R14
1 R2R17 1 R2R16 1 R2R18
2 CH
2 CH
10 KOHM 5%
1 2
U2
OUT
33
I2S_BCLK
OUT
23 33
I2S_SD
OUT
23 33
I2S_WS
OUT
23 33
SB_SPDIF_OUT
OUT
23
10 KOHM 5%
402
10 KOHM 5%
2 CH
402
B
10 KOHM 5%
2 CH
402
SATA_RBIAS
1 R2E1
374 OHM 1% 0.1 UF 10% 2 CH 6.3 V 402 X5R 402
C2E1
I2S_MCLK
47 OHM 5% CH 402
402
SATA_RBIAS
47 OHM 5% CH 402
SATA1_TX_DP SATA1_TX_DN
R2 P2
HDD_TX_DP HDD_TX_DN
OUT OUT
41 41
SATA0_TX_DP SATA0_TX_DN
N1 M1
ODD_TX_DP ODD_TX_DN
OUT OUT
41 41
X817692-001
A
A
DRAWING
MICROSOFT
PROJECT NAME
PAGE
FAB
REV
[PAGE_TITLE=SB, ETHERNET + AUDIO + SATA] 8
Wed Feb 10 16:23:30 2010
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5
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CONFIDENTIAL
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TRINITY_XDK
29/81
G
1.01
1
CR-30 : @TRINITY_LIB.TRINITY(SCH_1):PAGE30
8
4
1
PSB, STANDBY POWER + DECOUPLING
V_1P8STBY
V_1P8STBY 5 of 6
U3D1
D
1
1
1
ST3T1
ST2T2
2
V_AVDD_USB
AB13
AVDD_USB
V_AVSS_USB
AA13
AVSS_USB
C3T11 0.1 10% UF
6.3 V 2 X5R 402
SHORT
2 FB 603
0.2A 0.5 DCR
1
C3T14 2.2 UF 10% 6.3 V X5R 603
2
FB3T1
1
2 FB 603
0.2A 0.5 DCR
C3T17 4.7 10% UF 6.3 V X5R 805
V_CMPAVDD18_USB
1 2
2
D
PSB VERSION A0
FB3T2 1
V_3P3STBY
IC
C3T13
2.2 UF 10% 6.3 V X5R 603
1 2
Y13
VDD18_AUX VDD18_AUX VDD18_AUX
J18 H18 G18
VDD18_AUX VDD18_AUX VDD18_AUX VDD18_AUX VDD18_AUX VDD18_AUX VDD18_AUX
J15 H15 R14 H14 R12 P12 R9
V_1P8STBY
CMPAVDD18_USB
1
C3T10
C3T6
0.1 UF 10%
0.1 UF 10% 6.3 V X5R 402
6.3 V 2 X5R V_CMPAVSS18_USB
W13
CMPAVSS18_USB
V13 V12 V11 V10 V9 V8 V7 Y6 W6
VDD18_USB VDD18_USB VDD18_USB VDD18_USB VDD18_USB VDD18_USB VDD18_USB VDD18_USB VDD18_USB
V6
VDD18_USB
402
C2T6
0.1 UF 10% 6.3 V X5R 402
C3R12
0.1 UF 10% 6.3 V X5R 402
C3R13 0.1 UF 10% 6.3 V X5R 402
SHORT
C
FB2T3 1
1
C2T16
4.7 UF 10%
0.5 0.2DCR
2 FB 603
V_VDD18_USB
1
C2T15
10 UF 20%
V 2 6.3 X5R
6.3 V 2 X5R
805
1
C2T14
0.1 UF 10%
V 2 6.3 X5R
805
1
C2T10
0.1 UF 10%
V 2 6.3 X5R
1
0.1 UF 10%
V 2 6.3 X5R
402
402
C2T11
402
C VDD33_AUX VDD33_AUX VDD33_AUX
V19 D19 V18
VDD33_AUX VDD33_AUX VDD33_AUX VDD33_AUX VDD33_AUX VDD33_AUX VDD33_AUX VDD33_AUX VDD33_AUX VDD33_AUX VDD33_AUX VDD33_AUX
F18 E18 E17 D17 E16 E15 W5 V5 U5 W4 V4 U4
SB BALLS V18 AND V19 ARE IN THE LOWER RIGHT HAND OF THE CHIP THEY HAVE BEEN ISOLATED FOR BETTER POWER ROUTING
B
B
V_3P3STBY FB3T3
1
C3T19
4.7 UF 10% 6.3 V X5R 805
0.2A 0.5 DCR
2 FB 603
C3T15
2.2 UF 10%
1
ST3T2
Y14
CMPAVDD33_USB
V_CMPAVSS33_USB
W14
CMPAVSS33_USB
V_VDD33_USB
V17 V16 V15 V14
VDD33_USB VDD33_USB VDD33_USB VDD33_USB
V_CMPAVDD33_USB
1
V 2 6.3 X5R 603
2
1
C3T12
0.1 UF 10%
V 2 6.3 X5R 402
1
C3T9
0.1 UF 10%
6.3 V 2 X5R 402
SHORT
FB3R1 1
A
C3R5
4.7 UF 10% 6.3 V X5R 805
0.2A 0.5 DCR
2 FB 603
1 2
C3T4
2.2 UF 10% 6.3 V X5R 603
1 2
C3T7
0.1 UF 10% 6.3 V X5R 402
VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB VSS_USB
Y19 W19 AB18 AA18 Y17 W17 AB16 AA16 Y15 W15 AB14 AA14 AB12 AA12 Y11 W11 AB10 AA10 Y9 W9 AB8 AA8 Y7 W7 AB6 AA6
V_3P3STBY
C3R1
0.1 UF 10% 6.3 V X5R 402
C3R4
0.1 UF 10% 6.3 V X5R 402
A
X817692-001
DRAWING
MICROSOFT
PROJECT NAME
PAGE
FAB
REV
[PAGE_TITLE=PSB, STANDBY POWER + DECOUPLING] 8
Wed Feb 10 16:23:30 2010
7
6
5
7
6
5
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CONFIDENTIAL
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2
30/81
G
1.01
1
CR-31 : @TRINITY_LIB.TRINITY(SCH_1):PAGE31
8
4
1
PSB, MAIN POWER + DECOUPLING V_SBPCIE
U3D1
FB3R2 1
D
1 2
C3T2
4.7 UF 10% 6.3 V X5R 805
2 FB 603
0.2A 0.5 DCR
SHORT
V_AVSS_PEX
1
C3R16 2.2 UF 10% 6.3 V X5R 603
2
ST3R1
1
V_AVDD_PEX
1
C3R15
V_VDD_PEX_FB
0.01 UF 10% 16 V X7R 402
2
AVDD_PEX AVSS_PEX
T18 R18 P18 N18 M18
VDD_PEX VDD_PEX VDD_PEX VDD_PEX VDD_PEX
2
R3T1 1 2 0 OHM 805
6 of 6
% CH
1 2
C3T5
1
4.7 UF 10% 6.3 V X5R 805
C3T3
0.1 UF 10% 6.3 V X5R 402
2
1 2
C3T1
0.01 UF 10% 16 V X7R 402
C
U22 T22 R22 M22 K22 U21 P21 N21 M21 K21 T20 R20 P20 T19 N19 M19
VSS_PEX VSS_PEX VSS_PEX VSS_PEX VSS_PEX VSS_PEX VSS_PEX VSS_PEX VSS_PEX VSS_PEX VSS_PEX VSS_PEX VSS_PEX VSS_PEX VSS_PEX VSS_PEX
V_1P8
1
C2R10
4.7 UF 10%
V 2 6.3 X5R 805
1
C2T7
4.7 UF 10%
1FB2R3 2 FB 603
V_AVDD1_SATA V_AVSS1_SATA
0.2A 0.5 DCR
1
1
C2R19
2.2 UF 10%
V 2 6.3 X5R 805
1
ST2R2
V_AVDD0_SATA V_AVSS0_SATA
6.3 V 2 X5R
V_CMPAVDD_SATA
402
603
2
C2R18
0.1 UF 10%
V 2 6.3 X5R
V_CMPAVSS_SATA V_VDD_SATA
SHORT
FB2R2 1
B
2 FB 603
0.2A 0.5 DCR
1 2
1
ST2R1
2
C2R15
2.2 UF 10% 6.3 V X5R 603
1 2
J3 J2
AVDD1_SATA AVSS1_SATA
H1 H2
AVDD0_SATA AVSS0_SATA
U1 T1
CMPAVDD_SATA CMPAVSS_SATA
T5 R5 P5 N5 M5 L5
VDD_SATA VDD_SATA VDD_SATA VDD_SATA VDD_SATA VDD_SATA
C2R16
0.1 UF 10% 6.3 V X5R 402
SHORT
FB2T2 1
2 FB 603
0.2A 0.5 DCR
1
C2T8
2.2 UF 10%
1
ST2T1
V 2 6.3 X5R
2
603
1
C2T5
0.1 UF 10%
V 2 6.3 X5R 402
SHORT
FB2T1 1
A
0.5 0.2DCR
2 FB 603
1
C2T1
1
C2T3
10 UF 20%
0.1 UF 10%
805
402
6.3 V V 2 6.3 2 X5R X5R
1
C2T2
0.1 UF 10%
6.3 V 2 X5R 402
T4 R4 M4 L4 K4 J4 T3 R3 P3 N3 K3 T2 N2 M2 L2 K2 R1 P1 L1
VSS_SATA VSS_SATA VSS_SATA VSS_SATA VSS_SATA VSS_SATA VSS_SATA VSS_SATA VSS_SATA VSS_SATA VSS_SATA VSS_SATA VSS_SATA VSS_SATA VSS_SATA VSS_SATA VSS_SATA VSS_SATA VSS_SATA
V_1P8
IC
PSB VERSION A0
L19 L20
VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18
U19 U18 R15 P15 M15 M14 J12 H12 R11 J11 H11 M9 H9 R8 P8 M8 J8 H8
VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33
E14 E13 E12 E11 E10 E9 D8 D7 D6
V_1P8
D 1
C3R11
0.1 UF 10% 6.3 V 2 X5R 402
1
C3R10
1
0.1 UF 10% X5R .3 V 2 6 402
C3R7
1
C2R20
0.1 UF 10% 6.3 V 2 X5R 402
1
0.1 UF 10% 6.3 V 2 X5R 402
C3R18
G5 D5 F4 E4 D4
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
N15 L15 K15 P14 N14 L14 K14 J14 R13 P13 N13 M13 L13 K13 J13 H13 N12 M12 L12 K12 P11 N11 M11 L11 K11 R10 P10 N10 M10 L10 K10 J10 H10 P9 N9 L9 K9 J9 N8 L8 K8 A15
1
0.1 UF 10%
6.3 V 2 X5R 402
C2R14
0.1 UF 10% 6.3 V X5R 2 402
1
C2T4
0.1 UF 10% 6.3 V 2 X5R 402
1
C3R17
0.1 UF 10% .3 V X5R 2 6 402
V_1P8
C2T9
1
C2R17
1 UF 10% 16 V X5R 603
1 UF 10% 16 V X5R 603
C2T12
4.7 UF 10%
6.3 V 2 X5R
C
805
V_3P3
1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
C3R8
0.1 UF 10% 6.3 V 2 X5R 402
V_3P3
VDD33 VDD33 VDD33 VDD33 VDD33
1
C2R12
0.1 UF 10%
V 2 6.3 X5R 402
1
C2R11
0.1 UF 10%
V 2 6.3 X5R 402
1
C2R13
0.1 UF 10%
V 2 6.3 X5R 402
1
C3R6
0.1 UF 10%
6.3 V 2 X5R 402
1
C2R9
0.1 UF 10%
6.3 V 2 X5R 402
B
V_3P3
C3R3
1 UF 10% 16 V X5R 603
1
C2R7
4.7 UF 10%
V 2 6.3 X5R 805
A
X817692-001
MICROSOFT
PROJECT NAME
PAGE
FAB
REV
[PAGE_TITLE=PSB, MAIN POWER + DECOUPLING] 8
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PSB OUT, ETHERNET D
MICREL AND ATHEROS ENET
D
PHY
NOTE : THIS PAGE OF THE SCHEMATIC DISPLAYS ONLY THE MICREL PART AND ITS ASSOCIATED STUFFING OPTIONS. THE NO STUFF PARTS WILL BE STUFFED ALONG WITH THE ATHEROS PHY AND WILL BE IMPLEMENTED AS A BOM STUFFING OPTION.. DEFAULT ETHERNET PHY ADDRESS = 00001 AUTO_NEGOTIATION ENABLED BY DEFAULT USING INTERNAL PULL-UP ON LED0/NWAYEN AUTO MDIX ENABLED BY DEFAULT
V_3P3 FB2C1 1 0.5A
1 C2C8
2 0.1DCR 603
V_ENET
2
C2C9
10 UF 20%
4.7 UF 10%
V 1 6.3 X5R
V 2 6.3 X5R
805
805
1
C2D3
0.1 UF 10%
V 2 6.3 X5R 402
1
C2P4
0.1 UF 10%
V 2 6.3 X5R 402
1
C2P5
0.1 UF 10%
V 2 6.3 X5R 402
0 OHM R2D6 5% 402 1 2 CH
1
C
2
C2R6
10 UF 20% 6.3 V X5R 805
1
0 OHM 402
C2P3
1 2 R2R2 5% CH
10 UF 20%
1
C2D5
0.1 UF 10%
V 2 6.3 X5R
V 2 25 EMPTY
805
2
22
IN
ENET_CLK
26
IN
ENET_RST_N
1 UF +80%/-20% 50 V EMPTY 805
0 OHM 402
2 1 R2R5 5% EMPTY
VDD_V3P3_V2P5IP
1 R2D2
4.75 KOHM 1% 2 CH 402 29 29 29 29 29 29 29
VDDIO_3.3 VDD2.5 VDDA_3.3 VDD25_REG
INTRP INTP RXDV/CRSDV/CONFIG2 RX_DV CRS/CONFIG1 CRS COL/CONFIG0 COL
402
4.75 KOHM 1%
402
21 18 29 28
1 UF 10%
1 R2R15
1 R2R7
MII_RXDV MII_CRS MII_COL 1 R2R12
2 EMPTY
2 EMPTY
2 EMPTY
1 KOHM 1%
10 V 2 EMPTY
402
10% 25 V X7R 603
2
VDDPLL_1.8 VDD3
8 9
XO XO XI/REFCLK XI
2
1
ENET_REF_CLK_OUT
1 R2D1
6.81 KO KOHM 1% 2 CH 402
10
2
RXC RXC TXC TXC
MII_RX_CLK MII_TX_CLK
19 22
11 12
MDIO MDIO MDC MDC
IN IN IN IN IN
TXEN/TX_EN TXEN TXD3 TXD3 TXD2 TXD2 TXD1/TXD_1 TXD1 TXD0/TXD_0 TXD0
RXER/RX_ER/ISO RXER RXD3/PHYAD0 RXD[3] RXD2/PHYAD1 RXD[2] RXD1/RXD_1/PHYAD2 RXD[1] RXD0/RXD_0/DUPLEX RXD[0]
MII_RXER MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0
20 13 14 15 16
2 R2R11
1 R2R13
1 EMPTY
2 EMPTY
1 KOHM 1% 402
A
IN
ENET_RST_N
4 5
R2R8 1 2 0 OHM 402
5% CH
1 R2R6
2.37 KOHM 1% 2 EMPTY 402
1 R2D3
10 KOHM 1% 2 CH 402
1 R2R4
0 OHM 5% 2 CH 402
C2R3 1 C2D4 1 0.1 1 UF UF 2
10% 25 V EMPTY 603
2
10% 16 V EMPTY 603
OUT OUT
29 29
B
23 27 26 25 24
26
402
REXT RST#
MII_TXEN MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0
ENET_RX_DN ENET_RX_DP
C
1 KOHM 1%
5% 50 V NPO 402
MII_MDIO MII_MDC_CLK_OUT
BI BI
402
29 29 29
C2R5 1 100 PF
BI IN
38 38
1 KOHM 1%
OUT OUT OUT
20% 6.3 V X5R 805
ENET_REXT
10 KO KOHM 1% 2 EMPTY 402
17 3
C2D2
ENET_1.8VEXT
2
1 R2R1
2 CH
4.75 KOHM 1%
C2D1 C2PUF 2 1 0.1 UF 1 10
DB2R1
B
1 R2D4
2 CH
402
R2R3 2 1 1 C2C10
1 R2R10
2 EMPTY
402
603
0 OHM 5% 402 EMPTY
1 R2R9
1 KOHM 1%
ETHERNETPHY_KSZ8041NL_AR8032
VDDA_V3P3_V2P5OP
1
IC
U2D1
FB2R1 1 2 EMPTY 0.5A 603 0.1DCR
RX- RX RX+ RX+
ENET_RSTN_R
32
RST# REXT
GND_DECOUPLE
1 33
GND VDD12_REG GNDSLUG PAD
X819763-001
TX- TXTX+ TX+
LED1/SPEED LED1 LED0/NWAYEN LED0
29 29 29 29 29
1 KOHM 1% 402
ENET_TX_DN ENET_TX_DP
6 7
31 30
OUT OUT OUT OUT OUT
BI BI
38 38
ENET_ACT_N ENET_LINK_N
A
QFN
MICROSOFT
PROJECT NAME
PAGE
FAB
REV
[PAGE_TITLE=PSB OUT, ETHERNET] 8
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PSB OUT, AUDIO D
D
V_3P3
FT3N3 FTP
1
R3B22 1 2
0 OHM 805
% CH
V_AUD
1
C3B11 2.2 UF 10%
V 2 6.3 X5R 603
1
C3B12 0.1 UF 10%
6.3 V 2 X5R 402
1
C3A7
0.1 UF 10%
6.3 V 2 X5R
6
402
1
U3A5 IC AUDIODAC_CSS4354_WM1824 17 3 20
VCP LINEVDD
1
C3A6
VBIAS VMID
18
V_AUD_BIAS
VFILT_P NC
8
V_AUD_FILT_P
C3A5
0.1 UF 10%
2.2 UF 10%
6.3 V 2 X5R
V 2 6.3 X5R
402
603
VA AVDD VL DBVDD 1_2VRMS NC
1
C
2 FLYP_P NC
7
V_AUD_FLYP_P
FLYP NC
5
V_AUD_FLYP_N
1
C3A8
0.15 UF 10% 10 V X5R 402
2
C3M4 1 UF 10% 16 V X5R 603
1 C3M6
C
1 UF 10%
V 2 16 X5R 603
1 C3N41
FB3A2
2.2 UF 10%
IN
I2S_MCLK
2
MCLK MCLK
29
IN
I2S_BCLK
1
SCLK BCLK
29
IN
I2S_WS
IN
I2S_SD
29
29
23 24
AOUTA LINEVOUTL AOUT_REF NC
15 14
AUD_VOUTL
SDIN DACDAT
AOUTB LINEVOUTR
13
603
R3A8 1 2
1.33 KOHM 402
FLYN_P CPCA
AUD_VOUTR
R3A9 1 2
26
IN
AUD_RST_N
FT3M6 FTP
1
19
2 0.7DCR 603
AUD_L_OUT
OUT
37
OUT
37
1 R3A10
10 KOHM 1%
C3A4
1000 PF 10%
2 CH
402
50 V 1 X7R
2 AUD_VOUTR_R
1% CH
11
V_AUD_FLYN_N
12
V_AUD_FILT_N
10 KOHM 1%
1000 PF 10%
2 CH
402
2
1 R3A11
C3A3
50 V 1 X7R
V_AUD_FLYN_P
1 FLYN CPCB
2 AUD_VOUTL_R
1% CH
1.33 KOHM 402 9
0.2
402
LRCK LRCLK
B
1
6.3 V 2 X5R
FB3A1 1
C3A9
2.2 UF 10% 6.3 V X5R 603
0.2
2 0.7DCR 603
B
402
AUD_R_OUT
RESET MUTE
1 R3M6 1 KOHM 5%
2 CH
VFILT CPVOUTN
402
1 22
PS_N/LJ AIFMODE
21
DEM NC
X851154-002
AGND AGND DGND NC CPGND LINEGND
16 4 10
ME GNDPAD
25
2
C3A10
0.15 UF 10% 10 V X5R 402
1 2
C3M2
10 UF 10% 10 V X5R 805
1
C3M3
10 UF 10%
10 V 2 X5R 805
QFN25
A
A
MICROSOFT
PROJECT NAME
PAGE
FAB
REV
[PAGE_TITLE=PSB OUT, AUDIO] 8
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PSB OUT, FLASH D
D
V_3P3STBY
N: STUFFED AT CONFIG LEVEL 1 R1T9 FT1T8 FT1T7 FT1T6 FT1T5 FT1T4 FT1T3 FT1T2 FT1T1
C
FTP FTP FTP FTP FTP FTP FTP FTP
10 KOHM 5% 2 EMPTY 402
1 1 1 1 1 1 1 1
1 R1T10
10 KOHM 5% 2 CH 402
1 R1T5
10 KOHM 5% 2 CH 402
1
1
C1T2
4.7 UF 10%
C1T3
0.1 UF 10%
V 2 6.3 X5R
6.3 V 2 X5R
805
402
IN
C2T18 0.1 UF 10%
6.3 V 2 X5R 402
IC
U1E2 NAND FLASH
1
1 R1T8
1 R1T11 1 R1T12 1 R1T13 1 R1T15 1 R1T16 1 R1T17 1 R1T18
28
2 CH
2 EMPTY
28 28 28 28
402
10 KOHM 5%
10 KOHM 5% 402
2 CH
402
10 KOHM 5%
2 CH
402
10 KOHM 5%
2 CH
402
10 KOHM 5%
2 CH
402
10 KOHM 5%
2 CH
402
10 KOHM 28 5%
2 CH
402
B
IN IN IN IN IN IN
37 12
VCC1 VCC0
44 43 42 41 32 31 30 29
DATA DATA DATA DATA DATA DATA DATA DATA
9 8 18 19 17 16
CE_N* RE_N* WE_N* WP_N* ALE CLE
6 36 13
VSS/NC VSS1 VSS0
FTP FT1T11
7 6 5 4 3 2 1 0
10 KOHM 5%
FLSH_CE_N FLSH_RE_N FLSH_WE_N FLSH_WP_N FLSH_ALE FLSH_CLE
X818098-001
XSB SOUTHBRIDGE
A
7
RDY
FLSH_DATA
28
1
1 A T A D _ H S L F
FLSH_DATA0 0 1 0
8MB
16MB
1
32MB
64MB
NC NC NC NC
38 48 47 46
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
45 40 39 35 34 33 28 27 26 25 24 23 22 21 20 15 14 11 10 5 4 3 2 1
FLSH_NC38
FLSH_READY R1T14 2 1
OUT
C
28
0 OHM 5% 402 EMPTY
B
TSOP
PSB SOUTHBRIDGE N: RETAIL=16MB N: XDK=64MB
FLSH_DATA[1:0] 0X0 0X1 0X2 0X3
FLASH CONFIGURATION 0.5KB, 16KB BLOCKS, 16MB 0.5KB, 16KB BLOCKS, 16MB 2KB PAGES, 128KB BLOCKS, VARIOUS SIZES (256MB) 4KB PAGES, 256KB BLOCKS, VARIOUS SIZES
RETAIL XDK
A
MICROSOFT
PROJECT NAME
PAGE
FAB
REV
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CONN, INFARED + ACCELEROMETER + SWITCHES + AUDIBLE F/B ACCELEROMETER V_3P3STBY
D
TILT SWITCH, SOLICO
V_1P8STBY
1 R2N5
V_3P3STBY
1 2.2 KOHM 5% 2 EMPTY 2 402
Q1N3 1
EMPTY 55
IN
PMBUS_CLK
SOT23 3
1 R1N4
2.2 KOHM 5% EMPTY 402
2
2
1 R2N7
C2N5
1 2
0 OHM C2N4 5% 0.1 UF 10% 2 EMPTY 6.3 V 402 EMPTY 402
61 58 57 56 55 44
BI
PMBUS_DATA
Q1N2 1 EMPTY 2
U2N1 EMPTY BMAX20 2 10 5 7 9 6
VDD VDDIO CSB SCL SDA PS
CAPZ CAPY CAPX INT SDO VSS
X85130 X851300-0 0-001 01
PMBUS_DATA_FET
1 2
TILTSW_N_R2
11 12 1 4 8 3
CAPZ CAPY CAPX
1 1 1
ACCELEROMETER_INT
DB2N1 DB2N2 DB2N3
R5G2 2 1
TILTSW_N_R
TILTSW_N
10 KOHM 5% CH 402
X800550-004
BMA_PS_R
SOT23 3
4 3
402
PMBUS_CLK_FET
C
SW5G2 SM
10 KOHM 5%
0.1 UF 10% 6.3 V EMPTY 402
10 KOHM 5% 2 CH 402
SM
TILT
2 EMPTY
1 R2N4
R2N3 1 2 0 OHM 5% 402 EMPTY
D
1 R5G1
0 OHM 5% 2 EMPTY 402
V_BMA
1 R1N5
V_3P3STBY
1 R2N6
0 OHM 5% 2 EMPTY 402
OUT
27
R2N8 1 2 0 OH OHM 5% 402 EMPTY
3 1
Q2N1 EMPTY 2
LGA12 LGA12
R2N2 1 2
C
0 OHM 5% 402 EMPTY
IR MODULE
V_3P3STBY V_IR
R6G1 1 2
1
49.9 OHM 1% CH 402
C5G6
4.7 UF 10% 6.3 V X5R 805
IC
U6G1
1 C5G7 2
TH X850477-001
2 R3R11
SWITCH
10 KOHM 5% 1 CH 402
0.1 UF 10% 6.3 V X5R 402
VCC DATA GND ME2 ME1
SW3G1 THR
3 1 2 5 4
2
TH I186
IR
B
POWER BUTTON
IR_DATA
4 3
OUT
1 2
U1F5 TH X853774-001
PWRSW_N_R
IN
38
B
27
1
X821027-001
2
AUDIBLE FEEDBACK
V_3P3STBY
U3G4
1 2
A
26 26
U1G3 SMT X851794-001
C3G13
4.7 UF 10% 16 V X5R 1206
1 2
C3V5
0.01 UF 10% 16 V X7R 402
IN
AUD_SPI_CLK
IN
AUD_SPI_MOSI
1 2
C3V4
1000 PF 10% 50 V X7R 402
1 2
C3G14
4.7 UF 10% 16 V X5R 1206
1 2
C3V6
0.1 UF 10% 6.3 V X5R 402
14 10 6 20 19 2 4 3 8 5 21
IC
ISD2130 VCCO SPK_P SPK_N VCCD_PWM1 INTB/GPIO3 VCCD_PWM0 RDY/BSYB/GPIO4 NC5 GPIO5 NC4 NC3 SCLK/GPI1 MOSI/GPIO0 MISO/GPIO2 SSB NC2 VSSD_PWM NC1 VSSD NC0 GND
QFN21
X851696-001
1 7 9 11 12 15 18 1 17 16 13
SPKR_DRIVE_P
J1F1
FTP FT3V6
SPKR_DRIVE_N
1
FTP FT3V7
1X2HDR 1 2 TH HDR
NOTE: SPEAKER HEADER
EJECTSW_N AUD_RDY_BSBY PWRSW_N AUD_SPI_MISO 1 1
IN IN IN OUT
38 26 38
A
26
FTP FT2V4 FTP FT2R7
AUD_SSB
26
IN FT2T4 FTP FT2T5 FTP FT2R6 FTP
1 1
1 DRAWING
PROJECT NAME
PAGE
FAB
REV
[PAGE_TITLE=CONN,INFRARED+ACCELER [PAGE_TITLE=CONN, INFRARED+ACCELEROMETER+SWITCHES+A OMETER+SWITCHES+AUDIBLE UDIBLE F/B] 8
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CONN, FAN D
D
V_12P0 R4A7 2 1 1% 5.11 KOHM 402 EMPTY FAN1_Q1_C
3 23
IN
FAN1_OUT
1
Q4A1
V_3P3 V_12P0 2
1 3
Q5A2
MJD210 EMPTY
EMPTY 2
C 2
C4P1
1
2700 PF 10% 50 V EMPTY 402
1 R5A3
1 C6A7
3 D4A1 1N4148 SOT23 1 EMPTY
2
100 UF 20% 16 V EMPTY RDL
1 2
C5A12 1 UF 10% 16 V X5R 603
E _ 1 Q _ 1 N A F
R5A9 1 2
V_FAN1
100 OHM 2 R4A1
0 OHM % 805 EMPTY
5% 1 EMPTY 402
C5A15
402
P U L L U P _ N A F
C
J5A4 1X4HDR
1 2 3 4 HDR
1 UF 10%
16 V 2 EMPTY
1 R5M5
R _ K B D F _ 1 N A F
1
4.75 KOHM 1%
2 CH
603
30.1 KOHM 1%
2 EMPTY 402
R5M3 2 1
FAN1_FDBK
5.11 KOHM1% 402 EMPTY
OUT
23
1 R5M4
B
B
11 KOHM 1%
2 EMPTY 402
FAN CONTROL 27
IN
SMC_PWM1
R5A10 SMC_PWM1_R
33 OHM 5% CH 402
A
A
PROJECT NAME
PAGE
FAB
REV
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RT3A1 1 2 01.10 A
D
23
V_AVIP
THRMSTR 1206
1
1
C2A3
22 PF 5% 50 V
NPO 2 402
2
26
WSS_CNTL1
R3A3 1 2
5.36 KOHM 402
WSS_CNTL0
IN
1% CH
2 8 . 0 4 1
Q3A1
3
VID_DACA_RET
IN
VID_DACB_OUT
37
IN
VID_DACC_OUT
8 6
VID_DACC_OUT VID_DACC_RET
37
IN
VID_DACD_OUT
7 5
VID_DACD_OUT VID_DACD_RET
E _
1
L T N C _ S % H S 1 C W
SCART_RGB
B
VID_HSYNC_OUT VID_HSYNC_RET
IN
12 10
VID_VSYNC_OUT VID_VSYNC_RET
25
SPDIF
33
IN
AUD_R_OUT
15 13
AUD_R_OUT AUD_R_RET
AUD_L_OUT
16 14
AUD_L_OUT AUD_L_RET
17 19
WSS_CNTL SCART_RGB
2
SCART_RGB_R
C3A1
1
5% CH
3
XSTR
L4A4 1 2 1 R4A5
75 OHM 1%
2 CH
402
1
5% CH
VID_DACA_OUT 1
C4A10
1 2
A
1
2
VGA
Y
G
G
B
N/A
C(CHROMA)
PR
PR
R
R
C
N/A
N/A
PB
PB
B
B
EXT_PWR_ON_N
DDC_CLK DDC_DATA
21 23
HDMI_DDC_CLK HDMI_DDC_DATA
AV_MODE2 AV_MODE1 AV_MODE0
28 24 20
AV_MODE2 AV_MODE1 AV_MODE0
GND GND GND
26 22 18
SHIELD SHIELD SHIELD SHIELD
34 33 32 31
OUT
D
CVBS(COMP)
CVBS(COMP)
CVBS
N/A
BI BI OUT OUT OUT
OUT
37
23
23 27 40 55 23 27 40 55 27 37 27 37 27 37
C4A3
VID_DACB_OUT
EG4A7 X807267-001 ESDB-MLP7 DIO 402
1 R4A4
75 OHM 1% 2 CH 402
1
C4A9
62 PF 5%
2 50 V 402 NPO
1
C
V_3P3STBY
MTGB MTGA
60 59 37 37 37 37
TH
L4A2 1 2
VID_DACC_DP
IN 1
IND 1210
CVBS
1 R3R2
1 R2N1
1 R3R1
1 R2C3
2 5% CH
2 5% CH
2 5% CH
IN IN IN IN
EXT_PWR_ON_N AV_MODE2 AV_MODE1 AV_MODE0
2 5% CH
1 C3A2
1 C2M2 1 C2M1
50 V 2 X7R
V 2 50 X7R
10 KOHM
470 PF 5% 402
470 PF 5%
50 V 2 X7R 402
10 KOHM
402
402
402
402
10 KOHM
1 C2C2
470 PF 5%
50 V 2 X7R 402
B
0.01 UF 10% 16 V X7R 402
402
L4A3 1 2
CVBS
D
59 60 27 37 61
VID_DACC_OUT
OUT
37
IND 1210 EG4A6 X807267-001 ESDB-MLP7 DIO 402
1 R4A3
75 OHM 1%
2 CH
402
1
1
C4A8
23
IN
VID_VSYNC_OUT_R
R4B20 1 2
49 .9 .9 OH M 402
1% CH
OUT
37
23
C4A5
50 V 2 NPO 402
402
L4A1 1 2
VID_DACD_DP
IN 1
75 PF 5% NPO 402
402
2 50 V
2
VID_DACD_OUT
IND 1210 EG4A5 X807267-001 ESDB-MLP7 DIO
C4A6
1 R4A2
2
2 CH
1 50 V
75 OHM 1% 402
C4A7
62 PF 5%
NPO 402
VID_VSYNC_OUT 1
75 PF 5%
62 PF 5%
50 V 2 NPO
2
OUT
37
23
IN
VID_HSYNC_OUT_R
R3B24 1 2
49.9 OHM 402
1% CH
VID_HSYNC_OUT 1
C4A4
75 PF 5%
1 50 V 402 NPO
OUT
37
OUT
37
EG4A9 X807267-001 ESDB-MLP7 DIO 402
2
2
VID_DACB_DP
IN
Y
HDTV
LAYOUT:PLACE CLOSE TO CONNECTOR EMI CAPS
2
23
SDTV
C3M1
V 2 50 NPO
402
SCART
402
75 PF 5%
62 PF 5%
V 2 50 NPO
ADVANCED
470 PF 5%
IND 1210 EG4A8 X807267-001 ESDB-MLP7 DIO 402
Y(LUMA)
R3M7 1 2
33 OHM 402
0 0 1 4
1
N/A
T U O _ B G R _ T R A C S
Q3M1
H
VID_DACA_DP
A
402
SCART_RGB_OUT_R
IN
30
V 1 50 NPO
1 M C 2 % M H O 3 K 5 R 2 2
23
EXT_PWR_ON
X806743-001
75 PF 5%
V_3P3
0 0 1 4
STANDARD
10 KOHM
WSS_CNTL_OUT
CH
402
2
R3M3 2 1 10 KOHM 402
11 9
VID_VSYNC_OUT
5
0 6 3
IN
VID_HSYNC_OUT
33
XSTR
H 2 M 1 2 M 6 C H A H O A O 3 3 K 3 R 1 R 1 0 1 2
26
IN
IN R3A2 WSS_CNTL_OUT_R 2 1 1 KOHM 5% %
4
VID_DACB_OUT VID_DACB_RET
37 WSS_CNTL_B
DAC 39 40
XENON AVIP CONNECTOR V_AVIP V_AVIP_RET VID_DACA_OUT
6 2
CH 1%
29 27
1
CONN
2 3 1
37
5
R3A4 1 2
4.75 KOHM 402
J4A2
4
IN
37
H M C
IN
470 PF 5% 50 V X7R 402
402
1 H 5 O % A K 1 3 R 2 2
26
4.7 UF 10%
VID_DACA_OUT
37
OUT
C2A2
C2A8 805
EG2A1 X807267-001 ESDB-MLP7 DIO
V_12P0
C
1
V 2 6.3 X5R
HANA_SPDIF_OUT
IN
4
CONN, AVIP
V_5P0
A
EG4A10 X807267-001 ESDB-MLP7 DIO 402
2
PROJECT NAME
PAGE
FAB
REV
[PAGE_TITLE=[CONN, [PAGE_TITLE=[CONN , AVIP] 8
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8
7
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1
CONN, RJ45 USB AUX COMBO + BORON + PWR V_12P0
D
01.50 A FT2M2 FTP
RJ45 AUX COMBO
RT3A2 1 2 C2A13
THRMSTR 1206
1
2
FT2M1 FTP
32
IN
1
1 C2A10 2
220 UF 20% 10 V ELEC RDL
2
C2A14
470 PF 5% 50 V X7R 402
1
2 1
C2A5
1
1 R2A2 402
C IN
ENET_TX_DN
32
IN
ENET_RX_DP
2 CH
402
2
1 R2A4
1 R2A5
49.9 OHM 1%
2 CH
402
1
C2A6
2
0.1 UF 10% 6.3 V X5R 402
1
EG2A5 X807267-001 ESDB-MLP7 EMPTY 402
2
1
1 R4G5
100 KOHM 5% 2 CH 402
23 23
EG2A6 X807267-001 ESDB-MLP7 EMPTY 402
1 C2M6 2
EG2A7 X807267-001 ESDB-MLP7 EMPTY 402
100 KOHM 5% 2 CH 402
2
100 UF 20% 16 V ELEC RDL
OUT
BRD_TEMP_N
IN
BRD_TEMP_P
0 OHM 402
R3V5 1 2
PWRSW_N
OUT
PWRSW_N_R
35 27
OUT
EJECTSW_N
BI BI
BORONFPM_DATA BORONFPM_CLK
R4V2 5% 1 2 CH 0 OHM 5% CH 402
1
4.7 UF 10% 6.3 V X5R 805
1
EG2A3 X807267-001 ESDB-MLP7 DIO 402
13 14
DD+
EG2A2 X807267-001 ESDB-MLP7 DIO 402
12 1 2
SPARE1 LED_LEFT_A LED_LEFT_C
3 4
2
FB2M1 2 1 FB 0.5A 603 0.1DCR
11 10 7
TD+ TCT TD-
9 6
RD+ RCT
5
RD-
8
GND1
21 22 23 24
EMI1 EMI2 EMI3 EMI4
V_ENET_CT
1 C2M5 2
C2M3
4.7 UF 10% 6.3 V X5R 805
C2M4
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402
X820106-001
4 13
DD+
DB6M2 DB6M3 DB6N1 FT7N1 FTP
SPARE1 BINDSW_N
7
FP_TEMP_N
BRD_TEMP_P_R
1
FP_TEMP_P
IN
1 1 1 1
1 C7B2
1 C7A3
1 C7A2
1 C7A1
1 C7A4
2
2
2
2
2
0.1 UF 10% 25 V X7R 603
PSU_V12P0_EN
10 KOHM 5% CH 402
470 C5G5PF 5% 50 V 1 X7R 402
470 5% PF 50 V
1 X7R 402
2 C5G3 5% 470 PF 50 V
1 X7R 402
10
1 R6A5
10 KOHM 5% 2 CH 402
FP_PWR
ODD_EJECT
2 3
C_DATA C_CLK
9
GND1
11 14 15 16 17
GND2 ME1 ME2 ME3 ME4
X819886-001
DB6M1 FT6M1 FTP
0.1 UF 10% 25 V X7R 603
1 C6A5 2
100 UF 20% 16 V ELEC RDL
1 C6A4 2
100 UF 20% 16 V ELEC RDL
1 2
0.1 UF 10% 25 V X7R 603
0.1 UF 10% 25 V X7R 603
100 OHM 402
5% CH
1 2
C6A1
470 PF 5% 50 V X7R 402
J7A1
58
OUT
58
C6A2
0.1 UF 10% 6.3 V X5R 402
1 2
CONN
TRINITY PWR V_12P0_IN
5 6 7 8
V12P01 V12P02 V12P03 V12P04
PSU_V12P0_EN_R
9
PSU_EN
10
VSB5P0
C6A3
470 PF 5% 50 V EMPTY 402
1 2 3 4 11 12
A
GND1 GND2 GND3 GND4 ME1 ME2
MTGA[9..1] MTGB[9..1]
X819467-001
TH
OUT
SHORT
10 MOHM 1% 2512 CH
R6A6 1 2
1 1
B 1 VREG_V12P0_ISENSE_N
SHORT
R7A2 1 2 470 UF 20% 16 V POLY TH
ST7A1
R7A1 ST7A2 1 2 2 1 VREG_V12P0_ISENSE_P 10 MOHM 1% 2512 CH
V_12P0
V_5P0STBY EJECTSW_N_R
2 C5G4
TH
2
27
2
C
POWER
8
R4G7 2 1
LED_RIGHT_A LED_RIGHT_C
V_3P3STBY
BRD_TEMP_N_R
10 KOHM 5% CH 402
N: BORONFPMPORT_DX IS A USB DIFFERENTIAL PAIR.
SPARE2 SPARE3
EXPPORT_RJ45_DN EXPPORT_RJ45_DP
470 PF 5% 50 V X7R 402
BINDSW_N_R
R4V1 1 2
V5P0 GND2
19 20
2 C5G2
5 6
10 KOHM 1% CH 402
16 15
D
BORON CONN
1 C5G1
100 KOHM 5% 2 CH 402
V12P0 GND3
BORON FPM CONN J5G2 12
1 R4G4
R4G6 1 2
BINDSW_N
OUT
27 27
1 R3V6
V_3P3
2
BORONFPMPORT_DN BORONFPMPORT_DP
35
35 27
A
OUT
1
2
V_3P3STBY V_3P3STBY V_3P3STBY V_3P3STBY
27
BI BI
EG2A4 X807267-001 ESDB-MLP7 EMPTY 402
2
B
BI BI
28 28
2
1
49.9 OHM 1% 2 CH 402 ENET_RX_TERM
ENET_RX_DN
C2A7
0.1 UF 10% 6.3 V X5R 402
49.9 OHM 1%
32
1
ENET_TX_TERM
1 R2A3
28 28
A DFM REQUIREMENT OF THIEVING PADS DFM_THIEVING_PADS_REQUIREMENT3
4.7 UF 10% 6.3 V X5R 805
ENET_TX_DP 49.9 OHM 1%
IN
J2A1.16 HAS A PADS DFM REQUIREMENT FOR THIEVING
V5P0_EXPPORT_RJ45
THRMSTR 1206
17 18
4.7 UF 10% 16 V X5R 805
RT1B1 1
2 CH
32
470 PF 5% 50 V X7R 402
CONN
TRINITYRJ45AUX
C2A12
C2A11
100 UF 20% 16 V ELEC RDL
V_5P0 01.10 A
J2A1
V12P0_EXPPORT_RJ45
TH
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FAB G
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CONN, USB + MEM PORTS + TOSLINK + WAVEPORT N: ALL DIFFERENTIAL PAIRS ON THIS PAGE ARE USB DIFFERENTIAL PAIRS.
V_5P0DUAL
D
HORIZONTAL DUAL USB
RT6G1 2
1
01.10 A
2 C6G2 220 UF 470 PF
THRMSTR 1206
20% 10 V
BI BI
GAMEPORT1_DN GAMEPORT1_DP
1
2
4.7 UF 10%
1
2
01.10 A
EG6G2 X807267-001 ESDB-MLP7 DIO 402
J6G1
2
01.10 A
1
V_GAMEPORT2
1 C7G1
2 C7G2 220 UF 470 PF
THRMSTR 1206
20% 10 V
2 ELEC RDL 28 28
BI BI
2
C7V1
4.7 UF 10%
5% 50 V
V 1 6.3 X5R
X7R 1 402
1 2 3 4
VBUS DD+ GND
5 6 7 8
VBUS DD+ GND
9 10
805
GAMEPORT2_DN GAMEPORT2_DP 1
EG7G1 X807267-001 ESDB-MLP7 DIO 402
2
28 28
1 0.2A 0.5 DCR
2 EMPTY 603
V_5P0DUAL
0 OHM 402
WAVEPORT_DN WAVEPORT_DP 1
EG1A2 X807267-001 ESDB-MLP7 EMPTY 402
470 PF 5%
V+
2 C1N5 4.7 UF 10%
6.3 V 1 X5R
BOTTOM PORT
805
402
2 3 4 1
EG1A8 X807267-001 ESDB-MLP7 DIO 402
DATA DATA + GND
EG1A7 X807267-001 ESDB-MLP7 DIO 402
C
2
2
TH
1
V_EXPPORT_DUAL2
T 1206 HRMSTR
1 C2A9
2
ELEC 2 RDL
V 1 50 X7R
C1A9
470 PF 5% 402
2
5
V+
C1N1
4.7 UF 10%
6.3 V 1 X5R
MIDDLE PORT
805
28 28
1
C4A1
22 PF 5% 50 V
NPO 2 402
BI BI
EXPPORT_PORT2_DN EXPPORT_PORT2_DP
6 7 8 1
C1A7
2 1
C1A1
4.7 UF 10% 6.3 V X5R 805
2 1
V_5P0DUAL
J1A1 CONN wavereceptacle 1 3 4 6
1
EG1A4 X807267-001 ESDB-MLP7 DIO 402
GND1
DD+
GND2 EMI1
2 5 7
2
TBD
EMI2 ME1
8 9
01.10 A
EG4A1 X807267-001 ESDB-MLP7 DIO 402
2
DATA DATA + GND
EG1A3 X807267-001 ESDB-MLP7 DIO 402
B
2
2
VCC
X820104-001
1
RT1M1 1
V_EXPPORT_DUAL3
T HRMSTR 1206
1 C1A3
2
ELEC 2 RDL
V 1 50 X7R
220 UF 20% 10 V
TH
C1A6
470 PF 5% 402
2
9
V+
C1A2
4.7 UF 10%
6.3 V 1 X5R 805
TOP PORT
2
V_AVIP HANA_SPDIF_OUT 1
V 1 50 X7R
220 UF 20% 10 V
TOSLINK IN IN
ELEC 2 RDL
2
01.10 A
5% CH
2
A
2 C1A8
RT1M2
EG7G2 X807267-001 ESDB-MLP7 DIO 402
470 PF 5% 50 V X7R 402
R1A1 1 2
37 23
1 C1B9 220 UF
EXPPORT_PORT1_DN EXPPORT_PORT1_DP
ME ME
WAVE PORT
B
EG1A1 X807267-001 ESDB-MLP7 EMPTY 402
BI BI
1
FB1A1
BI BI
D
2
V_3P3
28 28
THRMSTR 1206
1
USB USBX2
X820108-001 1
V_EXPPORT_DUAL1
20% 10 V
RT7V1
C
1
X5R V 1 6.3 805
EG6G1 X807267-001 ESDB-MLP7 DIO 402
V_5P0DUAL
2
VERTICAL TRIPLE USB
2 C6G3
5%
50 X7RV 1 402
CONN
USB TRIPLE CONN
RT2M1
V_GAMEPORT1
1 C6G1 2 ELEC RDL
28 28
TH J1A2
V_5P0DUAL
J4A1
CONN TOSLINK
2 3 1
VCC VIN GND
4 5
EMI1 EMI2 X802398-001
28 28
BI BI
EXPPORT_PORT3_DN EXPPORT_PORT3_DP 1
2
EG1A6 X807267-001 ESDB-MLP7 DIO 402
1
2
EG1A5 X807267-001 ESDB-MLP7 DIO 402
10 11 12
DATA DATA + GND
13 14 15 16
EMI1 EMI2 EMI3 EMI4
TH X820107-001
A
8
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8 FT3M7 FTP FT3M1 FTP 23 23
IN IN
1
FT3M2 FTP FT3M8 FTP
CONN, HDMI
1
1 1
EG3A2 X807267-001 ESDB-MLP7 DIO 402
2
FT3M9 FTP FT3M3 FTP 23 23
IN IN
2
1
1 1
EG3A4 X807267-001 ESDB-MLP7 DIO 402
2
FT3M11 FTP FT3M5 FTP
23
IN IN
FT4M7 FTP
FT4M3 FTP
IN IN
2
1
J3A1
1
1 1
EG4A2 X807267-001 ESDB-MLP7 DIO 402
1
EG3A5 X807267-001 ESDB-MLP7 DIO 402
2
1 1
DB3M1
1
HDMI_CEC
HDMI_TXC_DP HDMI_TXC_DN 1
B
EG3A3 X807267-001 ESDB-MLP7 DIO 402
1
2
FT4M8 FTP
23
1
HDMI_TX0_DP HDMI_TX0_DN FT4M2 FTP
23
D
EG3A1 X807267-001 ESDB-MLP7 DIO 402
1
1
FT3M10 FTP
23
1
HDMI_TX1_DP HDMI_TX1_DN FT3M4 FTP
C
FT4M4 FTP FT4M9 FTP
1 1
1
EG4A4 X807267-001 ESDB-MLP7 DIO 402
2
EG4A3 X807267-001 ESDB-MLP7 DIO 402
1 R4M2 FT4M5 FTP
IN BI
1
HDMI_DDC_CLK HDMI_DDC_DATA
2 KOHM 1% 2 CH 402
TMDS_DATA1_SHD TMDS_DATA1_DN TMDS_DATA0_DP TMDS_DATA0_SHD TMDS_DATA0_DN TMDS_CLK_DP TMDS_CLK_SHD TMDS_CLK_DN CEC RESERVED SCL SDA DDC_CEC_GND 5VCC HOT_PLUG_DET
23 22 21 20
ME4 ME3 ME2 ME1
2
FT4M1 FTP
1
1 R4M1
R4M6 1 2
HDMI_HPD_PIN
2 KOHM 1% 2 CH 402
1
2
EG4M2 X807267-001 ESDB-MLP7 DIO 402
B
X806395-002
10 KOHM 5% CH 402
1 R4M5
1
47.5 KOHM 1%
1
1
C
HDR
HDMI TMDS_DATA2_DP TMDS_DATA2_SHD TMDS_DATA2_DN TMDS_DATA1_DP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
V_5P0STBY
37 27 23 55 37 27 23
1
HDMI_TX2_DP HDMI_TX2_DN 1
D
4
EG4M1 X807267-001 ESDB-MLP7 DIO 402
2 CH
402
FTP FT4M6
HDMI_HPD
OUT
23
EG4M5 X807267-001 ESDB-MLP7 DIO 402
2
2
A
A 37
IN
V_AVIP 1
C2A1
10% 0.1 UF V 2 6.3 X5R 402
[PAGE_TITLE=CONN, HDMI] 8
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FAB G
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CONN, ODD + HDD + MU D
29
IN
C1B11 1 2
HDD_TX_DP
HDD POWER
0.0 0.01 1 UF 10% 16 V X7R 402
1
29
IN
C1B10 1 2
HDD_TX_DN
1
EG1B3 X807267-001 ESDB-MLP7 DIO 402
0.0 0.01 1 UF 10% 16 V X7R 402
29
OUT
1
HDD_RX_DN
C1B7
HDD_TX_DP_C
1
HDD_TX_DN_C
1
EG1B4 X807267-001 ESDB-MLP7 DIO 402
OUT
RT5A1 1
FTP FT1N5
1 2
C5B17 0.1 UF 10% 6.3 V X5R 402
1 2 3 4
X819489-001 TH
C
HDD_RX_DN_C
1
HDD_RX_DP_C
1
FTP FT1N6
V_3P3
V_3P3STBY
FTP FT1N7
1
EG1B1 X807267-001 ESDB-MLP7 DIO 402
EG1B2 X807267-001 ESDB-MLP7 DIO 402
1
1 C1D1
1 C1D2
V 2 6.3 X5R
6.3 V 2 X5R
4.7 UF 10%
FTP FT1N8
805
0.1 UF 10% 402
2
ODD POWER DECOUPLING B
V_12P0
1
C5A6
4.7 UF 10%
ODD SATA
16 V 2 X5R 805
1 C1B4 2
4.7 UF 10% 6.3 V X5R 805
CONN
FT2U2 FTP FT2U3 FTP
ODD_TX_DP
C4B10
MEMORY UNIT
8
2
IN
1 2
J1B2 SATA
2
0.0 0.01 1 UF 10% 16 V X7R 402
29
V_HDD
2 THRMSTR 1206
1 2 3 4 5 6 7
1 C1B8 2
HDD_RX_DP
J5B2 1X5HDR2
9
2
2
1
29
FTP FT1N4
HDD SATA
0.01 UF 10% 16 V X7R 402
C
D
V_5P0
ODD_TX_DP_C
1
ODD_TX_DN_C
1
V_3P3
V_5P0
C5A8
0.1 UF 10% 25 V X7R 603
C5A11 4.7 UF 10% 6.3 V X5R 805
C5A7
0.1 UF 10% 6.3 V X5R 402
C4A14 4.7 UF 10% 6.3 V X5R 805
1 1
R1D6 1 2
28 28
BI BI
MUPORT_DN MUPORT_DP
59 55 27 22
BI
SMB_DATA
59 27
R1D5 1 2 0 OHM 5% 402 EMPTY 0 OH OHM 402
0 OHM 402
SMB_DATA_MU_R
5% CH
R2C10 1 2
SMB_CLK
IN
5% CH
R2C11 1 2 0 OHM 402
J1D1 1X6HDR V_MUPORT
1 2 3 4 5 6 CONN SMT
B
SMB_CLK_MU_R
5% CH
C5A14 0.1 UF 10% 6.3 V X5R 402
FTP FT1N2
0.01 UF 10% 16 V X7R 402 29
IN
ODD_TX_DN
1
C1B3
2
29
OUT
ODD_RX_DN
1
C1B1
2
29
OUT
ODD_RX_DP
1
C1B2
2
0.01 UF 10% 16 V X7R 402
ODD POWER AND CONTROL
9 1 2 3 4 5 6 7
ODD_RX_DN_C
0.01 UF 10% 16 V X7R 402
A
J1B1 SATA
FTP FT1N3
0.01 UF 10% 16 V X7R 402
1 ODD_RX_DP_C
1
FTP FT1M4
27
8
OUT
TRAY_STATUS
V_12P0 CONN
FTP FT1M3
R4A6 1 2
TRAY_STATUS_R
100 OHM OHM 5% CH 402
V_5P0
V_3P3
J4A3 1 3 5 7 9 11
4 6 8 10 12
TRAY_OPEN 1 2
1 FTP FT1M5
CONN
C4A11 75 PF 5% 50 V NPO 402
IN
27
A
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VREG, BLEEDERS D
D
V_12P0
V_5P0STBY
C
V_5P0DUAL 1 R6A7
2.2 KOHM 5% 2 CH 402
1 R6A8
1 R1T7
1 R1T6
1 R1T3
2 CH
2 CH
2 CH
10 KOHM 5%
3
1R6A92 1 C _ 0 P 2 1 V _ R E D E E L B
1
B
27
22
IN
PSU_V12P0_EN
IN
ANA_V12P0_PWRGD
2.2 KOHM 5% CH 402
3 BLEEDER_V12P0_B1
1
Q6M1 XSTR 24
1 R5M2
1 R6M2
1 R5M1
1 R6M1
2 CH
2 CH
2 CH
2 CH
10 OHM 1%
Q6A2
FET 3.2 OHM 2 SOT23
402
805
10 OHM 1% 805
10 OHM 1%
20 OHM 5%
1206
805
XSTR 2
R6A4 2 1
2 C _ R E D E E L B
1 C _ R E D E E L B
10 OHM 1% 805
1
Q6A1
20 OHM 5% 1206
22
IN
SMC_RST_N
R1T1 2 1 10 KOHM 5% CH 402
3 BLEEDER_B
1
Q1T1 XSTR 2
3
Q1T2 XSTR 2
B
2.2 KOHM 5% CH 402
V_12P0 & V_5P0 BLEEDERS
A
1
DB1E1
BLEEDER_V12P0_LOAD
3
R6A3 2 1
BLEEDER_V12P0_B2
549 OHM 1% CH 402
2 C _ 0 P 2 1 V _ R E D E E L B
C 1
V_12P0
2.2 KOHM 5% 2 CH 402
V_5P0DUAL BLEEDER
A
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1
VREGS, INPUT + OUTPUT FILTERS D 2
IN IN
CPU_VREG_APS5
2
IN
CPU_VREG_APS4
2
IN
CPU_VREG_APS3
2
2
IN
CPU_VREG_APS2
2
IN
CPU_VREG_APS1
R7P4 1 2 0 402 OHM
6 5
1R7P52
4
5% CH
0 OHM 402
R7P6 1 2
D
R7P3 1 2 0 OH M 5 % CH 402
CPU_VREG_APS6
5% CH
3
5% CH
R7P7 1 2
2
R7P8 1 2
0 OH M 5 % CH 402
1
0 OHM 402
0 OHM 402
VID CODE=1.050V V_MEM
5% CH
1 R7C15 1 R7C16
1 R7C17
1 R7C18
1 R7C19
1 R7C20
2 CH
2 CH
2 CH
2 EMPTY
2 CH
4
3
10 KOHM 5%
402
6
10 KOHM 5%
2 EMPTY 402
5
10 KOHM 5%
402
10 KOHM 5%
10 KOHM 5%
402
402
10 KOHM 5%
2
402
1
VREG_CPU_VID
OUT
44 61
C
C
V_12P0 L6B1
1 2
C7B1
0.45 UH IND TH 9 A 0.0042 OHM
4.7 UF 10% 16 V X5R 1206
V_CPUCORE INPUT FILTER V_VREG_CPU C6B1
470 UF 20% 16 V POLY TH
C7B3
470 UF 20% 16 V POLY TH
1 2
C6B3
4.7 UF 10% 16 V X5R 1206
1
OUT
44 45
C6B5
4.7 UF 10%
16 V 2 X5R 1206
B
B
1 1
V_CPUCORE OUTPUT FILTER
V_CPUCORE
1
DB6R2 DB6R1 FTP FT6R2
OUT C6C3
820 UF 20% 2.5 V POLY RDL
A
C6C1
820 UF 20% 2.5 V POLY RDL
C5C3
820 UF 20% 2.5 V POLY RDL
C6C2
820 UF 20% 2.5 V POLY RDL
C7C12
820 UF 20% 2.5 V POLY RDL
C7C13 820 UF 20% 2.5 V POLY RDL
1
FTP FT6R1
A
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VREGS, CPU CONTROLLER 43
IN
R7C11 1 2
V_VREG_CPU
681 OHM 603
VREG_CPU_VCC
1% CH
R7B5 1 2
R7C12 1 2
D
6 81 O HM 603 27
55
IN BI
PMBUS_CLK PMBUS_DATA
45
IN
VREG_CPU_PHASE2
45
IN
VREG_CPU_PHASE1
61
OUT
VREG_CPU_CSCOMP
61
OUT
VREG_CPU_CSSUM
61
OUT
VREG_CPU_CSREF
61 58 57 56 55 35
C
VREG_CPU_EN 1 FT3T3 FTP IN
422 KOHM 1% CH 402
1 KOHM 5% CH 402
1% CH
R7C4 1 2
RRAMP VREG_CPU_RAMPADJ_R
2
C7P2
C7C10 4.7 UF 10% 16 V X5R 1206
1 2
C7C11 1
0.1 UF 10% 25 V
2
R7C13
C7C9
0.1 UF 10% 6.3 V X5R 402
1 X7R 603
1 R7C10
VREG_CPU_RAMPADJ
R7C7 1 2 5% CH
DB7C2 DB7C3
R7C9 1 2
1 1
VREG_CPU_SW4 VREG_CPU_SW3 VREG_CPU_PHASE2_R VREG_CPU_PHASE1_R
2 KOHM 1% CH 402
FT7P1 FTP
RTH1
VREG_CPU_FB
1
R6C2
IC
U7C1 NCP4201 1 30
10 KOHM 5% 2 CH 402
0 OHM 402
OUT
44
VREG_CPU_VCC3_3P3
1 UF 10% 16 V X5R 603
11
PWRGD
40
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
31 32 33 34 35 36 37 38
PSI_N*
39
PWM4 PWM3 PWM2 PWM1
26 27 28 29
OD1_N* ODN_N*
21 20
ALERT* FAULT*
2 3
VCC3 VCC RAMPADJ
6
EN/VTT
5 4
SCL SDA
22 23 24 25
SW4 SW3 SW2 SW1
18
CSCOMP
17
CSSUM
16
CSREF
15
FB
VREG_CPU_COMP
14
COMP
VREG_CPU_FBRTN
13
FBRTN
VREG_CPU_TRDET
12
TRDET
D
2
10 KOHM 5% CH 1 402
1
FTP FT3T2
VREG_CPUCORE_VCS_PWRGD VREG_CPU_VID
6 5 4 3 2 1
OUT
51 27
IN
43
VID'S HAVE INTERNAL PULL DOWNS
1
VREG_CPU_OD1_N
VREG_CPU_ALERT_N VREG_CPU_FAULT_N
1 1
DB7C1
VREG_CPU_VCC
OUT
44
VREG_CPU_PWM2 VREG_CPU_PWM1
OUT OUT
45 45
VREG_CPU_DRV_EN
OUT
45
C
DB7P1 DB7P2
VREG_CPU_IMON
1 R _ P M O C S C _ U P C _ G E R V
RPH2
R7B3
27.4 KOHM 1% CH 402
RPH1
2 R7B4
2
27.4 KOHM 1% 1 CH 402
1
2
603 THRMSTR
TEMP SENSOR RCS2
35.7 KOHM 402 RCS1
9
VREG_CPU_IREF
R7B1 1 2
R7C1 1 2
1% CH
CCS2
C7C1
1
1
52.3 KOHM 1% 1 CH 402
1% 6.81 KOHM CH 402 NEED TO SET DURING VALIDATION
CCS1
C7C3
3300 PF 10%
3300 PF 10% 50 V X7R 2 402
2 R7B2
VREG_CPU_ILIMITFS
V 2 50 X7R
19
IMON RT GND
IREF GND_SLUG
VREG_CPU_RT
7
1 R7C5
41
909 KOHM 1%
ILIMITFS
2 CH
402
X817912-001
2 R7C6
ROSC = 909K FOSC = 250KHZ
121 KOHM 1%
402
8 10
1 CH
402
B
PARTS ARE TRIMMED AT FACTORY SUCH THAT VBOOT=1.05V
B
I2C ADDRESS 1100 000 R/W HEX WRITE 1100 000 0 0XC0 READ 1100 000 1 0XC1
V_CPUCORE FT7P2 FTP
1
V 2 6.3 X5R
5.76 KOHM 1%
2 CH
402
402
ST6C1 1 2
VREG_CPU_FBRTN
2
SHORT VENABLE ST6D1 VREG_V_CPUCORE_S R7C14 1 1 2 2 0 OHM % SHORT 805 EMPTY 1
DB7C5
1
DB7C6
PLACE SHORT NEXT TO POINT OF LOAD
A
C7C7
0.1 UF 10%
1
PLACE SHORT NEXT TO OUTPUT OF DUAL INDUCTOR
1 R7C8
CB C7C2 1 2
VREG_CPU_FB
1
C7C6
1000 PF 10%
50 V 2 X7R 402
CFB
C7C4
10 PF 5%
RB
1.1 KOHM 1% CH 402
1
1
1000 PF 10% 50 V X7R 402
470 PF 5% 50 V X7R 402
R7P1 1 2
C7P1
NOTE: VALID UP TO 58A
1
CA C7C5
RA
2
VREG_CPU_COMP_R
R7C2 1 2
402
18.2 KOHM1% CH 402
1500 PF 10% 50 V X7R 402
43.2 KOHM1% 402 CH
R7P2 1 2
50 V 2 NPO
1
ST6D2
2
SHORT
VREG_CPU_TRDET_R
1 C7B7
470 PF 5%
50 V 2 X7R 402
R7C3 1 2 10 KOHM 5% 402 CH
PLACE SHORT NEXT TO POINT OF LOAD
A
[PAGE_TITLE=VREGS, [PAGE_TITLE=VREGS , CPU CONTROLLER] 8
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VREG, CPU OUTPUT PHASE 1 & 2 D
43
IN
V_VREG_CPU
D R6N1 1 2 2.2 OHM 1% CH 805
VREG_CPU2_VCC
1 2
44 44
IN IN
D6B1 1N4148 1 3
C6B4
1 UF 10% 16 V X5R 603
R6N2 1 2 U6B1 4 2 3 6
VREG_CPU_PWM2 VREG_CPU_DRV_EN
VREG_CPU_BST2
SOT23 DIO
2
3 D
1 8 7 5
C6N2
VREG_CPU_BST2_R
2.2 OHM 1% CH 805
IC
MOS DRIVER VCC BST IN DRVH OD_N* SW PGND DRVL
1
C6N1
0.01 UF 10% 50 V EMPTY 805
C7B5UF 1 4.7
Q6B2 X819086-001
1 G
0.1 UF 10% 25 V X7R 603
S
2
1 C7N1
4.7 UF 10%
10%
16 V 2 X5R
DPAK
16 V 2 EMPTY
1206
V_CPUCORE
1206
FET
NOM.VOLTAGE: 0.9-1.2V
VREG_CPU_PHASE2
VREG_CPU_DRVH2
OUT
1 R6C1
3
3
X850497-001
D
Q6C2
Q6C1
D
X819087-001
C
1
VREG_CPU_DRVL2
DPAK G
S
2
1 OHM 1% 2 CH 805
FET
1
DPAK G
S
FET
2
V_CPUCORE
R _ 2 W S _ U P C _ G E R V
X819087-001
1
L6C1
2200 PF
2
S M E MP MP TY TY
1
DUAL INDUCTOR
C7C8
44
1
L1
L4
4
3
L3
L2
2
50 V 10% X7R 805
C DB7C4
X820048-001 420NH DCR +/-8%
V_CPUCORE L6C2
IND
DUAL INDUCTOR
B
1R5N72 2.2 OHM 1% CH 805
VREG_CPU1_VCC
1
VREG_CPU_BST1
SOT23 DIO
1 UF 10%
R5N8 1 2
V 2 16 X5R
2.2 OHM OHM 1% CH 805
603
U5B5
44
IN
VREG_CPU_PWM1
4 2 3 6
MOS DRIVER VCC BST IN DRVH OD_N* SW PGND DRVL
L2
L3
3
4
L4
L1
1
B
X850592-001 420NH 40 A 0.66
D5B1 1N4148 1 3
C5B10
2
IC 1 8 7 5
1 C5N5 2
0.01 UF 10% 50 V EMPTY 805 VREG_CPU_BST1_R
3 C5N6
D
Q6B1
S
FET
1
X819086-001 1
0.1 UF 10% 25 V X7R 603
2
DPAK G
2
C6B2
4.7 UF 10% 16 V X5R 1206
1 2
+/-4% NOTE: THRUHOLE PART IS 2% IMPROVEMENT ON DCR
C6N3
4.7 UF 10% 16 V EMPTY 1206
VREG_CPU_PHASE1
VREG_CPU_DRVH1
1 R5C1
3
X850497-001
D
A VREG_CPU_DRVL1
1
G
S
2
3 Q5C3
D
Q5C1
X819087-001
X819087-001
DPAK
DPAK
FET
1
G
S
2
FET
OUT
44
1 OHM 1% 2 CH 805 R _ 1 W S _ U P C _ G E R V
A
1 C5C1 2200 PF 10%
50 V 2 X7R 805
[PAGE_TITLE=VREGS, [PAGE_TITLE=VREGS , CPU OUTPUT PHASE 1,2] 8
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VREGS, V5P0 DUAL D
D
V_5P0STBY V_12P0
V_5P0STBY
2 10 KOHM 5% 2 CH 402
10 KOHM 5% 2 CH 402
C
R1N3 2 1 VREG_V5P0_SEL_C
10 KOHM 402
1% CH
6.3 V 1 X5R 402
IN
VREG_V5P0_SEL FT1P1 FTP
1
R1P1 1 2
U1B1
IC SI4501DY
2 1 XSTR
C1N3
1
0.22 UF 10% 6.3 V EMPTY 2 402
2 R1P2
D D D D
C1B12 22 20%UF V_5P0 10 V 2 EMPTY 1 1206
G1 S1
C
V_5P0DUAL
S2 G2
VREG_V5P0_SEL_NGATE
VREG_V5P0_SEL_B2
VREG_V5P0_SEL_B1
4.75 KOHM1% CH 402
220 UF 20% 10 V
2 ELEC RDL 3 4
VREG_V5P0_SEL_PGATE
Q1N1 27
1 C2B2
C1N4
0.22 UF 10%
1 R1N1
1 R1N2
5 8 7 6
V_5P0DUAL
NOM.VOLTAGE: 5.00V 1 1
FTP FT1N1 FTP FT1N9
X801132-002
4.75 KOHM 1%
1 CH
402
B
A
VREG_5P0_SEL
VREG_5P0_SEL NGATE/PGATE
V_5P0DUAL
HIGH
LOW
V_5P0STBY
LOW
HIGH
V_5P0
B
A
[PAGE_TITLE=VREGS, [PAGE_TITLE=VREGS , V5P0 DUAL] 8
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VREGS, V5P0 V_12P0 L2B1
D
0.45 UH 9 A 0.0042 OHM
V_VREG_V3P3_V5P0
330 UF 20% 16 V POLY TH
2 R1T4 10 OHM
2
1%
U1E1
1 CH
805 3 5 4
VREG_V3P3_V5P0_VDL
2
C2E2 1 UF 10% 16 V X5R 603
48
OUT
48
VREG_V5P0_PWRGD
OUT
27
1 2
2
VREG_V5P0_ISENSE_P
OUT
56
2
VREG_V5P0_ISENSE_N
OUT
56
C1E1 1 UF 10% 16 V X5R 603
1
1 UF 10% 16 V X5R 603
2
VIN VDL VCCO
1 OF 2 ADP1877
1 R2T3 10 KOHM
1 C2F3 4.7 UF 1 C2F10 4.7 UF
2 CH
16 V 2 X5R
10%
5%
IC
402
PGOOD1
1206
10%
CIV1
V 2 16 EMPTY 1206
27 RR1
RAMP1
1 R1T2
C1E2
29
R2E6 1 2
VREG_V5P0_RAMP
0 OHM 5% 2 CH 402
820 KOHM 402
1
5% CH
Q2F1
D
C
2
SYNC
DH1
23
1
VREG_V5P0_DH
1 R1E12
1
DPAK G
0 OHM 5% 2 EMPTY 402
ST2G2 SHORT
3 X819086-001
VREG_V3P3_V5P0_SYNC
S
2
ST2G3 SHORT
FET
C V_5P0
VOLTAGE: 5.09V
V_5P0
C2F1 FT2T2 FTP
R2E7
1 0 OHM 402
1
BST1 2 5% CH
VREG_V5P0_TRK
1 2
27
IN
D
1
C2E8
1
OUT
VREG_V3P3_V5P0_VCCO
IND TH
R2E3 2 1
VREG_V5P0_EN
422 KOHM 402
0.22 UF 10% 6.3 V EMPTY 402
2
1
0.1 UF 10% 25 V X7R 603
2
ST2U1
1
SW1 1
24
VREG_V5P0_SW
1
C2E6
ILIM1
0.01 UF 10% 16 V X7R 402
26
VREG_V5P0_ILIM
R2F1 1 2
3.48 K 402 DL1
1% CH
21
D
10 UF 20% 805
10 UF 20% 805
1
C2G2
10 UF 20%
1
C2V4
10 UF 20%
1
C2G1
10 UF 20%
1 R2G2
150 OHM 5%
6.3 V V 6.3 V 2 CH 2 6.3 EMPTY 2 EMPTY 2 EMPTY 1206 805
805
1 C2G5
820 UF 20% 6.3 V
2 POLY TH
805
G
S
2
FET 2
1% CH 2
ST2U2 SHORT
1
ST2G1
1
SHORT
402
FREQ
DB2G4
B
DPAK
1
VREG_V5P0_DL
22 VREG_V5P0_PGND
C2V1
1
1 CH
PGND1
1
DB2G2 FTP FT2V2
Q2F2
22.1 KOHM 1%
7
C2V5
6.3 V 6.3 V 2 EMPTY 2 EMPTY
2 R1F3 VREG_V3P3_V5P0_FREQ
1
X819086-001
RFREQ
R1E17 2 1
1
3
1% CH
RGCS1
97.6 KOHM 402
R2G1 2 1
10 MOHM 2512
IND TH 1.6 UH 0.00375 OHM 10 A
EN1
1
L2F1 1 2 VREG_V5P0_RSENSE
VREG_V5P0_SW_S
SHORT
RLIM1
2
10 KOHM 5% 2 CH 402
B
25
TRK1
C2E7
VREG_V5P0_EN_R
1% CH
1 R2E2
32
VREG_V5P0_BST
E L B A N E V
1 R2F7
0 OHM %
2 EMPTY 805
VREG_V5P0_FB
OUT
56
RF11
1 R2E4 30
VREG_V5P0_COMP
1 1
A
2
CC12
2
C2E4
330 PF 5% 50 V NPO 402
C _ P M O C _ 0 P 5 V _ G E R V
7.5 KOHM 1%
COMP1
2 EMPTY
CC11
C2E3
3300 PF 10% 50 V X7R 402
COMP2 BW= COMP1 BW=
FB1
VREG_V5P0_FB_MID
31
VREG_V5P0_SS
1 RC1 1%
2 CH
402
FTP FT2T3
OUT
56
RF12
1 R2T4
1 R2E5 11 KOHM
1
402
28
1 KOHM 1%
SS1
2 EMPTY
CSS1
C2E5
0.047 UF 10%
X7RV 2 10 402
402
6 33
AGND GNDSLUG
X817911-002
LCC32
A
DRAWING Wed Feb 10 16:23:32 2010
[PAGE_TITLE=VREGS, [PAGE_TITLE=VREG S, V5P0] 8
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PROJECT NAME TRINITY_XDK
MICROSOFT CONFIDENTIAL
3
2
3
2
FAB G
PAGE 47/81
REV 1.01
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8
4
1
VREGS, V3P3 D
47 47
IN IN
V_VREG_V3P3_V5P0 VREG_V3P3_V5P0_VCCO
D
R1E14
1
U1E1
2 OF 2
IC
2
ADP1877 PGOOD2
10 KOHM 5% CH 402 VREG_V3P3_PWRGD
OUT
27
VREG_V3P3_ISENSE_P
OUT
56
OUT
56
14 RR2
RAMP2
12
R1E22 1 2
VREG_V3P3_RAMP
422 KOHM 1% CH 402 1
ST1F1
2
SHORT
R1E15 2 1 0 OHM 402
C FT1T10 FTP 27
IN
DH2 9
VREG_V3P3_TRK
18
VREG_V3P3_DH
1 U1F1
1
VREG_V3P3_EN
8
BST2
16
VREG_V3P3_BST
EN2
2
C1F1
1
0.1 UF 10%
2
ST1U2
1
1 R1E16
SW2
17
4
GATE0
3
SRC0
2 1
GATE1
7 AMP
FET
SRC1
ST1F3
5 6
DRN1 DRN1
7 8
0.02 VREG_V3P3_SW_S
L1F1 1 2 VREG_V3P3_RSENSE
2.3 UH 6 A
IND TH
1
R1F9 1 2
VREG_V3P3_ILIM
R1F1 1 2
4.53 KOHM 402 DL2
B
20
1
SO-8
RGCS2
R1F2 2 1
VREG_V3P3_DL
R2F9 2 1 0 OHM % 805 EMPTY
VREG_V3P3_PGND
1 2
C1F6
4.7 UF 10% 6.3 V X5R 805
1 2
C1G2
4.7 UF 10% 6.3 V X5R 805
1
DB2G1
C1F3
4.7 UF 10% V 2 6.3 X5R 805 1 DB1F2
2
1
ST1F2
2
SHORT
1% CH
B
RR1 19
C1F9
4.7 UF 10% 6.3 V X5R 805
VENABLE
1% CH
22.1 KOHM 402
PGND2
FTP FT2V3 1
30 MOHM 2512 CH 1%
2 15
C
V_3P3 VOLTAGE: 3.3V
RLIM2 ILIM2
VREG_V3P3_ISENSE_N
2
SHORT
1206
V_3P3
DRN0 DRN0
VREG_V3P3_SW
X807111-001
1
16 V 2 X5R
SHORT
25 X7RV 603
10 KOHM 5% 2 CH 402
CIV2
C1U1
4.7 UF 10%
TRK2
5% CH
ST1U1
VREG_V3P3_FB
OUT
56
OUT
56
1
SHORT RF21
1 R1E20 11
VREG_V3P3_COMP
1 1 2
A
CC22
C1E4
120 PF 5% 50 V NPO 402
2
4.53 KOHM 1%
2 EMPTY
COMP2
402
CC21
C1E3
3300 PF 10% 50 V X7R 402
C _ P M O C _ 3 P 3 V _ G E R V
FB2
1 R1E19
1 RC2
1% 2 CH 402
FTP FT1T9
RF22 VREG_V3P3_SS13
1 R1E21 7.87 KOHM
1
VREG_V3P3_FB_MID
10
2
1 KOHM 1%
SS2
2 EMPTY 402
CSS2
C1E5
0.047 UF 10% 10 V X7R 402
X817911-002
LCC32
A
[PAGE_TITLE=VREGS, [PAGE_TITLE=VREG S, V3P3] 8
7
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PROJECT NAME TRINITY_XDK
MICROSOFT CONFIDENTIAL
DRAWING Wed Feb 10 16:23:33 2010
3
2
3
2
FAB G
PAGE 48/81
REV 1.01
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4
VREGS, VEDRAM
V_12P0 L7B1 0.45 UH 9 A 0.0042 OHM
D
470 UF 20% 16 V POLY TH
2
2
10 1% OHM
1 CH
U3G1
805
VREG_VMEM_VEDRAM_VDL
C3G1
1 2
C3G3
1 UF 10% 16 V X5R 603
1 2
VIN VDL VCCO
1 OF 2 ADP1877
2 R3F12 0 OHM 5% 1 CH 402
10 KOHM 5% CH 402 1
IC PGOOD1
50
VREG_VEDRAM_PWRGD
OUT
27
2
VREG_VEDRAM_ISENSE_P
OUT
55
29
2
VREG_VEDRAM_ISENSE_N
OUT
55
3 Q3F1
1
X819086-001 SYNC
DH1
23
1
VREG_VEDRAM_DH
G
S
2
32
25
VREG_VEDRAM_BST
2
C3F5
V_CPUEDRAM
FET
SW1
24
VREG_VEDRAM_SW
ILIM1
26
VREG_VEDRAM_ILIM
2
ST3F1
1
VREG_VEDRAM_SW_S
VREG_VEDRAM_RSENSE
10 MOHM 2512
FTP FT5T4
1
1% 820 C 4E3UF 20%
CH
820 C 4E6UF 20%
2.5 V POLY RDL
SHORT
RLIM1
B
DL1
21
1
R3F7 1 2
3.32 KOHM 402
D
Q4F1
16 V 2 EMPTY 1206
X819086-001 1
VREG_VEDRAM_DL
DB4E3
820 UF C4F7 20% 2.5 V EMPTY RDL
2.5 V POLY RDL
G
S
2
402
FREQ
1% CH PGND1
22
VREG_VEDRAM_PGND
2
ST4U1
1
C5E11
4.7 UF 10%
V 2 16 EMPTY 1206
1
C4T7
4.7 UF 10%
V 2 16 EMPTY 1206
1
C5E10
4.7 UF 10%
16 V 2 EMPTY 1206
B
FET 2
22.1 KOHM 1%
1 CH
1
DPAK
2 R3V1 RFREQ
C5T52
4.7 UF 10%
3
1% CH
RGCS1
7
1
R4F1 2 1
EN1
10 KOHM 5% 2 CH 402
VREG_VEDRAM_FREQ
C
V_CPUEDRAM
IND 1.7 UH TH 13.8 A 0.0034 OHM
1
0.1 UF 10% 25 V X7R 603
TRK1
1 R3F15
97.6 KOHM 402
ST4F2 SHORT ST4F4 SHORT
DPAK
L4F1 1 2
1
R3G4 2 1
FTP FT3V4
VOLTAGE: 1.075V
1
VREG_VEDRAM_EN
1
1
5% CH
D
BST1
FT3V1 FTP
CIV1
1206
R3F10 1 2
VREG_VEDRAM_RAMP
680 KOHM 402
2
D
C3F7
4.7 UF
27
0 OHM 5% 2 EMPTY 402
IN
OUT
10% 16 V 2 EMPTY
1206
0 OHM 5% 2 CH 402
VREG_VEDRAM_TRK
C3F1
4.7 UF
1 R3F14
VREG_VMEM_VEDRAM_SYNC
1
10%V 2 16 X5R
1 R3F13
27
50
RR1
RAMP1
SYNC HIGH=FORCED PWM MODE SYNC LOW =PULSE SKIP MODE
C
3 5 4
C3V1
1 UF 10% 16 V X5R 603
1
R3G16 2
2 R3G2
TH
2
OUT
VREG_VMEM_VEDRAM_VCCO
1 C7B8
1
330 UF 20% 16 V POLY
1 UF 10% 16 V X5R 603
V_VREG_VMEM_VEDRAM IND TH
C3F8
1
1
E L B A N E V
1 R3F11 0 OHM
1
DB4E4
1
DB4E5
ST4F1
1
SHORT
% 2 EMPTY 805
VREG_VEDRAM_FB
OUT
55
OUT
55
SHORT RF11
1 R3F8
7.87 KOHM 1%
2 EMPTY 402
VREG_VEDRAM_COMP
1 1
A
2
CC12
C3F3
62 PF 5% 50 V NPO 402
2 C _ P M O C _ M A R D E V _ G E R V
COMP1 1 FB1
1
1%
2 CH
402
CSS1
C3F4
0.047 UF
RC1
2
10%V 10 X7R 402
28
SS1
6 33
AGND GNDSLUG
X817911-002
1 R3F9
10 KOHM 1% 2 EMPTY 402
LCC32
FTP FT3U1
VREG_VEDRAM_FB_MID
31 RF12
VREG_VEDRAM_SS
1 43.2 R3F6KOHM RC1=120K
30
CC11
C3F2
4700 PF 10% 50 V X7R 402
A
[PAGE_TITLE=[VREGS, [PAGE_TITLE=[VREG S, VEDRAM] 8
MICROSOFT CONFIDENTIAL
DRAWING Wed Feb 10 16:23:33 2010
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PROJECT NAME TRINITY_XDK
FAB G
PAGE 49/81
REV 1.01
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8
4
1
VREGS, VMEM D
49 49
IN IN
D
V_VREG_VMEM_VEDRAM VREG_VMEM_VEDRAM_VCCO
1
2 OF 2
IC PGOOD2
10%V 2 16 X5R
10 KOHM 5% 1 CH 402
ADP1877 14
C7F3
1
4.7 UF
2 R3G15
U3G1
CIV2
C7U1
4.7 UF 10% 16 V 2 EMPTY
1206
1206
0 OHM 402
RR2
RAMP2
12
1
R3R5 1 2
VREG_VMEM_PWRGD_R
R3G13 1 2
VREG_VMEM_RAMP
FTP FT3V5
VREG_VMEM_PWRGD_CPU_TRST_N_R
5% CH 1
680 KOHM 5% CH 402
3 D
1
Q7G1
R3G5 2 1VREG_VMEM_TRK 9 0 OHM 402 FT3V3 FTP 27
IN
DH2
18
1
VREG_VMEM_DH
SHORT ST7F3
G
S
2
OUT
55
2
VREG_VMEM_ISENSE_N
OUT
55
V_MEM
VOLTAGE: 1.8V
FET
1
5% CH
1
1
L7F1 2 1
ST6V2
VREG_VMEM_EN
8
BST2
16
2 C3G9 1
VREG_VMEM_BST
EN2
0.1 UF 10% 25 V X7R 603
1 R3G14
10 KOHM 5% 2 CH 402
SW2
17
2
1
VREG_VMEM_SW_S
IND TH
SHORT
27
VREG_VMEM_ISENSE_P
DPAK
TRK2
OUT
2
SHORT
X819086-001
C
ST7F2
V_MEM
C
FTP FT6U1
R7F1 1 2
VREG_VMEM_RSENSE
1.7 UH 13.8 A 0.0034 OHM
DB7F1
10 MOHM 2512
1% CH
C7F2
820 UF 20% 2.5 V POLY RDL
1 C7F1
4.7 UF 10% 6.3 V
2 EMPTY 805
1
VREG_VMEM_SW
DB7F2
V_MEM RLIM2
ILIM2
15
VREG_VMEM_ILIM
R3G10 1 2
3.32 KOHM 402
D
20
330 UF 20% 2.5 V
Q7G2
2 EMPTY SM
X819086-001
B DL2
1 C7R1
3
1% CH
DPAK
1
VREG_VMEM_DL
G
RGCS2
S
2
V_MEM
1 R4G3
22.1 KOHM 1%
1 C4U4
2 CH PGND2
19
VREG_VMEM_PGND
2
SHORT
1
330 UF
ST7F1
402 ST6V1
B
FET
2 E L B A N E V
1 R3G17 0 OHM %
1 SHORT
20% 2.5 V 2 EMPTY SM
2 EMPTY 805
VREG_VMEM_FB
OUT
55
OUT
55
RF21
1 R3G11 11
VREG_VMEM_COMP
1
1
A
CC22
C3G7
62 PF 5%
50 V 2 NPO 402
2 C _ P M O C _ M E M V _ G E R V
20 KOHM 1%
COMP2
2 EMPTY
CC21
C3G6
402
4700 PF 10% 50 V X7R 402
FB2
13
10 KOHM 1%
SS2
2 EMPTY 402
RC2 1%
2 CH
402
FTP FT3V2
RF22
1 R3G12 VREG_VMEM_SS
1 43.2 R3V4KOHM
1
VREG_VMEM_FB_MID
10
1 2
CSS1
C3G8
0.047 UF 10% 10 V X7R 402
X817911-002
LCC32
A
[PAGE_TITLE=[VREGS, [PAGE_TITLE=[VREG S, VMEM] 8
7
6
5
7
6
5
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PROJECT NAME TRINITY_XDK
MICROSOFT CONFIDENTIAL
DRAWING Wed Feb 10 16:23:33 2010
3
2
3
2
FAB G
PAGE 50/81
REV 1.01
1
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8
4
1
VREGS, VCS D
D
V_12P0
V_5P0 1
L4B1 C4N9
27 44
OUT
R4B21 1 2
VREG_CPUCORE_VCS_PWRGD
0.45 UH IND 9 A TH 0.0042 OHM
C4N7
1 UF 10% 16 V X5R 603
1 UF 10% 16 V X5R 603
1
0 OHM 5% 402 EMPTY
C
2
C4B4
4.7 UF 10% 6.3 V X5R 805
V_CPUCORE
DB4P8 TP
2
IN
1
CPU_SRVID
5% CH
2
U4B3
ir3638
4
VCC
10 14 3 5 11 2
VC NC NC0 NC1 NC2 VP
DB4N2
1
DB4P7
1 1
1
2 CH
6.3 V 2 X5R
1 MOHM 5%
C4C5
0.1 UF 10%
402
402
VREG_VCS_NC1 VREG_VCS_RT_PWRGD
VREG_VCS_VP
1 R4C11
VREG_VCS_NC
VREG_VCS_OCP
C4B12
10 UF 20% 6.3 V X5R 805
4.7 UF 10% 16 V X5R 1206
1 5%KOHM 2 EMPTY 402
DB4P6 TP
C4B11
C4B14
1 R4C13
R4C14 1 2 0 OHM 402
1
10 UF 20% 6.3 V X5R 805
C5N11 10 UF 20% 6.3 V X5R 805
C4N10 10 UF 20% 6.3 V X5R 805
1 C5B21 1
C5N10 10 UF 20% 6.3 V X5R 805
2
D
HDRV LDRV
9 6
VREG_VCS_HDRV
2.2 OHM 805
VREG_VCS_HDRV_R
1
1% CH
VREG_VCS_LDRV
C4B7
2.2 OHM 805
0.1 UF 10% 402
VREG_VCS_COMP
12
COMP
2
VREG_VCS_ISENSE_N
OUT
57
C5B19
4.7 UF 10%
V 2 6.3 X5R
1
805
ST5C3 SHORT
Q5B1
PGND GND
V_CPUVCS
DPAK G
S
2
D
1
FET
Q5C2
L5C1 1 2
VREG_VCS_VOUT
VREG_VCS_LDRV_R
1% CH
1
S
2
1% CH
FTP FT5R17 1
1
C5P1
4.7 UF 10%
V 2 6.3 X5R 805
DPAK G
R5C2 1 2
10 MOHM 2512
IND 1.7 UH TH 13.8 A 0.0034 OHM
X819086-001
R4N15 1 2
SS
6.3 V 1 X5R
2
1
C5B20
4.7 UF 10% 6.3 V X5R 805
VOLTAGE: 1.25 - 1.3V
VREG_VCS_VOUT_L
2
57
X819086-001
R4B4 1 2
402
B
820 UF 20% 6.3 V POLY TH
3
13
OUT
3
2 KOHM 1%
VREG_VCS_SS_SD_N
VREG_VCS_ISENSE_P
C
2 EMPTY 1
2
V_CPUVCS
IC
1 R4C17
DB4N3 TP
ST5C1 SHORT
V_VREG_VCS
1
C5C6
4.7 UF 10%
6.3 V 2 X5R 805
DB5C1
1 C5C2 2
820 UF 20% 2.5 V POLY RDL
FET
B
8 7
1 R4B11
27.4 KOHM 1%
1
CH 2 402
2 1
C4B6
R _ P M O C _ S C V _ G E R V
22 PF 5% 50 V NPO 402
1 2
FB
VENABLE
X811812-001 SSOP
11 KOHM 402
R4B19
C4B5
4700 PF 10% 50 V X7R 603
1
20 KOHM 1% EMPTY 2 402
R4B22 1 2
R5B13 1 2
R4B17 1 2 1% CH
VREG_VCS_RC 1.33 KOHM KOHM 1% EMPTY 402
0 OHM % 805 EMPTY
C4B13 1 2
2
ST5C2
1
DB5B3 SHORT
1
DB5B2
1
VREG_VCS_FB
OUT
57
VREG_VCS_FB_MID
OUT
57
3300 3300 PF 10% 50 V EMPTY 402
A
A GAIN=0.4 WITH R4B17 = 11K, R4B19 = 27.4K OUTPUT = CPU_SRVID(1+GAIN)
[PAGE_TITLE=VREGS, [PAGE_TITLE=VRE GS, VCS] 8
7
6
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PROJECT NAME TRINITY_XDK
MICROSOFT CONFIDENTIAL
DRAWING Wed Feb 10 16:23:33 2010
3
2
3
2
FAB G
PAGE 51/81
REV 1.01
1
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8
4
1
VREGS, 1P8+GPUPCIE+SBPCIE+CPUPLL+EFUSE D
NOM.VOLTAGE: 1.5V
TARGET FOR VALHALLA=1.5V 1 R1D4
1 R1D3
1 R1D2
1 R1D1
V_1P8 3
V_VREG_1P8_IN
IC
1
1
2
OUT
ADJUST/GND
R1C1 1 2
V_VREG_1P8
1
X800500-001 DPAK 1.8V
0.1 UF 10% 2 25 V X7R 603
C
NCP1117 IN
2
0 OHM 805
1
% CH
2
1 C4E11
FTP FT2T1
1
1 C1C1
C1C2
0.1 UF 10% 25 V X7R 603
100 UF 20% 16 V ELEC RDL
IC
U4E2
NOM.VOLTAGE: 1.8V
U1C1
C1C3
V_GPUPCIE
V_3P3
V_1P8
6.2 OHM 6.2 OHM 6.2 OHM 6.2 OHM 1% 1% 1% 1% 2 CH 2 CH 2 CH 2 EMPTY 1210 1210 1210 1210
2 DB2E1
NCP1117
3
IN
1
ADJUST/GND
OUT
2
OUT/TAB
4
V_SBPCIE
0 OHM 805
V_3P3 IC
U4E1 3 1
1
C4E10
1 UF 10%
V 2 16 X5R 603
% CH
NCP1117 IN
OUT
2
1
ADJUST/GND
1 R4E6
1 R4E5
2 EMPTY
2 CH
1 KOHM 1%
X819037-001
DPAK 1.8V
402
1 OHM 1% 402
VREG_CPUPLL_ADJUST
1 2
0 OHM 805
1
1 V_CPUPLL
R4E4 1 2
V_VREG_1P8PLL
% CH
C4E13
0.1 UF 10% 6.3 V EMPTY 402
0 OHM 402
453 OHM 1% 2 CH 402
1 2
2 VREG_GPUPCIE_FB
OUT
58
R4E10 1 2 VREG_GPUPCIE_FB_MID
IN
58
1
5% CH
1 R4E9
1
2 CH
V 2 6.3 X5R
C4E12
4.7 UF 10%
402
805
NOTE: BOTTOM ADJUST RESISTOR LEFT IN TO REDUCE EFFECT OF ADJUST PIN CURRENT WHEN USED WITH 1K DIGIPOT
NOM.VOLTAGE: 1.83V 1 FTP FT4T3 1
B
DB4E2
OUT
58
IN
58
V_5P0
2 1
V_EFUSE
C4R2
NOM.VOLTAGE: 1.5V V_EFUSE
1 UF 10% 16 V X5R 603
IC
U4R1 LD39015
C4E9
4.7 UF 10% 6.3 V X5R 805
A NOTE: BOTTOM ADJUST RESISTOR LEFT IN TO REDUCE EFFECT OF ADJUST PIN CURRENT WHEN USED WITH 1K DIGIPOT
C
R _ X E I C P _ G E R V
191 OHM 1%
R _ L L P U P C _ G E R V
1 R4F2
DB4E1
5% CH
V_CPUPLL
5% CH
5% CH
R3T5 0 OHM 402
0 OHM 402
FTP FT3T1
R4U4 1 2 VREG_CPUPLL_SBPCIE_FB_MID
C4F8
0.1 UF 10% 6.3 V EMPTY 402
1 OHM 1% 2 CH 402
FTP FT4T1 1
DB3E1
R3F4 1 2 VREG_CPUPLL_SBPCIE_FB 0 OHM 402
1 R4E7
1
% CH
VREG_PCIEX_ADJUST
NOM.VOLTAGE: 1.83V
R3E5 1 2
0 OHM 805 1 KOHM 1% 2 EMPTY 402
V_SBPCIE NOTE: THIS WAS SET TO 1.83V TO ACCOMODATE DROP IN FERRITES
R4E11 1 2
V_VREG_GPUPCIE
1 R4E8
X800501-001 SOT223 1.5V
1 UF 10% 16 V X5R 603
2
B
D
V_GPUPCIE
V_5P0
2
IN
VREG_EFUSE_EN FT4R5 FTP
1
VIN
3
ENABLE
1
VREG_EFUSE_EN HIGH IS 1.8V (V_MEM)
2 R4R1
10 KOHM 5%
1 CH
402
X819038-001
VOUT
5
GND
2
NC
4 1.5V
VREG_EFUSE_VOUT
R4R4 1 2 0 OHM 805
C4R1
1 UF 10% 16 V X5R 603
C4R3
0.1 UF 10% 6.3 V X5R 402
% CH
1
FTP FT4R3 1
DB4D1
A
8
7
6
5
7
6
5
MICROSOFT CONFIDENTIAL
DRAWING Wed Feb 10 16:23:34 2010
[PAGE_TITLE=VREGS, [PAGE_TITLE=VREG S, 1P8+GPUPCIE+SBPC 1P8+GPUPCIE+SBPCIE+CPUPLL+EFUSE] IE+CPUPLL+EFUSE] 4
3
2
3
2
PROJECT NAME TRINITY_XDK
FAB G
PAGE 52/81
REV 1.01
1
CR-53 : @TRINITY_LIB.TRINITY(SCH_1):PAGE53
8
4
1
VREGS, STANDBY SWITCHERS D
D
V_5P0STBY
FT5M3 FTP
V_1P8STBY
1
2.2 UH IND 1210 1.6 A 0.05 OHM
C
V_VREG_STBY_VIN
1 2
C5A9
10 UF 20% 6.3 V X5R 805
1 2
C5B18 10 UF 20% 6.3 V X5R 805
1 2
V_3P3STBY C5B16 10 UF 20% 6.3 V X5R 805
1 R5B3
4
VIN
1
ENABLE
2
10 KOHM 1% 10 KOHM 2 CH 1% 402 2 EMPTY 402
SIMPLESWR SW
3
FB/VO
5
2.2 UH 1.6 A 0.05 OHM VREG_1P8STBY_FB
1 R5B2
237 KOHM 1% 2 CH 402
1 FT5N1 FTP
C5N9
1
R5B4 1 2
V_1P8STBY_R
0 OHM 805
IND 1210
R5B17 2 1
475 KOHM 402
SOT23
VREG_1P8STBY_EN
1
VREG_1P8STBY_SW
L5B2 1 2
GND
1 R5B5
X821327-001
V_1P8STBY
NOM.VOLTAGE: 1.802V
IC
U5B1
L6A1 1 2
1
1% CH
C5B1
1
2
2
C5B2
10 UF 20% 6.3 V X5R 805
1 2
C5B7
4.7 UF 10% 6.3 V EMPTY 805
1 2
1
% CH
DB5B4
FTP FT5N2
C C5B6
0.1 UF 10% 25 V X7R 603
18 50 PF V 5% NPO 402
1 UF 10%
1
V 2 16 X5R
DB5B5
603
V_3P3STBY
B
V_1P8STBY 1 R5A7
FT5M2 FTP
C5M5 1 UF 10%
V 2 16 X5R
1
ENABLE
2
GND X821327-001
SW
3
FB/VO
5
L5A1 1 2
VREG_3P3STBY_SW
2.2 UH 1.6 A 0.05 OHM
SOT23
1
105 KOHM 1% 2 CH 402
R5A11 1 2
V_3P3STBY_R
0 OHM 805
IND 1210
R5A6 2 1
475 KOHM 402
1 R5A5
VREG_3P3STBY_EN
1
VIN
VREG_3P3STBY_FB
10 KOHM 1% 10 KOHM 1% 2 CH 402 2 EMPTY 402
1 R5M6
SIMPLESWR
4
V_3P3STBY
NOM.VOLTAGE: 3.315V
IC
U5A1
1
C5A1
1
1% CH
1 2
1000 PF 50 V 10% X7R 402
2
C5A2
10 UF 20% 6.3 V X5R 805
1
% CH
1
DB5B1
B FTP FT5M1
C5A3
0.1 UF 10%
V 2 25 X7R 603
1
DB5A1
603
A
A
[PAGE_TITLE=VREGS, [PAGE_TITLE=VREGS , STANDBY SWITCHERS] 8
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MICROSOFT CONFIDENTIAL
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FAB G
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1
BOARD LEVEL DECOUPLING V_5P0
D
1
V_12P0
C1U3
2 1 2
C3N40
0.01 UF 10% 16 V X7R 402
1 2
1
C3M5
0.01 UF 10% 16 V X7R 402
2
C6N4
0.01 UF 10% 16 V X7R 402
1 2
1
0.1 UF 10% 6.3 V X5R 402 2
C1T4
0.1 UF 10% 6.3 V X5R 402
1
2
1
C1P1
0.1 UF 10% 6.3 V X5R 402 2
C1A10 0.1 UF 10% 6.3 V X5R 402
D
1
C2A15 0.1 UF 10% 6.3 V X5R 402
2
C7B4
0.01 UF 10% 16 V X7R 402
V_1P8STBY
1
V_5P0
C
V_5P0DUAL 2
1 2
C3E6
0.1 UF 10% 6.3 V X5R 402
1 2
C4P3
0.1 UF 10% 6.3 V X5R 402
1 2
C4N6
0.1 UF 10% 6.3 V X5R 402
1 2
C3T23
0.1 UF 10% 6.3 V X5R 402
1 2
C2V2
0.1 UF 10% 6.3 V X5R 402
1 2
C3U4
0.1 UF 10% 6.3 V X5R 402
V_3P3
1
C2U1
0.1 UF 10%
V 2 6.3 X5R 402
1 2
C3G12
0.1 UF 10% 6.3 V X5R 402
1 2
C3V3
0.1 UF 10% 6.3 V X5R 402
1 2
C3U1
0.1 UF 10%
V 2 6.3 X5R 402
1
C4M1
0.1 UF 10%
V 2 6.3 X5R 402
1
C3T21
0.1 UF 10%
6.3 V 2 X5R 402
1
C3T20
0.1 UF 10%
6.3 V 2 X5R 402
1
C2T19
0.1 UF 10%
V 2 6.3 X5R 402
1 2
C1R1
0.1 UF 10% 6.3 V X5R 402
0.1 UF 10% 6.3 V X5R 402
1 2
C3E7
1
0.1 UF 10% 6.3 V X5R 402
2
C3R21 0.1 UF 10% 6.3 V X5R 402
1
C3C3
0.1 UF 10%
6.3 V 2 X5R 402
C
C5G8
0.1 UF 10% 6.3 V X5R 402
V_3P3STBY
V_3P3 1
C3T24
1 2
C2N3
0.1 UF 10% 6.3 V X5R 402
1 2
C2R21
0.1 UF 10% 6.3 V X5R 402
B
1 2
C2P1
0.1 UF 10% 6.3 V X5R 402
1 2
C3R20
0.1 UF 10% 6.3 V X5R 402
1
C3P10
0.1 UF 10%
V 2 6.3 X5R 402
1
C4V1
0.1 UF 10%
V 2 6.3 X5R 402
1
C4G1
0.1 UF 10%
6.3 V 2 X5R 402
1
C4N2
0.1 UF 10%
V 2 6.3 X5R 402
1
C3R19 0.1 UF 10%
6.3 V 2 X5R 402
B V_1P8
V_1P8STBY
1 0.1 UF C2R22 10% V 2 6.3 X5R 402
1
C4N3
0.1 UF 10%
6.3 V 2 X5R 402
A
1
C4N5
0.1 UF 10%
V 2 6.3 X5R 402
1
C4N8
0.1 UF 10%
6.3 V 2 X5R 402
A
[PAGE_TITLE=BOARD, [PAGE_TITLE=BOARD , DECOUPLE] 8
MICROSOFT CONFIDENTIAL
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FAB G
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MARGIN, VMEM + VEDRAM V_5P0DUAL
D 37 27 23
40 37 27 23
59 27
59 41 27 22
HDMI_DDC_CLK
BI
HDMI_DDC_DATA
IN
BI
D
R2B3 1 2
IN
PMBUS_CLK
35 44 55 56 57 58 61
OUT
0 OHM 5% 402 EMPTY PMBUS_DATA
6.3 V 1 X5R
35 44 55 56 57 58 61
BI
0 OHM 5% 402 EMPTY
R2B4 1 2 0 OHM 402
5% CH
402
50
IN
VREG_VMEM_FB
50
IN
VREG_VMEM_FB_MID
0 OHM 402
R3G8 1 2 0 OHM 402
R2B2 1 2
SMB_DATA
C3G5
2.2 UF 20%
1R2B12
SMB_CLK
2
VREG_VMEM_FB_MID_R
5% CH
V_5P0DUAL
C
2 4
1 R3U3
1 R3G9
2 EMPTY
2 EMPTY
6
A1
A3
12
4
W1
W3
14
1 R3U1
1 R3G7
2 CH
2 CH
AD1 AD0
13
VSS DGND
8 10
VREG_VEDRAM_FB_MID_R
R3F16 1 2
0 OHM 402
PMBUS_CLK PMBUS_DATA
IN BI
55 35 44 55 56 57 58 61
VREG_VEDRAM_FB
IN
49
VREG_VEDRAM_FB_MID
IN
49
5% CH
C
AD5252 I2C ADDRESS 0101 1 AD1 AD0 R/W HEX WRITE 0101 1 0 0 0 0X58 READ 0101 1 0 0 1 0X59
1 KOHM 5%
402
9 7
B3
B1
402
1 KOHM 5%
IC SCL SDA
X819026-001 TSSOP VALUE=10K DEFAULT=127 (0X7F) SETPOINT1=VMEM 81 (0X51) SETPOINT2=VEDRAM 144 (0X90)
1 KOHM 5%
402
HDR
WP*
V_5P0DUAL
1 KOHM 5%
J5B1 2X2HDR 1 3
3
11 2
MARGIN_VMEM_VEDRAM_AD0
V_5P0STBY
U3V1 VDD
5 MARGIN_VMEM_VEDRAM_AD1
5% CH
1
402
N: PMBUS HEADER CAN BE USED AS A RELIABILITY INTERFACE HEADER.
V_5P0DUAL U3G3 1
1
B
IC REF3333
IN
2
GND
3
1
C3G11
2.2 UF 20% 6.3 V X5R 402
2
OUT
V_5P0
C3G10
B
0.1 UF 10%
6.3 V 2 X5R
X820467-001 SC70 3.3V +/-0.15%
402
V_3P3_VREF_VMEM_VEDRAM
2 C3G2 1
50 50 49 49
IN IN IN IN
2.2 UF 20% 6.3 V X5R 402
VREG_VMEM_ISENSE_P VREG_VMEM_ISENSE_N VREG_VMEM_CF2
VREG_VEDRAM_ISENSE_P VREG_VEDRAM_ISENSE_N VREG_VEDRAM_CF1
2 C3V2 U3V2 8
VAA
IC
2
0.22 UF 10% 6.3 V X5R 1 402
A
2 1
C3F6
0.22 UF 10% 6.3 V X5R 402
4
2 1 5
IN2_P IN2_N CF2
OUT2
9 10 6
IN1_P IN1_N CF1
OUT1
7
GND
3
VREG_VMEM_IOUT VREG_VEDRAM_IOUT
X817913-001 X817913001 MSOP10 C3G4
1
AD8213
2.2 UF 20% 6.3 V X5R 402
1 R3G6
1 R3G1
2 CH
2 CH
24.3 KOHM 1%
402
24.3 KOHM 1%
402
U3G2
IC AD7991
8
VDD
6 5 4 3
VIN3/VREF VIN2 VIN1 VIN0 X817914-001
SCL SDA
1 2
GND
7
PMBUS_CLK PMBUS_DATA
49
IN IN
VREG_VMEM_FB VREG_VEDRAM_FB
55 35 44 55 56 57 58 61
SOT23
AD7991-0 I2C ADDRESS 0101 000 R/W HEX WRITE 0101 000 0 0X50 READ 0101 000 1 0X51 PACKAGE IS SOT23-8 OR ALSO CALLED RJ-8
50
IN BI
A
[PAGE_TITLE=MARGIN, [PAGE_TITLE=MARGI N, VMEM + VEDRAM] 8
MICROSOFT CONFIDENTIAL
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FAB G
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MARGIN, V3P3 + V5P0 D
VREG_V3P3_FB
V_5P0DUAL 47
IN
1 R2U1
1
35.7 KOHM 1%
2 CH
402 2
47
IN
2
V_P Q2F3 ADR5043 NC3 X819033-001 3.0V 0.1% V_N IC R2T5 1 2
VREG_V5P0_FB_MID
0 OHM 402
C2F4
3
WP*
VREG_V5P0_FB_A1
6
A1
A3
12
VREG_V3P3_FB_A3
VREG_V5P0_FB_MID_R
4
W1
W3
14
VREG_V3P3_FB_MID_R
5
B1
B3
13
VSS DGND
8 10
402
5% CH
11 2
MARGIN_V3P3_V5P0_AD0
AD1 AD0
1 R1U4
1 R2F3
2 EMPTY
2 CH
AD5252 I2C ADDRESS 0101 1 AD1 AD0 R/W HEX WRITE 0101 1 0 1 0 0X5A
KOHM 1 1 R2F2 5% 2 EMPTY
READ
1 KOHM 5%
402
1 KOHM 5% 402
1 R1U3 1 KOHM 5% 2 CH 402
IN BI
48
D
22.1 KOHM 1% 2 CH 402
ADR5040A
55 35 44 55 56 57 58 61
R1T19 1 2 0 OHM 402
VREG_V3P3_FB_MID
IN
5% CH
48
X819026-001 TSSOP VALUE=10K DEFAULT=128 (0X7F) SETPOINT1=V5P0 69 (0X45) SETPOINT2=V3P3 123 (0X7B)
V_5P0DUAL
V_5P0DUAL
PMBUS_CLK PMBUS_DATA
IN
1 R1U5
NC3 X819034-001 2.048V 0.1% V_N IC
2
U1U1 VDD
MARGIN_V3P3_V5P0_AD1
C
IC 9 SCL 7 SDA
1
2.2 20% UF
6.3 V 1 X5R
V_P Q1F1
1
VREG_V5P0_FB
0101 1 0
1
1
C
0X5B
402
V_5P0DUAL IC
U1F3 1
1 2
OUT
2
GND
3
1
C1F10 2.2 UF 20% 6.3 V X5R 402
C1F11 0.1 UF 10%
6.3 V 2 X5R
X820467-001 SC70 3.3V +/-0.15%
V_5P0
B
REF3333 IN
402
B V_3P3_VREF_V5P0_V3P3
2
2
C1U2
2.2 UF 20% 402
47 47 48 48
IN IN IN IN
VREG_V5P0_CF2
2 1 5
VAA IN2_P IN2_N CF2
VREG_V3P3_CF1
9 10 6
IN1_P IN1_N CF1
VREG_V5P0_ISENSE_P VREG_V5P0_ISENSE_N VREG_V3P3_ISENSE_P VREG_V3P3_ISENSE_N C2F6
0.22 UF 10% 6.3 V X5R 402
2
2
1
6.3 V 1 X5R
C1F2
0.22 UF 10%
V_5P0
402
OUT2
4 VREG_V3P3_IOUT
OUT1
7
GND
3
X817913-001 MSOP10
1 R2F5
24.3 KOHM 1% 2 CH 402
24.3 KOHM 1% 2 CH 402
150 OHM 1% CH 402
R1F4 1 2
VREG_V3P3_FB_R
1 R1F6
1 R1F5
2 CH
2 CH
221 OHM 1%
402
221 OHM 1%
402
VDD
AD7991
VIN3/VREF VIN2 VIN1 VIN0
SCL SDA
1 2
GND
7
PMBUS_CLK PMBUS_DATA
IN BI
55 35 44 55 56 57 58 61
1 R2F8
VREG_V5P0_FB_R
150 OHM 1% CH 402
IC
U1F2 8 6 5 4 3
VREG_V5P0_IOUT
R2F4 1 2
402
V_3P3
A
6.3 V 1 X5R
AD8213
8
C2F2
2.2 UF 20%
IC
U2U1
6.3 V 1 X5R
X818998-001
SOT23
AD7991-1 I2C ADDRESS 0101 001 R/W HEX WRITE 0101 001 0 0X52 READ 0101 001 1 0X53 PACKAGE IS SOT23-8 OR ALSO CALLED RJ-8
A
[PAGE_TITLE=MARGIN, [PAGE_TITLE=MARGI N, V3P3 + VP50] 8
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3
PROJECT NAME TRINITY_XDK
FAB G
PAGE 56/81
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3
MARGIN, VREFS + VCS V_5P0STBY
D
REF3333
1
1 2
IN
2
OUT
1
C5N8
3
GND
2.2 UF 20% 6.3 X5R V 402
X820467-001 SC70 3.3V +/-0.15%
1
V_3P3_VREF_VCS
2
2.2 UF 20% 6.3 V X5R 402
57
IN
MEM_VREFS
IN
1 KOHM 5% 2 CH
C5N7
0.1 UF 10% 6.3 X5R V 402
1 R4N13 1 KOHM 5% 2 EMPTY 402
402
V_5P0 2 U5B2
2.2 UF 20%
C
V 1 6.3 X5R 402
VREG_VCS_CF2
51 51
IN
VREG_VCS_ISENSE_P VREG_VCS_ISENSE_N
C4B1
0.22 UF 10% 6.3 V X5R 402
1
V 1 6.3 X5R
C5B8
0.22 UF 10% 402
AD8213
1
VAA
2 1 5
IN2_P IN2_N CF2
OUT2
4
VREG_VCS_IOUT2
9
IN1_P IN1_N CF1
OUT1
7
VREG_VCS_IOUT
GND
3
N I _ S C V _ G E R V
2
IC
8
10 6
VREG_VCS_CF1
2
R4B2
1 R4N10
2 CH
2 CH
C5B5
2.2 UF 20% 6.3 V X5R 402
24.3 KOHM 1% 402
1 R4B3
1 KOHM 5% 2 CH 402
1 KOHM 5%
2 CH
402
MARGIN_VCS_AS
V_5P0STBY 2 1 R4N5 1 2 0 OHM 402
C4N1
2.2 UF 20% 6.3 V X5R 402
MEM_VREFS_R
5% CH
1 R4N7
2 R4N4
2 CH
2 CH
1 CH
1 R4N3 1 KOHM
1 R4N6 1 KOHM
402
1 KOHM 5% 402
100 OHM 5%
402 MARGIN_VMEM_VREFS_BOT
5% 2 EMPTY 402
5% 2 EMPTY 402
AGND2 AGND1
X814249-001
MSOP10
PMBUS_CLK PMBUS_DATA
8
D
AS CONVST_N*
AGND2 AGND1
X814249-001
MSOP10
2 CH
7 2
IC
1
1 R5B6
55 35 44 55 56 57 58 61
402
6
T S V N O C _ S C V _ N I G R A M
IN BI
AD7992-1 I2C ADDRESS AS=GND 0100011 R/W WRITE 0100011 0 0X46 READ 0100011 1 0X47 AS=VDD 0100100 R/W HEX
VIN2/REFIN VIN1
AD7992
SCL SDA
ALERT/BUSY
10 9
PMBUS_CLK PMBUS_DATA
IN BI
55 35 44 55 56 57 58 61
C
8
7 2
AD7992-1 I2C ADDRESS AS=VDD 0100100 R/W HEX WRITE 0100100 0 0X48 READ 0100100 1 0X49 AS=GND 0100011 R/W
1 KOHM 5%
B
402
IC
U4B1 VDD
3
WP*
6
A1
A3
12
4
W1
W3
14
5
B1
B3
13
VSS DGND
8 10
AD1 AD0
SCL SDA
1
AD5252 I2C ADDRESS 0101 1 AD1 AD0 R/W WRITE 0101 1 1 1 0 READ 0101 1 1 1 1
V_P
Q4B1 ADR510
PMBUS_CLK PMBUS_DATA
9 7
X819026-001 TSSOP VALUE=10K DEFAULT=128 (0X7F) SETPOINT1=VREFS 63 (0X3F) SETPOINT2=VCS 140 (0X8C)
V_MEM
1 R4N2
1 KOHM 5%
CONVST_N*
4 5
1
11 2
MARGIN_VREFS_AD0
V_5P0STBY
1
ALERT/BUSY
10 9
V_MEM
MARGIN_VREFS_AD1
V_5P0STBY
AS
VDD
2 EMPTY 402
MEM_VREFS
6
3
1 R4N1
1 KOHM 5%
OUT
VIN2/REFIN VIN1
U5N1
2 CH
1 R4B1
57
4 5
SCL SDA
AD7992
1 KOHM 5%
402
1 R5N2
1
24.3 KOHM 1% CH 2 402
X817913-001 MSOP10
B
A
1 R4N14 1 KOHM 5%
C5B15
VDD
T S V N O C _ S F E R V _ N I G R A M
VREG_VCS_FB
2
3
1 R4N8
MARGIN_VREFS_AS
57 51
1
IC
2 C4N4
IC
U5B6
2
U4B2
0X5E 0X5F
VREG_VCS_FB_MID_R
R4B18 1 2
0 OHM 402
5% CH
IN BI
55 35 44 55 56 57 58 61
VREG_VCS_FB
OUT
51 57
VREG_VCS_FB_MID
OUT
51
A
2
[PAGE_TITLE=MARGIN, [PAGE_TITLE=MARGI N, VREFS + VCS] 8
NC3 X821158-001 1.0V 0.35% IC
V_N
7
6
5
7
6
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PROJECT NAME TRINITY_XDK
MICROSOFT CONFIDENTIAL
DRAWING Wed Feb 10 16:23:34 2010
3
2
3
2
FAB G
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MARGIN, VGPUPCIE, VSBPCIE, VCPUPLL, V12P0, TEMP V_5P0DUAL
V_3P3STBY
U6A1 IC INA219
D 4
1
D 1
VS
C6M5 2
0.1 10% UF
6.3 V 2 X5R
C3E4
2.2 UF 20% 6.3 X5R V 402
402
38
IN
R6A10
VREG_V12P0_ISENSE_P
2
38
IN
VREG_V12P0_ISENSE_N
C
61 58 57 56 55 44 35 55
BI IN
52
10% 16 V X5R 603
WP*
6
A1
A3
12
VREG_CPUPLL_SBPCIE_FB
VREG_GPUPCIE_FB_MID
4
W1
W3
14
VREG_CPUPLL_SBPCIE_FB_MID
5
B1
B3
13
VSS DGND
8 10
VREG_GPUPCIE_B1
MARGIN_GPUPCIE_CPUPLL_AD0
11 2
AD1 AD0
1 R3F2 1 R3E3
PMBUS_DATA PMBUS_CLK VREG_V12P0_A1 VREG_V12P0_A0
1 R6M4 1 R6M3 0 OHM 5%
6 5
SDA SCL
8 7
A1 A0
3
0 OHM 5%
2 CH 402
1 KOHM 1 KOHM 5% 5% 2 CH 2 EMPTY 402 402
1 R3E1
0 OHM 5%
1 R3F3 1 R3E2 1 KOHM 5% 2 EMPTY 2 402
1 KOHM 5% CH 402
402
IN
OUT
2
GND
3
0 OHM 5%
2 CH
402
C
AD5252 I2C ADDRESS 0101 1 AD1 AD0 R/W HEX WRITE 0101 1 1 0 0 0X5C READ 0101 1 1 0 1 0X5D
1 1
2.2 UF 20%
V 2 6.3 X5R
C3U2
2
0.1 UF 10%
6.3 V 2 X5R
X820467-001 SC70 3 .3 .3 V + //- 0. 0. 15 15 %
402
402
61 58 57 56 55 44 35 55
1
C1G12
0.1 UF 10% 6.3 V X5R 402
BI IN
2
1
C1G11
100 PF 5% 50 V NPO 402
2
C1G13
10 UF 20% 6.3 V X5R 805
1 R1G1
0 OHM 5%
2 CH
402 U1G2
PMBUS_DATA PMBUS_CLK TEMP_RT_A0 TEMP_RT_D4_P TEMP_RT_D3_P
V_3P3_VREF_CPUPLL_PCIE
2
52 52
A
IN IN
1 R3U2
1 KOHM 5% 2 CH 402
C1G7 1 100 PF
C3E5
2
IC
U3E1 3
VDD
4 5
VIN2/REFIN VIN1
VREG_CPUPLL_PCIE_AS
6
AS
VREG_CPUPLL_PCIE_CONVST_N
1
CONVST_N*
AGND2 AGND1
X820047-001
MSOP10
VREG_GPUPCIE_FB VREG_CPUPLL_SBPCIE_FB
AD7992
SCL SDA
ALERT/BUSY
10 9
PMBUS_CLK PMBUS_DATA
IN BI
55 35 44 55 56 57 58 61
TEMP_RT_D_N TEMP_RT_D2_P TEMP_RT_D1_P
5 6 7 8
B
IC
LM95234
VDD SMBDAT SMBCLK A0 D4+ D3+ DD2+ D1+ GND
NC TCRIT3_N TCRIT2_N TCRIT1_N
X819406-001
1 14 11 10
DB_TM_CT3 DB_TM_CT2 DB_TM_CT1
1 1 1
DB1V1 DB1V2 DB1V3
LLP-14
5% 50 V NPO
8
2 402
LM95234 I2C ADDRESS 1001 110 R/W HEX WRITE 1001 110 0 0X9C READ 1001 110 1 0X9D
C1G9 1 100 PF
7 2
5% 50 V NPO
A
2 402 J1G3
AD7992-0 I2C ADDRESS 0100 001 R/W HEX WRITE 0100 001 0 0X42
5% 50 V NPO 402
2 12 13 9 3 4
C1G8 1 100 PF
1 R3E4
1 KOHM 5% 2 CH 402
52
IC REF3333
C3U3
2.2 UF 20% 6.3 V X5R 402
52
V_3P3STBY
1
1
IN OUT
X820501-001 SOT23-8
U3T1
B
55 35 44 55 56 57 58 61
1 R3F5
V_5P0DUAL
1
IN BI
VREG_CPUPLL_B3
X807129-001 TSSOP VALUE=1K DEFAULT=127 (0X7F) SETPOINT1=GPUPCIE 92(0X5C) SETPOINT2=CPUPLL 124(0X7C)
2 CH
GND
PMBUS_CLK PMBUS_DATA
9 7
VREG_GPUPCIE_FB
VIN-
1% CH
CH 2 402
3
IC SCL SDA
IN
MARGIN_GPUPCIE_CPUPLL_AD1
2
2
VDD
OUT
V_5P0DUAL
VREG_V12P0_ISENSE_N_R
INA219 I2C ADDRESS 1000 000 R/W HEX WRITE 1000 000 0 0X80 READ 1000 000 1 0X81
VIN+
C6A6 1 1 UF
R6A11 2 1
10 OHM 402
52
1
VREG_V12P0_ISENSE_P_R
1
1 0 O HM HM 1 % 402 CH
U3E2 1
1 3 5
2X4HDR
2 4 6
C1G10 5% PF 1 100 50 V NPO
2 402
SOLDER LUG DB1F1 1
READ
0100 001 1
0X43
7
8
HDR
[PAGE_TITLE=MARGIN, [PAGE_TITLE=MA RGIN, VGPUPCIE, VSBPCIE, VCPUPLL, V12P0, TEMP] 8
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XDK, DEBUG CONNECTORS V_3P3STBY
V_3P3
D 1 V_5P0STBY 2 J2C1 2X5HDR_10 28 28
OUT IN
SPI_SS_N SPI_MISO
2 4 6 8
HDR
1 3 5 7 9
SPI_MOSI SPI_CLK
0.1 UF 10% 6.3 V X5R 402
C
D
1 0.1 UF C4A12 10% 6.3 V X5R 402
0.1 UF C2C4 10% 6.3 V X5R 402
1 C3UF D1 10% 16 V X5R 603
0.1 UF C2C5 10% 6.3 V 2 X5R 402
1 C2UF C6 10% 16 V X5R 603
J2C3 2X7HDR_14 OUT OUT
28 28
26 27 27 55 41 22 27
C2C3
V_5P0STBY
IN IN OUT BI
KER_DBG_TXD SMC_DBG_TXD SMC_DBG_EN R2C6 SMB_CLK 1 2 100 OHM 402
5% CH
SMB_CLK_R
2 4 6 8 10 12
HDR
1 3 5 7 9 11 13
KER_DBG_RXD
OUT
26
SMC_RST_N
IN
22
SMB_DATA
BI
SMC_RST_XDK_N SMB_DATA_R EXT_PWR_ON_DBG
R3R13 1 2 100 OHM 5% CH 402
R2C7 1 2
100 OHM 5% CH 402
R2C4 1 2
1 KOHM 5% CH 402
EXT_PWR_ON_N
OUT
22 27 41 55
C
37 60 27 61
B
B
A
A
[PAGE_TITLE=XDK. DEBUG CONN] 8
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XDK DEBUG D
D
GCPU JTAG HEADER
J4C1 2X4HDR 60 5 5 60 5 5
OUT IN OUT IN
CPU_TDI CPU_TDO CPU_TCLK CPU_TRST_N_R
1 3 5 7
CPU_TMS GPU_TRST_N GPU_TRST_ED_N
2 4 6 8
OUT IN
5 60 5
IN
5
IN OUT
5 5
HDR
GCPU EEPROM HEADER
J4D1 2X3HDR 5 5 5
OUT OUT OUT
GPU_SROM_CLK_R GPU_SROM_SO_R GPU_SROM_CS_N_R
1 3 5
GPU_SROM_SI GPU_SROM_WP_N
2 4 6
HDR
C
C
HANA JTAG HEADER
J3C1 2X3HDR 22 22 22
OUT IN OUT
HANA_TDI HANA_TDO HANA_TCLK
1 3 5
2 4 6
HANA_TMS HANA_TRST
2 4 6
SB_TMS SB_TRST
OUT
22 22
IN
HDR SB JTAG HEADER
J3G1
2X3HDR 26 26 26
OUT IN OUT
SB_TDI SB_TDO SB_TCLK
1 3 5
OUT IN
26 26
HDR
B
V_5P0 1
B
D4D1
GREEN SM 2 LED
R4D3 CPU_CHECKSTOP_N_LED_C
CPU_CHECKSTOP_N_LED
2 825 1 OHM 1% CH 402
V_MEM
1
2 R4E3
C4C4
0.1 UF 10%
V 2 6.3 X5R
2 R4C6
10 KOHM 5% 1 EMPTY 402
R4C9 1 2
A
60 5 5 5 60 5
IN OUT OUT IN OUT
CPU_RST_V1P1_N CPU_TMS CPU_TRST_N CPU_TDO CPU_TDI
R4C10 2 1
R4C4 1 2
2 4 6 8 10
1
C4C3
0.1 UF 6.3 V 2 10% X5R 402
1 3 5 7 9
HDR
CPU_CHECKSTOP_N_R
R4C7 1 2 0 OHM 402
5% CH
1
Q4D2
1 CH
402
XSTR 2
1 KOHM 5% CH 402
J4C2 2X5HDR
CPU_RST_N_2_R
1 KOHM 5% 402 EMPTY
10 KOHM 5%
3 CPU_CHECKSTOP_N_LED_B
1 KOHM 5% CH 402
402
2
V_3P3STBY
SMC_CPU_CHKSTOP_DETECT
BI
27
3 SMC_CPU_CHKSTOP_DETECT_B
1
Q4D1 XSTR 2
CPU_CHECKSTOP_N CPU_TCLK EXT_PWR_ON_N
IN OUT OUT
2 5 60 37 59 27 61
A
[PAGE_TITLE=XDK, DEBUG TITAN] 8
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DEBUG BOARD, SPYDER CONN D
D
ALL STP POINTS SHALL BE ADDED TO TOP SIDE IN LAYOUT
V_MEM 1 1
C
STP7E1 STP7E2
C 43
V_CPUVCS 1 1
23
IN
STP5D1
CPU_TEMP_P R4P2 1 2
1
STP4C3
STP4C1
1
CPU_TEMP_N R4P1 1 2
1
EDRAM_TEMP_N R4P4 1 2
23
IN
V_CPUEDRAM
EDRAM_TEMP_P R4P5 1 2
1
STP4C6
STP4C4
1 1
STP4E2 STP4E1
23
IN
GPU_TEMP_P R4P6 1 2 0 OHM 5% 402 EMPTY
OUT
4 23
0 OHM 5% 402 EMPTY
0 OHM 5% 402 EMPTY
B
4 23
IN
VREG_CPU_VID
0 OHM 5% 402 EMPTY
0 OHM 5% 402 EMPTY
STP5D2
OUT
1
STP4C5
STP4C2
1
GPU_TEMP_N R4P3 1 2 0 OH M 5 % 402 EMPTY
OUT
4 23
1
1
2 3 4 5 6
1 1 1 1 1
44 44 44
IN IN IN
VREG_CPU_CSSUM VREG_CPU_CSCOMP VREG_CPU_CSREF
1 1 1
60 59 37
IN
EXT_PWR_ON_N
1
BI IN
PMBUS_DATA PMBUS_CLK
1 1
58 57 56 55 44 35 55
STP7C7 STP7C6 STP7C5 STP7C4 STP7C3 STP7C2
STP7B1 STP7C1 STP7N1
STP3C1
B STP5B1 STP5B2
V_CPUCORE 1 1
STP6C1 STP6C2
V_CPUPLL 1
A
STP4E3
A
[PAGE_TITLE=DEBUG [PAGE_TITLE=DEB UG BOARD, SPYDER CONN] 8
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LABELS AND MOUNTING D
D INTELLIGENT SERIAL NUMBER TARGET. LB2B1 LABEL 1
1375X250_TARGET X801181-001
WEST PCB MOUNTING HOLES
C
EDGE MTG1B1 MTG_HOLE 9 NC9 EMPTY GND=1,2,3,4,5,6,7,8 EDGE MTG1G1 MTG_HOLE 9 NC9
EAST PCB MOUNTING HOLES EDGE MTG7G1 MTG_HOLE NC9
EDGE MTG4G1 MTG_HOLE 9 NC9
9
C
EMPTY GND=1,2,3,4,5,6,7,8
EMPTY GND=1,2,3,4,5,6,7,8
EMPTY GND=1,2,3,4,5,6,7,8
B STD MTG4F1 MTG_HOLE 9 NC9 EMPTY GND=1,2,3,4,5,6,7,8
STD MTG4D1 MTG_HOLE 9 NC9 EMPTY GND=1,2,3,4,5,6,7,8
A
B
HEAT SINK MOUNTING HOLES
STD MTG6F1 MTG_HOLE 9 NC9 EMPTY GND=1,2,3,4,5,6,7,8
STD MTG6D1 MTG_HOLE 9 NC9 EMPTY GND=1,2,3,4,5,6,7,8
A
[PAGE_TITLE=LABELS [PAGE_TITLE=LABEL S AND MOUNTING] 8
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CR-64 : @TRINITY_LIB.TRINITY(SCH_1):PAGE64
WAVE CONN
USB TRIPPLE CONN
RJ45 AUX CONN
HDMI CONN
TOSLINK CONN
POWER CONN
CLOCK DIAGRAM
AVIP CONN
I2S_MCLK (12.288MHZ) ENET PHY
I2S_BCLK (3.072MHZ)
AUDIO DAC FAN CONN X TAL
HDD SATA CONN
ODD PWR CONN 27 MHZ
ODD SATA CONN
STANDBY SWITCHERS VR
HDD PWR CONN
ENET_CLK (25MHZ) STBY_CLK (48MHZ) SATA_CLK_REF (25MHZ) SATA_CLK_DP/DN (100MHZ)
CPU VR
VCS VR
HANA
PCIEX_CLK_DP/DN (100MHZ)
CPU_CLK_DP/DN (100MHZ)
AUD_CLK (24.576MHZ)
GPU_CLK_DP/DN (100MHZ) PIX_CLK_OUT_DP/DN (100MHZ)
V5P0 DUAL VR V1P8 VR
MA_CLK1_DP/DN (800MHZ) MA_CLK0_DP/DN (800MHZ) MEM
GCPU
A & B
MB_CLK1_DP/DN (800MHZ)
FLASH
CLAM
MB_CLK0_DP/DN (800MHZ)
PSB
VEFUSE VR
V5P0 V3P3 VR
VGPUPCIE VR VSBPCIE VR
VEDRAM VMEM VR
) Z H M 0 0 8 (
) Z H M 0 0 8 (
) Z H M 0 0 8 (
) Z H M 0 0 8 (
N D / P D _ 1 K L C _ C M
N D / P D _ 0 K L C _ C M
N D / P D _ 1 K L C _ D M
N D / P D _ 0 K L C _ D M
MEM C & D CLAM
TILT PWR BUTTON
EJECT BUTTON
BORON FPM
IR
2 X GAME CONN
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