Watchdog Timer for ATM

DESIGN OF TIMER FOR APPLICATION IN ATM USING VHDL AND FPGA A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF

Bachelor of Technology in Electronics & Instrumentation Engineering

By SUBHRAJIT MISHRA And ISHAN DHAR

Department of Electronics & Communication Engineering National Institute of Technology Rourkela 2007

DESIGN OF TIMER FOR APPLICATION IN ATM USING VHDL AND FPGA A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF

Bachelor of Technology in Electronics & Instrumentation Engineering By SUBHRAJIT MISHRA And ISHAN DHAR

Under the Guidance of Prof. K.K.MAHAPATRA

Department of Electronics & Communication Engineering National Institute of Technology Rourkela 2007

National Institute of Technology Rourkela

CERTIFICATE This is to certify that the thesis entitled, “Design of Timer for application in ATM using FPGA and VHDL” submitted by Sri Subhrajit Mishra and Sri Ishan Dhar in partial fulfillments for the requirements for the award of Bachelor of Technology Degree in Electronics & Instrumentation Engineering at National Institute of Technology, Rourkela (Deemed University) is an authentic work carried out by him under my supervision and guidance.

To the best of my knowledge, the matter embodied in the thesis has not been submitted to any other University / Institute for the award of any Degree or Diploma.

Date:

Prof. K.K.Mahapatra Dept. of Electronics & Instrumentation Engg National Institute of Technology Rourkela - 769008

ACKNOWLEDGEMENT We would like to articulate our deep gratitude to our project guide Prof. K.K.Mahapatra who has always been our motivation for carrying out the project. It is our pleasure to refer Microsoft Word exclusive of which the compilation of this report would have been impossible. An assemblage of this nature could never have been attempted with out reference to and inspiration from the works of others whose details are mentioned in reference section. We acknowledge out indebtedness to all of them. Last but not the least, our sincere thanks to all of our friends who have patiently extended all sorts of help for accomplishing this undertaking.

SUBHRAJIT MISHRA

ISHAN DHAR

CONTENTS Page No Abstract

ii

Chapter 1

GENERAL INTRODUCTION

1

Chapter 2

VHDL

3

Chapter 3

Chapter 4

Chapter 5

2.1 Introduction 2.2 Describing Structure 2.3 Describing behaviour

4

SPARTAN-II

9

3.1 What is FPGA?

10

3.2 Introduction to Spartan-II

12

3.3 General Overview

14

3.4 Architectural Description

17

3.5 Process Involved

19

5 6

WATCHDOG TIMER AND ITS APPLICATION IN ATM

24

4.1 Introduction

25

4.2 General Use of watchdog Timer

26

4.3 Watchdog timer as a long Interval Timer

31

4.4 Application of watchdog Timer in ATMs

35

EXPERIMENTATION AND RESULTS

36

5.1 Coding

37

5.2 Source Code

38

5.3 Conclusion

40 41

REFERENCES

i

ABSTRACT

Introduction A watchdog timer is a computer hardware timing device that triggers a system reset if the main program, due to some fault condition, such as a hang, neglects to regularly service the watchdog (writing a “service pulse” to it, also referred to as “petting the dog”). The intention is to bring the system back from the hung state into normal operation. Such a timer has got various important applications, one of them being in ATMs (Automated Teller Machine) which we have studied and designed in our project.

Steps involved 1. Coding using VHDL The key advantage of VHDL when used for systems design is that it allows the behaviour of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires).n information theory. To start coding in VHDL, one needs a simulation toolI. The simulation tool that we have used here is Xilinx ISI9.1i.First the required code for timer circuit was written in VHDL and simulated so as to obtain the required output waveforms. 2. Burning the code on Spartan-II kit After the coding was completed, VHDL model is translated into the "gates and wires" that are mapped onto a programmable logic device. The programmable logic device used here is Spartan-2

Experimental work The above coding and burning methods were completed and the output was observed on FPGA kit. The timer code was implemented using VHDL while burning was done using Spartan-2 kit.

ii

Chapter

1

GENERAL INTRODUCTION

1

Most embedded systems need to be self-reliant. It's not usually possible to wait for someone to reboot them if the software hangs. Some embedded designs, such as space probes, are simply not accessible to human operators. If their software ever hangs, such systems are permanently disabled. In other cases, the speed with which a human operator might reset the system would be too slow to meet the uptime requirements of the product. A watchdog timer is a piece of hardware that can be used to automatically detect software anomalies and reset the processor if any occur. Generally speaking, a watchdog timer is based on a counter that counts down

from

some

initial

value

to

zero.

counter's initial value and periodically restarts it. If

The

embedded

software

selects

the

the counter ever reaches zero before the

software restarts it, the software is presumed to be malfunctioning and the processor's reset signal is asserted. The processor (and the embedded software it’s running) will be restarted as if a human operator had cycled the power. The process of restarting the watchdog timer's counter is sometimes called "kicking the dog." The appropriate visual metaphor is that of a man being attacked by a vicious dog. If he keeps kicking the dog, it can't ever bite him. But he must keep kicking the dog at regular intervals to avoid a bite. Similarly, the software must restart the watchdog timer at a regular rate, or risk being restarted. Watchdog timers may also trigger control systems to move into a safety state, such as turning off motors, high-voltage electrical outputs, and other potentially dangerous subsystems until the fault is cleared. For example, a watchdog timer can be implemented with a x-bit counter in a system working with a clock signal of y MHz, therefore, the system will shut down if the timer is not reset in a period of seconds. Watch dog timers have got various important applications one of them being in ATMs which we have studied and designed in our project.

2

Chapter

VHDL

3

2

2.1 Introduction VHDL is a language for describing digital electronic systems. It arose out of the United States Government’s Very High Speed Integrated Circuits (VHSIC) program, initiated in 1980. In the course of this program, it became clear that there was a need for a standard language for describing the structure and function of integrated circuits (ICs). Hence the VHSIC Hardware Description Language (VHDL) was developed, and subsequently adopted as a standard by the Institute of Electrical and Electronic Engineers (IEEE) in the US.VHDL is designed to fill a number of needs in the design process. Firstly, it allows description of the structure of a design that is how it is decomposed into sub-designs, and how those sub-designs are interconnected. Secondly, it allows the specification of the function of designs using familiar programming language forms. Thirdly, as a result, it allows a design to be simulated before being manufactured, so that designers can quickly compare alternatives and test for correctness without the delay and expense of hardware prototyping. The purpose of this booklet is to give you a quick introduction to VHDL.This is done by informally describing the facilities provided by the language, and using examples to illustrate them. This booklet does not fully describe every aspect of the language. For such fine details, you should consult the IEEE Standard VHDL Language Reference Manual. However, be warned: the standard is like a legal document, and is very difficult to read unless you are already familiar with the language. This booklet does cover enough of the language for substantial model writing. It assumes you know how to write computer programs using a conventional programming language such as Pascal, C or Ada. The remaining chapters of this booklet describe the various aspects of VHDL in a bottom-up manner. Chapter2 describes the facilities of VHDL which most resemble normal sequential programming languages. These include data types, variables, expressions, sequential statements and subprograms. Then examines the facilities for describing the structure of a module and how it it decomposed into sub-modules. Then covers aspects of VHDL that integrate the programming language features with a discrete event timing model to allow simulation of behaviour. These facilities are combined to form a complete model of a system. Then there is a potpourri of more advanced features which you may find useful for modeling more complex systems. Throughout this booklet, the syntax of language features is presented in Backus-Naur Form (BNF). The syntax specifications are drawn from the IEEE VHDL Standard. Concrete examples are also given to illustrate the language features. In some cases, some alternatives are omitted from BNF productions where they are not directly relevant to the context. For this reason, the full syntax is included in Appendix A, and should be consulted as a reference. One should be attentive towards the following points: 1) The purpose of VHDL. 2) The overall structure of VHDL 3) The VHDL development and execution sequence 4) The VHDL simulation cycle 5) Basic VHDL object types and declarations 6) The syntax and semantics of basic VHDL sequential statements 7) The syntax and semantics of basic VHDL concurrent statements 8) VHDL modeling techniques for the simulation and evaluation of gate-level digital circuits. 4

Figure 1-1. Example of a structural description.

2.2 Describing Structure A digital electronic system can be described as a module with inputs and/or outputs. The electrical values on the outputs are some function of the values on the inputs. Figure1-1(a) shows an example of this view of a digital system. The module F has two inputs, A and B, and an output Y.Using VHDL terminology, we call the module F a design entity, and the inputs and outputs are called ports. One way of describing the function of a module is to describe how it is composed of sub-modules. Each of the sub-modules is an instance of some entity, and the ports of the instances are connected using signals Figure1-1(b) shows how the entity F might be composed of instances of entities G, H and I. This kind of description is called a structural description. Note that each of the entities G, H and I might also have a structural description.

5

2.3 Describing Behaviour In many cases, it is not appropriate to describe a module structurally. One such case is a module which is at the bottom of the hierarchy of some other structural description. For example, if you are designing a system using IC packages bought from an IC shop, you do not need to describe the internal structure of an IC. In such cases, a description of the function performed by the module is required, without reference to its actual internal structure. Such a description is called a functional or behavioral description. To illustrate this, suppose that the function of the entity F in Figure1-1(a) is the exclusive-or function. Then a behavioural description of F could be the Boolean function

More complex behaviours cannot be described purely as a function of inputs. In systems with feedback, the outputs are also a function of time. VHDL solves this problem by allowing description of behaviour in the form of an executable program.

2.3.1 Discrete Event Time Model Once the structure and behaviour of a module have been specified, it is possible to simulate the module by executing its behavioural description. This is done by simulating the passage of time in discrete steps. At some simulation time, a module input may be stimulated by changing the value on an input port. The module reacts by running the code of its behavioural description and scheduling new values to be placed on the signals connected to its output ports at some later simulated time. This is called scheduling a transaction on that signal. If the new value is different from the previous value on the signal, an event occurs, and other modules with input ports connected to the signal may be activated. The simulation starts with an initialization phase, and then proceeds by repeating a two-stage simulation cycle. In the initialization phase, all signals are given initial values, the simulation time is set to zero, and each module’s behaviour program is executed. This usually results in transactions being scheduled on output signals for some later time. In the first stage of a simulation cycle, the simulated time is advanced to the earliest time at which a transaction has been scheduled. All transactions scheduled for that time are executed, and this may cause events to occur on some signals. In the second stage, all 6

modules which react to events occurring in the first stage have their behaviour program executed. These programs will usually schedule further transactions on their output signals. When all of the behaviour programs have finished executing, the simulation cycle repeats. If there are no more scheduled transactions, the whole simulation is completed. The purpose of the simulation is to gather information about the changes in system state over time. This can be done by running the simulation under the control of a simulation monitor. The monitor allows signals and other state information to be viewed or stored in a trace file for later analysis. It may also allow interactive stepping of the simulation process, much like an interactive program debugger.

2.3.2 A Quick Example In this section we will look at a small example of a VHDL description of a two-bit counter to give you a feel for the language and how it is used. We start the description of an entity by specifying its external interface, which includes a description of its ports. So the counter might be defined as: entity count2 is generic (prop_delay: Time := 10 ns); port (clock : in bit; q1, q0 : out bit); end count2; This specifies that the entity count2 has one input and two outputs, all of which are bit values, that is, they can take on the values '0' or '1'. It also defines a generic constant called prop_delay which can be used to control the operation of the entity (in this case its propagation delay). If no value is

explicitly given for this value when the entity is used in a design, the default value of 10ns will be used. An implementation of the entity is described in an architecture body. There may be

7

more than one architecture body corresponding to a single entity specification, each of which describes a different view of the entity. Behavioural description of counter could be written as: architecture behaviour of count2 is begin count_up: process (clock) variable count_value : natural := 0; begin if clock = '1' then count_value := (count_value + 1) mod 4; q0 clock, q => ff0); inv : inverter port map (a => ff0, y => inv_ff0); bit_1 : t_flipflop port map (ck => inv_ff0, q => ff1); q0