SMTA Ohio Valley Chapter Advanced Packaging Technologies: Chip Scale, Embedded Chip and 3D Packaging Ray Fillion Fillion Consulting
[email protected] 518-810-1519
Chip Scale Packaging, Embedded Chip Packaging and 3D Packaging Presentation Outline Packaging Packaging Introduction Chip Scale Packaging Packaging Wafer Level Chip Scale Packaging Embedded Chip Packaging Packaging Embedded WLCSP Embedded Chip SiP/MCM Packaging 3D Packaging Summary
©Ray Fillion 2011
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Chip Scale Packaging, Embedded Chip Packaging and 3D Packaging Presentation Outline Packaging Packaging Introduction Chip Scale Packaging Packaging Wafer Level Chip Scale Packaging Embedded Chip Packaging Packaging Embedded WLCSP Embedded Chip SiP/MCM Packaging 3D Packaging Summary
©Ray Fillion 2011
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Functions of a Package? •
Signal Distribution: Minimize interconnect
inductance, resistance, crosstalk & delays: •
Power Delivery: Minimize rail inductance,
resistance, resistance, noise & ground bounce: •
Thermal Dissipation: Provide cooling paths:
•
Mechanical Protection: from damaging stress,
strain or shock: •
Environmental Protection: Provide a barrier to
moisture, liquids: •
I/O Pitch Reconfiguration: Transformation
from chip features to PCB compatible features: ©Ray Fillion 2011
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Background: Thru-Hole The first packages were Dual-in-Line packages (DIPs) that had leads on a 100 mil (2.5 mm) pitch, that were inserted into holes in a circuit board and soldered in place. The circuit board could be a simple single-sided or double-sided epoxyglass (FR-4) or a complex multilayer board with 4 or more layers. DIPs were limited to low I/O counts, typically 8 – 64 and the thru-holes limited PCB routing.
Ceramic DIP Dual-in-Line Package ©Ray Fillion 2011
Plastic DIP Dual-in-Line Package 4
Background: Surface Mount In the 1980’s, SMT was introduced with leaded and perimeter leadless surface mounted devices solder attached onto the surface of the circuit board. Lead pitch shrunk to 50 mils (1.25 mm) and later down to 25 (0.625 mm) and even 20 mils (0.50 mm) and I/O count increased to about 250, a 4x increase over DIPs. High pin count SMTs had fragile leads and low assembly yields.
TSOP- Thin Small Outline Packager
LQFP (0.5 mm) Leaded Quad Flat Package ©Ray Fillion 2011
LCC- Leadless Chip Carrier 5
Background: Ball Grid Array
IBM Cavity Down BGA In the 1990’s, Ball Grid Array (BGA) packages were introduced that utilized solder balls to connect an array pads on the package bottom surface to the board. Chips could be wire bonded or flip chip attached to the BGA carrier. Solder pads were on 1.5 mm and 1.25 mm grid arrays. This increased I/O capability by a factor of 5x to 10x permitting packages with 1000 to 2000 I/Os and had very high assembly yields. ©Ray Fillion 2011
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Chip Scale Packaging: A chip scale package is a packaged chip that is the same size as or no more than 40% larger than the chip itself.* Near Flip Chip Densities without Flip Chips Issues Packaged Part Robustness without the Size Penalties of a Packaged Part Supports Standard Pad Configurations, MultiSourcing and Lower Costs • •
•
The Ultimate in Small Packages * One of many different definitions for a CSP. ©Ray Fillion 2011
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Chip Scale Packaging Size Comparisons Leaded QFP BGA CSP
100%
35%
10%
Key Driving Forces Behind CSP: Footprint Area Reduction (10x) Package Thickness Reduction (3x) Package Costs (2x) • • •
Source: OKI
©Ray Fillion 2011
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Chip Scale Developments Chip scale packaging was developed as a means for assemblers to flip chip attach devices that were designed for wire bond assembly. •
Most off-the-shelf ICs (>>90%) are designed for wire bonding and not for flip chip solder bump attach. •
That means the I/O pads are distributed either on the perimeter of the chip or down the center of the chip. •
The pads are on tight pitches (50 to 100µm) and have Al metallurgy. •
Neither the pad pitch nor metallurgy support flip chip solder bump assembly. •
©Ray Fillion 2011
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Driving Forces Behind CSPs Size & Cost Driven: High Feature Content Portable Electronics •
Reduced device footprint: 40 – 80%
•
Improved power/ground delivery
•
Reduced interconnect losses: 20-40%
•
Lower EMI and EMS (for mixed logic, RF, analog)
Second source capability: CSPs from multiple suppliers are available with common pad-outs, permitting easy second sourcing. •
•
And most importantly, lower costs! ©Ray Fillion 2011
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Chip Scale Applications Value/ Complexity
Time Line
Chip Scale Packaging started out as a portable electronics packaging option for small, less complex chips and then moved to more complex logic devices were targeted. Source: T. Di Stefano
©Ray Fillion 2011
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Wire Bonded Chip Scale Packages Bare chips placed on an organic substrate, wire bonded and molded. Low investment costs: infrastructure, materials in place on PCB manufacturing lines. •
Low production costs: simple process, low cost material, large PCB panels. •
•
Small size: small footprint, low height.
Good electrical performance: better than standard chip carriers •
©Ray Fillion 2011
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Wire bonded Chip Scale Packaging
Chip Wire Bonded to a Thin, Single-Sided Flex Substrate, Over Molded with Backside BGA Solder Balls ©Ray Fillion 2011
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Chip Scale Packages Wire Bonded on Laminate
Chip Wire Bonded onto a Double-Sided Laminate Substrate, Over Molded with Back Side Solder Balls Source: ASE
©Ray Fillion 2011
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Fine Pitch BGA CSP Molding Compound
Wire Bond
Chip
Via Hole
Circuit Trace Solder Mask BT Resin Solder Ball
Chip Mounted onto a BT Resin Substrate, Wire Bonded and Molded. Higher I/O Count Devices Required More Complex and Costly Substrates. Source: NEC
©Ray Fillion 2011
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Wafer Level Chip Scale Packaging: Wafer Level CSPs Are the Fastest Growing Chip Scale Package Market Segment. •
WLSCPs replace assembly level processing steps and structures with BEOL wafer processing steps and structures. •
There is less handling and less material used and the resulting devices have minimized footprints and thickness’. •
©Ray Fillion 2011
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Wafer Level CSPs Processes Verses Conventional Packages QFP, BGA, Conventional CSP Wafer
Dicing
Packaging
Wafer Level CSP Wafer
Packaging
©Ray Fillion 2011
Dicing
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WLCSP & WLP Unit Volumes Forecasts
WLP MEMS WLP CMOS Imagers WLCSP Analog & RF WLCSP Wireless
Source: Electronics.CA Publications ©Ray Fillion 2011
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WLCSP Market Penetration WLCSP Penetration Rate Into Overall IC Packaging (in % Units) 8.3% 7.1%
4.8%
2008
6.1%
6.3%
2010
2011
5.4%
2009
2012
2013
WLCSP is the fastest growing packaging technology in the packaging industry today. Source: Yole
©Ray Fillion 2011
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WLCSP Array Ball Pitch Trends
0.3 mm 0.4 mm 0.5 mm
2008 • • •
2009
2010
2011
2012
I/O pitch reductions require finer/more costly PCBs. More costly PCB can be off-set by using smaller PCBs. Finer pitch WLCSP driven by higher I/O chips. Source: Yole
©Ray Fillion 2011
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Redistribution Layer (RDL) and Bump-onPad (BOP) WLCSP Technologies Bump-on-Pad (BOP) WLCSP processing keeps the pads where they are initially located and changes the pad metallurgy and the pad size to be compatible with solder bumps. •
Redistribution Layer (RDL) WLCSP processing at the BEOL wafer uses an interconnection layer to move the wire bond pads from their initial locations to an array of pads better suited to solder bumps. •
©Ray Fillion 2011
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Redistribution Layer (RDL) and Bump-on-Pad (BOP) WLCSP Technologies RDL and BOP use conventional BEOL wafer fabrication process steps. •
Both dielectric and metal processes, ie. deposition and patterning, are applied to the completed wafer. •
In most devices, the chip wire bond pads are redistributed to an area array of solder pads. •
UBM metallization is applied to the CSP I/O pads prior to the application of solder bumps. •
©Ray Fillion 2011
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Under Bump Metallurgy Solder ball attach requires the package I/O pads to have under bump metallization (UBM) such as Ni/Au to obtain a reliable solder joint. •
Solder ball pads must be large enough to support the solder ball, ~ 60% of the ball diameter. •
UBM is applied to expanded chip I/O pads on BOP approaches and on pads formed over the chip passivation on RDL approaches. •
On both BOP and RDL approaches, the chip surface is protected by at least one polymer coating. •
©Ray Fillion 2011
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Redistribution Layer Processing In most fine pitch wire bond devices, pads need to be spread out to increase pad pitch to support solder ball attach. •
Redistribution Layer (RDL) processing moves the chip I/Os from the peripheral (or center row) wire bond pads to an area array of pads. •
This redistribution technique improves chip reliability by providing for larger and more robust solder balls for next level assembly. •
©Ray Fillion 2011
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Redistribution Layer Processing A polymer dielectric such as polyimide or BCB, is applied over the wafer to passivate the surface. •
Vias are formed to the chip I/O pads by laser ablation, wet etch or photo-definition. •
A metallization layer, usually Cu, Au, or an alloy, is then deposited over this dielectric and onto the pads. •
The metal is patterned to form routing traces and array solder pads. •
A second dielectric layer is applied to passivate the non-pad metal (traces) and to form the solder mask. •
•
UMB is applied to the array pads.
•
Additional metal/polymer layers can be added. ©Ray Fillion 2011
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Solder Bump Polymer #2 Solder Mask UMB
Polymer #1 Passivation Si Wafer Al Pad
Typical Direct Bump or Bump-on-Pad •
Bump pad lies directly over wire bond pad.
•
Polymer applied to protect die surface.
•
Opening made to die I/O pad.
•
Metal applied to enlarged pad and provide UBM.
•
Second polymer dielectric can be applied. ©Ray Fillion 2011
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WLCSP Bump-on-Pad Process
Deposit and pattern BCB Passivation UBM Attach pre-formed solder spheres Sputter deposit UBM layers (Al/NiV/Cu)
Pattern UBM layers
Attach solder sphere by reflow
Single Metal Layer, Single Polymer Dielectric Layer Source: Flip Chip International
©Ray Fillion 2011
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Solder Bump Polymer #2 Solder Mask RDL Polymer #1
UMB
Passivation Si Wafer Al Pad
Typical Redistribution Layer Structure •
Bump pad lies over chip passivation.
•
Polymer applied and opened to die I/O pad.
•
Metal applied and patterned to form redistribution.
•
Second polymer applied and opened over bump pad.
Second metal is applied and patterned to form bump pad with UBM. •
©Ray Fillion 2011
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WLCSP Redistribution Process Chip Wire Bond Pad
Silicon
Chip Passivation
Coat, expose, pattern, cure first dielectric layer
Sputter and pattern etch redistribution layer (Ti/Al/Ti) to form routing traces
Coat, expose, pattern, cure second dielectric layer
Sputter deposit and pattern UBM layers (Al/NiV/Cu)
Two Metal Layers, Two Polymer Dielectric Layers Source : Flip Chip International
©Ray Fillion 2011
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WLCSP Redistribution, Bump-on-Polymer
Solder Ball Dielectric #1
BGA Pad Cu Dielectric #2
Chip Pad
Redistribution Metal (Ti/Al/Ti)
Chip Passivation
WLCSP Bump-on-Polymer Cross-Section Source: Flip Chip International
©Ray Fillion 2011
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Redistribution from Perimeter Pads to Area Array Solder Pads
Redistribution Layer Routing Examples ©Ray Fillion 2011
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WLCSP Redistribution, Bump-on-Polymer
Wafer Level CSP pad redistribution with up to four metal layers for complex, high I/O count chips
Source: Amkor
©Ray Fillion 2011
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WLCSP Redistribution, Bump-on-Polymer
Cross sectional view of a re-distributed solder bump using two layer BCB/CU RDL.
Source: MicroFab
Cross sectional view of a re-distributed solder bump using three layer BCB/CU RDL.
©Ray Fillion 2011
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WLCSP Redistribution, Bump-on-Polymer Center Pad to Array RDL
Close-up of Center Pad WLCSP showing solder balls, RDLs and Vias to Center Row Chip Pads Source: Micron
64 M DRAM WSCSP 68 bumps, 0.8mm pitch 34
Redistribution WLCSP Examples Source: ASE
Source: Infineon
Source: Oki ©Ray Fillion 2011
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