vlsi interview

1. General Digital Design Questions

1) Explain why & how a MOSFET works Ans: Inversion layer formed in the substrate connecting the source and drain when the gate voltage exceeds the threshold. Thus the device conducts and the conduction is controlled by the gate. 2) Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor width (c) considering Channel Length Modulation Ans: a) Ids is Quadratically proportional proportional to Vgs for a long channel MOSFET and linearly proportional to Vgs for a short channel MOSFET. Graph below shows Ids vs Vds for different Vgs for both short channel and long channel.

Vgs=1.2 Vgs=1.2

Vgs=0.8

Long channel

Vgs=0.8 Short Channel

b) With Increasing transistor width Ids increases. Ids W/L c) Even after the transistor reaches saturation region, Ids will slightly increase when Vds is changed. This is channel length modulation. 3) Explain the various MOSFET Capacitances & their significance Ans: The MOSFET capacitance varies depending depending upon the region region of operation of the transistor transistor 4) Draw a CMOS Inverter. Explain its transfer characteristics 5) Explain sizing of the inverter 6) How do you size NMOS and PMOS transistors to increase the threshold voltage? Short channel => vt decreases, long channel => vt increases. Narrow width effect  increases Vt. 7) What is Noise Margin? Explain the procedure to determine Noise Margin NMlow = VOL - VIL NMhigh = VIH - VOH Transfer characteristic of an inverter can be used to determine the noise margin

The p-device is in linear region and the n-device is in saturation. VIL is found by determining the unity gain point in the transfer characteristic where the output transitions from VOH. S imilarly, VIH is found by using the unity gain point at the VOL end of the characteristic. 8) Give the expression for CMOS switching power dissipation αCLVDDVswingf 

9) What is Body Effect? When the substrate of a NMOS or PMOS is not connected to the source, there exists a bias voltage Vsb across the source and substrate. 10) Describe the various effects of scaling Two types of scaling: 1) Constant Field Scaling => Voltages reduced to keep  E = V/L constant 2) Constant Voltage Scaling => Fields increase since L decreasing Look into this website for more details about scaling. He has given 3 pages of lecture. _   _  http://homepages.cae.wisc.edu/~ehoffman/ece555/l http://homepag es.cae.wisc.edu/~ehoffman/ece555/lectures/lecture2/lectur ectures/lecture2/lecture2.pdf  e2.pdf  11) Give the expression for calculating Delay in CMOS circuit

12) What happens to delay if you increase load capacitance? Delay increases given the VDD is the same…since it takes more time to charge and discharge the capacitor. 13) What happens to delay if we include a resistance at the output of a CMOS circuit? Delay increases T=RC. 14) What are the limitations in increasing the power supply to reduce delay? More power consumption 15) How does Resistance of the metal lines vary with increasing thickness and increasing length? 16) You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the center metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other 17) What happens if we increase the number of contacts or via from one metal layer to the next? More current, Resistance is reduced…improves electromigration 18) Draw a transistor level two input NAND gate. Explain its sizing (a) considering VTH(switching threshold) threshold) (b) for equal rise and fall times

19) Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output? 20) Draw the stick diagram of a NOR gate. Optimize it. 21) For CMOS logic, give the various techniques you know to minimize power consumption 22) What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus 23) Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter? 24) In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width? This is called legging or folding of devices…this gives a better aspect ratio for the layout and also by sharing the source and drains we could reduce the parasitic cap and improve the drive strength.

25) Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates) 26) Give the logic expression for an AOI gate. Draw its transistor level equivalent . Draw its stick  diagram sum of products and then inverter at the end 27) Why don't we use just one NMOS or PMOS transistor as a transmission gate?  Nmos doesn’t pass 1 well and pmos doesn’t pass 0 well..so Vt dro p….constant DC current and DC power consumption…

28) For an NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD 29) Draw a 6-T SRAM Cell and explain the Read and Write operations 30) Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)

It is used in memories for reading ..-> senses the change in voltage in the bit and bit_bar lines. 31) What happens if we use an Inverter instead of the Differential Sense Amplifier? For inverter-> the voltage has to go below threshold to detect a change in level. So it is very slow. Differential sense amplifier detects even a slight change so more fast in reading

32) Draw the SRAM Write Circuitry 33) Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

34) How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance? 35) What's the critical path in a SRAM? Memory cell 36) Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of  Clock signal? 37) Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers 38) In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why? I think the word line has to be in a higher metal layer because the signal has to propagate to all the bits of the word to read or write from/to the particular word…higher metal layers could be wider and carry more current.

39) How can you model a SRAM at RTL Level? 6-transistor cell 40) What’s the difference between Testing & Verification? Answer is in this website: http://www.vlsibank.com/ under EDA tools..I have copied then for you : 3 answers  Answer1:verification proves conformance with a specification. testing tries to find cases where the system does not meet its specification. the different kinds of verification are timing and f unctional verification, while timing verification is to verify or determine the longest delay path in a circuit to optimize performance and to make sure that the clock cycles are correct. Functional verification is to compare symbolic descriptions of circuit functionality with the derived behavior of the individual parts of the circuit, also described symbolically. In each case a specification is given (time delays or behavior) and the checker ensures that the rules are met. Answer2: I think testing is post-fabrication and is used to detect bad chips. While verification is pre-fabrication and is used to make sure the design is correct and meets the specs. Answer3: verification is verifying functionality of design whether it is working as intended.This should done before syntheizing phase.

Testing is technology dependent this should done after generating netlist. here going verify each gates in the design,it is working properly r not. 41) For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

42) What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up? ……..done ans) more sub contacts, STI, epilayer  Digital Design:

1) Give two ways of converting a two input NAND gate to an inverter …….done ans) short the 2 inputs or connect one input to VDD. 2) Given a circuit, draw its exact timing response. (I was given a Pseudo Random Signal Generator; you can expect any sequential ckt) 3) What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit? ……done 4) Give a circuit to divide frequency of clock cycle by two …D flip flop…connect the Q_bar to D input.. 5) Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the Clock) ….done 6) Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can't resize the combinational circuit transistors) …done either delay the clock to the second clock by intentionally adding skew or increase the clock  period…look at the answer below. 7) The answer to the above question is breaking the combinational circuit and pipelining it. What will be affected if you do this? …done Throughput is increased, delay is also increased. 8) What are the different Adder circuits you studied? RCA, CLA, carry select adder…carry save adder… 9) Give the truth table for a Half Adder. Give a gate level implementation of the same. …done 10) Draw a Transmission Gate-based D-Latch …..done

Two T-gates in series. D is the input of the first T-gate and Q is the o/p of the second T-gate 11) Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? (Without inverting the output) …done B

A B_bar

AxorB

To change to XNOR just interchange the B and B-Bar inputs 12) How do you detect if two 8-bit signals are same? ...XNOR and AND …we should get a 1… done 13) How do you detect a sequence of "1101" arriving serially from a signal line? ……..done 14) Design any FSM in VHDL or Verilog.

Computer Architecture:

1) What is pipelining?...done 2) What are the five stages in a DLX pipeline?..done 3) For a pipeline with 'n' stages, what’s the ideal throughput? What prevents us from achieving this ideal throughput?....throuput=1 …bubbles prevent….due to data, control and structural hazards….done

4) What are the different hazards? How do you avoid them?...done 5) Instead of just 5-8 pipe stages why not have, say, a pipeline with 50 pipe stages?....done…branch prediction , data forwarding paths become very long 6) What is Branch Prediction and Branch Target Buffers?...done 7) How do you handle precise exceptions or interrupts?...done

8) What is a cache?...done 9) What's the difference between Write-Through and Write-Back Caches? Explain advantages and disadvantages of each …..done Write-Through : whenever a value is updated in ca che, it is written back into the memory. Advantage: Coherency is maintained easily Disadvantage: High bandwidth reqd for memory Write-Back: Memory writing is done only when the cache location which is to be copied is updated with another value. Advantage: Less Bandwidth  – faster also Disadvantage: Cache coherency problem in multi-processors 10) Cache Size is 64KB, Block size is 32B and the cache is Two-Way Set Associative. For a 32bit physical address, give the division between Block Offset, Index and Tag ….done 11) What is Virtual Memory?....done 12) What is Cache Coherency?...done A protocol for managing the caches of a multiprocessor system so that no data is lost or overwritten before the data is transferred from a cache to the target memory 13) What is MESI? Processors providing cache coherence commonly implement a MESI protocol - where the letters of the acronym represent the four states that a cache line may be in: Invalid This cache line is not valid Exclusive This cache has the only copy of the data. The memory is valid. Shared More than one cache is holding a copy of this line. The memory copy is valid. Modified The line has been modified. The memory copy is invalid. This shud be enuf, but if more details needed see: http://ciips.ee.uwa.edu.au/~morris/CA406/cache_coh.html 14) What is a Snooping cache?...done Snooping -> A technique used in multi processors for maintaining cache coherency. When any variable is updated in a particular processor’s cache, there are 2 ways it can be updated in the other processors : 1. Write invalidate: Invalidate the caches of all other processors for the particular block and then when there is a read or write request, it will result in a miss and will be directed to the main memory.

2. Write update: Broadcast the new changed data to all caches as soon as it is changed along with the write update signal. 15) What are the components in a Microprocessor?...done 16) What is ACBF(Hex) divided by 16?convert to decimal and then divide …done 17) Convert 65(Hex) to Binary ….1100101..octal is groups of 3 and hex is groups of 4… 18) Convert a number to its two's complement and back ….done 19) The CPU is busy but you want to stop and do some other task. How do you do it?..done 2.Hitequest.com  Two capacitors are connected in parallel through a switch. C1= 1uF, C2= 0.25uF. Initially switch is open,C1 is charged to 10V. What happens if we close the switch? No loss in the wires and capacitors.

8uC and 2uC

Hint from Hitequest  You have 2 switches to control the light in the long corridor. You want to be able to turn the light on entering the corridor and turn it off at the other end. Do the wiring circuit.

Hint from Hitequest  This question is based on the previous one, but there are 3 switches that can turn on and off a light in the room. How to wire them up?

hint

Hint from Hitequest

 What will be the voltage level between the 2 capacitors? The Vcc = 10v DC. Sent by Tanh, VLSI engineer 

Hint from Hitequest  Suppose, you work on a specification for a system with some digital parameters. Each parameter has Min,Typ and Max colomns. In what column would you put a Setup time and a Hold time?

Hint from Hitequest 

Design a simple circuit based on combinational logic to double the output frequency.

Hint from Hitequest  8bit ADC with parallel output converts input signal into digital numbers. You have to come up with the idea of a circuit , that finds MAX of every 10 numbers at the output of the ADC.

Hint from Hitequest  Implement comparator that compares two 2-bit numbers A and B. The comparator should have 3 outputs: A > B, A < B, A = B. Do it two ways: - using combinational logic; - using multiplexers. Write HDL code for your schematic at RTL and gate level.

Hint from Hitequest  A small computer has an 8 bit CPU and only one register. XOR - is the only assembly command it understands. How to set a second bit of the register ? The initial state of the register is unknown.

Hint from Hitequest  You have 8 bit ADC clocking data out every 1mS. Design a system that will sort the output data and keep a statistics how often each binary number appears at the output of ADC.

Hint from Hitequest  What types of flip-flops do you know?

Hint from Hitequest  Implement D- latch from - RS flip flop; - multiplexer.

Hint from Hitequest  How to convert D-latch into JK-latch and JK-latch into D-latch?

Hint from Hitequest  You have two counters to 16, built from negedge D- FF . First circuit is synchronous and second is "ripple" (cascading). Which circuit has a less propagation delay?

Hint from Hitequest  What is the difference between flip-flop and latch? Write an HDL code for their behavioral models.

Hint from Hitequest  Describe the oper  ation of DAC? What are the most important parameters of DAC? Do we really need both INL and DNL to estimate linearity?

Hint from Hitequest

 Compare briefly all types of ADC,that you know .

Hint from Hitequest  How will the output signal of an ideal integrator look like after - a positive pulse is applied to the input; - a series of 10 positive pulses ?

Hint from Hitequest  how to design a divide-by-3 counter with equal duty cycle ? question from abc.

Hint from Hitequest  For an 8-bit flash A/D converter with an input range f rom 0V to 2.55V, describe what happens when the input voltage changes from 1.27V to 1.28V  Your system has 2 memory cells and ALU. The ALU can only perform XOR operation. How to swap the contence of the memory cells ? …xor a and b…xor the result with a and store in a…xor the result with b and store in b.  I swapped 2 transistors in CMOS inverter (put n-transistor at the top and p-transistor at the bottom). Can this circuit work as a noninverting buffer? (By E.Martovetsky,design eng from Transmeta)

Hint from Hitequest  Convert D-latch into divider by 2. What is the max clock frequency the circuit can handle ? T_setup= 6nS T_hold = 2nS T_propagation = 10nS

Hint from Hitequest  The circle can rotate clockwise and back. Use minimum hardware to build a circuit to indicate the direction of rotating.

Hint from Hitequest

 For ATE engineers (semiconductor test): Draw a shmoo plot of two parameters: Clock period Tclk and setup time Tsetup.

 For chip design/test/product engineers : An IC device draws higher current when temperature gets: - higher - lower

Hint from Hitequest

 To enter the office people have to pass through the corridor. Once someone gets into the office the light turns on. It goes off when noone is present in the room. There are two registration sensors in the corridor. Build a state machine diagram and design a circuit to control the light.

 A voltage source with internal impedance Z_source = 50 OHm is connected to a transmission line with Z = 50 OHm. Z_load is also 50 OHm. The voltage source generates a single voltage step 1V. What will be the voltage level on the load:

a) 2V , because the reflected signal will be in-phase with the incident signal; b) 0.33V , because the voltage is devided between Z_source , Z_load and Z_transm.line; c) 0.5V , because the voltage is devided between Z_source and Z_load.

Hint from Hitequest

 Draw a transistor schematic of NOR gate,it's layout and a cross section of the layout. This question is quite popular.

 The silicon of a new device has memory leak. When all "0" are written into RAM, it reads back all "0" whithout any problem. When all "1" are written, only 80% of memory cells are read back correctly. What can be possibly the problem with the RAM? Michael Altshuler, product engineer.

 Draw a CMOS inverter. Why does CMOS technology dominate in VLSI manufacturing? Leon Backer, DFT engineer

 Design a FIFO 1 byte wide and 13 words deep. The FIFO is interfacing 2 blocks with different clocks. On the rising edge of  clk the FIFO stores data and increments wptr. On the rising edge of  clkb the data is put on the b-output,the rptr points to the next data to be read. If the FIFO is empty, the b-output data is not valid. When the FIFO is full the existing data should not be overriden. When rst_N is asserted, the FIFO pointers are asynchronously reset. module fifo1 (full,empty,clk,clkb,ain,bout,rst_N) output [7:0] bout; input [7:0] ain; input clk,clkb,rst_N; output empty, full; reg [3:0] wptr, rptr; ...

endmodule

Hint from Hitequest

 What does CMOS stand for? VLSI? ASIC? This was in the series of quick questions in the interview at Analog Devices. We use these abbreviations daily, but not everyone remembers what they stand for.

Hint from Hitequest

 Design a COMBINATIONAL circuit that can divide the clock fr equency by 2.

 Design a 2bit up/down counter with clear using gates. (No verilog or vhdl)

 We have a circular wheel with half painted black and the other half painted white. There are 2 censors mounted 45 degree apart at the surface of this wheel (not touching the wheel) which give a "1" for black and "0" for white passing under them. Design a circuit to detect which way the wheel is moving. Can not assume any fixed position for start.

 We have a fifo which clocks data in at 100mhz and clocks data out at 80MHz. On the input there is only 80 data in any order during each 100 clocks. In other words, a 100 input clock will carry only 80 data and the other twenty clocks carry no data (data is scattered in any order). How big the fifo needs to be to avoid data over/under-run.

Hint from Hitequest

 Instead of specifying SETUP and HOLD time, can we just specify a SETUP time for '1' and a SETUP time for '0'?

 Here some hardware digital design specific questions, offered by Suhas: (1) When will you use a latch and a flipflop in a sequential design? (2) Design a 1-bit fulladder using a decoder and 2 "or" gates? (3) You have a circuit operating at 20 MHz and 5 volt supply. What would you do to reduce the power consumption in the circuit- reduce the operating frequency of 20Mhz or reduce the power supply of 5Volts and why? (4) In a nmos transistor, how does the current flows from drain to source in saturation region

when the channel is pinched off? (5) In a SRAM circuit, how do you design the precharge and how do you size it? (6) In a PLL, what elements(like XOR gates or Flipflops) can be used to design the phase detector? (7) While synthesis of a design using synopsys design compiler, why do you specify input and output delays? (8) What difference do you see in the timing reports for a propogated clock and an ideal clock? (9) What is timeborrowing related to Static timing anaylsis in P rimetime?

3.Verilog questions

VERIFICATION:

1. Difference between $display and $monitor and $write. $display displays variable values using specified format. Also prints new line.  $monitor display variable only on change in value.  $write behaves the same as $display. Only difference is it does not print new line.  2. Difference between compiled code and normal simulator. A compiled code simulator compiles all the files(design and verification) and writes out an executable(similar to a.out, for people familiar with C language). The engineer then needs to run this executable in order to perform the simulation. This simulator will speed up the simulation since it need not compile each and every file for every simulation run. It will detect the files that are modified and compile those files and files that depend on those modified files. A normal simulator performs compilation and execution in the s ame step. So it has to compile each and every file whenever a simulation is performed. 3. How do you ensure data integrity? Three most popular ways to ensure data integrity in a system are a) Parity b) CRC(Cyclic Redundancy Check) c) ECC(Error Correcting Code) Parity is calculated by doing a XOR on all the bits in the data or the address bus. On the sending side(or source side) parity is generated and transmitted. On the receiving side(or sink side) parity is received and checked. If there is any error in the transmission, it is detected on the r eceive side. If more than one bit is flipped during transmission, Parity may not detect the error. In such systems we use CRC or ECC. CRC is implemented using a pre-designed mathematical polynomial. CRC has a very good probability of detecting all kinds of errors during transmission. So it is more powerful than using Parity. Both Parity and CRC can only detect the error. They cannot correct the error. If error correction feature is necessary, then ECC needs to be used. ECC can also be implemented by ASIC designer. This method of data integrity can detect and CORRECT errors. There are many types of ECC. You need to pick a method depending on the level of data integrity your system needs. VERILOG:

1. Wire and register.Differences. A register is used when you want to store information in one clock cycle and access that same information in the next clock cycle. A wire is used for connectivity.

2. Blocking and Non-blocking assignments* Case I: Blocking Procedural Assignments Initial begin #1 a=b; #1 c=d; #1 e=f; end In this case, as soon as the initial block is entered, we wait for 1time unit and then sample the value of b and assign that value of b to a. Then wait for 1 more time unit, sample the value of d and assign that value of d to c and so on. Case II: Blocking Intra-procedural assignment Initial begin a= #1 b; c= #1 d; e= #1 f; end In this case, as soon as the initial block is entered, we sample the value of b, then wait for 1 time unit and assign that value of b to a. Then sample the value of d, wait for 1 more time unit, and assign that value of d to c and so on. Case III: Non-Blocking procedural assignment Initial begin #1 a