VLSI Design Notes
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A Course on
Design of Digital VLSI Systems & Circuits
By Pragnan Chakravorty Associate Professor & H O D (E&TC) CIET Raipur Associate Professor & H.O.D (E&TC),CIET, Raipur M.Tech (IIT Kharagpur), MIEEE Member IEEE(USA) :‐ Communication. Soc, Microwave Theory and Techniques Soc, Antenna & Wave Propagation. Soc Antenna & Wave Propagation. Soc IEEE Standards Soc.
INTRODUCTION TO INTEGRATED CIRCUITS
How is a VLSI Circuit Different? Unlike conventional electronic circuits, Transistors in a VLSI/ Integrated Circuits are carved / sculpted, sculpted over a single‐wafer (Monolith) of semiconductor, semiconductor almost concatenated so as to reduce the lengths of interconnects. The interconnects are made as the final layer of fabrication known as metallization layer. Metallizations are now done using polysilicon. The ability to manipulate the area/volume occupied by the carved transistors and the interconnects between them renders a tremendous scope of device miniaturization /scaling and a very large scale integration over a small space.
SSI, MSI, LSI,VLSI,ULSI: There has been a tremendous rise in the number of devices integrated into a single chip (conventionally 10mm x 10mm area chip) in the past few decades as a result the scale of device integration has been categorized as follows: Device Integration Table: S.No
Number of D i Devices
Small Scale Integration (SSI)
05 ‐to‐ 20
Medium Scale Integration (MSI)
20 ‐to‐ 200
Large Scale Integration (LSI)
200 ‐to‐ 2000
Very Large Scale Integration (VLSI)
2000 ‐to‐ 20000
Ultra Large Scale Integration (ULSI) 1989
20000 ‐to‐ ?
Moor’s Law: In 1965, a Caltech Professor, Gordon Moore observed that plotting the number of transistors that can be most economically manufactured on a chip gives a straight line on a semi logarithmic scale. At the time, he found transistor count doubling every 18 months. This observation has been called Moore’s Law and has become a self‐fulfilling prophecy
Moor’s graph compared with actuality
Date of Introduction
Advantages of High Scale Integration/Device Miniaturization: The most important p message g here is that the logic g complexity p yp per chip p has been (and still is) increasing exponentially. The monolithic integration of a large number of functions on a single chip usually provides: Less area/volume and therefore, compactness Less power consumption Less testing requirements at system level Higher reliability, reliability mainly due to improved on‐chip on chip interconnects Higher speed, due to significantly reduced interconnection length Significant cost savings due to batch processing g yyield due to batch p processingg Lesser fabrication error //Higher
VLSI Design Flow A VLSI system is a multi domain system where designs need to be carried out from b h i l levels behavioral l l to t physical h i l layout l t levels. l l With in i each h domain d i the th design d i can be b categorized into certain levels of abstraction and then the designs need to follow certain hierarchically categorized steps. Domains of Design: Domains are different distinct categories over which any engineering system spans. There can be three such major domains stated below: Behavioral domain: Which describes the behavior of the system for example the transmitting behavior of a transmitter system. Structural domain: Which describes the structure of the system for example where and how are the various amplifiers ,oscillators, filters etc are structured in the transmitter system. Geometrical layout domain. Describe the physical layout or placement of different components or devices in a system for example the placement and connections b t between various transistors , RLCs, in amplifiers oscillators filters etc. i t it RLC i lifi ill t filt t
Generalized Design Flow
The Y Chart The Y‐chart (first introduced by D. Gajski) shown in Fig. illustrates a design flow for mostt logic l i chips, hi using i design d i activities ti iti on three th diff different t axes (domains) (d i ) which hi h resemble the letter Y.
Levels of Abstraction Domains can further be hierarchically divided into different levels of design abstraction. Classically, these have included the following b t ti Cl i ll th h i l d d th f ll i for digital chips: Architectural or functional level Logic or Register Transfer Level (RTL) Logic or Register Transfer Level (RTL) Circuit level The relationship between description domains and levels of abstraction is elegantly shown by the Gajski Gajski‐Kuhn Kuhn Y chart in Figure. In this diagram, the three radial lines represent the behavioral, structural, and p physical y domains. The annular regions between concentric circles show different levels of abstraction.
Design Hierarchy The levels of abstraction are generic divisions which can map designs of one domain i t another. into th D Domain i specific ifi divisions di i i off the th levels l l off abstractions b t ti are called ll d hierarchical divisions. The hierarchical design approach reduces the design complexity by dividing the large system into several sub‐modules
Hierarchical divisions in structural domain of a 4‐bit adder
Concepts of Regularity, Modularity and Locality Though the design complexity reduces down with hierarchical sub‐modules, such sub b module d l themselves th l mustt have h some consonance and d integrity i t it with ith each h other th so as to further simplify the design process and make them effective. Such consonance between the sub‐modules are brought in by the following concepts: Regularity: Regularity is the division of the hierarchy into a set of similar building blocks (modules/sub‐modules). Regularity can exist at all levels of the design hierarchy. At the circuit level, uniformly sized transistors can be used, while at the gate level, a finite library of fixed‐height, variable‐length logic gates can be used Modularity: Modularity states that modules/sub‐modules have well‐defined functions and interfaces. If modules/sub‐modules are “well‐formed,” the interaction with other modules/sub‐modules can be well characterized. Locality: Locality is the localized composition of components with in a module/sub‐ module so that they do not interact with other modules/sub‐modules. Therefore internals of a module/sub‐modules are unimportant to other modules/sub‐modules. S external So, t l interfaces i t f d nott affect do ff t internal i t l interfaces i t f and d visa‐versa. i
VLSI Design Styles/Methods The VLSI design styles or methods depend upon the target IC platform or standard. Depending p g upon p the IC standards the design g style y varyy and have p platform specific p limitations and flexibility or advantages and disadvantages.
Overview VLSI Design Styles/ Standards/Platforms
Complex Programmable Logic Device(CPLD) CPLD is a single device with multiple simple programmable logic devices(SPLDs) such as Programmable P bl Array A L i (PLA) or Generic Logic G i Array A L i (GLA). Logic (GLA) PALs PAL and d GALs GAL are based on sum of products (SOP) architecture with a programmable AND array and a fixed OR array PLA/GLA CKT View
PLA/GLA Block Diagram
CPLD Block Diagram
Field Programmable Gate Array (FPGA) Design A typical field programmable gate array (FPGA) chip consists of I/O buffers, an array of configurable logic blocks (CLBs), (CLBs) and programmable interconnect structures. structures The programming of the interconnects is implemented by programming of RAM cells whose output terminals are connected to the gates of MOS pass transistors. General and detailed blocks of an FPGA are shown below.
The LUT is a di i l digital memory that stores the truth table of the Boolean function. XILINX Model XC2000
Configurable Logic Block (CLB): A simple CLB (model XC2000 from XILINX) is shown above where it consists of four signal input terminals (A, B, C, D), a clock signal terminal user‐programmable multiplexers, terminal, multiplexers an SR‐latch, SR‐latch and a look‐up table (LUT). (LUT) The LUT is a digital memory that stores the truth table of the Boolean function. It can generate any function of up to four variables or any two functions of three variables
Gate Array/ Sea of Gates Design While the design implementation of the FPGA chip is done with user programming, that of the gate array is done with metal mask design and processing. Gate array implementation requires a two‐step manufacturing process: The first phase, which is based on generic (standard) masks, results in an array of uncommitted transistors on each GA chip. These uncommitted chips can be stored for later customization, which is completed by defining the metal interconnects between the transistors of the array
Standard Cell Based Design In this design style, all of the commonly used logic cells are developed, characterized, and stored in a standard cell library. y A typical yp libraryy mayy contain a few hundred cells including inverters, NAND gates, NOR gates, complex AOI, OAI gates, D‐latches, and flip‐flops. It is almost a full custom design but for the predesigned cells which can’t be customized.
Full Custom Design In full custom design the customization starts at transistor level itself. Therefore different cells can be customized and optimized according to the various design specifications and constraints. Full custom designs are usually prevalent with analog designs and not digital.
General Purpose IC & ASSP System Design System y level digital g designs g are often p practicallyy done byy p programming g g ggeneral purpose ICs. These general purpose ICs are programmed using high level languages and are different from the ASICs described so far. These ICs include various microprocessors microcontrollers, MIPS , RISC and SISC processors. Application Specific System Processors(ASSPs) are also a kind of dedicated general purpose processors such as DSP processors which are programmed using high level languages.
DESIGN & FABRICATION ASPECTS of Standard Cell Based Design Style
Basic Steps of Fabrication Process Each processing step requires that certain areas are defined on chip by appropriate masks. Consequently, the integrated circuit may be viewed as a set of patterned layers of doped silicon, polysilicon, metal and insulating silicon dioxide. In general, l a layer l mustt be b patterned tt d before b f th nextt the layer of material is applied on chip. The process used to transfer a pattern to a layer on the chip is called lithography/Photolithography. g p y/ g p y Since each layer has its own distinct patterning requirements, the lithographic sequence must be repeated for every layer, using a different mask Figure at the right shows simplified process sequence for fabrication of the n‐well CMOS integrated circuit with a single polysilicon layer, showing only major fabrication steps.
Lithographic Steps of Patterning
Set of Masks for Patterning The cross‐section view is of an inverter
In a CMOS circuit fabrication, the h hypothetical h l set off six masks: k n‐ well, polysilicon, n+ diffusion, p+ diffusion, contacts, and metal. Masks specify p y where the components will be manufactured on the chip. Figure shows a top view of the six masks.
Different Development Stages in CMOS Fabrication
Fabrication of NMOSFET & PMOSFET
Fabrication of N Well Laying out interconnects and thick insulating oxides
2D & 3D Representations of NMOS & PMOS in CMOS Process
Layout Design Rules The physical mask layout of any circuit to be manufactured using a particular process must conform to a set of ggeometric constraints or rules,, which are ggenerallyy called layout design rules. These rules usually specify the minimum allowable line widths for physical objects on‐chip such as metal and polysilicon interconnects or diffusion areas, minimum feature dimensions, and minimum allowable separations between two such features. The main objective of design rules is to achieve a high overall yield and reliability while using the smallest possible silicon area, for any circuit to be manufactured with a particular process. The design rules are usually described in two ways : •Micron rules: in which the layout constraints such as minimum feature sizes and minimum allowable feature separations, are stated in terms of absolute dimensions in micrometers, or, •Lambda rules: These rules specify the layout constraints in terms of a single parameter λ (which is generally half the channel length and equal to the thickness of polysilicon p y layer) y ) and,, thus,, allow linear,, p proportional p scalingg of all ggeometrical constraints. The design rules are usually given by Metal Oxide Silicon Implementation Service (MOSIS‐ established in 1981).
Basic Lambda Design Rules
Sti k Di Stick Diagram As layout is time‐consuming, designers need fast ways to plan cells and estimate area before committing to a full layout. Stick diagrams are easy to draw because they do not need to be drawn to scale. scale It is easy to estimate the area of a layout from the corresponding stick diagram even though the diagram is not to scale. As an example stick diagrams of an inverter and 3 I/P NAND gate are shown below
MOSIS Design Rule (Sample Set) Rule number R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20
Description Minimum active area width Mi i Minimum active area spacing ti i Minimum poly width Minimum poly spacing Minimum gate extension of poly over active Mi i Minimum poly‐active edge spacing l ti d i (poly outside active area) Minimum poly‐active edge spacing (poly inside active area) Mi i Minimum metal width t l idth Minimum metal spacing Poly contact size Minimum poly contact spacing Minim m pol contact to pol ed e spacin Minimum poly contact to poly edge spacing Minimum poly contact to metal edge spacing Minimum poly contact to active edge spacing Active contact size Minimum active contact spacing Minimum active contact spacing (on the same active region) Minimum active contact to active edge spacing Minimum active contact to metal edge spacing Minimum active contact to poly edge spacing Minimum active contact to poly edge spacing Minimum active contact spacing (on different active regions)
L‐Rule 3 L 3L 3 L 2 L 2 L 2 L 1L 1 L 3 L 3 LL 3 3 L 2 L 2 L 1L 1 L 1 L 3 L 2 L 2L 2 L 1 L 1 L 3L 3 L 6 L
Illustration of some of the typical MOSIS layout design rules listed above
NMOS & PMOS Transistors as Switches( Binary Logic Generators)
An NMOS transistor is built with a p p‐type type body and has regions of n n‐type type semiconductor adjacent to the gate called the source and drain. They are physically equivalent and for now we will regard them as interchangeable. The body is typically ggrounded. A PMOS transistor is jjust the opposite, pp consistingg of p p‐type yp source and drain regions with an n‐type body. In a CMOS technology with both flavors of transistors, the substrate is either n‐type or p‐type. The other flavor of transistor must be built in a special well in which dopant atoms have been added to form the body of the opposite type.
Transistor in OFF state Considering NMOS transistor, the body is generally grounded so the p–n junctions of the source and drain to body are reverse‐biased. If the gate is also grounded, no current flows through the reverse‐biased junctions. Hence, we say the transistor is OFF. Just the opposite happens with PMOS transistors. Transistor in ON state When the gate voltage is raised, it creates an electric field that starts to attract free electrons to the underside of the Si–SiO2 interface. If the voltage is raised enough, the electrons outnumber the holes and a thin region under the gate called the channel h l is i inverted i d to act as an n‐type semiconductor. i d Hence, a conducting d i path h off electron carriers is formed from source to drain and current can flow. We say the transistor is ON. Similarly in case of PMOS the conditions are reversed
MOS Transistors as Switches
Layout Examples: CMOS Inverter
Circuit Diagram Layout Diagram
Circuit Diagram Layout Diagram
Calculation of Capacitances & Resistances Capacitances and resistances are the most vital factors governing the performance of a digital VLSI circuit. circuit Perhaps the most significant aspect of a digital circuit is its speed of operation which can be determined through delay calculations. Resistances and capacitances in an IC form ‘RC’ pairs and cause various delays in the signal flow. Resistances and capacitances in ICs can be categorized into two: Intrinsic RCs: Those resistances and capacitances which occur inside the transistors Extrinsic RCs: The resistances and capacitances which occur outside the transistors. i.e. those which are contributed from the interconnects. Resistance & Capacitance Calculation through RC Delay Model Effective resistance in transistors: A unit NMOS transistor is defined to have effective resistance R. The size of the unit transistor is arbitrary but conventionally refers to a transistor with minimum length and minimum contacted diffusion width (i.e., (i e 4/2λ). 4/2λ) Alternatively, Alternatively it may refer to the width of the NMOS transistor in a minimum‐sized inverter in a standard cell library. An NMOS transistor of k times unit width has resistance R/k because it delivers k times as much current. current A unit PMOS transistor has greater resistance, resistance generally in the range of 2R because of its lower mobility. R is typically on the order of 10 kΩ for a unit transistor.
Effective capacitance in transistors: Each transistor also has gate and diffusion capacitance. We define C to be the gate capacitance of a unit transistor of either flavor. A transistor of k times unit width has capacitance kC. kC Diffusion capacitance depends on the size of the source/drain region. region Using the approximations we assume the contacted source or drain of a unit transistor to also have capacitance of about C. Wider transistors have proportionally greater diffusion capacitance. Increasing channel length increases gate capacitance proportionally but does not affect diffusion capacitance. Although capacitances have a nonlinear voltage dependence, we use a single average value. We roughly estimate C for a minimum length transistor to be 1 fF/micron of width. In a 65 nm process with a unit transistor being 0.1 micron wide, wide C is thus about 0.1 0 1 fF. fF
Equivalent RC Circuit Representations
Equivalent Circuit for an Inverter
Generalized model for MOSFET capacitances: The capacitances associated with a MOSFET are shown in Fig as lumped elements between the device terminals. Based on their physical origins, the device capacitances can be classified into two major groups: (1) oxide‐related oxide related capacitances and (2) junction capacitances. The gate‐oxide‐related capacitances are Cgd (gate‐to‐drain capacitance), Cgs (gate‐to‐source capacitance), and Cgb (gate‐to‐substrate capacitance). Notice that in reality, the gate‐to‐channel capacitance is distributed and voltage dependent. Consequently, all of the oxide‐related capacitances described here change with the bias conditions of the transistor.
Effective resistance in interconnects: The resistance of a metal or polysilicon line also have a profound influence on the signal propagation delay over that line. The resistance of a line depends on the type of material used (polysilicon aluminum, (polysilicon, aluminum gold, gold ...), ) the dimensions of the line and finally, finally the number and locations of the contacts on that line. Consider the interconnection line shown in Fig. The total resistance in the indicated current direction can be found as
Where ρ represents the characteristic resistivity of the interconnect material, and Rsheet represents the sheet resistivity of the line, in (ohm/square). For a typical polysilicon layer, the sheet resistivity is between 20‐40 ohm/square, whereas the sheet resistivity of silicide is about 2 4 ohm/square. 2‐ ohm/square Using the formula given above, above we can estimate the total parasitic resistance of a wire segment based on its geometry. Typical metal‐poly and metal‐diffusion contact resistance values are between 20‐30 ohms, while typical via resistance is about 0.3 ohms.
Effective capacitance in interconnects: A set of simple formulas developed by Yuan and Trick in the early 1980’s can be used to estimate the capacitance of the interconnect structures in which fringing fields complicate the effective capacitance calculation. calculation The following two cases are considered for two different ranges of line width (w).
These formulas permit the accurate approximation of the parasitic capacitance values to within 10% error, even for very small values of (t/h).
Power Dissipation Static CMOS gates are very power‐efficient because they dissipate nearly zero power while idle. For much of the history of CMOS design, power was a secondary consideration behind speed and area for many chips. As transistor counts and clock frequencies have increased, power consumption has skyrocketed and now is a primary design constraint. constraint We begin by reviewing some definitions. The instantaneous power P(t) drawn from the power supply is proportional to the supply current iDD(t) and the supply voltage VDD
The energy consumed over some time interval T is the integral of the instantaneous power
Static Power Dissipation Considering the static CMOS inverter shown in Figure 4.26, 4 26 if the input = '0 0,' the associated nMOS transistor is OFF and the pMOS transistor is ON. The output voltage is VDD or logic '1.'When the input = '1,' the associated nMOS transistor is ON and the pMOS transistor is OFF. The output voltage is 0 volts (GND). Note that one of the transistors is always OFF when the gate is in either of these logic states. Ideally, no current flows through the OFF transistor so the power dissipation is zero when the circuit is quiescent, i.e., when no transistors are switching. Zero quiescent power dissipation is a principle advantage of CMOS over competing transistor technologies. However, secondary effects including sub threshold conduction, tunneling, and leakage lead to small amounts of static current flowing through the OFF transistor. Assuming the leakage current is constant so instantaneous and average power are the same, the static power dissipation is the evaluation product of total leakage current and the supply voltage.
Dynamic Power Dissipation
Combinational & Sequential Logic Design With VHDL With VHDL
What is VHDL? VHDL is an acronym for VHSlC Hardware Description Language (VHSIC is an acronym for Very High Speed Integrated Circuits). Circuits) It is a hardware description language that can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the gate level. The complexity of the digital system being modeled could vary from that of a simple gate to a complete digital electronic system, or anything in between. The digital system can also be described hierarchically. Timing can also be explicitly modeled in the same description. The VHDL language can be regarded as an integrated amalgamation of the following languages: sequential language + concurrent language + net‐list language + timing specifications + waveform generation language => VHDL Therefore, the language has constructs that enable you to express the concurrent or sequential behavior of a digital system with or without timing. It also allows you to model the system as an interconnection of components. Test waveforms can also be generated using i th same constructs. the t t All the th above b constructs t t may be b combined bi d to t provide id a comprehensive description of the system in a single model
Use of VHDL in digital logic design VHDL is used to describe a model for a digital hardware device. This model specifies the external view of the device and one or more internal views. The internal view of the device specifies the functionality or structure, structure while the external view specifies the interface of the device through which it communicates with the other models in its environment. The Figure drawn below shows the hardware device and the corresponding software model.
What is an entity? Entity is an abstraction level of the hardware device in cosideration. The device to device model mapping is strictly a one to many. That is, a hardware device may have many device models. For example, a device modeled at a higher level of abstraction may not have a clock as one of its inputs, since the clock may not have been used in the description. Also the data transfer at the interface may be treated in terms of say, integer values, instead of logical values. In VHDL, each device model is treated as a distinct representation of a unique device, called an entity .
Basic Terminologies The digital system can be as simple as a logic gate or as complex as a complete electronic system. A hardware abstraction of this digital system is called an entity. An entity X, when used in another entity Y, becomes a component for the entity Y. Therefore, a component is also an entity, depending on the level at which you are trying to model. To describe an entity, VHDL provides five different types of primary constructs, called design units. i They Th are 1. Entity declaration 2. Architecture bodyy 3. Configuration declaration 4. Package declaration 5. Package body An entity is modeled using an entity declaration and at least one architecture body. The entity declaration describes the external view of the entity, for example, the input and output signal names. The architecture body contains the internal description of the entity, for example, as a set of interconnected components that represents the structure of the entity, or as a set of concurrent or sequential statements that represents the behavior of the entity. Each style of representation can be specified in a different architecture body or mixed within a single architecture body .Figure Figure given below shows an entity and its model. model
A configuration declaration is used to create a configuration for an entity. entity It specifies the binding of one architecture body from the many architecture bodies that may be associated with the entity. It may also specify the bindings of components used in the selected architecture body to other entities. An entity may have any number of different configurations. A package declaration encapsulates a set of related declarations such as type declarations, subtype declarations, and subprogram declarations that can be shared across two or more design units. A package body contains the definitions of subprograms declared in a package declaration.
Once an entity has been modeled, it needs to be validated by a VHDL system. A typical VHDL system consists of an analyzer and a simulator. The analyzer reads in one or more design units contained in a single file and compiles them into a design library after validating the syntax and performing some static semantic checks. checks The design library is a place in the host environment (that is, the environment that supports the VHDL system) where compiled design units are stored. The simulator simulates an entity, represented by an entity‐architecture pair or by a configuration, by reading in its compiled description from the design library and then performing the following steps: 1. Elaboration 2 Initialization 2. 3. Simulation EXAMPLES Entity Declaration: The entity declaration specifies the name of the entity being modeled and lists the set of interface ports. Ports are signals through which the entity communicates with the other models in its external environment.
Here is an example of an entity declaration for the half‐adder circuit shown in Fig above entity HALF y _ADDER is port (A, B: in BIT; SUM, CARRY: out BIT); end HALF_ADDER; ‐‐ This is a comment line. The entity, called HALF_ADDER, has two input ports, A and B (the mode in specifies input port), and two output ports, SUM and CARRY (the mode out specifies output port). BIT is a predefined type of the language; it is an enumeration type containing the character literals '0' and '1'. The port types for this entity have been specified to be of type BIT, which means that the ports can take the values, '0' or '1'. Architecture Body: The entity declaration specifies the name of the entity being modeled and lists the set of interface ports. Ports are signals through which the entity communicates with the other models in its external environment. architecture HA_Archbody of HALF_ADDER is begin SUM