Vlsi Design Lab Manual

VLSI Design

EC 705

VII

Index S No. 1.

2.

Experiment Name

Date

Design of inverter using microwind and observe the waveform. Design of NAND using microwind and observe the waveform.

3.

4.

Design of NOR using microwind and observe the waveform.

5.

Design of AND using microwind and observe the waveform.

6.

Design of OR using microwind and observe the waveform.

7.

Design of XOR using microwind and observe the waveform.

8.

9.

10.

Design of XNOR using microwind and observe the waveform. Design of Full adder using microwind and observe the waveform. Design of Boolean Expression using microwind and observe the waveform. Vout = [(A + B) * C + (DE)] Design of Boolean Expression using microwind and observe the waveform. Vout = [(A*Bbar+ B*Abar) * (C + D)*CD)]

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VLSI Design

EC 705

Experiment No.1 Aim- Design of inverter using microwind and observe the waveform. Software required- Microwind 3.0 Theory- In digital logic, an inverter or NOT gate is a logic gate which implements logical negation. An inverter circuit outputs a voltage representing the opposite logic-level to its input. Inverters can be constructed using two complimentary transistors in a CMOS configuration. This configuration greatly reduces power consumption since one of the transistors is always off in both logic states. Processing speed can also be improved due to the relatively low resistance compared to the NMOS-only or PMOS-only type devices. Truth table of NOT Gate:

Traditional NOT Gate logic symbol:

Static CMOS Inverter:

Result-

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VLSI Design

EC 705

Viva Questions 1.

What is a Boolean equation?

2.

What is a truth table?

3.

What are the advantages of CMOS over NMOS and PMOS?

4.

What is pull up and pull down network?

5.

Why do we go for low power VLSI Circuits?

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6.

How can we design low power VLSI Circuits?

7.

What is the difference between Simulation and Synthesis?

8.

How do you convert a XOR gate into a buffer (Use only one XOR gate)?

9.

10.

How do you convert a XOR gate into an inverter(Use only one XOR gate)?

Implement an 2-input AND gate using a 2x1 mux.

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VLSI Design

EC 705

Experiment No.2 Aim- Design of NAND using microwind and observe the waveform. Software required- Microwind 3.0 Theory- The NAND gate is a digital logic gate that behaves in such a way that when A LOW output results only if both the inputs to the gate are HIGH. If one or both inputs are LOW, a HIGH output results. The NAND gate is a universal gate in the sense that any Boolean function can be implemented by NAND gates. Truth table of NAND Gate:

Traditional NAND Gate Logic symbol:

CMOS NAND Gate:

Result-

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VLSI Design

EC 705

Viva Questions 1. What is Rail Logic?

2. What are the different design domains used in Y charts?

3. Explain the different type of oxidation process used in fabrication?

4. What is etching?

5. What is ion implantation?

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6. What is the effect of temperature on mobility?

7. Give various factors on which threshold voltage depends.

8. What are the different types of scaling?

9. What is meant by device modeling?

10.A common-source amplifier is similar in configuration to which BJT amplifier?

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EC 705

Experiment No.3 Aim- Design of NOR using microwind and observe the waveform. Software required- Microwind 3.0 Theory- The NOR gate is a digital logic gate that implements logical NOR. A HIGH output (1) results if both the inputs to the gate are LOW (0). If one or both input is HIGH (1), a LOW output (0) results. NOR is the result of the negation of the OR operator. NOR is a functionally complete operation -- combinations of NOR gates can be combined to generate any other logical function. By contrast, the OR operator is monotonic as it can only change LOW to HIGH but not vice versa. Traditional NOR Gate logic symbol:

Truth table for NOR Gate:

CMOS NOR Gate:

Result-

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VLSI Design

EC 705

Viva Questions 1. What is ‘Strong 1’, ‘Strong 0’, ‘Weak 1’ and ‘Weak 0’?

2.

3.

What are the different regions of operation of MOSFET?

What are the different conditions for MOSFET to operate in cutoff, depletion and saturation?

4.

Explain the Resolution Logic?

5.

What are the advantages of CMOS process?

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6.

What is CAD?

7.

What is EDA?

8.

What is an ASIC?

9.

What is Microwind?

10.

What is a Full Custom IC?

EC 705

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EC 705

Experiment No.4 Aim- Design of AND using microwind and observe the waveform. Software required- Microwind 3.0 Theory- The AND gate is a digital logic gate that implements logical conjunction. A HIGH output (1) results only if both the inputs to the AND gate are HIGH (1). If neither or only one input to the AND gate is HIGH, a LOW output results. In another sense, the function of AND effectively finds the minimum between two binary digits, just as the OR function finds the maximum. Traditional AND Gate logic symbol:

Truth table for AND Gate:

CMOS AND Gate:

Result-

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VLSI Design

EC 705

Viva Questions 1. What is meant by Crow barred output?

2. Write down the equation for Ids in cutoff, depletion and saturation?

3. What is threshold voltage?

4. Why does the present VLSI circuits use MOSFETs instead of BJTs?

5. Why does the present VLSI circuits use MOSFETs instead of BJTs?

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6. Give the Cross-sectional diagram of the CMOS.

7. What does it mean "the channel is pinched off"?

8. Design a 4X1 Mux using a 2X1 Mux.

9. Arrange the following in the increasing order of their complexity: FPGA,PLA,CPLD,PAL.

10.In CMOS digital design, why is the size of PMOS is generally higher than that of the NMOS?

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VLSI Design

EC 705

Experiment No.5 Aim- Design of OR using microwind and observe the waveform. Software required- Microwind 3.0 Theory- The OR gate is a digital logic gate that implements logical disjunction. A HIGH output (1) results if one or both the inputs to the gate are HIGH (1). If neither input is HIGH, a LOW output (0) results. In another sense, the function of OR effectively finds the maximum between two binary digits, just as the complementary AND function finds the minimum. Traditional OR Gate logic symbol:

Truth table of OR Gate:

CMOS OR Gate:

Result-

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VLSI Design

EC 705

Viva Questions 1.

What are the different second order effects?

2.

What is body effect?

3.

What are the factors influencing threshold voltage of CMOS?

4.

What are the objectives of floor planning?

5.

What is the difference between Enhancement MOSFET and Depletion MOSFET?

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6.

What is early effect?

7.

What are the basic gates?

8.

What is substrate bias effect?

9.

What is a current mirror?

10.

What are the various VLSI design strategies?

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EC 705

Experiment No.6 Aim- Design of XOR using microwind and observe the waveform. Software required- Microwind 3.0 Theory- The XOR gate (sometimes EOR gate) is a digital logic gate that implements exclusive disjunction. A HIGH output (1) results if one, and only one, of the inputs to the gate is HIGH (1). If both inputs are LOW (0) or both are HIGH (1), a LOW output (0) results. XOR gate is short for exclusive OR. This means that precisely one input must be 1 (true) for the output to be 1 (true). A way to remember XOR is "one or the other but not both." This function is addition modulo 2. As a result, XOR gates are used to implement binary addition in computers. Traditional ExOR Gate logic symbol:

Truth table for ExOR Gate:

CMOS ExOR Gate:

Result-

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VLSI Design

EC 705

Viva Questions 1. What is meant by channel length modulation?

2. What is mean by pinch off condition?

3. What is Euler’s path? Define Euler’s theorem?

4. What is latch up?

5. Why is the size of inverters in buffer design gradually increased? Why not give the output of a circuit to one large inverter?

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6. What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus?

7. What happens to delay if load capacitance is increased?

8. Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates)usually limited to four?

9. What are static and dynamic power dissipation w.r.t to CMOS gate?

10.Which is fastest among the following technologies: CMOS, BiCMOS, TTL, ECL?

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EC 705

Experiment No.7 Aim- Design of XNOR using microwind and observe the waveform. Software required- Microwind 3.0 Theory- The XNOR gate (sometimes spelled 'exnor') is a digital logic gate whose function is the inverse of the exclusive OR (XOR) gate. The two-input version implements logical equality. A HIGH output (1) results if both of the inputs to the gate are the same. If one but not both inputs are HIGH (1), a LOW output (0) results. Truth table for Exnor Gate:

Traditional Exnor Gate logic symbol

CMOS Exnor Gate:

Result-

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Viva Questions 1. Explain n-well process?

2. Explain p-well process?

3. Explain twin-tub process?

4. What is Scaling?

5. What is a transmission gate, and what is its typical use in VLSI?

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6. What should be done to the size of a pMOS transistor inorder to increase its threshold voltage?

7. Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) considering Channel Length Modulation.

8. Explain the various MOSFET Capacitances and their significance.

9. Explain the voltage transfer characteristics of a CMOS Inverter.

10.What are the advantages of CMOS technology?

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EC 705

Experiment No.8 Aim- Design of Full adder using microwind and observe the waveform. Software required- Microwind 3.0 Theory- An adder or summer is a digital circuit that performs addition of numbers. A full adder is capable of adding three bits: two bits and one carry bit of earlier calculation. It has three inputs - A, B, and carry C, such that multiple full adders can be used to add larger numbers. Full Adder circuit diagram:

Truth table for full adder:

CMOS Full adder Circuit:

Result-

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VLSI Design

EC 705

Viva Questions

1.

Explain the different type of oxidation process used in fabrication?

2.

Explain the Photolithography process?

3.

Explain the Ion Implantation process?

4.

What is latch up problem?

5.

Give the expression for CMOS switching power dissipation.

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6.

Why is static power dissipation very low in CMOS technology when compared to others?

7.

Why are pMOS transistor networks generally used to produce high signals, while nMOS networks are used to product low signals?

8.

What is meant by 90nm technology?

9.

What are the differences between a flip-flop and a latch?

10.

Design a Transmission Gate based XOR. Now, how do you convert it to XNOR (without inverting the output)?

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VLSI Design

EC 705

Experiment No.9 Aim- Design of Boolean Expression using microwind and observe the waveform. Vout = [(A + B) * C + (DE)] Software required- Microwind 3.0 Theory- An Euler path in a graph is a path which traverses each edge of the graph exactly once. An Euler path which is a cycle is called an Euler cycle. For loopless graphs without isolated vertices, the existence of an Euler path implies the connectedness of the graph, since traversing every edge of such a graph requires visiting each vertex at least once. A connected graph has an Euler path if it has exactly zero or two vertices of odd degree. If every vertex has even degree, the graph has an Euler cycle. CMOS Circuit Diagram:

Euler’s Path:

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Truth table for the given Boolean expression: A

B

C

D

E

A

(A

Vo

Result-

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Out = (A+B)*C + DE

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VLSI Design

EC 705

Viva Questions 1.

Explain the Layout Design rules?

2.

What is the need of Design rules?

3.

What is Stick Diagram?

4.

What are the color codes used in layout? what is the need of color codes?

5.

Why is NAND gate preferred over NOR gate for fabrication?

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6.

Which transistor has higher gain: BJT or MOSFET and why?

7.

Why PMOS and NMOS are sized equally in a transmission gates?

8.

In CMOS digital design, why is the size of PMOS is generally higher than that of the NMOS?

9.

What happens to delay if load capacitance is increased?

10.

What are the various noise sources in MOSFET?

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VLSI Design

EC 705

Experiment No.10 Aim- Design of Boolean Expression using microwind and observe the waveform. Vout = [(A*Bbar+ B*Abar) * (C + D)*CD)] Software required- Microwind 3.0 Theory- An Euler path in a graph is a path which traverses each edge of the graph exactly once. An Euler path which is a cycle is called an Euler cycle. For loopless graphs without isolated vertices, the existence of an Euler path implies the connectedness of the graph, since traversing every edge of such a graph requires visiting each vertex at least once. A connected graph has an Euler path if it has exactly zero or two vertices of odd degree. If every vertex has even degree, the graph has an Euler cycle. CMOS Circuit Diagram:

Euler’s Path:

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VLSI Design

EC 705

Truth table for the given Boolean expression:

A

B

C

D

Result-

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VLSI Design

EC 705

Viva Questions

1.

What is Current mirror circuit?

2.

Explain the different types of design methodology?

3.

What are the different types of circuit representation?

4.

What is SPICE?

5.

Draw the High Frequency model of MOSFET?

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EC 705

6.

What are the noise sources present in diode?

7.

What are the short channel effects of MOSFET?

8.

What is yield?

9.

What is the application of CMOS?

10.

What are compound gates?

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