Vhdl Simulation of Fir Filter

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VHDL SIMULATION OF FIR FILTER LIST OF FIGURES

Title

Figure

Page

1. Domain & level representation of VHDL

1

11

2. Direct form FIR Filter

2.1

21

3. Cascaded form FIR Filter

2.2

24

4. lattice form FIR Filter

2.3

24

5. Basic FIR Filter

3.1

32

6. 27 Tap FIR Filter

3.2

33

7. RTL Systematic of Multiplier Multiplie r

3.3, 3.4

40, 41

8. Multiplier Output

3.5

42

9. RTL Systematic of MAC

3.6, 3.7

45, 46

10. MAC Output

3.8

47

11. RTL Systematic of FIR

3.9, 3.10,

52, 53

3.11

54

12. FIR Output

3.12

56

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LIST OF TABLES

Title

Table

Page

1. Multiplier Output

3.1

41

2. MAC Unit Output

3.2

48

3. FIR Output

3.3

57

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TABLE OF CONTENT Declaration Certificate Acknowledgement List of figure List of Tables Chapter 1  –  Introduction

1.1 Abstract 1.2 VLSI an Introduction 1.3 VHDL Introduction 1.4 Current Research in India and Abroad Chapter 2 - Mathematical Background

2.1 Introduction to FIR Filters 2.1.1 Advantages of digital filters 2.2 Realization of FIR Filters 2.3 Structures of FIR Filters 2.3.1 Direct Form 2.3.2 Cascaded Form 2.3.3 Lattice Form 2.4 Methods of Designing FIR Filters 2.4.1 Fourier Series Method 2.4.2 Window Technique 2.4.3 Frequency Sampling Method 2.5 Comparisons of various design methods for FIR Filters 2.5.1 Kaiser window 2.5.2 Design specification

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Chapter 3  – Design Design of 27 tap FIR filter

3.1 Design Description 3.2 The design of 27 tap FIR filter. 3.3 Statement of problem. 3.4 How we designed the FIR filter 3.5 Code , RTL systematic and simulation for multiplier 3.6 Code , RTL systematic and simulation for MAC unit. 3.7 Code, RTL systematic and simulation for 27 TAP FIR filter .

Chapter 4  –  Usefulness and Application Chapter 5  –  Conclusion and Scope for future extension.

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ABSTRACT

The main aim of this project is VHDL SIMULATION OF FIR FILTER. It involves 27 taps for improving the accuracy of the filter. It is implemented using a popular HDL(Hardware Description Language ) called VHDL(very high speed integrated circuit hardware description language).The filter is implemented through the use of three basic components used for any DSP system implementation  – Adder, Adder, Multiplier and Delay, along with some other components. Filter is one of the most fundamental processing element in any digital processing system (DSP) which is frequency selective. Here the term frequency selective means that the system passes certain frequency components and totally rejects others. Digital filters can be classified into two classes known as FIR (finite impulse response) and IIR (infinite impulse response) filters. Advantage of FIR over IIR is that they are guaranteed to be stable and to have linear phase response. Linear filters are widely used in digital communication system, in spectral analysis and particularly in application where non-linear phase can be tolerated.

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CHAPTER 1

INTRODUCTION

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VLSI (VERY LARGE SCALE INTEGRATION) VLSI means Very Large Scale Integration. It is an effort to integrate

discrete

components circuit in a single silicon base (chip). The integration results in high reliability, low power consumption, less weight, low volume and low cost of products. The growing need for sophistication of application continuously pushes the design as well as manufacturing of electronic components and systems to anew level of  complexity. For less complex operation we can design using discrete components (transistors, gate IC’s, IC’s, etc) When we want complex operation to be performed by the electronic system, it is very difficult to design the system using discrete components. The system becomes very bulky, unreliable, and less redundant. Also it takes a lot of time to develop the system. Hence there is need to develop an integrated circuit or a single chip dedicated to a specific task. The chip is referred to as an application specific integrated circuit (ASIC). A single chip has the following advantage over the circuit from discrete components.

1. Size: Size: -

Integrated circuits/chips are much smaller. Both transistors and wires are

shrunk to micrometric (and nowadays to nanometric) sizes.

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VHDL INTRODUCTION VHDL is an acronym which for VHSIC hardware description language. VHSIC means very high speed integrated circuit. VHDL can wear many hats. It is used for documentation,verification, and synthesis of large digital design. This is actually one of  the key feature of VHDL, since the same VHDL code can achieve the all the three of  these goals, it can also be used to take three different approach for describing hardware. They are structural, behavioural and data flow. As a standard description VHDL is used as input and output to various simulation, synthesis and layout tools. The language provides the ability to describe the system, networks and components at a very high behavioural level as well as low gate level. It also represents top down methodology and environment. Simulation can be carried out any level from general functional analysis to a very detail gate level waveform analysis. Synthesis is carried out currently only at the register level. Top down design first describes the system at a very high level of abstraction, like a specification. Designers simulate and debug the system at this very high level before refining it into smaller components.

VHDL TERMINOLOGY

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ARCHITECTURE:-

All entities simulated have an architecture description. The architecture describes the behaviour of the entity. A single entity can have multiple architecture. One architecture might be behavioural another might be structural.

CONFIGURATION:-

A configuration statement is used to bind component instants to an entity architecture pair. A configuration can be considered like a part list for a design. It describes which behaviour to use for each entity much as a part list describes which part to use in the design.

GENERIC:-

A generic is VHDL term for a parameter that passes information to an entity for instance , if an entity is gate level model with a rise and fall delay, the values for the rise and fall delays could be passed into the entity with generics.

PROCESS:-

A process is a basic unit of execution in VHDL. All operations that are performed in

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that verifies the functionality of the design using files on the host computer to define stimuli, interacts with the user, and compares results with those expected. VHDL is a strongly typed language. It is relatively easy for an inexperienced developer to produce code that simulates successfully but that cannot be synthesized into a real device, or is too large to be practical. One particular pitfall is the accidental production of transparent latches rather than D-type flip-flops as storage elements. VHDL is not a case sensitive language. One can design hardware in a VHDL IDE (such as Xilinx or Quartus) to produce the RTL schematic of the desired circuit. After that, the generated schematic can be verified using simulation software (such as ModelSim) which shows the waveforms of inputs and outputs of the circuit after generating the appropriate testbench. To generate an appropriate testbench for a particular circuit or VHDL code, the inputs have to be defined correctly. For example, for clock input, a loop process or an iterative statement is required. The key advantage of VHDL when used for systems design is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires). Another benefit is that VHDL allows the description of a concurrent system (many parts, each with its own sub-behavior, working together at the same time). VHDL is dataflow language, unlike procedural computing languages such as BASIC, C, and assembly code, which all run sequentially, one instruction at a time. A final point is that when a VHDL model is translated into the "gates and wires" that are

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The flow of data through the entity is modelled primarily using concurrent signal assignment statements.



The structure of the entity is not explicitly specified but it can be implicitly deduced.





Architecture MYARCH of MYENT is begin SUM
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