vhdl mcq

November 19, 2017 | Author: toshit jain | Category: Operational Amplifier, Cmos, Amplifier, Random Access Memory, Electrical Circuits

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mcq...

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.If the declarative part in the architecture of a half adder is as below component XOR2 port (X,Y:in BIT;z: out BIT); end component component AND2 port (L,M:in BIT;z:out BIT); end component Then what kind of architecture is it ? behavourial structural dataflow none of these

2.What is the symbol used for signal assignment? == = :=

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