Vhdl Codes for Mips Instructions Lw,Sw,Beq,Bne,j,Jal,Lui,Add,Addi,Or,Ori,Slt,Nor,And,Exceptions

VHDL Code for ALU LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; ENTITY alu IS PORT( a, b

: IN STD_ULOGIC_VECTOR(31 DOWNTO 0);

aluctl : IN STD_ULOGIC_VECTOR(3 DOWNTO 0); aluresult : OUT STD_ULOGIC_VECTOR(31 DOWNTO 0); zero

: OUT STD_ULOGIC);

END alu; ARCHITECTURE behavioral OF alu IS BEGIN PROCESS(a, b, aluctl) VARIABLE a_u : UNSIGNED(31 DOWNTO 0); VARIABLE b_u : UNSIGNED(31 DOWNTO 0); VARIABLE result_u : UNSIGNED(31 DOWNTO 0); VARIABLE zero_u : UNSIGNED(0 DOWNTO 0); BEGIN a_u := UNSIGNED(a); b_u := UNSIGNED(b); result_u := (OTHERS => '0'); zero_u(0) := '0'; CASE aluctl IS WHEN "0000" =>result_u := a_u AND b_u;--and

WHEN "0001" =>result_u := a_u OR b_u; --or WHEN "0010" =>result_u := a_u + b_u;--add WHEN "0110" =>result_u := a_u - b_u;--sub WHEN "0111" =>result_u := a_u - b_u;--slt IF SIGNED(result_u) SIGNED(result_u) < 0 THEN result_u := TO_UNSIGNED(1, result_u'LENGTH); ELSE result_u := (OTHERS => '0'); END IF; WHEN "1100"=>result_u:=(a_u nor b_u);--nor WHEN OTHERS => result_u := (OTHERS => 'X'); END CASE; IF TO_INTEGER(result_u) = 0 THEN zero_u(0) := '1'; ELSE zero_u(0) := '0'; END IF; aluresult ALUCtl ALUCtl ALUCtl ALUCtl ALUCtl ALUCtl ALUCtl AluCtl ALUCtl mux_A_out,

b => mux_B_out, aluctl => ALUctl, aluresult => alu_result, zero => zero ); alu_control:ALUControl PORT MAP( Funct=>instruction15_0(5 downto 0), ALUOp=>ALUOp, ALUCtl=> ALUctl ); -- Multiplexor for ALU input A: mux_A : PROCESS (ALUSrcA, PCout, reg_A) BEGIN CASE ALUSrcA IS WHEN '0' => mux_A_out mux_A_out mux_A_out 'X'); END CASE; END PROCESS; -- Multiplexor for AlU input B: mux_B : PROCESS(ALUSrcB) BEGIN CASE ALUSrcB IS WHEN "00"=>mux_B_outmux_B_out mux_B_out mux_B_out mux_B_out 'X'); END CASE; END PROCESS; -- Computation of Jump Address: Process (instruction25_21,instruction20_16,instruction15_0) VARIABLE instruction25_0:STD_ULOGIC_VECTOR(25 DOWNTO 0) ; BEGIN instruction25_0:=instruction25_21&instruction20_16&instruction15_0;  jump reset, reg_in => data_1, reg_out => reg_A ); B : register32 PORT MAP ( clk => clk, reset => reset, reg_in => data_2, reg_out => reg_B ); inst_regfile : registerfile PORT MAP ( clk => clk, reset => reset, registerwrite => RegWrite, writedata => write_data, writeregister => write_reg,

readregister1 => instr_25_21, readregister2 => instr_20_16, readdata1 => data_1, readdata2 => data_2 ); -- multiplexer for write register write_reg 'X'); -- multiplexer for write data write_data 'X'); PROCESS(instr_15_0) -- variables needed for reading result of sign extension VARIABLE temp_instr_15_0_se

: STD_ULOGIC_VECTOR(31 DOWNTO 0);

VARIABLE temp_instr_15_0_se_sl : STD_ULOGIC_VECTOR(31 DOWNTO 0); BEGIN -- sign extend instr_15_0 to 32 bits temp_instr_15_0_se := STD_ULOGIC_VECTOR(RESIZE(SIGNED(instr_15_0), instr_15_0_se'LENGTH)); -- shift left 2 temp_instr_15_0_se_sl := temp_instr_15_0_se(29 DOWNTO 0) & "00"; ShiftLeft16out