Vhdl Code for Updown Cnt

VHDL CODE FOR 4-BIT UPDOWN COUNTER :

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity up_dn_beh4 is Port ( clk,rst : in STD_LOGIC; u_d : in STD_LOGIC; q : out STD_LOGIC_VECTOR (3 downto 0)); end up_dn_beh4; architecture Behavioral of up_dn_beh4 is signal cnt: std_logic_vector (3 downto 0); signal en : std_logic; begin q