VHDL code for 8:1 Multiplexer.

EXPERIMENT NO: 07 AIM: Write VHDL code for 8:1 Multiplexer. APPARATUS: MODELSIM THEORY: 8:1 Multiplexer The multiplexer is a combinational circuit which accepts several data inputs and allows only one of them at a time to get through to the output.

Fig.1

EN

CONTROL INPUTS

OUTPUT(Y) (Selected Inputs)

SEL(3)

SEL(3)

SEL(3)

0

0

0

0

D0

1

0

0

1

D1

1

0

1

0

D2

1

0

1

1

D3

1

1

0

0

D4

1

1

0

1

D5

1

1

1

0

D6

1

1

1

1

D7

VHDL Code For 8:1 Multiplexer ------------------------------------------------------------------------------- File : mux8_1.vhd -- Entity : mux8_1 -------------------------------------------------------------------------------- College : Rizvi College Of Engineering -- Simulators : Mentor Graphics Modelsim -------------------------------------------------------------------------------- Description : 8 TO 1 MULTIPLEXOR --------------------------------------------------------------------------------The IEEE standard 1164 package, declares std_logic, etc. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; ---------------------------------- Entity Declarations ------------------------entity mux8_1 is port ( D: in STD_LOGIC_VECTOR (7 downto 0); EN: in STD_LOGIC; SEL: in STD_LOGIC_VECTOR (2 downto 0); Y: out STD_LOGIC ); end mux8_1; architecture mux8_1_arch of mux8_1 is begin process(EN,SEL,D) begin if(EN='1')then y y y y y y y y y