VHDL code for 4-bit ALU

VHDL code for 4-bit ALU

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VHDL code for 4-bit ALU BY ADMIN · PUBLISHED MAY 19, 2014 · UPDATED MAY 23, 2016

ALU’s comprise the combinational logic that implements logic operations such as AND, OR, NOT gate and arithmetic operations, such as Adder, Subtractor. Functionally, the operation of typical ALU is represented as shown in diagram http://allaboutfpga.com/vhdl-code-for-4-bit-alu/

VHDL code for 4-bit ALU

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below,

Functional Description of 4-bit Arithmetic Logic Unit Controlled by the three function select inputs (sel 2 to 0), ALU can perform all the 8 possible logic operations

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VHDL code for 4-bit ALU

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VHDL Code for 4-bit ALU 1 2 3 4 5 6 7 8

library IEEE; use IEEE.STD_LOGIC_1164.ALL ALL; use IEEE.NUMERIC_STD.ALL ALL; entity alu is Port ( inp_a : in signed(3 downto 0); inp_b : in signed(3 downto 0); sel : in STD_LOGIC_VECTOR (2 downto 0);

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VHDL code for 4-bit ALU

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out_alu : out signed(3 downto 0)); end alu; architecture Behavioral of alu is begin process process(inp_a, inp_b, sel) begin case sel is when "000" => out_alu out_alu out_alu out_alu out_alu out_alu out_alu out_alu NULL NULL; end case case; end process process; end Behavioral;

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VHDL code for 4-bit ALU

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Testbench VHDL Code for 4-Bit ALU 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

LIBRARY ieee; USE ieee.std_logic_1164.ALL ALL; USE ieee.numeric_std.ALL ALL; ENTITY Tb_alu IS END Tb_alu; ARCHITECTURE behavior OF Tb_alu IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT alu PORT PORT( inp_a : IN signed(3 downto 0); inp_b : IN signed(3 downto 0); sel : IN std_logic_vector(2 downto 0); out_alu : OUT signed(3 downto 0) ); END COMPONENT COMPONENT; --Inputs signal inp_a : signed(3 downto 0) := (others others => signal inp_b : signed(3 downto 0) := (others others => signal sel : std_logic_vector(2 downto 0) := (others others --Outputs signal out_alu : signed(3 downto 0);

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VHDL code for 4-bit ALU

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BEGIN -- Instantiate the Unit Under Test (UUT) uut: alu PORT MAP ( inp_a => inp_a, inp_b => inp_b, sel => sel, out_alu => out_alu ); -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; -- insert stimulus here inp_a