Verilog Lab Manual

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Verilog HDL Lab Manual

Experiment No. 01 Write a program in Verilog HDL for AND Gate using Dataflow and Behavioral Modeling Style Block Diagram: A AND GATE

C

B

Boolean Equation:

C = A.B

Truth Table: A 0 0 1 1

B 0 1 0 1

C 0 0 0 1

a) Data Flow Modeling module test_aand (a,b,out); input a,b; output out; assign out = a & b; endmodule

b) Behavioral Modeling module test_andgg(a,b,cin); input a; input b; output cin; reg cin; always@ (a or b) begin Prepared By: Atush Jain ([email protected]) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology – Indore(M.P.)

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Verilog HDL Lab Manual

case ({a,b}) 2'b00: begin cin = 1'b0; end 2'b01: begin cin = 1'b0; end 2'b10: begin cin = 1'b0; end 2'b11: begin cin = 1'b1; end default: begin cin = 1'b0; end endcase end endmodule

Prepared By: Atush Jain ([email protected]) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology – Indore(M.P.)

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Verilog HDL Lab Manual

Experiment No. 02 Write a program in Verilog HDL for OR Gate using Dataflow and Behavioral Modeling Style Block Diagram: A OR GATE

C

B

Boolean Equation:

C=A+B

Truth Table: A 0 0 1 1

B 0 1 0 1

C 0 1 1 1

a) Data Flow Modeling module test_or_ex (a,b,out); input a,b; output out; assign out = a | b; endmodule

b) Behavioral Modeling module test_orgg(a,b,cin); input a; input b; output cin; reg cin; always@ (a or b) begin Prepared By: Atush Jain ([email protected]) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology – Indore(M.P.)

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Verilog HDL Lab Manual

case ({a,b}) 2'b00: begin cin = 1'b0; end 2'b01: begin cin = 1'b1; end 2'b10: begin cin = 1'b1; end 2'b11: begin cin = 1'b1; end default: begin cin = 1'b0; end endcase end endmodule

Prepared By: Atush Jain ([email protected]) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology – Indore(M.P.)

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Verilog HDL Lab Manual

Experiment No. 03 Write a program in Verilog HDL for NAND Gate using Dataflow and Behavioral Modeling Style Block Diagram: A NAND GATE

C

B

Boolean Equation:

C = (A.B)’

Truth Table: A 0 0 1 1

B 0 1 0 1

C 1 1 1 0

a) Data Flow Modeling module test_nand_ex (a,b,out); input a,b; output out; assign out = ~(a & b); endmodule

b) Behavioral Modeling module test_nandgg(a,b,cin); input a; input b; output cin; reg cin; always@ (a or b) begin Prepared By: Atush Jain ([email protected]) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology – Indore(M.P.)

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Verilog HDL Lab Manual

case ({a,b}) 2'b00: begin cin = 1'b1; end 2'b01: begin cin = 1'b1; end 2'b10: begin cin = 1'b1; end 2'b11: begin cin = 1'b0; end default: begin cin = 1'b0; end endcase end endmodule

Prepared By: Atush Jain ([email protected]) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology – Indore(M.P.)

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Verilog HDL Lab Manual

Experiment No. 04 Write a program in Verilog HDL for NOR Gate using Dataflow and Behavioral Modeling Style Block Diagram: A NOR GATE

C

B

Boolean Equation:

C = (A + B)’

Truth Table: A 0 0 1 1

B 0 1 0 1

C 1 0 0 0

a) Data Flow Modeling module test_nor_ex (a,b,out); input a,b; output out; assign out = ~(a | b); endmodule

b) Behavioral Modeling module test_norgg(a,b,cin); input a; input b; output cin; reg cin; always@ (a or b) begin Prepared By: Atush Jain ([email protected]) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology – Indore(M.P.)

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Verilog HDL Lab Manual

case ({a,b}) 2'b00: begin cin = 1'b1; end 2'b01: begin cin = 1'b0; end 2'b10: begin cin = 1'b0; end 2'b11: begin cin = 1'b0; end default: begin cin = 1'b0; end endcase end endmodule

Prepared By: Atush Jain ([email protected]) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology – Indore(M.P.)

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Verilog HDL Lab Manual

Experiment No. 05 Write a program in Verilog HDL for XOR Gate using Dataflow and Behavioral Modeling Style Block Diagram: A XOR GATE

C

B

Boolean Equation:

C = (A.B’ + A’.B)

Truth Table: A 0 0 1 1

B 0 1 0 1

C 0 1 1 0

a) Data Flow Modeling module test_xor_ex (a,b,out); input a,b; output out; assign out = (a ^ b); endmodule

OR module test_xorg2 (a,b,c); input a,b; output c; assign c = (~a & b) | (a & ~b); endmodule

Prepared By: Atush Jain ([email protected]) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology – Indore(M.P.)

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Verilog HDL Lab Manual

b) Behavioral Modeling module test_xorgg(a,b,cin); input a; input b; output cin; reg cin; always@ (a or b) begin case ({a,b}) 2'b00: begin cin = 1'b0; end 2'b01: begin cin = 1'b1; end 2'b10: begin cin = 1'b1; end 2'b11: begin cin = 1'b0; end default: begin cin = 1'b0; end endcase end endmodule

Prepared By: Atush Jain ([email protected]) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology – Indore(M.P.)

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Verilog HDL Lab Manual

Experiment No. 06 Write a program in Verilog HDL for XNOR Gate using Dataflow and Behavioral Modeling Style Block Diagram: A XNOR GATE

C

B

Boolean Equation:

C = (A.B + A’.B’)

Truth Table: A 0 0 1 1

B 0 1 0 1

C 1 0 0 1

a) Data Flow Modeling module test_xnor_ex (a,b,out); input a,b; output out; assign out = ~ (a ^ b); endmodule OR module test_xorg2 (a,b,c); input a,b; output c; assign c = (a & b) | (~a & ~b); endmodule

Prepared By: Atush Jain ([email protected]) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology – Indore(M.P.)

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Verilog HDL Lab Manual

b) Behavioral Modeling module test_xnorgg(a,b,cin); input a; input b; output cin; reg cin; always@ (a or b) begin case ({a,b}) 2'b00: begin cin = 1'b1; end 2'b01: begin cin = 1'b0; end 2'b10: begin cin = 1'b0; end 2'b11: begin cin = 1'b1; end default: begin cin = 1'b0; end endcase end endmodule

Prepared By: Atush Jain ([email protected]) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology – Indore(M.P.)

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Verilog HDL Lab Manual

Experiment No. 07 Write a program in Verilog HDL for Half Adder using Dataflow and Gate Level Modeling Style Block Diagram: A

SUM HALF ADDER

B

Boolean Equation:

CARRY

Sum = (A’.B + A’.B) Carry = A.B

Truth Table: A 0 0 1 1

B 0 1 0 1

SUM 0 1 1 0

CARRY 0 0 0 1

a) Data Flow Modeling module test_halfadder (a, b, sum, carry); input a, b; output sum, carry; assign sum = a ^ b; assign carry = a & b; endmodule

b) Gate Level Modeling module test_halfadd (a, b, sum, carry); input a, b; output sum, carry; xor(sum, a, b); and(carry, a, b); endmodule

Prepared By: Atush Jain ([email protected]) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology – Indore(M.P.)

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Verilog HDL Lab Manual

Experiment No. 08 Write a program in Verilog HDL for Full Adder using Dataflow, Gate Level and Structural Modeling Style Block Diagram: A SUM B

FULL ADDER CARRY

C Boolean Equation:

Sum = A Xor B Xor C Carry = A.B + B.C + C.A

Truth Table: A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

SUM 0 1 1 0 1 0 0 1

CARRY 0 0 0 1 0 1 1 1

a) Data Flow Modeling module test_fulladder_df (a, b, c, sum, carry); input a, b, c; output sum, carry; assign sum = a ^ b ^ c; assign carry = (a & b) | (b & c) | (c & a); endmodule

b) Gate Level Modeling module test_fulladd (a, b, c, sum, carry); input a, b, c;

Prepared By: Atush Jain ([email protected]) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology – Indore(M.P.)

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Verilog HDL Lab Manual

output sum, carry; wire temp, temp1, temp2; xor(temp, a, b); and(temp1, a, b); xor(sum, temp, c); and(temp2, temp, c); or(carry, temp2, temp1); endmodule

c) Structural Modeling module struc_fa(a1, b1, c1, sum1, carry1); input a1, b1, c1; output sum1, carry1; wire temp, temp1, temp2; test_halfadder haa (.a(a1),.b(b1),.sum(temp),.carry(temp1)); test_halfadder hab (.a(temp),.b(c1),.sum(sum1),.carry(temp2)); and(carry1,temp1,temp2); endmodule

Prepared By: Atush Jain ([email protected]) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology – Indore(M.P.)

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Verilog HDL Lab Manual

Experiment No. 09 Write a program in Verilog HDL for 2:1 Multiplexer Block Diagram: A 2:1 Mux

Output

B Sel Boolean Equation:

Output = A if {Sel = 0} Output = B if {Sel = 1}

Truth Table: Input A B

Sel 0 1

Output A B

a) 2:1 Mux using Conditional Assignment module mux_condi (f, a, b, sel); input a, b, sel; output f; assign f = sel ? a : b; endmodule

b) 2:1 Mux using ‘always’ Statement module mux211(f, a, b, sel); output f; input a, b, sel; reg f; always@(a or b or sel) if (sel) f = a; else f = b; endmodule Prepared By: Atush Jain ([email protected]) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology – Indore(M.P.)

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Verilog HDL Lab Manual

Experiment No. 10 Write a program in Verilog HDL for 4:1 Multiplexer using Behavioral & Structural Modeling Style Block Diagram: A Output

B

4:1 Mux

C D Sel1

Sel2

Truth Table: Input A B C D

Sel1 0 0 1 1

Sel2 0 1 0 1

Output A B C D

a) Behavioral Modeling module test_mux41(a, s, c); input [3:0] a; input [1:0] s; output c; reg c; always @ (a or s) begin case(s) 2'b00: c = a[0]; 2'b01: c = a[1]; 2'b10: c = a[2]; 2'b11: c = a[3]; Prepared By: Atush Jain ([email protected]) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology – Indore(M.P.)

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Verilog HDL Lab Manual

default: c = a[0]; endcase end endmodule

b) Sturctural Modeling module test_mux41_struc (a, b, s, cout); input [1:0]a, b, s; output cout; wire temp1, temp2; mux_condi la1 (.a(a[0]),.b(b[0]),.sel(s[0]),.f(temp1)); mux_condi la2 (.a(a[1]),.b(b[1]),.sel(s[0]),.f(temp2)); mux_condi la3 (.a(temp1),.b(temp2),.sel(s[1]),.f(cout)); endmodule

Prepared By: Atush Jain ([email protected]) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology – Indore(M.P.)

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Verilog HDL Lab Manual

Experiment No. 11 Write a program in Verilog HDL for 1: 2 De - Multiplexer using Behavioral Modeling Style Block Diagram: Y[0] Input

1:2 De - Mux

Y[1]

Sel

Truth Table: Input A B

a)

Sel 0 1

Output Y[0] Y[1]

Behavioral Modeling

module test_demux12 (a, s, c); input a; input s; output [1:0] c; reg c; always @(a or s) begin if (s) c = (a & ~s); else c = (a & s); end endmodule

Prepared By: Atush Jain ([email protected]) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology – Indore(M.P.)

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Verilog HDL Lab Manual

Experiment No. 12 Write a program in Verilog HDL for 2: 4 Decoder using Behavioral Modeling Style Block Diagram: I N P U T

O U T P U T

2:4 Decoder

Truth Table: Input A 0 0 1 1

B 0 1 0 1

Output Y[0] Y[1] Y[2] Y[3]

a) Behavioral Modeling module test_decoder24 (a, b); input [1:0] a; output [3:0]b; reg [3:0] b; always @(a) begin b[3] = a[1] & a[0]; b[2] = !a[1] & a[0]; b[1] = a[1] & !a[0]; b[0] = !a[1] & !a[0]; end endmodule

Prepared By: Atush Jain ([email protected]) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology – Indore(M.P.)

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Verilog HDL Lab Manual

Experiment No. 13 Write a program in Verilog HDL for D – Flip Flop using Behavioral Modeling Style Block Diagram: CLK RESET

D – Flip Flop

OUTPUT

INPUT Truth Table: Input 0 1

Output 0 1

a) Behavioral Modeling module test_dff (d, clk, reset, q); input d, clk, reset; output q; reg q; always@ (posedge clk) begin if (reset) q