Verilog FAQ

Verilog FAQ What is VCD and is there any free tool to view it ? VCD - Value Change Dump format - is an ASCII file that contains the "Changes in Values of Signals". This is a STANDARD format and is compatible between different waveform viewers etc. Also most of the simulators can write out VCD files - both VHDL & Verilog, though in Verilog you could do it more easily (than in VHDL - where you have to go through your simulator's C-API) with the system tasks like $dumpvars. VCD (Value Change Data)

Verilog simulator dumps the simulation information for waveform viewing in VCD Format (Value Change Data). Different types of Verilog Simulators

There are mainly two types of simulators available. Event Driven Cycle Based Event-based Simulator: This Digital Logic Simulation method sacrifices performance for rich functionality: every active signal is calculated for every device it propagates through during a clock cycle. Full Event-based simulators support 4-28 states; simulation of Behavioral HDL, RTL HDL, gate, and transistor representations; full timing calculations for all devices; and the full HDL standard. Event-based simulators are like a Swiss Army knife with many different features but none are particularly fast. Event based simulators are further categorized in 2 types. Compiled-Code Simulators: This technique takes the input definition (HDL) of the design and spends time compiling it into a new data structure in order to enable much faster calculations during run-time. You sacrifice compile time to be able to run large numbers of tests faster. it is used in some high end, Event-based simulators. e.g. Synopsys Inc.'s VCS Simulator converts verilog files into C code which then be compiled and run, just like any other executable file. It is 10 to 50 times faster than any other interpretive simulator. see http://www.synopsys.com/products/simulation/vcs_ds.html

Cadence's Native Compiled Verilog generates direct machine language instructions from verilog files. see http://www.cadence.com/datasheets/affirma_nc_verilog_sim.html Interpreted Code Simulators: This method of simulation allows for rapid change of the source HDL of the design and restart of the simulation since there is little or no compilation involved after every design change. This is good for interaction but leads to poor run times of large tests compared to Compiled Code Techniques. e.g. Cadence Design Systems Verilog - XL. see http://www.cadence.com/technology/pcb/products/prev_ds/verilog-xlfamily.html Cycle Based Simulator: This is a Digital Logic Simulation method that eliminates unnecessary calculations to achieve huge performance gains in verifying Boolean logic: 1.) Results are only examined at the end of every clock cycle; and 2.) The digital logic is the only part of the design simulated (no timing calculations). By limiting the calculations, Cycle based Simulators can provide huge increases in performance over conventional Event-based simulators. Cycle based simulators are more like a high speed electric carving knife in comparison because they focus on a subset of the biggest problem: logic verification. Cycle based simulators are almost invariably used along with Static Timing verifier to compensate for the lost timing information coverage. In following table differences between Event based and Cycle based simulation are summarized. Event based Simulation Evaluates inputs looking for state change Schedule events in time Calculate time delay Store state values and time

Cycle Based Simulation Evaluate entire design every clock cycle No event scheduling No delay calculations or timing checks No such storage. Very fast, very efficient

information Identify timing violations

memory usage. Does not identify timing violations

Where two simulations are appropriate

Comparison between Event Based and Cycle based Simulation

What is the difference between cycle and event based Verilog simulators ? •

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Cycle based Simulator :Cycle simulation is a technique (i.e. an algorithm) for digital circuit simulation. It does not simulate detailed circuit timing, but instead computes the steady state response of a circuit at each clock cycle. The user cannot see the glitch behavior of signals between clock cycles. Instead the user observes circuit signals once per clock cycle. Cycle based simulators work only with synchronous designs. Event based Simulator: Simulation based on events in logic means that whenever there is change in a input event, the output is evaluated. This makes the simulation very slow compared to Cycle based simulators. Verilog-XL is an event based simulator.

Consider the circuit below: if a cycle based simulator runs a simulation on the circuit below, then it will evaluate B, C, D and E only at each cycle. In the case of an event based simulator, B, C, D and E are evaluated not only at clock cycle, but also when any of the events at the input of gates and flip-flops occurs.

What is the difference between compiled and interpreted Verilog simulator ? •

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Compiled Simulator : This kind of simulator converts the whole Verilog code into machine dependent code and then runs the simulation. Example : VCS generates the binary file, which can be run from the command prompt. Compiled simulators are very fast. Interpreted Simulator : This kind of simulator executes line by line, thus is very slow compared to a compiled simulator. Verilog-XL is one such simulator.

Finite State Machines in Verilog State machine design is becoming more complex due to increasing time constraints and verification issues. Following papers provide good insight into design and optimization.

1] State Machine Design Techniques for Verilog and VHDL : by Steve Golson, Trilobyte Systems PDF version of article Text Version : http://www.synopsys.com/news/pubs/JHLD/JHLD-099401

TIDBITS Wire And Reg Well I had this doubt when I was learning Verilog: What is the difference between reg and wire? Well I won't tell stories to explain this, rather I will give you some examples to show the difference. From the college days we know that wire is something which connects two points, and thus does not have any driving strength. In the figure below, in_wire is a wire which connects the AND gate input to the driving source, clk_wire connects the clock to the flip-flop input, d_wire connects the AND gate output to the flip-flop D input.

There is something else about wire which sometimes confuses. wire data types can be used for connecting the output port to the actual driver. Below is the code which when synthesized gives a AND gate as output, as we know a AND gate can drive a load. 1 module wire_example( a, b, y); 2 input a, b; 3 output y; 4 5 wire a, b, y; 6 7 assign y = a & b; 8 9 endmodule

SYNTHESIS OUTPUT

What this implies is that wire is used for designing combinational logic, as we all know that this kind of logic can not store a value. As you can see from the example above, a wire can be assigned a value by an assign statement. Default data type is wire: this means that if you declare a variable without specifying reg or wire, it will be a 1-bit wide wire. Now, coming to reg data type, reg can store value and drive strength. Something that we need to know about reg is that it can be used for modeling both combinational and sequential logic. Reg data type can be driven from initial and always block. Reg data type as Combinational element 1 2 3 4 5 6 7 8 9 10 11 12 13

module reg_combo_example( a, b, y); input a, b; output y; reg y; wire a, b; always @ ( a or b) begin y = a & b; end endmodule

SYNTHESIS OUTPUT

This gives the same output as that of the assign statement, with the only difference that y is declared as reg. There are distinct advantages to have reg modeled as combinational element; reg type is useful when a "case" statement is required (refer to the Verilog section for more on this). To model a sequential element using reg, we need to have edge sensitive variables in the sensitivity list of the always block. Reg data type as Sequential element 1 module reg_seq_example( clk, reset, d, q); 2 input clk, reset, d;

3 4 5 6 7 8 9 10 11 12 13 14 15

output q; reg q; wire clk, reset, d; always @ (posedge clk or posedge reset) if (reset) begin q