UNIT - V

Computer Architecture and Microprocessor 

UNIT - V Introduction The primary function of the microprocessor (MPU) is to accept data from input devices such as keyboards and A/D converters, read instructions, and send the results to output output devices devices such such as LEDs, LEDs, printe printers, rs, and video video mon monit itors ors.. These These input input and output output devices are called either  peripherals or  I / Os; memory can be viewed as a special type of I / O. Designing logic circuits (hardware) and writing instructions (software) to enable the microprocessor to communicate with these peripherals is called interfacing , and the logic circuits are called I / O ports or interfacing devices . The microprocessor (MPU) communicates with the peripherals in either of two formats: asynchronous or  synchronous . Similarly, it transfers data in either of two modes: parallel I / O or  serial I / O . The 8085 identifies peripherals either as memory mapped I / O or peripheral I / O based on their interfacing logic circuits. In peripheral I / O, peripheral is identified with an 8-bit address. The 8085 has two instructions – IN and OUT – to implement data transfer between the microprocessor  and peripherals. These are 2-byte instructions; the second byte specifies the address or the  port number of a peripheral. The instruction IN transfers (copies) data from an input device to the accumulator, accumulator, and the instruction instruction OUT transfer’ transfer’ss data from accumulator accumulator to an output device.

5.1

Objective

This lesson provides you the detailed study about 8080A and 8085 interrupt, Concepts Concepts of serial serial I/O, Synchronous and Asynchronous Asynchronous transmission transmission,, Programmabl Programmablee inte interf rfac acee devi device ces, s, 8185 8185/8 /818 186 6 prog progra ramm mmab able le I/O I/O port portss and and time timerr and and the the 8279 8279 Progra Programma mmable ble Keyboa Keyboard/ rd/Dis Displa play y interf interface. ace. Toward Towardss end of this this lesson lesson student student can understand the applications of microprocessors and a temperature monitoring system.

5.2

Content

5.2. 5.2.1 1

Thee 8080 Th 8080A A Inte Interr rrup uptt

The 8080A interrupt process is controlled by the Interrupt Enable flip-flop, which is internal internal to the processor processor and can be set or reset by using software software instructio instructions. ns. If the flip-flop is enabled and the input to the interrupt signal INT (pin 14) goes high, the microproces microprocessor sor is interr interrupted. upted. This is is a maskable maskable interrupt interrupt and can be disable disabled. d. The 8080A has only one interrupt signal; signal; it does not have a nonmaskable interrupt. The 8085 has an interrupt signal called INTR (pin 10), functionally identical with the 8080A interr interrupt upt.. Howeve However, r, the 8085 8085 has additi additional onal inter interrup ruptt signals signals as well well.. To avoid avoid confusion, we will refer to the interrupt process that is common to both the processors as the 8080A interrupt. The best way to describe the 8080A interrupt interrupt process is to compare compare

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Computer Architecture and Microprocessor  it to a telephone with a blinking light instead of a ring. Assume that you are reading an interesting novel at your your desk where there is a telephone. In order for you you to receive and respond to a telephone call, the following steps should occur. 1. The telepho telephone ne system system should should be enable enabled, d, meaning meaning that the recei receiver ver should should be on the hook. 2. You should should glance glance at the light light at certain certain interv intervals als to check check whether whether someone someone is calling. 3. If you see see a blinking blinking light, light, you should should pick up the receive receiver, r, say hello, hello, and wait for  for  a response. response. Once you pick up the phone, the the line is busy, busy, and no more calls can  be received until you replace the receiver. 4. Assuming Assuming that the the caller caller is you roommat roommate, e, the request request may be: be: It is going going to rain rain today. Will you please shut all the windows in my room? 5. You inse insert rt a bookm bookmark ark on the the page page you are are readin reading. g. 6. You replac replacee the the recei receiver ver on the the hook  hook  7. You shut you yourr roomm roommate’ ate’ss window windows. s. 8. You go back your your book, find your your mark, mark, and start start reading reading again. again. Steps 6 and 7 may be interchanged, depending on the urgency of the the request. If the request is critical and you do not want to be interrupted while attending to the request, you like to attend to the request first, first, then put the receiver back on the hook. The 8080A interrupt process can be described in terms of those eight steps. Step 1: writing the instruction EI in the main program should enable the interrupt process. This is similar similar to keeping keeping the phone receiver receiver on the hook. The instructio instruction n EI sets the Interr Interrupt upt Enable Enable flip-f flip-flop lop.. The instruct instruction ion DI resets resets the flip-f flip-flop lop and disabl disables es the interrupt process. Instruction EI (Enable Interrupt) 1. This This is is a 1-byt 1-bytee instr instruct uction ion.. 2. The instruc instructio tion n sets sets the Interr Interrupt upt Enable Enable flip-f flip-flop lop and enables enables the interru interrupt pt  process.. 3. System System reset or an interrupt interrupt disable disabless the interr interrupt upt process process.. Inst nstruct ructio ion n DI (Di (Disa sabl blee Int Interr errupt upt) 1. This This is is a1-b a1-byt ytee inst instruc ructi tion. on. 2. Th Thee inst instru ruct ctio ion n rese resets ts the the Inte Interr rrup uptt En Enab able le flip flip-f -flo lop p and and disa disabl bles es the the interrupt. 3. It should should be inclu included ded in a program program segmen segmentt where an inter interrup ruptt from an outside source cannot be tolerated. Step 2: When the microprocessor is executing a program, it checks the INT line (INTR in the 8085) during the execution of each instruction. Step 3: If the line INT is high and the interrupt is enabled, the microprocessor completes the current instruction, disables the Interrupt Enable flip-flop and sends a signal called

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Computer Architecture and Microprocessor  INTA – Interrupt Acknowledge (active low). The processor cannot accept any interrupt interrupt requests until the interrupt flip-flop is enabled again. Step 4: The signal INTA is used to insert an instruction, preferably, a restart (RST) instruction, through additional additional hardware. The RST instruction is a 1-byte call call instruction (explained below) that transfers the program control to a specific memory location on  page 00H and restarts the execution at that memory location after executing Step 5. Step 5: If the microprocessor receives an RST instruction, it saves the memory address of  the next instruction instruction on the stack. stack. This is similar to inserting a bookmark. bookmark. The program is is transferred to the CALL location. Step 6: Assuming that the task to be performed is written as a subroutine at the specified location, the processor performs the task. This subroutine is known as a service routine. Step 7: The service routine should include the instruction EI to enable the interrupt again. This is similar to putting the receiver back on the hook. Step 8: At the end of the subroutine, the RET instruction retrieves the memory address where where the program program was interru interrupte pted d and continue continuess the executio execution. n. This This is similar similar to finding the page where you interrupted by the phone call and continuing to read. We will elaborate further on the restart instructions and additional hardware mentioned in Step 4. RST (RESTART) INSTRUCTIONS The 8085/8080A instruction set includes eight RST (Restart) (Restart) instructions. instructions. These are 1 byte Call instructions and a nd transfer the program execution to a specific location on page 00H, as listed in Table 5.1. Table 5.1 Restart Instructions Hex Code

Binary Code Mnemonics

RS T 0 RS T 1 RS T 2 RS T 3 RS T 4 RS T 5 RS T 6 RS T 7

D7 D6

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1

D5

D4

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

D3 D2 D1

D0

0 1 0 1 0 1 0 1

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1

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C7 CF D7 DF E7 EF F7 FF

Call Location in Hex

0 0 00 0 00 8 0 01 0 0 0 18 0 0 20 0 02 8 0 030 0 0 38

Computer Architecture and Microprocessor  To implement Step 4 in the interrupt process, insert one of these instructions in the micr microp opro roce cess ssor or by usin using g exte extern rnal al hard hardwa ware re and and the the sign signal al INTA INTA (Int (Inter erru rupt pt Acknowledge), as shown in Figure 5.1.

Fig 5.1 A circuit to implement the Instruction RST 5

Fig 5.2 8085 Timing of the Interrupt Acknowledge Machine Cycle an Execution

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Computer Architecture and Microprocessor  In Figure 5.1, the instruction RST 5 is built using resistors and a tri-state buffer. Figure 5.2 shows the timing of the 8085 Interrupt Acknowledge machine cycle. In response to the INTR (Interrupt Request) high signal, the 8085 send the INTA (Interrupt Acknowledge) low signal, which is used to enable the buffer, and the RST instruction is  placed on the data bus during M1. During M1, the program counter holds the memory address of the next instruction, which should be stored on the stack so that the program can continue after the service routine. During M2, the address of the stack pointer minus one (SP – 1) location is placed on the address bus, and the high-order address of the  program counter is stored on the stack. During M3, the low-order address of the program counter is stored in the next location (SP – 2) of the stack. The machine cycle M1 of the interrupt acknowledge is identical with the Opcode Fetch cycle, with two exception. The INTA signal is sent out instead of the RD signal, and the status lines (IO/M, S0 and S1) are ! 1 1 instead of 0 1 1 (see Figure 12.2). During M1, the RST 5 is decoded, a 1-byte Call instruction to location 0028H. The Machine cycles M2 and M3 are Memory Write Cycles that store the contents of the program counter on the stack, and then a new instruction cycle begins. In this next instruction cycle, the program is transferred to location 0028H. However, there are only eight memory locations available for RST 5 if RST 6 is being used in the system; RST 6 begins at 0030H. If the service routine requires more than eight locations, the routine is written somewhere else in R/W memory, and the Jump instruction is written at 0028H to specify the address of the service routine. 5.2.2

The 8085 Interrupts

The 8085 has five interrupt inputs (Figure 5.3). One is called INTR, which is identical with the INT input in the 8080A. The other four are automatically vectored (transferred) to specific locations on memory page 00H without any external hardware. They do not require the INTA signal or an input port; the necessary hardware is already implemented inside the 8085. These interrupts and their call locations are as follows: Interrupts

1. 2. 3. 4.

Call Locations

TRAP RST 7.5 RST 6.5 RST 5.5

0024H 003CH 0034H 002CH

The TRAP has the highest priority, followed by RST 7.5, 6.5, 5.5, and INTR, in that order.

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Computer Architecture and Microprocessor 

Fig 5.3 The 8085 Interrupts and Vector Locations

TRAP TRAP, a nonmaskable interrupt known as NMI, is analogous to the smoke detector  described earlier: It has the highest priority; it need not be enabled; and it cannot be disabled. It is level and edge sensitive, meaning that the input should go high and stay high to be acknowledged. It cannot be acknowledged again until it makes a transition from high to low to high. Figure 5.3 shows that when this interrupt is triggered, the program control is transferred to location 0024H without any external hardware or the interrupt enable instruction EI. TRAP is generally used for such critical events as power failure and emergency shut-off. RST 7.5, 6.5,and 5.5 These maskable interrupts (shown in Figure 5.4) are enabled under program control with two instructions: EI (Enable Interrupt) described earlier, and SIM (Set Interrupt Mask) described below: Instruction.

SIM: Set Interrupt mask 

1. This is a 1-byte instruction.

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Computer Architecture and Microprocessor  2. This instruction reads the contents of the accumulator and enables or disables the interrupts according to the contents of the accumulator. 3. Bits D7 and D6 of the accumulator are used for serial I/O and do not affect the interrupts. D6 = 1 enables the serial I/O. 4. Bit D3 is a control bit and should = 1, in order for bits D 0, D1, and D2 to be effective. Logic 0 in D0, D1, and D2 will enable the corresponding interrupts, and logic 1 will disable the interrupts. 5. Bit D4 is additional control for the RST 7.5. If D4 = 1, the RST 7.5 flip-flop is reset. This is used to override RST 7.5 without servicing it.

Fig 5.4 Interpretation of the Accumulator Bit Pattern

The mnemonic SIM is confusing. The wording – Set Interrupt Mask – implies that the instruction masks the interrupts. However, the instruction must be executed in order to use the interrupts. The process required to enable these interrupts can be likened to a switchboard controlling three telephone extensions in a company. Let us assume these  phone extensions are assigned to the president (RST 7.5), the vice-president (RST 6.5) and the manager (RST 5.5), in that priority, and are monitored by their receptionist according to the instructions given. The protocols are placing a telephonic call to one of  the executives and of interrupting the microprocessor using RST 7.5, 6.5, and 5.5 can be compared as follows: Placing a telephone call

Interrupting 8085 (Figure 5.4)

1. The switchboard is functional and all telephones lines are open.

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1. The interrupt process is enabled. The instruction EI sets the Interrupt Enable flip-flop, and one of the inputs to the AND gates is set to logic 1 (Figure 5.3). These AND gates activate the program

Computer Architecture and Microprocessor  trans ransffer to locations.

var various ious

vect vector ored ed

2. All ex executives le leave in instructions on th the receptionist’s desk as to whether they wish to receive any phone calls.

2. An An app apprropr opriate bi bit pa pattern ern is is loaded into the accumulator.

3. The recepti ptioni onist reads the inst nstructions.

3. If bit D3 = 1, the respective interrupts are enabled according to  bits D2 – D0

4. The receptionist is on duty, and send calls through for whomever is available.

4. RST 7.5, 6.5, and 5.5 are being Monitored.

5. The receptionist is busy typing. Phone calls can be received directly According to previous instructions.

5. If bit D3 = 0, bits D2 – D0 have no effect on previous conditions.

6. No calls for the president now. Call back later.

6. Bit D4 = 1, this resets RST 7.5

This analogy can be extended to the interrupt INTR, which is viewed as one telephone line shared by eight engineers with a switchboard operator (external hardware) who rings the appropriate extension. The entire interrupt process (except TRAP) is disabled by resetting the Interrupt Enable flip-flop (Figure 5.3). The flip-flop can be reset in one of the the three ways: by instruction instruction DI, system Reset, or by recognition of an interrupt request. Figure 5.3 shows that these three signals are ORed and the output of the OR gate is used to reset the flip-flop. TRIGGERING LEVELS These interrupts are sensitive to different types of triggering as listed below: 1. RST RST 7.5. 7.5.

This This is posi positi tive ve edge edge sensit sensitive ive and and can can be trigg triggere ered d with with a short short puls pulse. e. The request is stored internally by the D flip-flop (Figure 5.3) until the microprocessor responds to the request or until it is cleared by Reset or by  bit D4 in SIM instruction.

2. RST 6.5 and RST 5.5. These interrupts are level sensitive, meaning that the trigger triggering ing level level sho should uld be on until until the micro microproc process essor or comple completes tes the execution execution of the current instructi instruction. on. If the microprocess microprocessor or is unable to respond to these requests immediately, they should be stored or held by external hardware. Example . Enable all the interrupts in an 8085 system. Instructions.

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Computer Architecture and Microprocessor 

EI ;Enable Interrupts MVI A, A, 08H ;Load ;Load bit patt pattern ern to to enable enable RST RST 7.5, 7.5, 6.5 and and 5.5 SI M ;Enable RST 7.5, 6.5 and 5.5 Bit D3 =1 in the accumulator makes the instruction SIM functional, and bits D2, D1 and D0 = 0 enable the interrupts 7.5, 6.5 and 5.5 Example .

Rese Resett the the 7.5 7.5 inte interr rrup uptt fro from m prev previo ious us Ex Exam ampl plee Instructions MVI MVI A, A, 18H 18H ;Set Set D4 D4 = 1 SI M ;Reset 7.5 interrupt flip-flop

PENDING INTERRUPTS Because there are several interrupt lines, when one interrupt request is being served, other  interrupt requests may occur and remain remain pending. The 8085 has an additional instruction instruction called RIM (Read Interrupt Mask) to sense these pending p ending interrupts.

Accumulator Bit Pattern for the RIM Instruction Fig 5.5. Interpretation of the Accumulator Inst Instru ruct ctio ion n

RIM: RIM: Read Read Int Inter errrupt upt Mas Mask  k 

1. This This is is a1-byt a1-bytee inst instruc ructi tion on 2. This instruct instruction ion loads the the accumulator accumulator with eight eight bits indicati indicating ng the current current status status of the interrupts masks, the the interrupt enable, pending interrupts, and serial input data. See Figure 5.5. Assuming the microprocessor is completing an RST 7.5 interrupt request, check to see if  RST 6.5 is pending. pending. If it is pending, pending, enable enable RST 6.5 without without affect affecting ing any other  other  interrupts; otherwise, return to the main program.

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Computer Architecture and Microprocessor 

Instructions

 NEXT:

RIM MOV B,A ANI 20H JNZ NEXT EI RET MOV A, B ANI 0DH ORI 08H SIM JMP JM P SER SERV V

;Read interrupt mask. ;Save mask info nformation ;Check whe whetther RS RST 6. 6.5 is is pending

;RST 6.5 is not pending, return to main program. ;Get bit patter, RST 6.5 is pending. ;Enables RST 6.5 6.5 by setting D1 = 0. ;Enable SIM by setting D3 = 1 ;Jum ;Jump p to to ser servi vice ce rout routin inee for for RST RST 6.5 6.5

The instruction RIM checks for for a pending interrupt. Instruction ANI 20H masks all the  bits except D5 to check pending RST 6.5. If D5 = 0, the program control is transferred to the main program. program. D5 = 1 indicates that RST 6.5 is pending. Instruction ANI 0DH sets D1 = 0 (RST 6.5 for SIM), instruction ORI sets D3 = 1 (this is necessary for SIM to be effective), and instruction SIM enables RST 6.5 without affecting any other interrupts. The JMP instruction transfers the program to the service routine (SERV) written for RST 6.5. 5.2. 5.2.3 3

Conc Concep epts ts in Seri Serial al I/O I/O

The basic concepts concerning the serial I/O mode can be classified into the categories as shown; they will be discussed in the following sections. 1. 2. 3. 4. 5.

I/O I/O req requi uire reme ment ntss Alph Alphan anum umer eric ic cod codes es Tran Transm smis issi sion on form format at Serial Serial transm transmiss ission ion standa standards rds Softwa Software re vs. progra programm mmabl ablee hardware hardware approac approaches hes

I/O Requirements The 8085/8080A MPU identifies a serial I/O peripheral in the same manner that it identifies any other peripheral – through a decoder port address and the control signals IOR and IOW. The control control signal IOR is used to receive receive data, IOW is used to transmit transmit data, as shown in Figure 5.6. Similarly, the memory-mapped I/O technique can be employed using the memory-related control signal MEMR and MEMW. MEMW. The primary differences between parallel parallel I/O and

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Computer Architecture and Microprocessor 

Fig 5.6 Block Diagram: Serial I/O and Control Signals

serial I/O are the number of data lines and the number of bits transferred by the I/O instruction instructions. s. The 8085/8080A MPU can transfer transfer bits serially under various various conditions conditions depending depending upon the type of peripheral peripheral and its interfacing interfacing logic. logic. Serial Serial I/O data transfer  can be unconditional, with the status check, or with the interrupt. Alphanumeric Codes A comput computer er is a bina binary ry mach machin ine; e; in order order to comm communi unicat catee with with the the comp comput uter er in alphabetic letters and decimal numbers, translation codes are necessary. The commonly used code known as ASCII, the American Standard Code for for Information Interchange. Interchange. It 7 is a 7-bit code with 128(2 ) combinations, and each combination from 00H to 7FH is assigned to a letter, a decimal number, a symbol, symbol, or a machine command. For example, hexadecimals 30H to 39H represent numerals 0 to 9; 41H to 5AH represent capital letter  A through Z; 21H to 2FH represent various symbols; and the initial codes 00H to 1FH represent machine commands such such as Carriage Return Return (CR) or Line Feed (LF). Devices that use ASCII characters include ASCII terminals, teletype machine (TTY), and printers. When the key 9 is pressed on an ASCII terminal, the computer receives 39H in binary, and the system programs translate ASCII characters into appropriate binary or BCD numbers. Another code, called EBCDIC (Extended Binary Coded Decimal Interchange Code), is widely used in IBM computer. This is an 8-bit code representing 256 combinations; however, several combinations are not being used. Transmission Format A transmission format is concerned with issues such as synchronization, direction of data flow, speed, errors, and medium of transmission (telephone lines for example).

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Computer Architecture and Microprocessor  5.2.4

Synchronous Vs. Asynchronous Transmission

Serial communication occurs either in synchronous or asynchronous format. In the asynchronous format, a receiver and a transmitter are synchronized; a block of characters is transmitted along with the synchronization information, as in Figure 16.2(a). This format is generally used for high-speed transmission (more than 20k bits/second).

Fig 5.7 Transmission Format: Synchronous (a) and Asynchronous (b)

The asynchronous format is character-oriented. Each character carries the information of  the START and the STOP bits, shown in Figure 5.7(b). When no data are being transmitted, a receiver stays high at logic 1, called MARK; logic 0 is called SPACE. Transmission begins with one START bit (low), followed by a character and one or two STOP bits (high). This is also known as framing. Figure 5.7(b) shows the transmission of eleven bits for an ASCII character in the asynchronous format: one START bit, eight character bits, and two STOP bits. The format shown in Figure 5.7(b) is similar to Morse code, but the dots and dashes are replaced by logic 0s and 1s. The asynchronous format is generally used in low speed transmission (less than 20 k bits/second.) SIMPLEX AND DUPLEX TRANSMISSION Serial communication also can be classified according the direction and simultaneity of  data flow.

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Computer Architecture and Microprocessor  In simplex transmission, data are transmitted in only one direction. A typical example is the transmission from a microcomputer to a printer. In duplex transmission, data flow in both directions. However, if the transmission goes one way at a time, it is called half duplex; if it goes both ways simultaneously, it is called full duplex. Generally, transmission between two computers or between a computer and a terminal is full duplex. PARITY CHECK  During transmission, data bits may change (e.g., because of noise) and a receiver may receive a wrong character. The MSB bit in the ASCII code can be used to check an error; this process is called parity check. To check the parity, the transmitter simply counts whether the number of 1s in a character  is odd or even, and transmits that information to the receiver as the MSB bit. The receiver checks the MSB bit and the number of 1s in the received character. If there is an error, the receiver sends back an error message to the transmitter. The parity check can be either odd or even, depending upon the system. In an odd parity system, when a character has an even number of 1s, bit D7 is set to 1 and an odd number  of 1s is transmitted. For example, the code for the character G is 47H (01000111) with four 1s. When the character G is transmitted in an odd parity system, the transmitter will set bit D7 to 1, making the code C7H (11000111). On the other hand, the character I (49H = 01001001) has three 1s; when the character I is transmitted, bit D7 is set to 0, keeping the code 49H. The parity check cannot detect multiple errors in any given character. The 8085/8080A microprocessor sets a parity flag when the number of 1s in the accumulator is even. This flag can be used for the parity check in an 8085/8080A system. BAUD The rate at which the bits are transmitted – bits/second – is called a baud in serial I/O; however, technically, it is defined as the number of signal changes/second. Each piece of  equipment has its own baud requirement. For example, a teletype (TTY) generally runs on a 110 baud. However, in most terminals and printers, the baud is adjustable, typically, in the range of 50 to 9600 baud. MODEM A modem (Modulator / Demodulator) is a circuit that translates digital data into audio tone frequencies for transmission over telephone lines an converts audio frequencies into digital data for reception. The modulation technique generally used is called frequency

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Computer Architecture and Microprocessor  shift keying (FSK); it converts logic 1 (MARK) and logic 0 (SPACE) into audio tones around 1200 and 2000 Hz frequencies.

Fig 5.8 Communication between Two Computers Using Modems

Computers can exchange information over telephone lines by using two modem – one on each side (Figure 5.8). A calling computer (or a terminal) contacts a receiving computer  through a telephone number, and a communication link is established after control signals have been exchanged between computers and modems. A typical process of communication is shown in Figure 5.8. A parallel word is converted into serial bits; in turn, they generate two audio frequencies according to logic 0 or 1, and these audio frequencies are transmitted over telephone lines. At the receiving end, audio frequencies are converted back into 0s and 1s, and serial bits are converted into a parallel word that can be read by the receiver computer. 5.2.5

Programmable Interface Devices

A programmable interface device is designed to perform various input/output functions. Such a device can be set up to perform specific functions by writing an instruction (or  instructions) in its internal register, called the control register. Furthermore, functions can be changed anytime during execution of the program by writing a new instruction in the control register. These devices are flexible, and multifunctional. They are widely used in microprocessor-based products. The I/O functions of a programmable device are determined through software instructions. The MPU writes an appropriate instruction (or instructions) in the device to define its I/O functions. The functions performed by the interfacing I/O devices, are as follows: 1. A latch is used as an output port to hold and display data. 2. A tri-state buffer is used as an input port to read data from devices such as a keyboard or data converters.

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Computer Architecture and Microprocessor  3. A tri-state buffer is used as a 1-bit input port to check the status and determine whether  the device is ready to input data. 4. An interrupt signal can be generated by an interfacing device. Therefore, a programmable device should include at least these functions in its hardware. In addition, it should have control logic, chip select logic, and a register (or registers) in which to write an instruction for defining its hardware functions. The programmable I/O device is likely to have the following elements: 1. A control register in which the MPU can write an instruction. 2. A status register that can be read by the MPU. 3. I/O devices or registers. 4. Control logic. 5. Chip Select logic. 6. Bidirectional data bus. 7. Handshake signals and Interrupt logic. A programmable I/O device is programmed by writing a specific word, called the control word, according to the internal logic; its status can be verified by reading the status register. This I/O device can be expanded to include elements such as multiple I/O ports, counter, and parallel to serial register. The 8155 and the 8355 are two multipurpose programmable devices specifically designed to be compatible with the 8085 microprocessor. The ALE, IO/M, RD, and WR signals from the 8085 can be connected directly to these devices; this eliminates the need for  external demultiplexing of the low-order bus AD7 - AD0 and generation of the control signals such as MEMR, MEMW, IOR and IOW. The 8155 includes 256 bytes of R/W memory, three I/O ports, and a timer. The 8156 is identical with 8155, except that the 8156 requires Chip Enable (CE) active high. The 8355 includes 2K of ROM and two I/O ports. The 8755 is similar to the 8355, except that the 8755 is EPROM. The programmable I/O sections of these devices are illustrated in the following sections. 5.2.6

The 8155/8156 Programmable I/O Ports and Timer

The 8155/8156 is a device with two sections: the first is 256 bytes of R/W memory, and the second is a programmable I/O. Functionally, these two sections can be viewed as two independent chips. The I/O section includes two 8-bit parallel I/O ports (A and B), one 6-bit port (C), and a timer (Figure 5.9). All the ports can be configured simply as input/output ports -- similar to the 8212. Ports A and B also can be programmed in the handshake mode, each port using three signals as handshake signals from port C. The

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Computer Architecture and Microprocessor  timer is a 14-bit down-counter and has four modes. Pins PA, PB, and PC, shown in Figure 5.9, correspond to ports A, B, and C.

Fig 5.9 8155 Pin Configuration and Block Diagram

CONTROL LOGIC The control logic of the 8155 is specifically designed to eliminate the need for externally demultiplexing lines AD7 -- AD0 and generating separate control signals for memory and I/O. Figure 14.5 shows five control signals; all except the Chip Enable (CE) are input signals directly generated by the 8085. 1. CE -- Chip Enable: This is a master Chip Select signal connected to the decoded highorder bus.

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Computer Architecture and Microprocessor  2. IO/M -- When this signal is low, the memory section is selected, and when it is high the I/O section (including timer) is selected. 3. ALE -- Address Latch Enable: This signal latches the low-order address AD7 -- AD0, CE, and IO/M into the chip. 4. RD and WR -- These are control signals to read from and write into the chip registers and memory. 5. RESET -- This is connected to RESET OUT of the 8085 and this resets the chip and initializes I/O ports as input. THE 8155 I/O PORTS The I/O section of the 8155 includes a control register, three I/O ports, and two registers for the timer (Figure 5.10). The 8155 I/O section requires three address lines -- AD2 to AD0 and the Chip Enable logic to specify one of the seven registers. In addition, two control signals, RD and WR, are necessary to read from and write into these I/O registers.

Fig 5.10

Expanded Block Diagram of the 8155 (a) and Its I/O Address: Selection (b)

To communicate with peripherals through the 8155 the following steps are necessary: 1. Determine the addresses (port numbers of the registers and I/Os) based on the Chip Enable logic and address lines AD0, AD1, and AD2. 2. Write a control word in the control register to specify I/O functions of the ports and the timer characteristics. 3. Write I/O instructions to port addresses to communicate with peripherals.  Page 182

Computer Architecture and Microprocessor  4. Read the status register, if necessary, to verify the status of the I/O ports and the timer. In simple applications, this step is not necessary. CHIP ENABLE LOGIC AND PORT ADDRESSES Address lines AD2 to AD0, also shown as A2 to A0 after internal demultiplexing, select one of the registers as shown in Figure 5.10(b). Address A3 to A7 are don't care lines; however, the logic levels on the corresponding high-order lines, A11 to A15, will be duplicated on lines A3 to A7, as explained in the next example. Example 1. Determine the addresses of the control/status register, I/O ports, and timer  registers in Figure 5.11

To select the chip, the output line O4 of the 8205 (3-to-8) decoder (Figure Solution . 5.11) should go low. Therefore, the logic levels of A15 to A11 should be as follows: A15 0

A14 0

A13 1

Enable lines of the 8205

A12 0

A11 0

Input logic to activate the output line 4 of the 8205

By combining five high-order address lines with three low-order address lines (A 2 - A 0), the port numbers in Figure 14.8 will range from 20H to 25H, as shown below. A15 A14 A13 0 0 1 status register 

A12 0

A11 0

AD2 0

AD1 0

AD0 Addresses Ports 0 = 20H -- Control

A3

0 0 0 1 1

0 1 1 0 0

1 0 1 0 1

(2H) A7

A6

A5

A4

= = = = =

21H -22H -23H -24H -25H --

or

Port A Port B Port C Timer (LSB) Timer (MSB)

This raises a question: How is it possible to combine five high-order address lines with three low-order address lines to generate a port address? To find an answer to this question, examine the execution of either the IN or OUT instruction. When these instructions are executed, the high-order and low-order address buses carry the same information. In this case, the logic levels required on lines A15 to A11 for the Chip Enable are also duplicated on the address lines from A7 through A3, as shown above.

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Computer Architecture and Microprocessor 

Fig 5.11 Interfacing 8155 I/O Ports

CONTROL WORD Writing a control word in the control register can configure the I/O ports and the timer. The control register bits are defined as shown in Figure 5.12. In this control word, outputs are defined with logic 1 and inputs with logic 0. The first two LSBs, D0 and D1, determine I/O functions of ports A and B; and the MSBs, D 7 and D6, determine timer functions. Bits D4 and D5 are used only in the interrupt mode to enable or disable internal flip-flops of the 8155. These bits do not have any effect on the Interrupt Enable flip-flop (INTE) of the MPU. The next section shows an application of the 8155 to design two output ports for the SDK-85 system. An application of the 8155 in the handshake mode is illustrated later. Illustration: Interfacing Seven-Segment LED Output Ports Using the 8155 PROBLEM STATEMENT 1. Design two seven-segment LED displays using ports A and B of the 8155. 2. Write initialization instructions and display data bytes at each port. HARDWARE DESCRIPTION Figure 5.13 shows two seven-segment output ports: port A with the Hewlett Packard HP 5082/7340, and port B with the Fairchild FND 507, and 9370. The HP 5082 includes an internal decoder/driver, while the FND 507 is driven by a separate decoder/driver 9370.

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Computer Architecture and Microprocessor 

Fig 5.12 Control Word Definition in the 8155 (a) and Table of Port C Bit Assignments (b)

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Computer Architecture and Microprocessor 

Fig 5.13 Interfacing 8155 I/O Ports with Seven-Segment LEDs

Both are functionally similar; however, a seven-segment display with an internal built-in decoder/driver is more expensive. The decode logic is the same as that used in the previous discussion; therefore, the port addresses are as follows: Control Register = 20H Port A = 21H Port B = 22H CONTROL WORD To configure ports A and B as outputs, the control word is as follows:

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Computer Architecture and Microprocessor  D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

1

1

= 03H

Port A Output Port B Output No effect Not on timer Applicable

Port C is not being used for  handshake

PROGRAM MVI A, 03H OUT 20H MVI A, BYTE1 OUT 21H MVI A, BYTE2 OUT 22H HLT

; Initialize ports A and B as output ports.

; Display BYTE1 at port A. ; Display BYTE2 at port B.

PROGRAM DESCRIPTION The instruction MVI A, 03H initializes ports A and B as simple output ports, and the following instructions display data BYTE1 and data BYTE2 at ports A and B, respectively. The 8155 Timer

The timer section of the 8155 has two 8-bit registers; fourteen bits are used for counter, two bits for the timer mode, and it requires a clock as an input. This 14-bit down-counter   provides output in four different modes, as described below. Figure 5.14 (a) shows two registers for a 14-bit count, one for LSB (low significant byte) and one for MSB (most significant byte). The most significant bits M2 and M1 are used to specify the timer mode.

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Computer Architecture and Microprocessor 

Fig 5.14 Timer Loading Format (a) and Modes (b)

To operate the timer, a 14-bit count and mode bits are loaded in the registers. An appropriate control word starts the counter, which decrements the count at each clock   pulse. The timer outputs vary according to the mode specified (Figure 5.14(b)). The timer can be stopped either in the midst of counting, or at the end of a count (applicable to Modes 1 and 3). In addition, the actual count at a given moment can be obtained by reading the status register. These details will be described later. Illustration: Designing a Square Wave Generator Using the 8155 Timer  PROBLEM STATEMENT Design a square wave generator with a pulse width of 100 µs by using the 8155 timer. Set up the timer in Mode 1 if the clock frequency is 3 MHz. Use the same decode logic and the port addresses as in Example1 (Figure 5.11).

 Page 188

Computer Architecture and Microprocessor  PROBLEM ANALYSIS Timer Count. The pulse width required is 100 µs; therefore, the count should be calculated for the period of 200 µs. The timer output stays high for only half the count. Clock Period = 1/f = 1/3 x 106 = 330 ns Timer Count = Pulse Period / Clock Period = 200 x 10-6 / 330 x 10-9 = 606 Count =

025EH

Assuming the same decode logic for the 8185 Chip Enable line as in Example 1, the port addresses for the timer registers are Timer LSB = 24H Timer MSB = 25H The least significant byte, 5EH (of the count 025EH), should be loaded in the timer  register with address 24H. The most significant byte is determined as follows: M2 0

M1 1

T13 0

T12 0

Timer Mode 1

T11 0

T10 0

T9 1

T8 0

= 42H

MSB

Therefore, 42H should be loaded in the timer register with the address 25H. Assuming the same configuration for ports A and B as before, only Control Word.  bits D7 and D6 should be set to 1 to start the counter (see control word definition in Figure 14.8). Therefore, Control Word: 1100 0011 = C3H Initialization Instructions

MVI A, 5EH OUT 24H MVI A, 42H OUT 25H MVI A, C3H OUT 20H HLT

; LSB of the count ; Load the LSB timer register   ; MSB of the count ; Load the MSB timer register   ; Start the timer  

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Computer Architecture and Microprocessor 

The 8185 I/O Ports in Handshake Mode In the handshake mode, data transfer occurs between the MPU and peripherals using control signals called handshake signals. Two I/O ports of the 8155, A and B, can be configured in the handshake mode; each uses three signals from port C as control signals (Figure 5.15). Another alternative (ALT 3 in the Table in Figure 5.12) available in the 8155 is to configure port A in the handshake mode with three control signals from port C; configure port B as simple I/O; and configure the remaining three bits of port C as outputs. The details of configuring ports A and B in the handshake mode by using the  pins of port C are given below.

Fig 5.15 8155 with Handshake Mode

CONTROL SIGNALS IN HANDSHAKE MODE When both ports A and B are configured in the handshake mode, port A uses the lower  three signals of port C (PC0, PC1, and PC2), and port B uses the upper three signals (PC3, PC4, and PC5) as shown in Figure 5.15. The functions of these signals are as follows: 1. STB (Strobe Input) : This is an input handshake signal from a peripheral to the 8155. The low on this signal informs the 8155 that data are strobed into the input port. 2. BF (Buffer Full) : This is an active high signal, indicating the presence of a data byte in the port. 3. INTR (Interrupt Request) : This signal is generated by the rising edge of the STB signal if the interrupt flip-flop (INTE) is enabled. This signal can be used to interrupt the MPU. 4. INTE (Interrupt Enable) : This is an internal flip-flop used to enable or disable the interrupt capability of the 8155. Bits D4 and D5 control the interrupts for port A and port B, respectively, in the control register. These control signals can be used to implement either interrupt I/O or status check I/O. INPUT Figure 5.16(a) shows the sequence of events and timing in data input to the 8155; they can be described as follows:

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Computer Architecture and Microprocessor 

1. An external peripheral places data in the input port and informs the 8155 by causing the STB signal to go low.

Fig 5.16 Timing Waveforms of the 8155 I/O Ports with Handshake: Input Mode (a) and Output Mode (b)

2. The falling edge of the STB sets signal BF (Buffer Full) high, informing the peripheral to wait. 3. When the STB goes high, the rising edge of the STB can generate signal INTR if the internal interrupt flip-flop INTE is set. The interrupt flip-flops are set or reset by the control word. 4. The last step is to transfer data from the 8155 input port to the MPU. This can be done either by interrupting the MPU with the INTR signal or by checking the status of signal BF. The MPU can check the status by reading the status register (described later). When the MPU reads data, the INTR and BF signals are reset. When the BF signal goes low, it informs the peripheral that the port is empty, and the device is ready for the next byte.

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Computer Architecture and Microprocessor 

OUTPUT The sequence of events and timing in data output from the 8155 port to a peripheral are as follows (see Figure 5.16(b)); 1. When the output port is empty, the MPU writes a byte in the port. 2. The falling edge of WR signal resets the INTR signal and the rising edge sets the BF (Buffer Full) signal high, which is used to inform the peripheral that a byte is available in the port. 3. After receiving the data byte, the peripheral acknowledges by sending the STB signal (active low). 4. The STB signal resets the BF signal low and generates the interrupt request by setting INTR high. Now the MPU can be informed by the interrupt signal to send the next byte, or the MPU can sense that the port is empty through status check. STATUS WORD The MPU can read the status register to check the status of the ports or the timer. The control register and the status register have the same port address; they are differentiated only be the RD and WR signals. The status register bits are defined in Figure 5.17.

Fig 5.17 Status Word Definition

Illustration: Interfacing I/O Ports in Handshake Mode Using the 8185

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Computer Architecture and Microprocessor 

PROBLEM STATEMENT Design an interfacing circuit using the 8155 to read and display data from an A/D converter to meet the following requirements: 1. Set up port A in the handshake mode to read data from an A/D converter. 2. Set up port B as an output port to display data at seven-segment LEDs. 3. Use line PC3 from port C to initiate a conversion. 4. Use the same decode logic as in Example 14.2 (Figure 14.7) to assign I/O port addresses. 5. Use the 8155 timer to record the conversion time. PROBLEM ANALYSIS Figure 5.18 shows an interfacing circuit that uses the 8155 I/O ports as follows: 1. Port A is configured as an input port in the handshake mode for reading data from the A/D converter. 2. Port B is configured as a simple output port for seven-segment LEDs. 3. The upper half of port C is a simple output port, and bit PC 3 is being used to start conversion. 4. The lower half of port C provides handshake signals for port A. Bit PC2 is being used as a strobe (STB) to inform the 8155 that the conversion is complete and that the output of  the converter has been placed in port A. INPUT WITH STATUS CHECK  The circuit shows that the INTR signal (bit PC0) is not being used. This suggests that  port A is configured for status check and not for interrupt I/O. Therefore, the control word (see Figure 5.12) required to set up the ports as specified above and the masking  byte to check the Data Ready (DR) line are as follows: Control Word

D7 0

D6 0

Do not affect counter Input operation

D5 0

D4 0

D3 0

Interrupts are are not being used

D2 1

D1 1

D0 0

= 06H

Port A =

Port B = Output Port CH = Output

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Computer Architecture and Microprocessor  ALT3

Port CL = Handshake signals

Fig 5.18 Interfacing the A/D Converter AD570 in the Handshake Mode Status Word. The MPU needs to check bit D1 of the status register to verify the end of  conversion and the availability of data in port A. The status word will have the following information (see Figure 14.13):

D7

D6

D5

D4

D3

D2

D1

D0

X

X

X

X

X

X

BFA

X

Timer INTEB BFB

INTR B INTEA

INTR A

When the status word is masked with byte 02H, the availability of a data byte in port A can be verified.

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Computer Architecture and Microprocessor 

8155 TIMER 

The timer can be used to calculate the conversion time. When a conversion begins, the timer should be started with a known count, and at the end of conversion the timer should  be stopped. The difference between the two counts multiplied by the clock period of the timer should provide a fairly accurate reading of the conversion time. To start the timer, set bits D 7 and D6 of the control register to 1 without affecting the other   bits of the register. Therefore, to start the timer, the control word should be: =

1

1

0

Start Timer

0

0

1

1

0

=

C6H

1

0

=

46H

I/O Assignments

To stop the timer, the control word should be: 0

1

Stop Timer

0

0

0

1

I/O Assignments

PORT ADDRESSES The decode logic is the same as in Example 1; therefore, the I/O port addresses range from 20H (control register) to 25H (Timer -- MSB).

PROGRAM MVI A, 06H OUT 20H MVI A, 00H OUT 24H OUT 25H MVI A, 08H OUT 23H MVI A, C6H OUT 20H MVI A, 00H

Control word for I/O ports Set up ports as specified Load 0000H in the timer registers

Byte to set PC3 = 1 Send START pulse Control word to start timer  Start timer   Byte to set PC3 = 0

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Computer Architecture and Microprocessor 

STATUS:

OUT 23H IN 20H ANI 02H JZ STATUS MVI A, 46H OUT 20H IN 21H OUT 22H IN 24H MOV L, A IN 25H ANI 3FH MOV H, A LHLD RWM

Start conversion Read status register   Check status of DR   If BFA = 0, wait in the loop until a data byte is available Byte to stop counter  Stop counter   Read A/D converter output Display data at port B Read LSB of timer count Save timer count in register L Read MSB of timer count Delete D7 and D6 from the MSB; they represent timer mode Save MSB timer count in H Store timer count from HL register in R/W memory locations

HLT

PROGRAM DESCRIPTION The comments are self explanatory; however, some explanation is needed for the timer  count, start conversion (convert) pulse, and status check. The program loads 0000H in the timer register, and after the first decrement, the count  becomes 3FFFH. This is a 14-bit counter, with bits D15 and D14 reserved to specify the mode. However, in this particular problem, the counter mode is irrelevant. This program assumes that the A/D conversion time is less than time period given by the maximum count. The difference between the initial count and the final count will provide the necessary value to calculate the conversion time. The program does not perform this subtraction; it just stores the final count in two consecutive memory locations labeled as RWM. The second item needing explanation is the start conversion (convert) pulse. This is an active high pulse provided by turning on and off bit PC3 in port C. Finally, instruction IN 20H reads the status register, and instructions ANI 02 and JZ check whether the buffer in port A (BFA) is full. The program stays in the loop until the BFA goes high, indicating the availability of data. INTERRUPT I/O This example illustrates all the important I/O operations of the 8155 except the interrupt I/O in the handshake mode. To implement the interrupt I/O in the above example, the INTR A -- the output bit PC0 -- should be connected to a vectored interrupt such as RST 6.5 and the control word should be changed accordingly.

 Page 196 

Computer Architecture and Microprocessor  5.2.7

Interfacing the 8355/8755 Programmable I/O Ports

The 8355/8755 is a 2K-byte (2048 x 8) memory with two I/O ports; each I/O line of the  ports can be programmed either as input or output. The 8355 is ROM and the 8755 is EPROM Figure 5.19 shows: (a) the block diagram of the 8755, and (b) the internal control registers called Data Direction Registers (DDR). Each bit in the DDR registers controls the corresponding bit in the I/O ports. The port addresses of the DDR registers and I/O  ports are determined by the Chip Enable (CE) logic and address lines AD0 and AD1. The table, Figure 14.15(c) shows the logic levels required for address lines AD0 and AD1 to select a port. These logic levels are combined with CE logic to determine the port addresses, as explained below. Figure 5.20 is a schematic from the SDK-85 system. The interfacing logic shows the 3to-8 decoder; its output line 0 is connected to the CE signal of the 8755. To select the 8755, the logic on the address lines should be as follows: A15/ AD7

A14/ AD6

A13/ AD5

A12/ AD4

A11/ AD3

AD2

AD1

AD0

0

0

0

0

0

X

0 0 1 1

0 1 0 1

Selected Register  = 00 = 01 = 02 = 03

A B DDR A DDR B

The logic levels on the high-order address lines (A15 -- A11) are duplicated on the loworder address lines (AD7 -- AD3). Each bit of port A and port B can be programmed by writing control words in their  respective DDR registers; logic 0 in a DDR register specifies input mode for the corresponding bit in the I/O port. For example, byte F0H in the DDR A specifies that lines PA0 to PA3 are inputs and lines PA4 to PA7 are outputs.

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Computer Architecture and Microprocessor 

Fig 5.19

8755 Block Diagram (a), Data Direction Register (b), and I/O Selection Table (c)

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Computer Architecture and Microprocessor 

Fig 5.20 Interfacing the 8755 I/O Ports Example 2. Write initialization instructions to configure port A and port B as output  ports, and display 32H at port A. Instructions

MVI A, FFH OUT 02H OUT 03H MVI A, 32H OUT 00H HLT 5.2.8

; Control word to set up all bits as output bits ; Initialize port A as output ; Initialize port B as output ; Display 32H at port A

The 8279 Programmable Keyboard/Display Interface

The 8279 is a hardware approach to interfacing a matrix keyboard and a multiplexed display. There is a software approach to interfacing a matrix keyboard and a multiplexed display of seven-segment LEDs. The disadvantage of the software approach is that the microprocessor is occupied for a considerable amount of time in checking the keyboard and refreshing the display. The 8279 relieves the processor from these two tasks. The disadvantage of using the 8279 is the cost. The trade-offs between the hardware approach and the software approach are the production cost vs. the processor time and the software development cost. The 8279 (Figure 5.21) is a 40-pin device with two major segments: keyboard and display. The keyboard segment can be connected to a 64-contact key matrix. Keyboard entries are debounced and stored in the internal FIFO (First-In-First-Out) memory, while an interrupt signal is generated with each entry. The display segment can provide a

 Page 199

Computer Architecture and Microprocessor  sixteen-character scanned display interface with such devices as LEDs. This segment has 16 x 8 R/W memory (RAM), which can be used to read/write information for display  purposes. The display can be set up either in right-entry or left-entry format.

Fig 5.21 The 8279 Logic Pinout

Block Diagram of the 8279 The block diagram (Figure 5.22) shows four major sections of the 8279: keyboard, scan, display, and MPU interface. The functions of these sections are described below.

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Computer Architecture and Microprocessor 

Fig 5.22 The 8279 Logic Block Diagram

KEYBOARD SECTION This section has eight lines (RL0 -- RL7) that can be connected to eight columns of a keyboard, plus two additional lines: Shift and CNTL/STB (Control/Strobe). The status of  the SHIFT key and the Control key can be stored along with a key closure. The keys are automatically debounced, and the keyboard can operate in two modes: two-key lockout or N-key rollover. In the two-key lockout mode, if two keys are pressed almost simultaneously, only the first key is recognized. In the N-key rollover mode, simultaneous keys re recognized and their codes are stored in the internal buffer; it can also be set up so that no key is recognized until only one key remains pressed. The keyboard section also includes 8 x 8 FIFO (First-In-First-Out) RAM. The FIFO RAM consists of eight registers that can store eight keyboard entries; each is then read in the order of entries. The status logic keeps track of the number of entries and provides an IRQ (Interrupt Request) signal when the FIFO is not empty. SCAN SECTION The scan section has a scan counter and four scan lines (SL 0 -- SL3). These four scan lines can be decoded using a 4-to-16 decoder to generate sixteen lines for scanning.

 Page 201

Computer Architecture and Microprocessor  These lines can be connected to the rows of a matrix keyboard and the digit drivers of a multiplexed display. DISPLAY SECTION The display section has eight output lines divided into two groups, A 0 - A3 and B0 - B3. These lines can be used, either as a group of eight lines or as two groups of four, in conjunction with the scan lines for a multiplexed display. The display can be blanked by using the BD line. This section includes 16 x 8 display RAM. The MPU can read from or write into any of these registers. MPU INTERFACE SECTION This section includes eight bidirectional data lines (DB 0 - DB7), one Interrupt Request line (IRQ), and six lines for interfacing, including the buffer address line (A0). When A0 is high, signals are interpreted as control words or status; when A0 is low, signals are interpreted as data. The IRQ line goes high whenever data entries are stored in the FIFO. This signal is used to interrupt the MPU to indicate the availability of data. PROGRAMMING THE 8279 The 8279 is a complex device that can accept eight different commands to perform various functions. The discussion here is specific to the circuit in the SDK-85 system. The initialization commands can specify 1. left or right entry and key rollover. 2. clock frequency prescaler. 3. starting address and incrementing mode of the FIFO RAM. 4. RAM address to read and write data and incrementing mode. 5. blanking format. In order to illustrate important command words, the next section will illustrate the keyboard/display circuit from the SDK-85 system.

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Computer Architecture and Microprocessor 

ILLUSTRATION: SDK-85 KEYBOARD SCHEMATIC

Fig 5.23 SDK – 85 Keyboard / Display Circuit

CIRCUIT DESCRIPTION Figure 5.23 shows the following components: 1. The 8279 Programmable Keyboard/Display Interface. 2. A matrix keyboard with 22 keys. 3. Six seven-segment LEDs: DS1 - DS6. (Only one is shown; other five are identical). 4. The 74LS156 decoder with open collector outputs. 5. Transistors as current drivers. 6. The 8205 decoder for the decoding logic.

 Page 203

Computer Architecture and Microprocessor  Lines RL0 - RL7 (Return Lines) of the 8279 are connected to the columns of the matrix keyboard, and the output lines (A0 - A3 and B0 - B3) are connected to drive the LED segments through the transistors. The three scan lines are connected to the decoder, the 74LS156, to generate eight decoded signals. In this circuit, six output lines of the decoder are connected as digit drivers to turn on six seven-segment LEDs; two output lines are unused. In addition, the first three output lines are also used to scan the rows of  the keyboard. The 8279 has four scan lines that can be decoded to generate sixteen output lines to drive sixteen displays. The data lines of the 8279 are connected to the data  bus of the 8085, and IRQ (Interrupt Request) is connected to the RST 5.5 of the system. Four signals -- RD, WR, CLK, and RESET OUT -- are connected directly from the 8085. The system has a 3.072 MHz clock; and when the 8279 is reset, the clock prescaler is set to 31. This divides the clock frequency by 31 to provide the scan frequency of  approximately 100 kHz. The RESET signal also sets the 8279 in the mode of sixteen character display with two-key lockout keyboard. After the initialization of the 8279, the respective codes are sent to the display RAM to display any characters. The 8279 takes over the task of displaying the characters by outputting the codes and digit strobes. To read the keyboard, the 8279 scans the columns; if a key closure is detected, it debounces the key. If a key closure is valid, it loads the key code into the FIFO, and the IRQ line goes high to interrupt the system. DECODING LOGIC AND PORT ADDRESSES The port addresses of the 8279 registers are determined by two signals: CS and A0. The CS signal of the 8279 is connected to the CS-3 output of the 8205 decoder, and A0 is directly connected to the address line A8 of the 8085. For commands and status, and A0 should be high. For data transfer, A0 should be low. By examining the decoder input lines and assuming logic 0 for the don't care address lines, one can determine that the port addresses are as follows: A15 0

A14 0

Decoder Enable

A13 0

A12 1

A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 0 0 I/O 0 0 0 0 0 0 0 0

Decoder Input

Command/Status Port: Data Port :

Don't Care

A0 of   8279

=

1900H/1800H

Don't Care

1900H 1800H

INITIALIZATION INSTRUCTIONS In the SDK-85 system, the 8279 is initialized for the keyboard/display mode: Two-key Lockout; Left Entry; and 8-bit, 8-Character Display. The RESET signal sets the clock 

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Computer Architecture and Microprocessor   prescaler to 31; thus, the scan frequency is approximately 100 kHz. When the 8279 detects a key closure, the IRQ signal interrupts the 8085, using RST 5.5. The interrupt service routine sends the command word to read from the keyboard (Command Port 1900H), reads the character data from the keyboard (Data Port 1800H), and stores it in the input buffer of the system's R/W memory. The following instructions illustrate the initialization and the interrupt-service routine. Initialization MVI A, 00H Control word to set mode: Left entry, 8-character, 2-key lockout encoded scan keyboard STA 1900H Initialize 8279

Keyboard/Display Mode 0 0 0 D D K K K 

Interrupt Routine to Read Keyboard PUSH H PUSH PSW LXI H, 1900H Keyboard control register address MVI M, 40H Control word to read from keyboard DCR H Data Port Address 1800H MOV A, M

Read FIFO RAM: Control Word 0 1 0 A1 X A A A

Read data D7

ANI 3FH

STA IBUFF POP PSW POP H RET

Mask D7 and D6. CNTL, Shift keys are not being used Store in R/W memory

Data Format D6 D5 D4

D3

D2

D1

CNTL SHFT ROW

D0 COL

To display characters, the routine determines whether it is displaying a 4-digit memory address or a 2-digit data value. Then it sends the control word to read the display RAM. For example, to display a 4-digit memory address, the control word instructions are as follows: MVI A, 90H Control word to write starting at first RAM Write Display RAM Control Word location STA 1900H 1 0 0 A1 A A A A MVI A, CODE Load seven-segment code

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Computer Architecture and Microprocessor  STA 1800H

Output the code

To display a 2-digit data value, the control instructions are as follows: MVI A, 94H : Control word to display data STA 1900H In this example, the control word 94H points to the fifth memory location in the display RAM; the first four locations are reserved for memory addresses.

5.2.9

Applications Of Microprocessors

INTRODUCTION Since the advent of the µP in 1971, its application domain has been expanding rapidly. This trend will definitely continue especially in the wake of the fact that new µPs and µCs with superior performance are now available to the system designer, e.g. Intel’s 80386,80196, Motorola’s MC68030, M68CH11A8, NEC’s 7800 series of  microcontrollers. The purpose of this chapter is to familiarize the reader with a variety of application areas of  µPs. Obviously, it is not possible to present each application in detail. We have therefore presented a brief description of several application areas and one application in detail. The application presented in detail is that of a temperature monitoring system for  which the detailed software and hardware design is also presented. 5.2.10

A Temperature Monitoring System

One of the application areas of  µPs is process control. In a typical process control application, the µP continuously monitors one or more process variables and generates outputs to the electro-mechanical elements which in turn control the process variables. This kind of control is known as closed loop control. If the µP outputs the control variables to human operators, via displays or line printers, who in turn apply the necessary control inputs, then the control strategy is known as open loop control. In this section we shall present an example to illustrate the use of a µP in open loop process control. To illustrate, we shall use the 8085 as the control µP. For simplicity, only one  process variable, namely the temperature at a point, will be monitored and displayed. We shall present the detailed software and hardware design. SYSTEM REQUIREMENTS It is required to design a µP-based open loop control system that monitors a process temperature and displays it on a four-digit seven-segment display. The system should have the facility to input, from a human operator, the lower and upper limits of the temperature being monitored. If at any moment these limits are violated, one of the two  Page 206 

Computer Architecture and Microprocessor  suitable alarms must be set. The alarms in our case are two LED displays. One of these indicates that the temperature has violated the upper limit (the H1 alarm). The other LED indicates that the temperature has violated the lower limit (the LO alarm). OVERALL SYSTEM DESIGN The complete system can be partitioned into three distinct subsystems: 1. Processor and memory subsystem 2. Input subsystem

3. Output subsystem We have decided to use the 8085 µP as the control processor. We use the 2716A, 2K   byte EPROM, for the program and fixed data storage. For storing stacks and other  variable data, we use the 6116A, 2K byte static RAM. We use the 8255A Programmable Peripheral Interface, described earlier in Chapter 7, to get the necessary ports for  interfacing various I/O devices. The counters in the 8254 Programmable Interval Timer  chip are used to provide the two timers needed in our application.

THE INPUT SUBSYSTEM In order to satisfy the design requirements, the µP should be able to input the following variables: 1. temperature, and 2. low and high limits.

The temperature may be converted to an analog voltage by means of a suitable transducer  and this output applied to an ADC. The output of the ADC may be read by the µP when desired. We assume that successive temperature readings are to be taken

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Computer Architecture and Microprocessor 

Figure 5.24: Operator panel for temperature monitoring system.

with a minimum of 50 ms inter-reading gap. A transducer that can be used if the temperature being measured is within the range of –55°C to +150°C, is the Analog Devices’ AD590. It has a wide power supply range of +4 V to +30 V. It generates a current output of 1 µA/Kelvin. For example, at 25°C, the output current is 298 µA. There are several ways in which the low and high limits may be set and read by the µP. We shall use a very simple scheme described below. Assume that a switch is provided which may be closed by the operator to indicate to the µP whether limit setting is desired or not. Call this as the SET LIMIT switch. Another  switch, called the LO/HI switch, can be used to indicated whether lower or upper limit is

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Computer Architecture and Microprocessor  to be set. Using sixteen LIMIT switches, divided into groups of four each, may set the limit itself. Thus, the operator using the BCD code may set a four-digit limit. When the operator desires to change a limit, the following sequence of actions should be  performed: 1. Set a 4-digit limit on the sixteen LIMIT switches. Note that these must be BCD digits. 2. Set the LO/HI switch to LOW (close it) or HIGH (open it) depending on which limit is to be set. 3. Close the SET LIMIT switch. After the processor recognizes the set limit request, it will read the limit from the LIMIT switches and acknowledge this fact by turning on an LED display named LIMIT SET. At this point, the SET LIMIT switch may be opened. If it remains closed, the µP scans it again after, approximately, 15s and, if found closed, resets the appropriate limit. The LED display is turned off approximately 5s after it was turned on. Fig. 5.24 exhibits the operator panel with all these switches and the output displays. In this figure, the output produced by the output subsystem is also shown. All switches shown are of the simple toggle type. THE OUTPUT SUBSYSTEM The output subsystem should be able to display the value of the temperature on a 4-digit 7-segment display. When required, the alarms LO or HI must be appropriately set. We assume that the temperature display is updated when sixteen reading have been accumulated. The average of these readings is displayed. As the output is displayed using four digits, the µP may display the successive digits one  by one at a rate that would not impair the readability of the display. It would be sufficient to display the next digit 50 ms after the previous one. Thus, in a total of about 200 ms, all the digits would be displayed once in the cycle. This rate is high enough to keep the flicker in the display once in the cycle. This rate is high enough to keep the flicker in the display within tolerance. The advance of using the display in a multiplexed mode is that only one digit driver would be required at a slight increase in software complexity. After obtaining the average temperature reading, the µP should check whether the temperature is within limits or not. If not, then appropriate alarm lamp should be turned on, otherwise, any ON lamp must be turned off. Fig. 5.25 shows a block diagram of the system we plan to design. Fig. 5.26 and Fig. 5.27 show the flow charts embodying the overall algorithm that must be executed by the 8085 in order to achieve the desired design objectives. In the design of these flow charts,

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Computer Architecture and Microprocessor 

Fig 5.25: Block diagram of a microprocessor-based temperature monitoring system

it is assumed that timers will be used for interrupting the µP to indicate the two conditions – time to input limits and time to turn off the LIMIT-SET lamp. HARDWARE DESIGN Let us begin the detailed hardware design of the system. To begin with, we assume that we shall not require more than 2K bytes of EPROM and 2 K bytes of RAM. This decision is difficult to make so early in the design when the software has not been designed. However, we postpone a discussion on this aspect to the end of this section. Thus, we require one 2716A and one 6116A. We can now assign addresses to these chips. As the 8085 jumps to location 0 when it is reset, we must have at least one instruction stored at this location. Generally, this instruction is a jump to an initialization routing for the application. This implies that location 0 must be in EPROM. Thus, we may assign addresses 0-2047 to the bytes in the 2716A and addresses 2048-4095 to the  bytes in the 6116A static RAM. To design the address decoding circuitry, we have selected the 11 least significant bits of  the 16-bit address for each memory chip. Bit A11 selects one of the two memory chips. Fig. 5.28 shows this assignment.

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Computer Architecture and Microprocessor  With this assignment, the chip select signals can be generated using an 74LS138 decoder  as shown in Fig. 5.29. Note that bits A12, A13, A14, and A15 must all be 0 for the decoder to be enabled. This ensures that each memory byte has a unique address. INPUT/OUTPUT SUBSYSTEM DESIGN For data input from the operator panel, the ports available in the 8255A are used. Similarly, some of the ports are used for data output to LED’s. Table 5.1 shows all the  port assignments for the two 8255A chips used in our design. We need to generate two timing signals in our system. One of these is a signal, with a  period 0f 15 s, for scanning the SET LIMIT switch. The other signal has a period of 5 s and is used for turning off the LED display that indicates that the limit set by the operator  has been recognized by the µP. We use the Intel 8254 timer chip to generate these two signals. The address assignment for different ports and the timer chip appear in Fig. 5.30(a). Fig. 5.30(b) shows how the chip select signals can be generated using one 74LS138. Notice that the IO/M signal has been used to ensure that when the address on the address bus is from the memory, only the 74LS138 in Fig. 5.30(b) is enabled, and when it is for a port or a timer, then only the 74LS138 in Fig. 5.30(b) is enabled. As the 8254 has not been described earlier, let us examine it before using it in our design. THE 8254 PROGRAMMABLE INTERVAL TIMER  General description The 8254 is a 40 pin programmable interval timer from Intel. It has three independent 16-bit counters which are referred to as counter 0, counter 1, and counter 2. Each counter  can be programmed to operate in any one of five different operating modes. The  programming is done by writing a command word into the control word register of the 8254. Each counter can count at a rate that depends on its own input clock. Depending on which version of the 8254 is used, the counting can be done at a rate as low as DC to as high as 10 MHz. For example, the 8245-5 can count at a maximum rate of 5 MHz.

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. Fig 5.26 Temperature monitoring and display algorithm

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Computer Architecture and Microprocessor 

Fig 5.27 Flow Chart of subroutine to read limits.

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INPUT AND OUTPUT SIGNALS Fig. 5.31 shows the input and output signals available in the 8254. The data bus D0-D7 is used for sending programming information to the 8254 and obtaining status of the counters. The WR and RD inputs indicate, respectively, a write or a read operation. When asserted, the CS input select the chip. The A0 and A1 inputs select one of three counters or the control register in the 8254. Table 5.2 lists the combinations of RD, WR, A0, A1 and CS signals and the corresponding read/write operations. The respective counters to count down use the CLK inputs. The rate at which a counter  counts, depends on the corresponding input CLK signal. Counting can be suspended by negating the GATE input of the counter. The OUT signal depends on the mode in which a counter has been programmed to operate.

Fig 5.28 Address assignment for EPROM and RAM

MODES OF OPERATION Though the 8254 provides five different modes of operation for the counters, we shall describe only mode 0. We shall use mode 0 in our design. When programmed to operate in mode 0, a counter generates an interrupt on terminal count. The entire operation, from loading the counter to the generation of the interrupt,  proceeds as follows: 1.

2.

The control word is written into the control register. This should specify that a counter, say counter 0, is to operate in mode 0. Writing the control word forces OUT 0 to go low. The initial count is written to the counter. This count can be programmed to  be a 16-bit or an 8-bit value.

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Table 5.1. Port and Timer Assignment

Chip No. Port No.

8255A #1

Input or Output

Function

PA0 – PA3 Input Digit 1 limit PA4 – PA7 Input Digit 2 of limit PA0 – PA3 Input Digit 3 of limit PA4 – PA7 Input Digit 4 of limit PC1 Input LO/HI switch input PC0 Input SET LIMIT switch input

8255 A #2 PA0 – PA3

Output

PC0 PC1 PC2 – PC5

Output Output Output

PC6 PB0

Output Output

One digit, in BCD, to be displayed HIGH alarm display LOW alarm display Cathode of seven-segment display LIMIT SET Blanking input Of 7448 seven-segment driver 

All ports or port pins not mentioned are unused

Fig 5.29 Generation of chip select signals for memory

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Computer Architecture and Microprocessor 

Fig 5.30 (a) Address assignment and (b) chip select signals for I/O ports and c ounters.

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Computer Architecture and Microprocessor  Table 5.2. Read/Write Operations in 8254

3. 4.

5.

CS

RD

WR

A1

A0

0 0 0 0 0 0 0 0 1 0

1 1 1 1 0 0 0 0 X 1

0 0 0 0 1 1 1 1 X 1

0 0 1 1 0 0 1 1 X X

0 1 0 1 0 1 0 1 X X

Operation

Write to counter 0 Write to counter 1 Write to counter 2 Write to control word Read from counter 0 Read from counter 1 Read from counter 2 No-operation, data bus tri-stated No-operation, data bus tri-stated No-operation, data bus tri-stated

Count-down begins one clock pulse after the count has been written into the counter. If GATE 0 is high, then counter 0 counts down. For each CLK 0 pulse, counter 0 decrements by 1. If GATE 0 is low, countdown is inhibited. Countdown resumes when GATE 0 goes high. When the counter reaches 0, which is the terminal count, OUT 0 goes high. OUT 0 remains high until a new count is written or the counter is reprogrammed with the control word.

The above operation sequence is identical for all the three counters. Note that the counter  does not stop after the count has reached 0. It wraps around to 0FFFFH and continues the countdown. In some other modes, the counter gets reloaded to the count that was loaded initially. Thus mode 0 can be used to interrupt a µP. The time delay before an interrupt is generated after the counter has been loaded, can be controlled by the value loaded into the counter. Note that a count of 0 leads to the maximum delay. It corresponds to a total count of 216 CLK pulses. Thus, if the clock period is 320 ns and the counter is loaded with a count of 0, then OUT will go high 216 x 320 ns = 20.972 ms after the counter was loaded. PROGRAMMING THE 8254 The control word format for the 8254 appears in Fig. 5.32. As an example of how to set the control word, assume that we desire to use counter 0 (a) in mode 0, (b) as a binary counter, and (c) as a 16-bit counter. The control word can be set to: 00 11 00 0. Setting the RW0 and RW1 bits to 11 implies that counter 0 must be loaded with a 16-bit count. The count itself is sent to the counter in two steps. First, the least significant byte is sent followed by the most significant byte.

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Computer Architecture and Microprocessor 

Fig 5.31 Signals in the 8254

Writing data to the 8254 can be accomplished using the OUT instruction of the 8085. Bits A0 and A1 of the port address specified in this instruction will determine the destination of the data as shown in Table 5.2. USING THE 8254 IN OUR DESIGN We shall use counter 0 of the 8254 for read limit and counter 1 for turning off LIMIT SET display timing. The OUT 0 output can be connected to the RST 7.5 input of the 8085. Thus, when OUT 0 goes high, implying that counter 0 has reached the terminal count, the 8085 will be interrupted. Later, we describe how this interrupt is processed.

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Computer Architecture and Microprocessor 

Fig 5.32 Control word format for the 8254 timer. Table 5.3: Memory, Port, and Timer Addresses

Chip No.

Type

Address

2716A 6116A 8255A #1

EPROM Static RAM Port A Port B Port C Control word register Port A Port B Port C Control word register Counter 0 Counter 1 Control word register

0000-07FFH 08FFH-0FFFH 0 1 2 3 4 5 6 7 12 13 15

8255A #2

8254

The OUT 1 output is connected to the RST 5.5 input of the 8085. Thus when counter 1 reaches the terminal count, the 8085 will be interrupted. Recall that RST 7.5 input is rising edge sensitive and the RST 5.5 input is high level sensitive. Thus, after OUT 1 goes high, and the RST 5.5 interrupt has been processed, the 8085 will be interrupted

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Computer Architecture and Microprocessor  immediately after the interrupts are enabled unless OUT 1 goes low before the interrupts are enabled. The software described later takes care of this problem. INTERFACING THE SWITCHES AND LED’S Fig. 5.33 shows the design of the I/O subsystem excluding the ADC. The limit switch  positions are input directly as shown in Fig. 8.10. The 1 K resistors are for limiting the supply current when the switches are closed (note that if these resistors were not present, the supply VCC would be shorted when the switch is closed). In the open state, a 1 and in the closed state a 0 is read from the corresponding pins.

Fig 5.33 Port A (input) limit digits (note that all other input ports are to be connected as in this figure and therefore are not shown here.).

An N7448 BCD-seven segment Decoder/Driver drives the 7-segment display. The 7448 is used in multiplexed mode. Its outputs a – g are always connected to the anodes of all the digit segments. The common cathode of each digit is driven separately through port C pins. Thus, for example, if digit 1 is to be displayed, its cathode should be driven low. Making transistor T1 conduct by driving its base low can do this. Thus PC0 should be set to 1 if digit 1 is to be displayed.

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Computer Architecture and Microprocessor  The 7437 NAND gates, used here as buffers by tying the input signal to both the inputs,  provide the required current for driving the 7-segment display. The 7437 has an IOH of –  1.2 mA and an IOL of 48 mA, which is sufficient to drive most LED displays. The chip selects inputs of the 8255A chips are connected to the 74LS138 decoder outputs as shown in Fig. 5.11.

Fig 5.34 Seven segment display hardware.

Fig 5.35 Alarm and LIMIT SET display hardware

ANALOG INPUT To input the analog signal corresponding to the temperature, we shall use the AD 7820 ADC. The complete interface including the A/D converter and the temperature transducer is shown in Fig. 5.36.  Page 221

Computer Architecture and Microprocessor 

Fig 5.36

A/D converter and temperature transducer interface

The AD7820 has been interfaced using I/O mapped I/O. The 74LS138 decoder generates the chip select signal. The O4 output of the 74LS138 selects the AD7820. See Fig. 5.11 for the decoder circuit. Evidently, there are several addresses that will select the ADC. The reader can find out all the other addresses and ensure that they do not overlap with the memory and I/O ports. The RDY output of the ADC drives the READY input of the 8085. As the conversion time in the RD-mode is about 1.6 µs, it is essential for the RDY signal to be connected to the 8085. With the circuit shown in Fig. 5.36, any 8085 instruction that can read a byte from an I/O port can be used to read the digital data from the ADC. The temperature transducer interface is quite simple. We know that the AD590 generates 1µA current per Kelvin. Over the temperature range of this transducer, the generated current will vary from 218 µA to 423µA. These numbers can be obtained easily be noticing that –55°C to +150°C corresponds to 218 Kelvin to 423 Kelvin. A 10 K Ω resistance shown in Fig. 5.36 will force the VIN of the ADC to vary between approximately 2.18 V to 4.23 V. This corresponds to approximately half the full scale range of the ADC which is 5 V. If we set the VREF (-) input of the ADC to 2.18 V, then the ADC will output all zeroes when the input temperature is approximately –55°C. However, for economy of components, we shall not do so. The least significant bit of the ADC output corresponds to approximately 19 mV. Thus, an input of 2.18 V will result in approximately. (2.18/19 mV ~ 01101110B)

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Computer Architecture and Microprocessor  as the digital output of the ADC. approximate digital output of:

Similarly, an input of 4.23 V will result in an

(4.23/19 mV ~ 11100000B) The BINBCD routine can use this data to transform the digital output of the ADC to the corresponding temperature reading to be displayed. Note that as we are using an 8-bit ADC, we need only three digits to display the temperature. However, as we have used for 7-segment displays, the BINBCD routine must always generate the fourth, or the highest order digit, to be 0. That completes the hardware design of the temperature monitoring system. Figure 5.42 gives the complete design for an overview by the reader. We shall now design the software without which all the hardware designed so far would not work as desired. SOFTWARE DESIGN As is evident from the flow charts presented earlier, the complete software may be  partitioned into the following subroutines. 1. INIT – for initializing program variables immediately after system RESET. 2. DISPLAY – for displaying the next digit of the current average value of  temperature. It is called once each time the main loop shown in Fig 8.3 is executed. 3. UPDATE – for computing the average value of the temperature. It is invoked after sixteen readings have been accumulated. 4. RLIMITS – for reading new limit values, if desired by the operator. Called when an interrupt occurs. It reads only one limit at a time, high or low, at 15s intervals. 5. LAMPOFF – for putting off the lamp that was turned on to indicate that a limit has been read from the input switches. It is called when an interrupt occurs or after the lamp has been turned ON. The lamp is turned off 5 s after  it was turned ON. 6. DELAY – for creating a 50 ms delay before the next temperature reading. 7. ATOD – for getting one temperature reading and assigning it to variable RDNG. In addition to these subroutines, several other subroutines are required one for converting an input BCD number to equivalent binary and another for converting a binary number (average temperature) to BCD. We shall refer to these as BCDBIN and BINBCD subroutines, respectively. The other subroutine requirements will arise as we develop the software. We shall now design each of the above subroutines and the main program. In order that these subroutines are readable; we shall use symbolic addresses for various I/O ports and

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Computer Architecture and Microprocessor  devices in the IN, OUT, and other instructions. These symbols can be equated to their  numeric values using the EQU statements at the beginning of the program. All these statements are given below. These may be referred to while reading the program that follows. ;*Temperature monitoring program.* ;*Ports, device, and data address equates.* CR1 PORTA1 PORTB1 PORTC1

EQU 3 EQU 0 EQU 1 EQU 2

;Control register of 8255 #1 ;Port A of 8255A # 1 ;Port B of 8255A #1 ;Port C of 8255A #1

CR2 PORTA2 PORTB2 PORTC2

EQU 7 EQU 4 EQU 5 EQU 6

;Control register of 8255 #2 ;Port A of 8255A #2 ;Port B of 8255A #2 ;Port C of 8255A #2

CWR CNTR0 CNTR1 LCRS

EQU

;Control word register of 8254 12 ;Counter 0 of 8254 13 ;Counter 1 of 8254 ;Address of AD7820

15 EQU EQU EQU 16

; Address of the list of cathode addresses. DADDR LSADDR

EQU DIGITS ;First cathode address. EQU DDIGITS ;LSD address.

DATAL

EQU

RDNG

;Address of the temperature reading.

INITIALIZATION: THE INIT ROUTINE Several variables and I/O ports are to be initialized before the infinite loop in the main  program begins. We shall first initialize various ports and timers by a subroutine named INIT. The variables shall be initialized in the main program using DB and DW statements. All ports must be initialized to be in modes specified in Table 5.1. The command words for 8255A #1 and 8255A #2 are given in Fig. 5.37(a) and (b). The control word for the two counters inside the 8254 appears in Fig. 5.37(c). Note that in Fig. 5.37(c), altering the leftmost two bits from 00 to 01 changes the control word for counter 0 to that for  counter 1.

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Computer Architecture and Microprocessor 

Fig 5.37 Command word for (a) 8255A#1 (b) 8255A#2 (c) Control word for the 8254

The command words may be assigned the symbols CWR1 and CWR2 for the two 8255A chips and CCWR0 an CCWR1 for the two counters, respectively. These symbols can be defined as shown below. ; *Command words for I/O ports and timer* CWR1 CWR2

EQU EQU

1 00 11011B ;8255A # command word 1 00 00000B ;8255A # 2 command word

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Computer Architecture and Microprocessor  CCWR0 CCWR1

EQU EQU

00 11 000 1B ;Control word for counter 0 01 11 000 1B ;Control word for counter 1

; Next two bytes are to turn the LIMIT set lamp on or off. BLMSET LLMSET

EQU EQU

00000 0 0B 00000 1 0B

BHALRM LHALRM BLALRM LLALRM

EQU 000000 0B EQU 000000 1B EQU 000000 0B EQU 000001 0B

;Bit 6 is 0 to blank the LIMIT SET lamp. ;Bit 6 is 1 to light the LIMIT SET lamp. ;Bit 0 is 0 to turn off the H1 alarm ;Bit 0 is 1 to turn on the H1 alarm ;Bit 1 is 0 to turn off the LO alarm ;Bit 1 is 1 to turn on the H1 alarm

INITIALIZING THE TIMERS The mode bits for both the counters in the 8254 are set to 00 which implies that each counter will generate a pulse on reaching the terminal count. The counter will continue counting after reaching the terminal count. In our case, as the initial count is 0, each counter will begin counting from 0FFFFH after it has reached the terminal count for the first time. Recall that counter 0 is used for getting the 15s delay between two successive limit settings. Counter 1 is used for deriving the 5s delay after which the LIMIT SET lamp is turned off. Counter 1 should be stopped after resetting the lamp. Counter 0 must be started immediately after all variables have been initialized. Counter 1 should be started immediately after the LIMIT SET lamp is turned ON. Note that the counters should be programmed first and only then any command issued to them. STARTING AND STOPPING THE COUNTERS Immediately after the control word has been writing into the control register, the corresponding OUT line goes low. This does not affect any 8085 interrupt input. When the initial count has been written into the counter, the counter starts counting. For  counter 0, this approach is acceptable. It keeps counting down and generates an interrupt on the RST 7.5 input. After reaching the terminal count, it begins counting again. However, we would like to start counter 1 only when the 5s delay is desired. This implies that once the counter has interrupted the 8085, it should be stopped and started again only when the LIMIT SET lamp is to be reset. How can we stop the counter and synchronize it with the software? This can be done by sending only the low byte of the count to counter 1. When this low byte is received by counter 1, it stops and waits for the high byte to arrive. The high byte can be sent when the counter needs to be started. This is the procedure used in the INIT routine described below. We can now write the INIT subroutine as given below.

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Computer Architecture and Microprocessor 

;*Subroutine to initialize I/O ports and the timer.* ; INIT; MVI OUT MVI OUT MVI OUT CALL CALL EI RET

A, CWR1 CR1 A, CWR2 CR2 A, BLMSET PORTC2 RALARM STCNTR0

;Get 8255A #1command word ;Get 8255A #2 command word ;Get byte to blank the LIMIT SET lamp. ;Send to port C of 8255 #2 ;Reset alarms. ;Start counter 0. ;Enable interrupts ;End of subroutine.

;*Subroutine to program the 8254 and initialize counters.* ; STCNTR0: MVI A, CCWR0 OUT CWR 

;Get counter 0 command word.

; Send count (=0) to counter 0. This will start the counter. MVI A, O OUT CNTR0 OUT CNTR0 RET

; Get low byte of initial count. ; Send low byte to counter 0. ; Send high byte to counter 0.

; Program counter 1 by sending only the ; control word and the low byte of the count for counter 1. PRCNTR1: MVI A, CCWR1 OUT CWR 

; Get counter 1 command word.

; Send only the low byte to counter 1. This will force ; the counter to stop counting and OUT 1 will be ; set to low by the 8254. The counting can be started, ; when necessary, by sending the high byte. MVI A, 0 OUT CNTR1

; This is the low byte of the count. ; Send low byte to counter 1.

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Computer Architecture and Microprocessor  RET

; End of subroutine.

Start counter 1. STCNTR1; CALL PRCNTR1 OUT CNTR1

; Program the counter. ; Send high byte of count to counter. ; This starts is.

RET *Subroutine to reset alarm displays. RALARM: IN ANI

PORTC2 03FH

OUT

PORTC2

RET

; Get status of port C of 8255 #2. ; Retain current status of all bits and ; set PC0-PC1 to 0. ; Out to port C to turn off   ; the alarm displays ; End of reset alarm routine.

*Subroutine to blank 7-segment display.* BDSPLY: MVI A, 01H OUT PORTB2 RET

; Set LSB to 1 ; Send to blanking input, BI, of 7448. ; End of subroutine.

*Subroutine to unblank the 7-segment display.* LDSPLY: MVI A, 00H OUT PORTB2 RET

; Set LSB to 0. ; Send to blanking input, BI, of 7448. ; End of subroutine.

DISPLAYING THE TEMPERATURE: THE DISPLAY ROUTINE As we have already seen, the temperature is displayed digit by digit, using a multiplexing scheme. Thus, when DISPLAY is called, it should first ascertain the digit that is being displayed currently and then display the next digit after blanking out the previous one. The DISPLAY subroutine given below, performs this task by first blanking the currently ON display by applying a 1 at the BI input of 7448. It then selects the cathode of the next

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Computer Architecture and Microprocessor  digit and sends a 1 to the corresponding port thereby driving the cathode low. However, the LED’s of this digit would not yet start conducting as the anodes are all at low voltage.  Next, the appropriate BCD digit is output to 7448 and the blanking input removed thereby displaying the next digit. Finally, the next digit pointer is advanced. In order to perform the above mentioned tasks, DISPLAY uses auxiliary variables CADDR, NXTDG, TEMPD, and LSDADDR. DIGITS is a 4-byte array that holds the addresses of the four cathodes corresponding to the four digits to be displayed. The contents of this array are 04H, 08H, 10H, and 20H, respectively. These values are the bit  patterns output to port C, corresponding to the digit to be displayed, by driving the cathode low. ;*Subroutine to display the next* ;*digit on 7-segment display* ;*It uses H, L, B, and A registers.* DISPLAY: CALL IN ANI MOV LHLD

BDSPLY PORTC2 43H B, A CADDR

MOV ORA OUT LHLD MOV OUT CALL LDA INR ANI JNZ

A, M B PORTC2 TEMPD A, M PORTA2 LDSPLY NXTDG A 03H ADDR1

STA NXTDG LHLD DADDR SHLD CADDR LHLD LSDADDR SHLD TEMPD JMP FINIS ADDR1:LHLD CADDR INX H SHLD CADDR  LHLD TEMPD

; Blank the 7-segment display. ; Get status of port C of 8255 #2 ; Retain status of alarms and LIMIT SET lamp ; Save in register B. ; Get address of next cathode. ; to be selected ; Get corresponding port bit to output. ; OR in the current port C contents. ; Drive next digit cathode low. ; Get digit to be ; displayed. ; Send it to 7448. ; Unblank the display. ; Get next digit number. ; Increment it. ; AND it with 3. ; If < 4 then update addrs. ; Reset next digit to 0. ; Get first cathode address ; and reset ; Get least significant digit address ; Reset TEMPD ; Move to next ; digit.

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Computer Architecture and Microprocessor  INX H SHLD TEMPD FINIS: RET

; End of display

CADDR is the address of the next displayable element of DIGITS. It is initialized to  point to the first byte of DIGITS. After each digit is displayed, it is incremented to point to the next one. After all the four digits have been displayed, it is reset to point to the first byte of DIGITS.  NXTDG indicates the digit number to be displayed next. It assumes values from 0 to 3 in a round-robin fashion. When NXTDG reaches 4, it is reset to 0. At this time, CADDR  is also reset to point to the first byte of DIGITS. DADDR denotes the address of the first  byte of the DIGITS array. TEMPD holds the address of the next BCD digit to be displayed. LSDADDR is a constant that point to the least significant BCD digit. All the variables mentioned above are initialized in the main program. UPDATING THE DISPLAY DATA: THE UPDATE ROUTINE This routine is invoked after 16 temperature readings have been accumulated. It computes the average of all these readings, checks these against lower and upper limits and accordingly sets or resets the alarms. It also calls BINBCD to convert the average reading to 4 BCD digits for display. ;*Subroutine to update display data and reset alarms* UPDATE: MVI STA CALL CALL CALL RET

A, 0FH UPCNT AVRG BINBCD CHECK

; Get 15 in ACC ; Reset update count ; Compute average temperature ; Convert to 4 BCD digits. ; Set/reset alarms if required. ; End of UPDATE.

;*Subroutine to compute the average of 16 readings. ;*ACCUML and ACCUMH contain, respectively, the low and ;*high byte of this value. The low and high bytes ;*of the average value are stored in AVRGL and AVRGH, ;*respectively.* AVRG: LDA

ACCUML

; Get low byte

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Computer Architecture and Microprocessor  CALL MOV LDA CALL ORA STA LDA CALL STA RET

SHR4 B, A ACCUMH SHL4 B AVRGH ACCUMH SHR4 AVRGH

; Shift ACC right by 4 bits. ; Save in B ; Get high byte ; Shift left by 4 bits. ; Get low byte of   ; average ; Again get high byte ; Shift right by 4 bits. ; Get high byte of average ; End of AVRG

;* Subroutine to shift the ACC right by 4 bits.* SHR4: RRC RRC RRC RRC ANI RET

OFH

; Zero high order 4 bits. ; End of SHR4.

;* Subroutine to shift the ACC left by 4 bits.* SHL4: RLC RLC RLC RLC ANI RET

0F0H ; Zero low order 4 bits. ; End of SHL4.

The CHECK subroutine finds out whether the averaged reading, stored as BCD digits in a 4-byte array DDIGITS, has crossed the limits. The LOLMT and HILMT arrays contain the BCD codes of low and high limits respectively. If any limit is crossed, the corresponding alarm is set, otherwise only the alarm, that is currently set, is reset. Fig. 5.38 shows the logic used by CHECK in flow chart form. The program appears below. The reader is invited to design a more structured flow chart and readable program. ;* Subroutine to check whether averaged reading is in or  ;* out of range and accordingly reset alarms.* CHECK: MVI

A, 04H; Initialize counter 

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Computer Architecture and Microprocessor  STA

COUNT

; Initialize H-L, D-E and B-C to addresses of MSK of LOLMT, ; HILMT and DDIGITS, respectively. These are symbolically ; denoted by MSDL, MSDH, and MSDT, respectively.

Fig 5.38 Flow chart for comparing the averaged temperature reading with low and high limits and accordingly resetting alarms.

LXI LXI LXI

H, LOLMT + 3 B, DDIGITS + 3 D, HILMT + 3

BEGIN: LDAX B CMP M

; Get temp digit. ; Compare with LOLMT

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Computer Architecture and Microprocessor  JC RHSL ; Go reset HIGH, set LOW. JNZ HIGH ; Go compare with HIGH. DCX H DCX D LDA COUNT ; Check if over   SUI 01H STA COUNT ; Save new count. JNZ BEGIN ; Go compare next digit. RESET: CALL RALARM ; Reset both HI and LO. RET : Return to caller. HIGH: XCHG ; Get address of HILMT in H-L. MVI A, 04H STA COUNT LXI B, DDIGITS + 3 LDAX B HIGH1: CMP M ; Compare with HILMT digit. JC RESET ; If less, go reset alarm. JNZ RLSH ; Go reset LO, set H1 alarm. DCX H ; Point to next high digit. DCX B ; Point to next temp digit. LDA COUNT ; Check if all over. SUI 1 STA COUNT ; Save new count. JNZ HIGH1 ; Go compare next digit. JMP RESET ; Go reset alarms. ; Reset H1 alarm and set LO alarm. RHSL: IN ANI ORI

PORTC2 0FCH 02H

OUT RET

PORTC2

; Get port c of 8255 #2 status. ; Mask off the alarm bits (PC0 – PC1). ; Set H1 alarm bit to 1(PC0) and LO ; alarm bit to 0(PC1). ; Send to port C of 8255 #2/ ; Return

; Reset LO alarm and set HI alarm RLSH: IN ANI ORI

PORTC2 0FCH 01H

; Get port C of 8255 #w status. ; Mask off the alarm bits. ; Set H1 alarm bit to 0(PC0) and LO ; alarm bit to 1(PC1).

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Computer Architecture and Microprocessor  OUT RET

PORTC2

; Send to port C of 8255 #2. ; End of subroutine.

READING LIMITS FROM THE OPERATOR PANEL: THE RLIMITS ROUTINE As required, the limits are to be read every 15 s. We are using counter 0 to interrupt the 8085 on RST 7.5 every, approximately, 20.972 ms by setting the corresponding count to 0. Thus, to get an interval of 15 s we need to count this interrupt 15/20.972 ~ 715 times. A 2-byte software counter may be initialized to 715 and decremented by 1 each time the interrupt occurs. When this counter reaches 0, the limit value could be read. The  program appears below. The software counter SCNTR0 in initialized to 715 before any interrupt occurs. VALCT0 holds the value to which SCNTR1 should be initialized each time it reaches 0. ;*Subroutine to read lower/upper limits. Reads once every ;*15 seconds. Locations 3C-2E should contain a JMP RLIMITS ;*instruction to force the 8085 to enter RLIMITS on RST 7.5 ;*interrupt.* RLIMITS: CALL LHLD DCD SHLD MOV ORA CPI JNZ LHLK SHLD IN RRC JC RRC

SAVE SCNTR0 H SCNTR0 A, H L 0 ROVER   VALCT0 SCNTR0 PORTC0

JC

HIADDR

ROVER

; Save 8085 status. ; Get current counter value ; Decrement it. ; Save it ; Check if 0.

; Reset SCNTR0 to ; 715 ; Get operator’s request. ; Check if resetting ; desired. ; Check if LOW/HIGH ; limit should to be reset. ; Go get high limit.

; Get LOLMT address. LXI JMP

H, LOLMT + 3 GETLMT

; Get HILMT address.

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Computer Architecture and Microprocessor  HIADDR:

LXI

H, HILMT + 3;

GETLMT; IN MOV CALL MOV DCX MOV CALL CALL MOV

PORTA0 B, A SHR4 M, A H A, B SHL4 SHR4 M, A

; Get 2 MSD’s of limit. ; Save them ; Get digit 1. ; Move to LO/HI limit. ; Point to digit 2. ; Strip next digit ; and store it in LO/HI limit area

;Point to digit 3, strip next digit and store it in LO/HI limit area. DCX IN MOV CALL MOV

H PORTB0 B, A SHR4 M, A

; Get 2 least significant digits of the limit. ; Strip digit 3. ; and store it.

.;Point to digit 4, strip next digit and store it in LO/HI limit area.

DCX H MOV A, B CALL SHL4 CALL SHR4 MOV M, A IN PORTC2 ANI 8FH ORI 40H OUT PORTC2 CALL STCNTR1 ROVER: CALL EI RET

; Point to digit 4 ; get digit 4 and ; store it in ; LO/HI limit area ; ; Get status of port C of 8255 #2 ; Mask out LIMIT SET display bit (PC6) ; set LIMIT SET bit to 1. ; Send to LIMIT SET display. ; Start counter 1 to get 5’s delay RESTORE ; Restore 8085 status. ; Enable interrupts. ; End of RLIMITS

; *Subroutine to save and restore 8085 status.* SAVE: XTHL PUSH PSW PUSH B PUSH D RET

; Get return address, that is currently ; on stack top, into H-L and save H-L on stack. ; Save PSW. ; Save B-C pair. ; Save D-E pair   ; End of SAVE

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Computer Architecture and Microprocessor 

RESTORE: POP POP POP POP XTHL

H D B PSW

RET

; Pop return address into H-L. ; Restore D-E pair. ; Restore B-C pair. ; Restore PSW. ; Get return address on ; stack top and restore H-L pair. ; End of RESTORE

TURNING OFF THE LIMIT SET LAMP: THE LAMPOFF ROUTINE Immediately after the LIMIT SET indicator is turned ON, counter 1 is also started. This would generate an interrupt after 20.972 ms on RST 5.5. The lamp should be reset after 5 s which implies that approximately 239 such interrupts should be counted before resetting the lamp. We get this number as: 5 s/20.972 ms ~ 239 This can be done using the method already described above with the RLIMITS routine. For this purpose, we use a software counter named SCNTR1. The value to which SCNTR1 should always be reset is held in VALCT1. The desired routine appears below. ;*Subroutine to turn off limit-set lamp 5 s after it ;* is turned on to indicate that the limits have been set.* LAMPOFF: CALL LHLD DCX SHLD MOV ORA CPI JNZ LHLD SHLD

SAVE SCNTR1 H SCNTR2 A, H L 0 LMOVER VALCT1 SCNTR1

IN PORTC2 ANI 8FH OUT PORTC2 CALL PRCNTR1 LMOVER: CALL RESTORE EI

; Save 8085 status. ; Get current value of the software counter. ; Decrement it. ; Save it ; If zero then ; turn off   ; the lamp, else return. ; Reinitialize software counter.

; Get status of port C of 8255 #2 ; Mask out LIMIT SET display bit (PC6). ; Send to port C of 8255 #2 ; and turn off the lamp ; This will stop counter 1. ; Restore 8085 status. ; Enable interrupts.

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Computer Architecture and Microprocessor  RET

; End of LAMPOFF.

ANALOG TO DIGITAL CONVERSION: THE ATOD ROUTINE Obtaining a temperature sample from the ADC is simple. The ATOD routine given  below does it by merely reading the ADC output. Reading from the ADC will force its RDY output to go low and will remain so until the conversion is over. The RDY output forces the 8085 to wail until the conversion is over. Thus, the IN instruction in ATOD initiates the A-to-D conversion and also reads the digital output. The data obtained is stored at location RDNG from where the BINBCD routine can pick it up for conversion to BCD. ;* Subroutine to get an 8-bit temperature reading from the AD7820 ;* Hardware handshaking is used.* ATOD:

STA

IN

LCRS

RDNG

RET

; This command starts conversion, ; forces the 8085 to wait until conversion ; is over, and gets the data into ACC. ; Save reading in memory. ; End of ATOD subroutine

THE DELAY ROUTINE The DELAY subroutine uses a nested loop to decrement the L and H registers until both reach zero. Before DELAY is called, both the H and L registers should be initialized to  proper values in order to get a (approximately) 8 ms delay. ;* Subroutine to get desired delay. Registers H and L ;* should be initialized before calling this routine.* LOOP: DCR JNZ DCR JNZ RET

L LOOP H LOOP

It can be proved that the delay D caused by this subroutine is given as (approximately) D = 24 + (L’ – 1) x 14 + (H’ – 1) x [(255 x 14) + 21] (states) Where H’ and L’ denote the initial values of the H and L registers, respectively, when DELAY is entered. Assuming a 320 ns clock cycle, the approximately values of H and L for a 50 ms delay are H = 12, L = 3 (other values are also possible).

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Computer Architecture and Microprocessor   Note that when the DELAY routine is entered, the interrupts are not disabled. Thus, the interrupts from the counters will increase the delay to more than 8 ms. You may compute the maximum possible increase as an exercise. In case we decide to disable the interrupts at the beginning of DELAY, the 15s and 5s delays would be increased since many counter pulses would then go uncounted. Other criteria may be used to take a suitable decision (e.g. maximum per cent tolerable error in the delay between successive input signal sampling instants). THE MAIN PROGRAM: THE MAIN ROUTINE The main program defines various constants, initializes ports and devices, and enters an infinite loop as exhibited in Fig. 5.9. The main program is entered after the 8085 is RESET. Thus, before calling the INIT subroutine, it initializes the stack pointer, SP, to the highest address in RAM. From our hardware design, we know this address to be 4095. Recall that the stack grows from high addresses to low addresses. For example, when INIT is called, its return address will be saved in locations (SP) –1 and (SP)-2 which are bytes 4094 and 4093, respectively. Before the program can be executed, location 0, 2C and 3C should be filled with JMP instructions to MAIN, LAMPOFF, and RLIMITS routines, respectively. This will ensure that when the 8085 is reset, the jump to main program is executed. Also, when the RST 5.5 and RST 7.5 interrupts are recognized by the 8085, it jumps to the appropriate interrupt processing routine. Note that the RST 0 instruction can be used for a software reset. ;* Main program for temperature monitoring.* ;* The entire program is stored in EPROM starting at location 40H. ;* Variable data is stored in RAM starting at location 0800H. ;* Initialize constants.*

CADDR: DIGITS:

 NXTDG: UPCNT: ACUML: ACUMH: AVRGL: AVRGH: LOLMT:

ORG DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB

800H DIGITS 04H 08H 10H 20H 00H 0FH 0 0 0 0 0 0 0 0

; Set the address of the next byte to be 800H. ; Cathode address reset in display. ; Cathode digit 3. ; Cathode digit 2 ; Cathode digit 1 ; Cathode digit 0. ; Next digit to be displayed ; Update display counter. ; Accumulated reading low ; and high bytes ; Average value, low and high ; bytes. ; LSD of low limit ; ; MSD of low limit.

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Computer Architecture and Microprocessor  HILMT:

COUNT: SCNTR0: VALCT0: SCNTR1: VALCT1: RDNG: DDGIT:

TEMPD:

DB DB DB DB DS DW DW DB DB DB DB DB DB DB DW

9 9 9 9 1 715 715 239 239 0 0 0 0 0 DDGIT

; LSD of high limit

; MSD of high limit. ; Counter for check routine. ; Counter for a delay of 15 s. ; Value to reinitialize SCNTR0 ; Counter for delay of 5 s. ; Value to reinitialize SCNTR1. ; ATOD reading ; LSD of BCD digit to be displayed.

; MSD of BCD digit to be displayed. ; Address of next display digit.

;* Begin main program execution.* ;* The program instructions are in the EPROM.* ORG

40H

; Set the address of the next byte to be 40H.

LXI SPHL CALL LDA ANI JNZ CALL JMP SUI STA CALL MVI MVI CALL CALL LDA MOV LDA ADD STA MOV LDA ADC

H, 0FFFH

; Initialize stack pointer to ; 0FFFH. This is the highest RAM address. ; Initialize other variables. ; Get update counter. ; Check if zero. ; Do not update display ; Update display ; Go display next digit ; Decrement UPCNT by 1. ; Save it ; Display next digit. ; Prepare for 8 ms delay.

MAIN: START:

MLOOP:

MODFY: DISP:

INIT UPCNT OFFH MODFY UPDATE DISP 01H UPCNT DISPLAY H, 0CH L, 03H DELAY ATOD RDNG B, A ACUML B ACUML B, A ACUMH B

; Generate the delay. ; Get next reading. ; Get temperature reading into the ACC. ; Save it in register B. ; Get low byte of sum. ; Add low byte. ; Save it in memory. ; Also get it in register B. ; Get the high byte of sum in ACC. ; Add with carry.

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Computer Architecture and Microprocessor  STA JMP

ACUMH MLOOP

; Save it ; Repeat the above process.

;Place jumps to interrupt processing routines. ORG

2C

; This is the RST 5.5 interrupt branch

JMP ORG JMP END

LAMPOFF 3CH RLIMITS START

address

4.2.11

; This the RST 7.5 interrupt branch address ; Begin execution from start

Closed Loop Process Control

In the previous section we developed a system illustrating how µPs can be effectively used in open loop process control. In this section we shall briefly describe one of the many µP applications in closed loop process control. The specific example chosen is the control of the growth of synthetic quartz. The control system was developed by Robert Pettirossi (1977). THE PROCESS OF GROWING SYNTHETIC QUARTZ The growth of synthetic quartz takes place inside a long, vertically placed, growing chamber (autoclave) made of steel. Before the process starts, sodium hydroxide solution is used to fill the bottom of the autoclave. Small pieces of natural quartz (known as the nutrient) are mixed with this solution to be dissolved at a later stage. Thin wafers of  quartz (known as seeds) are sliced along the desired crystallographic structure and suspended at the top of the autoclave. The growth process begins by turning on two heaters-one at the bottom and the other at the top. Thus, a two zone temperature system is maintained. The bottom is maintained at a higher temperature than the top. The nutrient dissolves in the solution and is carried to the top by convection currents. The growth of desired crystals begins on seeds after the growth zone (top) becomes supersaturated. The growth is a pressure, temperature and time dependent process. The growth period is about 30 days and can be subdivided into three stages-the startup, intermediate, and the growth cycle. Fig. 5.39 shows the relationship between the top zone temperature (Tt) and the bottom zone temperature (T b). This relationship must be maintained for proper  growth. During the startup period, the rate of temperature rise is critical and must be maintained taking into account T b, Tt, and t1. The intermediate period is the one during which the temperatures move towards stabilization with a difference of t2. During the final growth

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Computer Architecture and Microprocessor   period T bf , T ft and t2 must be maintained within specified limits. The pressure within the autoclave should also not exceed the upper limit and not go below a lower limit.

Fig 5.39

Growth profile of synthetic quartz

In order to meet the demand, a group of 30 independent such chambers need to be operated. As the control is critical, independent microprocessor based control is employed for each autoclave.

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Computer Architecture and Microprocessor 

Fig 5.40 Control system for growth of synthetic quartz.

MICROPROCESSOR BASED CONTROL SYSTEM HARDWARE The hardware is centered around an 8080 µP. For each autoclave to be controlled, the following are the inputs from the process, which are converted to digital form using transducers and ADCs. 1. Top zone temperature (16 bits). 2. Bottom zone temperature (16 bits) 3. Autoclave pressure (8 bits) The growth is controlled by controlling the power supplied to various heater. When any of the three values corresponding to temperatures and pressure exceed limits, an alarm is set. Thus, the µP outputs digital data to DACs for controlling the two heaters and setting/resetting the alarm. An overall block diagram of the complete control system appears in Fig. 5.40. The 8080 require an external clock generator to supply a two phase overlapping clock. This is unlike the 8085, which generates an internal clock using an externally supplied crystal. This function is performed by the 8224. Another chip, known as the system controller, is required to latch the 8-bit status code sent out by the 8080 at the beginning of every machine cycle. The controller, 8228 chips, latches the code and decodes it to  produce control signals for memory and I/O devices. Recall that all control signals; IO/M, RD, WR, etc. are generated on chip in 8085.

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Computer Architecture and Microprocessor  SOFTWARE The software is divided into three distinct modules-startup, intermediate and growth modules. The startup and growth modules have almost the same logic. It is essentially loop-20 hours long for startup and about 30 days for growth. Within the loop, the program first waits for 3 minutes, reads T b and adjusts power to  bottom heaters. It then adjusts power to the bottom heater to control the rate of rise of  temperature (for startup) or to maintain T b within limits (for growth). Next, it reads Tt, checks if Ti (I = 1 for startup, 2 for growth) is too small, too large or within limits. In the first two cases, the difference is adjusted by applying power to bottom or top heater. Fig. 5.41 shows this loop.

Fig 5.41 Overall logic of the control algorithm

During the intermediate phase, only T b is read and adjusted until it reaches the desired final value T bf . The successive values are read at 3-minute intervals. Apart from these three main modules, there are a few other routines for manipulating 16 bit data approximating T b and Tt. The complete software requires about 1.2 K bytes of  memory. This is partitioned into 1 K bytes of ROM and 256 bytes of RAM. One  prototype system costs (in 1977) about $400. Thus, to control 30 autoclaves the total cost would be about $12000. However, the designers also experimented with a centralized

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Computer Architecture and Microprocessor  minicomputer control, the cost of which (including the cost of a redundant mini for high reliability) is as high as $26000.

  2   4  .  5   g   i   F

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Computer Architecture and Microprocessor  5.3

Revision Points

8080A interrupt The 8080A interrupt process is controlled by the Interrupt Enable flip-flop, which is internal to the processor and can be set or reset by using software instructions. If the flipflop is enabled and the input to the interrupt signal INT (pin 14) goes high, the microprocessor is interrupted. This is a maskable interrupt and can be disabled. The 8080A has only one interrupt signal; it does not have a nonmaskable interrupt. The 8085 has an interrupt signal called INTR (pin 10), functionally identical with the 8080A interrupt. However, the 8085 has additional interrupt signals as well. Alphanumeric Codes A computer is a binary machine; in order to communicate with the computer in alphabetic letters and decimal numbers, translation codes are necessary. The commonly used code known as ASCII, the American Standard Code for Information Interchange. Another code, called EBCDIC (Extended Binary Coded Decimal Interchange Code), is widely used in IBM computer. This is an 8-bit code representing 256 combinations; however, several combinations are not being used. Transmission Format A transmission format is concerned with issues such as synchronization, direction of data flow, speed, errors, and medium of transmission (telephone lines for example). Serial communication occurs either in synchronous or asynchronous format. In the asynchronous format, a receiver and a transmitter are synchronized; a block of characters is transmitted along with the synchronization information. Simplex and Duplex Transmission In simplex transmission, data are transmitted in only one direction. A typical example is the transmission from a microcomputer to a printer. In duplex transmission, data flow in  both directions. However, if the transmission goes one way at a time, it is called half  duplex; if it goes both ways simultaneously, it is called full duplex. Generally, transmission between two computers or between a computer and a terminal is full duplex. BAUD The rate at which the bits are transmitted – bits/second – is called a baud in serial I/O. MODEM A modem (Modulator / Demodulator) is a circuit that translates digital data into audio tone frequencies for transmission over telephone lines and converts audio frequencies into digital data for reception.

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Computer Architecture and Microprocessor  5.4

Intext Questions 1. Write a brief note on interrupts? 2. Write a brief note on 8155? 3. What does ALE stand for? 4. Write a short note on application area of microprocessors?

5.5

Summary •

These input and output devices are called peripherals or I / Os; memory can be viewed as a special type of I / O.

•

The microprocessor (MPU) communicates with the peripherals in either of  two formats: asynchronous or synchronous.

•

Similarly, it transfers data in either of two modes: parallel I / O or serial I / O.

•

The 8085 has five interrupt inputs.

•

These interrupts are sensitive to different types of triggering.

•

Serial communication also can be classified according the direction and simultaneity of data flow.

•

A tri-state buffer is used as an input port to read data from devices such as a keyboard or data converters.

•

5.6

The timer can be used to calculate the conversion time.

Terminal Exercises 1. What is a RST instruction? 2. What is a Control word? 3. What are the functions performed by a interfacing I/O device? 4. What is TRAP? 5. What is Parity Check?

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