UMC_180nm_mm_rf_FDK_CDN_userguide_vB04_PB_3
Short Description
Download UMC_180nm_mm_rf_FDK_CDN_userguide_vB04_PB_3...
Description
UM180FDKMFC000000A_B
UMC 0.18um 1P6M Mixed-Mode/RF Thick Top Metal (20KA) Process Foundry Design Kit (PDK) User Guide
Copyright UMC, 2005 All information contained herein is subject to change without prior notice. No liability shall be incurred from its use or application.
UMC Confidential
1 Ver. B04_PB
UM180FDKMFC000000A_B
Contents 0. Release Notes ..…………………………………………………….. 4 1. Overview
………………………………...………..………..…….. 7
2. Foundry Data
………….………………...………..…..………….. 8
3. What makes up a PDK? ..………………...………..…..…………. 9 4. Installation of the PDK
..………………...………..…..………….. 10
5. PDK Install Directory Structure/Contents
..………..………….. 11
6. Creation of a Design Project ............……...……………..………... 12 7. Techfile Methodology
..……......………...……………..………... 14
8. Customizing Layer Display Properties Using Display.drf File .. 15 9. Schematic Design
…….……………………………………………. 17
10. Library Device Setup ……………………………………………… 18 11. Supported Devices ………………………………………………… 20 12. Views provided …………………………………………………….. 23 13. CDF parameters ……………………………………………………
24
14. Component Label Defaults ………………………………………. 37 15. Simulation Models
………………………………………………… 40
16. AddWire Utility ……………………………………………………… 41 17. UpdateCDFs Utility …………………………………………………. 42 18. Setting Environment Variables 19. Techfile Layers
………………………………….. 43
……………………………………………………… 45
20. Virtuoso XL …………………………………………………………..
46
21. Dracula Support ……………………………………………………… 48 22. Assura Decks
……………………………………………………….
49
23. DEVICE SPECIFICATIONS ………………………………………… 59 UMC Confidential
2 Ver. B04_PB
UM180FDKMFC000000A_B
24. DEVICE DATASHEETS ……………………………………………… 72 25. Known Problems and Solutions ………………………………….
253
Appendix A.1
Revision History ………………………………………………….. 258
A.2. UMC Utilities …………………………………………………………… 258 A.2.1. Callback Re-trigger Utility ………………………………………………………………….…… 258 A.2.2. Alphabet Generator
UMC Confidential
……………………………………………………….... 259
3 Ver. B04_PB
UM180FDKMFC000000A_B
0 Release Notes 0.1 Foundry Process Documents The following documents were used to develop or verify this Design Kit. Classification Design Support Manual Electrical Design Rule Topological Layout Rule
Version
Date
G-01-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-DSM-8C
2.0_P2
8/25/2005
G-02-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-EDR
1.4_P1
11/29/2005
G-03-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-TLR
2.8_P1
11/16/2005
Interconnect Capacitance
G-04-MIXED_MODE/RFCMOS18-1P6M-MMC-INTERCAP
1.1_P2
5/9/2003
SPICE Modeling
G-05-MIXED_MODE/RFCMOS18-1.8V/3.3V-TRI_WELL/MMC-SPICE-8C
1.4_P1
11/4/2005
G-05-MIXED_MODE/RFCMOS18-1.8V/3.3V-TWIN_WELL/MMC-SPICE-8C
1.5_P1
11/4/2005
GT-DBT-030922-007 (MM salicide resistors and metal resistors)
B.B1PB
9/22/2003
Mask Tooling
Spec. No.
G-06-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-MASKTOO L-8C
2.4_P1
11/2/2005
DRC Rule Deck
G-DF-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC/CALIBRE-DRC
2.8_P1
11/23/2005
LVS Rule Deck
G-DF-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC/CALIBRE-LVS
1.3_P3
10/24/2005
LPE Rule Deck Official Layer Mapping Table
G-DF-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC/XRC-LPE
1.1_P13
7/14/2005
2.3_P1
11/4/2005
G-DF-GENERATION18-VIRTUOSO-TF
NOTE: The model files and rule decks included in this release Design Kit were available at the time of this revision. The user should keep accessing the latest model files and rule decks. Please contact your Account Manager if you failed to access them.
0.2 EDA Tools Supported and Verified for Use with this FDK (PDK) Classification Schematic Entry Simulation Interface Simulation Tool Layout Editor DRC Tool LVS Tool Parasitic RC Extractor
EDA Tools Cadence Composer Cadence Analog Design Environment Cadence Spectre Synopsys Hspice Cadence Virtuoso Mentor Calibre Mentor Calibre Mentor XRC
Version 5.10.41_USR1.7.43 5.10.41_USR1.7.43 5.10.41_USR1.7.43 2003.09 5.10.41_USR1.7.43 2005.1_10.20 2005.1_10.20 2005.1_10.20
NOTE: This Design Kit did not verify the other EDA tools not mentioned above.
UMC Confidential
4 Ver. B04_PB
UM180FDKMFC000000A_B
UMC Confidential
Symbol View
Model Type
Spectre Netlist
Hspice Netlist
CDL Netlist
Layout View
SDL Check
Spectre Sim.
Hspice Sim.
DRC Check
LVS Check
MOS P_18_MM N_18_MM N_BPW_18_MM P_33_MM N_33_MM N_BPW_33_MM P_LV_18_MM N_LV_18_MM N_ZERO_18_MM P_LV_33_MM N_LV_33_MM N_ZERO_33_MM P_L18W500_18_RF P_PO7W500_18_RF N_L18W500_18_RF N_PO7W500_18_RF P_L34W500_33_RF P_PO7W500_33_RF N_L34W500_33_RF N_PO7W500_33_RF BJT PNP_V50X50_MM PNP_V100X100_MM Diode DION_MM DIONW_MM DIOP_MM RES RSND_MM RSPD_MM RNND_MM RNPD_MM RNNPO_MM RNPPO_MM RNHR1000_MM RSNWELL_MM RM1_MM RM2_MM RM3_MM RM4_MM RM5_MM RM6_MM RNNPO_RF
Terminals
Device Name
Device Type
0.3 Component List
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 2 2 2 3 3 3 3 3 3 3 3 2 2 2 2 2 2 3
V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V
C* C* C* C* C* C* C* C* C* C* C* C* S* S* S* S* S* S* S* S* C* C* C* C* C* S* S* S* S* S* S* S* S* S* S* S* S* S* S* S*
V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V
V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V
V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V
V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V
V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V
V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V
V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V
V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V
V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V
5 Ver. B04_PB
UM180FDKMFC000000A_B RNPPO_RF RNHR_RF CAP NCAP_MM PCAP_MM MIMCAPS_MM MIMCAPM_RF IND L_SLCR20K_RF VAR VARMIS_18_RF VARDIOP_RF PAD PAD_RF
3 3 3 3 2 3 3 3 2 2
V V V V V V V V V V
S* S* C* C* S* S* S* S* S* S*
V V V V V V V V V V
V V V V V V V V V V
V V V V V V V V V V
V V V V V V V V V V
V V V V V V V V V V
V V V V V V V V V V
V V V V V V V V V V
V V V V V V V V V V
V V V V V V V V V V
* C means compact model, and S means sub-circuit model.
0.4 Verification Notes Calibre LVS: (1) Please let LVS setup options of “LVS REDUCE PARALLEL CAPACITORS” and “LVS REDUCE SERIES CAPACITORS” be NO when you run Calibre LVS rule eck on RF Capacitors (MIMCAPM_RF, VARDIOP_RF & VARMIS_18_RF). RF capacitors defined in Calibre LVS rule deck trace geometrical parameters (L, W, NX, NY, NF) instead of the capacitance.
UMC Confidential
6 Ver. B04_PB
UM180FDKMFC000000A_B
1 Overview The purpose of this User Guide is to describe the technical details of the UMC .18 MM/RF, 1P6M thick top metal (20KA) Process Design Kit (“PDK”) provided by Cadence Design Systems, Inc. (“Cadence”). NOTE: The RM6_MM resistor uses thick metal (20KA) values. This PDK requires the following environmental variables “CDS_Netlisting_Mode” to be set to “Analog” “CDS_INST_DIR” to be set to the Cadence DFII installation path Cadence DFII Tool Training is not provided as part of this PDK.
1.1 Software Releases
The following releases of software were used to develop and test this PDK: Cadence DFII Version: 5.0.33_USR3.16.35 (USR3) Cadence Assura DRC/LVS Versions: 3.1.3.USR1 Cadence Assura RCX Version: 3.1.3.USR1
UMC Confidential
7 Ver. B04_PB
UM180FDKMFC000000A_B
2 Foundry Data
G-03-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-TLR 0.18 um Mixed Mode/RFCMOS Technology 1.8V/3.3V 1P6M Process Topological Layout Rule (With Metal/Metal Capacitor Module) (Rev. 2.8_P1) G-02-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-EDR 0.18um Mixed Mode/RFCMOS Technology 1.8V/3.3V 1P6M Electrical Design Rule (With Metal/Metal Capacitor Module) (Ver. 1.4_P1) G-04-MIXED_MODE/RFCMOS18-1P6M-MMC-INTERCAP 0.18um 1P6M Mixed Mode with MMC Process Interconnect Capacitance Model (Ver. 1.1_P2)
UMC Confidential
8 Ver. B04_PB
UM180FDKMFC000000A_B
3 What makes up a PDK? PDK stands for Process Design Kit. A PDK contains the process technology and needed information to do device-level design in the Cadence DFII environment.
PDK
Cadence Tool
Schematic (Composer)
Schematic Symbols & CDF Analog Simulation & callbacks
Spectre Models
Fixed Layouts Parameterized Cells
Simulation
Analog Front-end Design
Spectre Foundry
Analog Design Environment
Device Generation/Cell Design Virtuoso XL (Advanced Layout Editor)
Techfile: - Layer maps - Layer props - symbolics - Connectivity - VCR setup
Physical Verification - DRC - LVS - LPE
UMC Confidential
Interconnect Wire Editor/Routing Virtuoso Custom Router (VCR)
VirtuosoXL Layout
Interactive Physical Verification Diva, Dracula, Assura
9 Ver. B04_PB
UM180FDKMFC000000A_B
4 Installation of the PDK Logon to the computer as the user who will own and maintain the PDK. Choose a disk and directory under which the PDK will be installed. This disk should be exported to all client machines and must be mounted consistently across all client machines. Connect to the directory where the PDK will be installed: cd Extract the PDK from the archive using the following commands: gzip -d / xxx.tar.gz tar xvf xxx.tar The default permissions on the PDK have already been set to allow only the owner to have write, read and execute access. Other users will have only read and execute access.
UMC Confidential
10 Ver. B04_PB
UM180FDKMFC000000A_B
5 PDK Install Directory Structure/Contents REVISION - ASCII file containing the PDK revision history. cds.lib - file containing the Cadence initialization file. display.drf - ASCII version of display resources file icc.rules - Virtuoso Custom Router and Virtuoso Custom Placer rules file Models – directory containing SPICE model files used to test the PDK umc18mmrf.tf - ASCII version of technology file umc18mmrf – UMC .18 MM/RF Process PDK Cadence Library RuleDecks – directory containing Calibre rule decks used to test the PDK celview.cellmap – cell map file for Calibre view
UMC Confidential
11 Ver. B04_PB
UM180FDKMFC000000A_B
6 Creation of a Design Project A unique directory should be created for each circuit design project. The following command can be executed in UNIX: mkdir ~/circuit_design cd ~/circuit_design All work by the user should be performed in this circuit design directory. The following file should be copied from the PDK install directory to begin the circuit design process. The following command can be used: cp /display.drf
.
Next the user should create a "cds.lib" file. Using any text editor the following entry should be put in the cds.lib file: INCLUDE /cds.lib Where "pdk_install_directory" is the path to where the UMC .18 MM/RF PDK was installed.
Because the UMC .18 MM and UMC .18 MM/RF PDK, differ in their top metal thicknesses, you can not use the same techfile for both PDKs. The UMC .18 MM PDK uses thin top metal, and the UMC .18 MM/RF PDK uses thick top metal. The symbolic contacts for M6_M5 and the path width for ME6 differ between these two PDKs. Both of these settings are defined in the techfile. This will require a techfile for each PDK. Given that two techfile are required, what follows is a step by step flow that can be executed to switch between PDK's. For example, If you would like to reuse an existing test library (developed for UMC .18 MM) for your UMC .18 MM/RF tests, please do the following: ***NOTE: Assuming that the test library that you want to change is named "umc18mm_test" 1) Rename the reference library: In the library manager select Edit->Rename Reference Library... Make sure that the following fields are entered:
UMC Confidential
12 Ver. B04_PB
UM180FDKMFC000000A_B In Library From Library To Library
umc18mm_test umc18mm umc18mmrf
Then click on the "OK" button. 2)Attach the UMC .18 MM/RF technology file: In the CIW window, select Technology File->Attach To... Make sure that the "Design Library" field is set to "umc18mm_test". Make sure that the "Technology Library" is set to "umc18mmrf" Then click on the "OK" button. 3) Update CDFs: In the CIW window, enter the following command: umc18mmrf_updateCDFs("umc18mm_test") Once all 3 of these steps have been executed, you will then be able to reuse existing designs in the "umc18mm_test" library that was developed in "umc18mm" on the "umc18mmrf" PDK.
UMC Confidential
13 Ver. B04_PB
UM180FDKMFC000000A_B
7 Techfile Methodology The umc18mmrf Library techfile will be designated as the master techfile. This techfile will contain all required techfile information. There is an ASCII version of this techfile shipped with the PDK. This ASCII version represents the techfile currently compiled into the umc18mmrf library The attach method should be used for any design library that is created. This allows the design database techfile to be kept in sync with the techfile in the process PDK. To create a new library that uses an attached techfile, use the command File->New->Library from either the CIW or library manager and select the Attach to an existing techfile option. Select the umc18mmrf library when asked for the name of the Attach To Technology Library.
UMC Confidential
14 Ver. B04_PB
UM180FDKMFC000000A_B
8 Customizing Layer Display Properties Using Display.drf File The display.drf can be autoloaded at Cadence start-up time or manually loaded during the Cadence session. For the file to be autoloaded, the display.drf file must be located in the Cadence start-up directory. To manually load the display.drf file (or load a new version), choose Tools->Display Resources->Merge Files... from the CIW and enter the location of the display.drf file that you want to use. If the display.drf file is not autoloaded and you do not manually load it, you will get error messages about missing packets when you try to open a schematic or layout view and you will not be able to see any process specific layers. The UMC .18 MM/RF 1P6M process display.drf file can be found in the PDK install directory. Listed below are the packet, color, lineStyle, and stipplePattern definitions for a ME3 drawing layer. The packet info references predefined color, lineStyle, and stipplePattern definitions. Any of these can be changed to suit an individual user’s preferences in the project copy of the display.drf file. drDefinePacket( ;( DisplayName PacketName Fill Outline )
Stipple
( display
solid
green green )
Red
Green
204
102
Size
Pattern )
m3
dots
LineStyle
) drDefineColor( ;( DisplayName ( display
green
ColorName 0
Blue
Blink )
nil )
) drDefineLineStyle( ;( DisplayName ( display
solid
LineStyle 1
(1 1 1) )
) drDefineStipple(
UMC Confidential
15 Ver. B04_PB
UM180FDKMFC000000A_B ;( DisplayName ( display
dots
StippleName
Bitmap ) (
(0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
UMC Confidential
16 Ver. B04_PB
UM180FDKMFC000000A_B
9 Schematic Design The user should follow the guidelines listed below while building schematics using Composer: Project libraries should list the primitive PDK library as a reference library in the library properties form. Users can add instances from the PDK library to designs stored in the project libraries. When performing hierarchical copy of schematic designs care should be taken to preserve the references to the PDK libraries. These references should not be copied locally to the project directories and the references set to the local copy of PDK cells. This would prevent your designs from inheriting any fixes done to the PDK library from an upgrade. Users should exercise caution when querying an instance and changing the name of the cell and replacing it with a reference to another cell. While like parameters will inherit values, callbacks are not necessarily executed. This would cause dependent parameters to have incorrect values. Schematics should be designed with schematic driven layout methodology in mind. Partitioning of schematics, hierarchical design, input and output ports, should be done in a clean and consistent fashion. Usage of pPar and iPar in a schematic design context is discouraged. While this works fine in schematic design, this could lead to problems while performing schematic driven layout.
UMC Confidential
17 Ver. B04_PB
UM180FDKMFC000000A_B
10 Library Device Setup 10.1 Resistors
The resistors in the library consist of two types; diffused and insulated. The diffused types include n+ and are 3 terminal resistors with diode backplates. The insulated resistors are those that are isolated from silicon by an insulator (oxide) such as poly resistors. The resistors in this PDK are 3 terminal devices. Serpentine resistor layouts are not allowed. Dog-bone configurations are allowed. Units: The width is specified in meters for schematic simulation. All parameters entered into the resistor form must be integers or floating-point numbers. No design variables are supported due to the calculations that must be performed on the entries. Calculation: The width and length are snapped to grid, and the resistances are recalculated and updated on the component form based on actual dimensions. Simulation: The UMC provided model definitions are used to model the resistors.
10.2 Capacitors
All capacitors in the PDK library are 2 and 3 terminals. The capacitors for this process are MIMCAPS_MM, MIMCAPM_RF, NCAP_MM and PCAP_MM. MIMCAPS_MM and MIMCAPM_RF are metal on metal capacitors and they have 2 and 3 terminals respectively. The NCAP_MM and PCAP_MM are MOSFET capacitors and they have 4 terminals. Units: The length and width are specified in meters for schematic simulation. All parameters entered into the capacitor form must be integers or floating-point numbers. Design variables are supported here. Calculation: The width and length are snapped to grid, and the capacitance is recalculated and updated on the component form based on actual dimensions. Simulation: The UMC provided model definitions are used to model the capacitors.
10.3 MOSFETS
All mosfets in the PDK library are 4 terminal, with the body terminal explicitly connected. To conform to electromigration rules, customer must choose proper finger width, finger number, or source/drain metal width according to device operating point.
UMC Confidential
18 Ver. B04_PB
UM180FDKMFC000000A_B Units: Length and width are in meters, with areas and perimeters in meters squared and meters, respectively. Design variables are allowed for Length and Width entries. Calculation: The area and perimeter parameters for the sources and drains are calculated from the width and the number of fingers used. This calculation assumes that the drain will always have the lesser capacitance (area) when there is an even number of fingers (odd number of diffusion areas). The Width per finger is calculated by dividing the width by the number of fingers. This parameter is for viewing by the designer. Simulation: The UMC provided model definitions are used to model the MOSFET devices.
10.4 Bipolar Transistors
This PDK contains 2 vertical PNP transistors that have a substrate collector. The device has fixed dimensions for its emitter size. Units: The emitter size is specified in meters for schematic entry. All parameters entered into the PNP_V50X50_MM and PNP_V100X100_MM forms must be integers or floating-point numbers. Simulation: The UMC provided model definitions are used to model the bipolar transistors.
UMC Confidential
19 Ver. B04_PB
UM180FDKMFC000000A_B
11 Supported Devices 11.1 MOSFETS
• N_18_MM – 1.8 volt NMOS transistor • P_18_MM – 1.8 volt PMOS transistor • N_33_MM – 3.3 volt NMOS transistor • P_33_MM – 3.3 volt PMOS transistor • N_LV_18_MM – 1.8 volt low vt NMOS transistor • P_LV_18_MM – 1.8 volt low vt PMOS transistor • N_LV_33_MM – 3.3 volt low vt NMOS transistor • P_LV_33_MM – 3.3 volt low vt PMOS transistor • N_ZERO_18_MM – 1.8 volt zero vt NMOS transistor • N_ZERO_33_MM – 3.3 volt zero vt NMOS transistor • N_BPW_18_MM – 1.8 volt triple-well NMOS transistor • N_BPW_33_MM – 3.3 volt triple-well NMOS transistor • N_L18W500_18_RF - 1.8 volt variable finger RF NMOS transistor • N_L34W500_33_RF - 3.3 volt variable finger RF NMOS transistor • N_PO7W500_18_RF - 1.8 volt variable length RF NMOS transistor • N_PO7W500_33_RF - 3.3 volt variable length RF NMOS transistor • P_L18W500_18_RF - 1.8 volt variable finger RF PMOS transistor • P_L34W500_33_RF - 3.3 volt variable finger RF PMOS transistor • P_PO7W500_18_RF -1.8 volt variable length RF PMOS transistor • P_PO7W500_33_RF - 3.3 volt variable length RF PMOS transistor
11.2 RESISTORS
• RSPD_MM – P+ diffused resistor w/salicide • RSND_MM – N+ diffused resistor w/ salicide • RNPPO_MM – P+ poly resistor w/o salicide • RNNPO_MM – N+ poly resistor w/o salicide • RSNWELL_MM – N-Well resistor • RNHR1000_MM – High Resistive poly resistor • RNND_MM – N+ diffused resistor w/o salicide • RNPD_MM – P+ diffused resistor w/o salicide
UMC Confidential
20 Ver. B04_PB
UM180FDKMFC000000A_B • RM1_MM – Metal 1 resistor • RM1_MM – Metal 2 resistor • RM3_MM – Metal 3 resistor • RM4_MM – Metal 4 resistor • RM5_MM – Metal 5 resistor • RM6_MM – Metal 6 resistor • RNHR_RF - RF High resistive poly resistor • RNNPO_RF - RF N+ poly resistor w/o salicide • RNPPO_RF - RF P+ poly resistor w/o salicide
11.3 CAPACITORS
• MIMCAPS_MM – Single-squared mixed-mode metal-to-metal capacitor - CapA = 0.001F/M^2
CapP = 7.5e-11F/M
• NCAP_MM - NMOS transistor configured as a capacitor • PCAP_MM - PMOS transistor configured as a capacitor • MIMCAPM_RF – RF Metal Capacitor
11.4 BIPOLARS
• PNP_V50X50_MM - 5x5 CMOS vertical substrate PNP • PNP_V100X100_MM - 10x10 CMOS vertical substrate PNP
11.5 DIODES
• DION_MM – N+/psub diode • DIONW_MM – Nwell/psub diode • DIOP_MM – P+/nwell diode
11.6 Inductors
• L_SLCR20K_RF– Circular spiral RF inductor
11.7 Bond Pads
• PAD_RF – RF Bond Pad
11.8 Varactors
• VARDIOP_RF - P+/Nwell RF diode varactor • VARMIS_18_RF - 1.8V N+/Nwell RF MIS varactor
UMC Confidential
21 Ver. B04_PB
UM180FDKMFC000000A_B
11.9 PARASITICS
NOTE: These symbols are used for internal use only. They are placed in the extracted view of a layout to display parasitic values. They are not devices that designers should use in their designs. • pcapacitor • presistor
UMC Confidential
22 Ver. B04_PB
UM180FDKMFC000000A_B
12 Views provided 12.1 MOSFETS
• Four terminals (D, G, S, B) • symbol, spectre, auLvs, auCdl, ivpcell, hspiceS, layout (Pcells)
12.2 RESISTORS
• Two terminals (PLUS, MINUS) for RM1_MM, RM1_MM, RM3_MM, RM4_MM, RM5_MM, RM6_MM • Three terminals (PLUS, MINUS, B) for RSPD_MM, RSND_MM, RNPPO_MM, RNNPO_MM, RSNWELL_MM, RNHR1000_MM, RNND_MM, RNPD_MM, RNHR_RF, RNNPO_RF, RNPPO_RF • symbol, spectre, auLvs, auCdl, ivpcell, hspiceS, layout (Pcells)
12.3 CAPACITORS
• Two terminals (PLUS, MINUS) for MIMCAPS_MM • Three terminals (PLUS, MINUS, B) for NCAP_MM, PCAP_MM, MIMCAPM_RF • symbol, spectre, auLvs, auCdl, ivpcell, hspiceS, layout (Pcells)
12.4 BIPOLARS
• Three terminals (C, B, E) • symbol, spectre, auLvs, auCdl, ivpcell, hspiceS, layout (Fixed)
12.5 DIODES
• Two terminals (PLUS, MINUS) • symbol, spectre, auLvs, auCdl, ivpcell, hspiceS, layout (Fixed)
12.6 Inductors
• Three terminals (PLUS, MINUS, B) • symbol, spectre, auLvs, auCdl, ivpcell, hspiceS, layout (Pcells)
12.7 Bond Pads
• Two terminals (PLUS, MINUS) • symbol, spectre, auLvs, auCdl, ivpcell, hspiceS, layout (Pcells)
12.8 Varactors
• Two terminals (PLUS, MINUS) for VARDIOP_RF • Three terminals (PLUS, MINUS, B) for VARMIS_18_RF • symbol, spectre, auLvs, auCdl, ivpcell, hspiceS, layout (Pcells)
UMC Confidential
23 Ver. B04_PB
UM180FDKMFC000000A_B
13 CDF parameters 13.1 MOSFETS
• l (M) - gate length in meters • w (M) - gate width in meters
• Number of Fingers - Number of poly gate stripes used in layout (w/nf width) • Source Drain Metal Width (M) – Width of metal on Source and Drain in meters. • Width Per Finger - Width of each gate stripe (non-editable) • Multiplier - Number of Parallel MOS devices • Calc Diff Params - cyclic which controls the calculation of area and periphery of the source/drain regions for simulation. Default is true which auto calculates the values. If nil, the user can enter the values. • Source diffusion area - Calculated source diffusion area in square meters • Drain diffusion area - Calculated drain diffusion area in square meters • Source diffusion periphery - Calculated source diffusion periphery in meters • Drain diffusion periphery - Calculated source diffusion periphery in meters
NOTE: To conform to electromigration rules, customer must choose proper finger width, finger number, or source/drain metal width according to device operating point.
13.2 RF MOSFETS
• Width per Finger (M) - gate width in meters • Length (M) - gate length in meters
• Number of Fingers - Number of poly gate stripes used in layout (w/nf width)
UMC Confidential
24 Ver. B04_PB
UM180FDKMFC000000A_B
MOSFET ADD INSTANCE FORM
UMC Confidential
25 Ver. B04_PB
UM180FDKMFC000000A_B
13.3 RESISTORS
• Resistance - Resistance value used for simulation • w (M) - resistor width in meters • l (M) - resistor length in meters (non-editable) • Rho - resistor layer sheet rho (non-editable) • Area (M^2) - resistor area for parasitics in meters squared(non-editable) • Perim (M) - resistor perimeter for parasitics in meters (non-editable)
13.4 RF RESISTORS
• Resistance - Resistance value used for simulation • Width (M) - resistor width in meters • Length (M) - resistor length in meters (non-editable) • Rsh (ohm/sq) - resistor layer sheet rho (non-editable) • Rend (ohm-um) – resistor end sheet rho (non-editable) • delta Width (um) – resistor delta width (non-editable) • delta Length (um) – resistor delta length (non-editable)
UMC Confidential
26 Ver. B04_PB
UM180FDKMFC000000A_B
RESISTOR ADD INSTANCE FORM
UMC Confidential
27 Ver. B04_PB
UM180FDKMFC000000A_B
13.5 CAPACITORS – MIMCAPS_MM
• Capacitance - capacitance value used in simulation (non-editable) • Total Capacitance (non-editable)
-
Capacitance
multiplied
times
Multiplier
• w (M) - capacitor width in meters • l (M) - capacitor length in meters • CapA (F/M^2) - Plate Capacitance (non-editable, units are Farads per Meter Squared) • CapP (F/M) - Fringe Capacitance (non-editable, units are Farads per Meter) • Multiplier - Number of devices in layout (non-editable for mimcap)
13.6 CAPACITORS – NCAP_MM, PCAP_MM
• Capacitance – capacitance value used in simulation ( based on rough calculation) • Total Capacitance – total capacitance value is Capacitance * Multiplier (non-editable) • Spec – cyclic used to choose capacitor entry method (Capacitance, Cap & l, l & w) • l (M) – capacitor length in meters • w (M) – capacitor width in meters • Multiplier - Number of Parallel MOS devices • CapA (F/M^2) – Plate Capacitance (non-editable, units are Farads per Meter Squared) • CapP (F/M) – Fringe Capacitance (non-editable, units are Farads per Meter) • Number of Fingers - Number of poly gate stripes used in layout (w/nf width)
• Width Per Finger - Width of each gate stripe (non-editable using totalWidth) • Calc Diff Params - cyclic which controls the calculation of area and periphery of the source/drain regions for simulation. Default is true which auto calculates the values. If nil, the user can enter the values. • Source diffusion area - Calculated source diffusion area in square meters
UMC Confidential
28 Ver. B04_PB
UM180FDKMFC000000A_B • Drain diffusion area - Calculated drain diffusion area in square meters • Source diffusion periphery - Calculated source diffusion periphery in meters • Drain diffusion periphery - Calculated source diffusion periphery in meters
13.7 CAPACITORS – MIMCAPM_RF
• Capacitance - capacitance value used in simulation • Multi Square X - multiple square capacitors in x-direction • Multi Square Y - multiple square capacitors in y-direction • Width (X) - capacitor width in meters • Length (Y) - capacitor length in meters
UMC Confidential
29 Ver. B04_PB
UM180FDKMFC000000A_B
CAPACITOR ADD INSTANCE FORM
UMC Confidential
30 Ver. B04_PB
UM180FDKMFC000000A_B
13.8 BIPOLARS
• Model name - Spectre model name (non-editable) • Multiplier - Number of Parallel Bipolar devices • Width (M) – Emitter Width in metres (non-editable) • Length (M) – Emitter Length in metres (non-editable) • Emitter area – Calculated emitter area in meters squared (non-editable) • Device initially off – bolean to turn device model off for simulation start-up. • Estimated operating region – Simulation operating region (off, fwd, rev, sat) • Linearized Region – Simulation operating region (yes, no)
UMC Confidential
31 Ver. B04_PB
UM180FDKMFC000000A_B
BIPOLAR ADD INSTANCE FORM
UMC Confidential
32 Ver. B04_PB
UM180FDKMFC000000A_B
13.9 DIODES
• Device Area - Calculated junction area in meters squared (non-editable) • Multiplier - Number of Parallel Diode devices • Length (M) - diode length in meters
• Width (M) - diode width in meters
DIODE ADD INSTANCE FORM
UMC Confidential
33 Ver. B04_PB
UM180FDKMFC000000A_B
13.10
Inductors
• Inductance – Inductance in Henries • Inner Diameter (M) – inner diameter in meters • Width (M) – width of inductor in meters • Number of Turns – number of inductor turns.
INDUCTOR ADD INSTANCE FORM
UMC Confidential
34 Ver. B04_PB
UM180FDKMFC000000A_B
13.11
Bond Pads
• Specified Index – multi layer number of PAD metal (1, 2, 3, 4, 5)
INDUCTOR ADD INSTANCE FORM
13.12
Varactors – VARDIOP_RF
• Capacitance (zero bias) – zero bias capacitance value • Number of Fingers – number of finger stripes used in layout • Parasitic Cap. (fF/um^2) – area capacitance in fF/um2 • Fringe Cap. (fF/um) – fringe capacitance in fF/um
13.13
Varactors – VARMIS_18_RF
• Capacitance (max) – maximum capacitance value • Number of Fingers – number of finger stripes used in layout
UMC Confidential
35 Ver. B04_PB
UM180FDKMFC000000A_B • Parasitic Cap. (fF/um^2) – area capacitance in fF/um2 • Fringe Cap. (fF/um) – fringe capacitance in fF/um
VARACTOR ADD INSTANCE FORM
UMC Confidential
36 Ver. B04_PB
UM180FDKMFC000000A_B
14 Component Label Defaults 14.1 MOSFETS
• component parameters: model, l, w, fingers, m • operating point: ids, vgs, vds, vth, vdsat • model: vtho, vsat • instance name prefix: NM, NP
14.2 RF MOSFETS
• component parameters: model, l, w, nf • operating point: ids, vgs, vds, vth, vdsat • model: vth, vsat • instance name prefix: NM, NP
14.3 RESISTORS
• component parameters: model, r, w, l • operating point: v i res • model: • instance name prefix: R
14.4 RF RESISTORS
• component parameters: model, r, w, l • operating point: v, res • model: • instance name prefix: R
14.5 CAPACITORS – MIMCAPS_MM
• component parameters: model, c, l, w, m • operating point: cap • model: • instance name prefix: C
14.6 CAPACITORS – NCAP_MM, PCAP_MM
• component parameters: model, c, l, w, fingers, m • operating point: cap • model: vtho, tox, cj
UMC Confidential
37 Ver. B04_PB
UM180FDKMFC000000A_B • instance name prefix: C
14.7 CAPACITORS – MIMCAPM_RF
• component parameters: model, nx, ny, w, l • operating point: cap • model: • instance name prefix: C
14.8 BIPOLARS
• component parameters: model, area, m • operating point: betadc, ic, vce • model: bf, is, vaf • instance name prefix: Q
14.9 DIODES
• component parameters: model, area, m • operating point: id, vd, region • model: is, rs, n • instance name prefix: D
14.10
VARACTORS
• component parameters: model, nf, c • operating point: • model: • instance name prefix: C
14.11
Bond Pads
• component parameters: model, index • operating point: - i • model: • instance name prefix: C
14.12
Inductors
• component parameters: model, d, w, n • operating point: - i, ind • model: -
UMC Confidential
38 Ver. B04_PB
UM180FDKMFC000000A_B • instance name prefix: C
UMC Confidential
39 Ver. B04_PB
UM180FDKMFC000000A_B
15 Simulation Models
The following simulators are supported in the PDK: Spectre hSpiceS UltraSim NOTE: MMSIM60 is recommended to run Spectre or UltraSim simulations. The following model library setup is done automatically when the user first opens the umc18mmrf library or uses a component from that library. The user may disable or modify this feature by editing the libInitCustomExit.il file found in the umc18mmrf library. Spectre: /Models/Spectre/018-rf-v2d4-control.scs /Models/Spectre/MM180_BJT_V112.mdl.scs /Models/Spectre/MM180_DIODE_V113.mdl.scs /Models/Spectre/MM180_LVT18_V113.lib.scs /Models/Spectre/MM180_LVT33_V113.lib.scs /Models/Spectre/MM180_MIMCAP_V101.lib.scs /Models/Spectre/MM180_REG18BPW_V123.lib.scs /Models/Spectre/MM180_REG18_V123.lib.scs /Models/Spectre/MM180_REG33BPW_V123.lib.scs /Models/Spectre/MM180_REG33_V113.lib.scs /Models/Spectre/MM180_RES_V111.lib.scs /Models/Spectre/MM180_RES_V132.lib.scs /Models/Spectre/MM180_ZVT18_V113.lib.scs /Models/Spectre/MM180_ZVT33_V113.lib.scs
tt tt mimcaps_typ tt tt tt tt res_typ res_typ tt tt
Where is the path where the UMC90nm PDK is installed and the second entry is the simulation corner that the user wants to simulate. The user should follow the instructions provided with the device models from UMC to ensure the proper selection of sections for simulation.
UMC Confidential
40 Ver. B04_PB
UM180FDKMFC000000A_B
16 AddWire Utility
Certain devices in the library have bulk pins (i.e N_18_MM, P_18_MM, RSND_MM, etc..). A utility has been added to the PDK to automatically wire these bulk terminals to user specified signals (i.e. gnd!, vdd!, etc..). This will help reduce schematic clutter while maintaining required circuit hookup. The following picture shows the result of executing the "addWire" routine.
There are no arguments to run the program, the user must type umc18mmrf_addWire() in the CIW. If you don’t have a schematic cellview open it will give you an error message. If the user has instances selected when they run addWire, it will prompt them for the label name for those specific instances and will only add the wires to those instances. It does nothing to the schematic hierarchy. If no instances are selected then the program will wire up all instances that have their bulk nodes unconnected. The user gets prompted for the label name for each type of instance, and they also have the option of running it down through the hierarchy or just at the current cellview. And, finally, if the user does not want to use gnd! or vdd! as the label name, there is an entry box for the user to type in an alternative net name. If another wire name is used, it will be added to the cyclic list of label name choices - but only for that DFII session. Once you exit the dfII session, the cyclic is reset to gnd! and vdd!
UMC Confidential
41 Ver. B04_PB
UM180FDKMFC000000A_B
17 UpdateCDFs Utility
When changes are made to a device inside the PDK, these changes often affect circuit design, which have already been created. For example, a sheet rho value may change on a resistor, which affects the length of the device passed to the simulator and used to generate the layout. These parameters are not automatically updated in each of the designer’s circuit libraries. A function has been written and included as a part of the PDK to complete the update to an existing library such that all modifications made to a PDK since a previous release are reflected in each of the circuit designs inside a library. The name of the function for this PDK is called "umc18mmrf_updateCDFs". There is a single argument to this function, which represents the design library, which is to be updated with the new CDF information. Once this routine has been run, all design schematics in the designated library will be in sync with the latest release of the PDK. Please note, however, that possible LVS violations may arise as a result of running this routine depending upon what changes have been made to the PDK. For example, a sheet rho change as specified earlier could cause a resistor to shrink in length in the schematic thus causing a mismatch as far as LVS is concerned. Please be sure that you verify again each design in simulation, DRC, and LVS to insure that no unintended modifications have been overlooked. The syntax for this function is as follows:
In the CIW, type umc18mmrf_updateCDFs(libName) for the library which you wish to operate on. For example, given a library named designLib, the proper syntax for this routine would be: umc18mmrf_updateCDFs("designLib") Please be sure that the library name you choose to pass as an argument is present in the library manager window (i.e. - be sure that it is visible and located in your cds.lib file)
UMC Confidential
42 Ver. B04_PB
UM180FDKMFC000000A_B
18
Setting Environment Variables
Environment variables control how various DFII commands work by default. These variables can be stored in the Library .cdsenv file which is located in the umc18mmrf directory. This library .cdsenv file is loaded by default in the PDK libinit.il file. The .cdsenv file, which is provided with the UMC .18 MM/RF PDK, contains five environment variables; setPPConn, xSnapSpacing, ySnapSpacing, updatePCellIncrement, and InitIOPinLayer. 1. setPPConn is a boolean layoutXL editor environment variable which recognizes pseudo-parallel nets. These nets can be connected, or not connected as in the schematic, to produce an electrically equivalent layout. If set to nil, pseudo-parallel nets are ignored. These nets then require interconnect that matches the schematic exactly. In this PDK the setPPConn environment variable has been set to nil. The designer can change the value of the setPPConn environment variable by editing the following line in the .cdsenv file: layoutXL setPPConn boolean nil The valid values for setPPConn are nil and t. 2. xSnapSpacing is a floating-point layout editor environment variable which controls the minimum distance the cursor moves in the X direction. In this PDK the xSnapSpacing environment variable has been set to 0.01. The designer can change the value of the xSnapSpacing environment variable by editing the following line in the .cdsenv file: layout xSnapSpacing float 0.01 The valid values for xSnapSpacing are 0.01 to the desired value. 3. ySnapSpacing is a floating-point layout editor environment variable which controls the minimum distance the cursor moves in the Y direction. In this PDK the ySnapSpacing environment variable has been set to 0.01. The designer can change the value of the ySnapSpacing environment variable by editing the following line in the .cdsenv file: layout ySnapSpacing float 0.01 UMC Confidential
43 Ver. B04_PB
UM180FDKMFC000000A_B
The valid values for ySnapSpacing are 0.01 to the desired value. 4. updatePCellIncrement is a floating-point layout editor environment variable specifying how often the system updates pcell parameters and regenerates the pcell during a stretch operation. The designer can change the value of the updatePCellIncrement environment variable by editing the following line in the .cdsenv file: layout updatePCellIncrement float 0.01 The valid values for updatePCellIncrement are 0.01 to the desired value. 5. initIOPinLayer is a string layoutXL editor environment variable specifying the default layer to use in the Gen From Source Form for I/O Pin creation. The designer can change the value of the initIOPinLayer environment variable by editing the following line in the .cdsenv file: layoutXL initIOPinLayer string “ME1 drawing” The valid values for initIOPinLayer are any layer defined in the techfile.
UMC Confidential
44 Ver. B04_PB
UM180FDKMFC000000A_B
19 Techfile Layers
Cadence will provide a standard display setup, and will not support desired changes to the display. The customer is free to modify the display.drf file used on-site to achieve any desired display. Techfile layers defined in this PDK are done in accordance with UMC document G-06LMT-GENERATION18-LAYER_MAPPING_TABLE, Revision 2.3_P1 (UMC Official Layer Mapping Table). The user is referred to this UMC document for a complete listing of all layer/levels of the process technology.
UMC Confidential
45 Ver. B04_PB
UM180FDKMFC000000A_B
20 Virtuoso XL
The standard Cadence Virtuoso XL design flow will be implemented. This includes basic connectivity of connection layers, wells, and substrate, and symbolic contacts. The M factor will be used for device instance multiplier - there will be no conflict with the parameter used in cell operation. Names will be displayed on the layout views to aid in schematic-layout instance correlation. Auto-abutment of MOSFET devices is supported. Pin permuting of MOSFET and Resistor device is also supported. The skill pcell layouts are compiled into the PDK. The users should follow the guidelines listed below for layout design: The VirtuosoXL tool requires a separate license for operation. Users obtain maximum leverage from the PDK by doing schematic driven layout in the Virtuoso XL environment. This flow will produce a correct design layout. The Virtuoso Custom Router (IC Craftsman) can be used to finish the interconnects in the layout. The VCR rules file for the target process is provided with the PDK. Abutment is currently supported only for MOS transistors. Note, abutment will work only on schematic driven layouts. Schematic Driven Layout is recommended over Netlist Driven Layout. NOTE: Skill pcell source code is not included in the PDK kit.
UMC Confidential
46 Ver. B04_PB
UM180FDKMFC000000A_B
20.1 SYMBOLIC CONTACTS
• M1_NACTIVE – Metal 1 to NPLUS DIFF contact • M1_NWELL – Metal 1 to NWEL contact • M1_PACTIVE – Metal 1 to PPLUS DIFF contact • M1_POLY – Metal 1 to PO1 contact • M1_PSUB - Metal1 to Substrate contact • M2_M1 – Metal 2 to Metal 1 via contact • M3_M2 – Metal 3 to Metal 2 via contact • M4_M3 – Metal 4 to Metal 3 via contact • M5_M4 – Metal 5 to Metal 4 via contact • M6_M5 – Metal 6 to Metal 5 via contact
ADD CONTACT FORM
UMC Confidential
47 Ver. B04_PB
UM180FDKMFC000000A_B
21 Dracula Support
No Dracula support will be provided with the exception of creating an auCdl netlist. Listed below is an example of the CDL netlist for each device.
CDL OUT FORM
UMC Confidential
48 Ver. B04_PB
UM180FDKMFC000000A_B
22 Assura Decks
NOTE: This PDK revision B04_PB does not incorporate Assura Decks. The following descriptions are for reference only The user needs to do the following in order to implement and use the Assura Verification decks: 1) Create a directory named: •
assura_umc18mmrf_tech
2) Place all Assura decks in the directory created above ( assura_umc18mmrf_tech). 3) Create a file named: • assura_tech.lib 4) In this file ( assura_tech.lib ), the user needs to enter only one line: DEFINE umc18mmrf_rcx ./assura_umc18mmrf_tech Once these four steps have been completed, the user will then be able to run Assura Verification on this PDK. The user needs the licenses for these tools to perform verification. When performing verification you have to provide the library name to the verification deck. Select the desired switches before starting the verification run. Refrain from working on the target layout being verified while the run is in progress. Following are the tar files for the description of Assura verification setup only: Assura RCX tar file name: G-DF-MIXED_MODE_RFCMOS18-1.8V_3.3V-1P6M-MMC-ASSURA-LPE-1.1-P3 Files Included: Topm_20k.tar g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-assura-lvs-1.2-p5-extract.rul g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-assura-lvs-1.2-p5compare.rul bind.Model Version: 1.2_p5 Date: 05/12/03 Assura DRC tar file name: G-DF-MIXEDMODE_RFCMOS18-1.8V-3.3V-1P6M-MMC-Assura-drc-2.2-p5 Files Included: g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-Assura-drc-2.2-p5.rul
UMC Confidential
49 Ver. B04_PB
UM180FDKMFC000000A_B g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-Assura-drc-2.2-p5.rsf umc_ant_assura_all.0.rul umc_ant_assura_all-.0.rsf Version: DRC version: 2.2-p5 ANT version: 0 Date:
UMC Confidential
DRC date: 04/11/03 ANT date: 04/21/03
50 Ver. B04_PB
UM180FDKMFC000000A_B
22.1 Assura DRC
The following 3 Assura DRC files were tested with the PDK and were placed in the assura_umc18mmrf_tech directory: • g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-Assura-drc-2.2-p 5.rul. • umc_ant_assura_all.0.rul • assuraESD.rul The following switches are available in the
g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-Assura-drc-2.2-p5.rul: Technology Switches: • BDSP_rule – checks rules for the bordered SP SRAM core regions • BLSP1_rule – checks the rules for the borderless SP SRAM core regions • BLSP_rule – checks the rules for the Virage SP SRAM core regions • DP1_rule – checks the rules for the DP1 SRAM core regions • DP2_rule – checks the rules for the DP2 SRAM core regions • DP_rule – checks the rules for the DP SRAM core regions • ROM_rule – checks the rules for the ROM regions • metal2_is_top – specifies 2-Metal Technology • metal3_is_top – specifies 3-Metal Technology • metal4_is_top – specifies 4-Metal Technology • metal5_is_top – specifies 5-Metal Technology • top_metal_is_thick – specifies Thick Top Metal Chip-Level Switches: • SR – Seal ring rules are checked Run-Time Intensive Switches: • check_max_metal_space – Maximum Metal spacing rules are checked • check_density – Metal coverage rules are checked • check_slots – Slot rules are checked
UMC Confidential
51 Ver. B04_PB
UM180FDKMFC000000A_B By default, if none of the switches are set, the file will assume the following: • The design incorporates 6-metal technology • Off-grid checks will be performed • The chip-level checks will NOT be performed • The run-time intensive checks will NOT be performed.
22.2 Assura Antenna
The following Assura Antenna file was tested with the PDK and was placed in the assura_umc18mmrf_tech directory: • umc_ant_assura_all.0.rul The following switches are available in the assuraANT.rul file: Technology Switches: • metal1_is_top – specifies 1-Metal Technology • metal2_is_top – specifies 2-Metal Technology • metal3_is_top – specifies 3-Metal Technology • metal4_is_top – specifies 4-Metal Technology • metal5_is_top – specifies 5-Metal Technology • metal6_is_top – specifies 6-Metal Technology By default, if none of the switches are set, the file will assume 6-metal process.
Antenna Check Format Switches: • Check_All_Top_Antenna – Performs one level area and perimeter antenna checks. For example, checks m3 area/gate area and m3 perimeter/gate perimeter check. • Check_Cumulative_Area_Antenna – Performs antenna checks.
cumulative
• Check_Cumulative_Perimeter_Antenna – Performs perimeter antenna checks.
UMC Confidential
area
cumulative
52 Ver. B04_PB
UM180FDKMFC000000A_B
22.3 Assura ESD
The Assura Antenna files tested with the PDK were placed in the assura_umc18mmrf_tech directory and are named: • assuraESD.rul No switches are available in the assuraESD.rul file.
ASSURA DRC FORM
UMC Confidential
53 Ver. B04_PB
UM180FDKMFC000000A_B
22.4 Assura LVS
The Assura LVS files tested with assura_umc18mmrf_tech directory:
the
PDK
were
placed
in
the
• g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-assura-lvs-1.2-p 3-extract.rul • g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-assura-lvs-1.2-p 3-compare.rul • bind.Model – for use with any devices from VST or Artisan libraries. Please see usage notes in extract.rul for more information. The following switches are available in the extract.rul file: • Artisan_Lib – for extraction of devices from Artisan libraries • Skip_Soft-Connect_Checks - Select the switch to skip the reporting of multStamp, floating, and multConnect errors. By default, this switch is not set. • Top_Metal_Thickness--20K – Sets Metal Resistor Coefficients for 20KA thick Top Metal. To avoid RCX run-time errors, use the switches below to skip the extraction statements of the devices without IVPCELL view. • Skip_Logic_Device_Extraction—Skips extraction of logic devices. • Skip_Mixed_Mode_Device_Extraction—Skips extraction Mode ( _MM) devices.
of
Mixed
• Skip_RF_Device_Extraction—Skips extraction of RF ( _RF) devices. DO NOT SELECT ANY OF THE FOLLOWING SWITCHES: • Top_Metal—ME4 – This is not supported in this PDK. • Top_Metal—ME5 – This is not supported in this PDK.
UMC Confidential
54 Ver. B04_PB
UM180FDKMFC000000A_B The default switch is for the 8KA 1P6M process.
ASSURA LVS FORM
22.5 Assura RCX The Assura RCX files tested with the PDK were placed in the following directory: • assura_umc18mmrf_tech - Directory where Assura RCX files are provided
UMC Confidential
55 Ver. B04_PB
UM180FDKMFC000000A_B Please consult the Assura RCX users manual for available RCX options.
NOTE: The av_extracted view is not supported in these Assura rules. To enable av_extracted views please follow the instructions below: 1) Convert the extract rules with the “Skip_Logic_Device_Extraction” switch set for capgen input The following files should be found in your assura_umc18mmrf_tech directory: cap_coeff.dat
- assura 3.0 binary file output from capgen -S run
compare.rul
- compare rules for LVS
extract.rul
- extract rules file for LVS
lvsfile
- converted Assura extract file for RCX
p2lvsfile
- layer mapping file for procfile & extract.rul
procfile
- Process description file (SEE NOTE BELOW)
umc18mm_20k_rcx.rsf - sample RSF to run Assura RCX Additional files
- RCXdspfINIT, RCXspiceINIT, RCXutilities - cap.so, s2d.log, caps2d - paxfile_coeff, rcxfs.dat
The capgen lvsfile is created from the Assura extract rules file. A sample RSF file, lvsfile.rsf is shown below to do this. The Cadence PDK compatible Assura extract rules file, extract.rul is included. You may use this or your own file. Change the lvsfile.rsf file as needed. Within the assura_umc18mmrf_tech directory, run Assura from Unix: Sample lvsfile.rsf: /**********************************************************************
UMC Confidential
56 Ver. B04_PB
UM180FDKMFC000000A_B Assura RCX sample RSF for capgen lvsfile creation Use this file to create the capgen "lvsfile" from extract.rul ***********************************************************************/ avParameters( ?rulesFile "extract.rul" ?rcxFile "lvsfile" ?inputLayout ("df2" "dummyLayoutName" ) ?cellName "dummyCellname" ?viewName “dummyviewName” ?cdslib “./cds.lib” ?set “Skip_Logic_Device_Extraction” ?runName "lvs_convert" ?compileOnly t )
Note: Set ?inputLayout, ?cellName and ?viewName to point to data. 2) Run “assura lvsfile.rsf > lvs_convert.log” from the Unix prompt The output will be the file "lvsfile" which will be used as an input to capgen. The other files from the run (lvs_convert.???) can be deleted.
3) Execute the second capgen command from Unix prompt within the assura_umc18mmrf_tech. % capgen -C -lvs lvsfile -p2lvs p2lvsfile -mos_diff_ap -cap_unit 1 . Note: The period “.” at the end of the command stands for current directory. UMC Confidential
57 Ver. B04_PB
UM180FDKMFC000000A_B
ASSURA RCX FORM
UMC Confidential
58 Ver. B04_PB
UM180FDKMFC000000A_B
23 DEVICE SPECIFICATIONS Model and Layout Source
Device
Description
Spectre Model received
HspiceS Model received
GDS or DFII Sample Layout Received
Fixed Layout or Variable Layout (Pcell)
Mos N_18_MM
1.8 volt NMOS transistor
y
y
y
Pcell
N_BPW_18_MM
1.8 volt triple-well NMOS transistor
y
y
y
Pcell
N_33_MM
3.3 volt NMOS transistor
y
y
y
Pcell
N_BPW_33_MM
3.3 volt triple-well NMOS transistor
y
y
y
Pcell
N_LV_18_MM
1.8 volt low vt NMOS transistor
y
y
y
Pcell
N_LV_33_MM
3.3 volt low vt NMOS transistor
y
y
y
Pcell
N_ZERO_18_MM
1.8 volt zero vt NMOS transistor
y
y
y
Pcell
N_ZERO_33_MM
3.3 volt zero vt NMOS transistor
y
y
y
Pcell
P_18_MM
1.8 volt PMOS transistor
y
y
y
Pcell
P_33_MM
3.3 volt PMOS transistor
y
y
y
Pcell
P_LV_18_MM
1.8 volt low vt PMOS transistor
y
y
y
Pcell
P_LV_33_MM
3.3 volt low vt PMOS transistor
y
y
y
Pcell
N_L18W500_18_RF 1.8 volt variable finger RF NMOS transistor
y
y
y
Pcell
N_L34W500_33_RF 3.3 volt variable finger RF NMOS transistor
y
y
y
Pcell
N_PO7W500_18_RF 1.8 volt variable length RF NMOS transistor
y
y
y
Pcell
N_PO7W500_33_RF 3.3 volt variable length RF NMOS transistor
y
y
y
Pcell
P_L18W500_18_RF 1.8 volt variable finger RF PMOS transistor
y
y
y
Pcell
P_L34W500_33_RF 3.3 volt variable finger RF PMOS transistor
y
y
y
Pcell
P_PO7W500_18_RF 1.8 volt variable length RF PMOS transistor
y
y
y
Pcell
P_PO7W500_33_RF 3.3 volt variable length RF PMOS transistor
y
y
y
Pcell
RF Mos
Resistor RSND_MM
N+ diffused resistor w/ salicide
y
y
y
Pcell
RSPD_MM
P+ diffused resistor w/ salicide
y
y
y
Pcell
RNPPO_MM
P+ poly resistor w/o salicide
y
y
y
Pcell
UMC Confidential
59 Ver. B04_PB
UM180FDKMFC000000A_B RNNPO_MM
N+ poly resistor w/o salicide
y
y
y
Pcell
RSNWELL_MM
N-well resistor
y
y
y
Pcell
RNHR1000_MM
High resistive poly resistor
y
y
y
Pcell
RNND_MM
N+ diffused resistor w/o salicide
y
y
y
Pcell
RNPD_MM
P+ diffused resistor w/o salicide
y
y
y
Pcell
RM1_MM
Metal 1 resistor
y
y
y
Pcell
RM2_MM
Metal 2 resistor
y
y
y
Pcell
RM3_MM
Metal 3 resistor
y
y
y
Pcell
RM4_MM
Metal 4 resistor
y
y
y
Pcell
RM5_MM
Metal 5 resistor
y
y
y
Pcell
RM6_MM
Metal 6 resistor
y
y
y
Pcell
RNHR_RF
RF High resistive poly resistor
y
y
y
Pcell
RNNPO_RF
RF N+ poly resistor w/o salicide
y
y
y
Pcell
RNPPO_RF
RF P+ poly resistor w/o salicide
y
y
y
Pcell
MIMCAPS_MM
Single-squared MM Metal capacitor
y
y
y
Pcell
NCAP_MM
NMOS gate capacitor
y
y
y
Pcell
PCAP_MM
PMOS gate capacitor
y
y
y
Pcell
RF Metal capacitor
y
y
y
Pcell
DION_MM
N+/psub diode
y
y
y
Fixed
DIONW_MM
Nwell/psub diode
y
y
y
Fixed
DIOP_MM
P+/nwell diode
y
y
y
Fixed
Vertical substrate PNP ( 5x5 )
y
y
y
Fixed
PNP_V100X100_MM Vertical substrate PNP ( 10x10 )
y
y
y
Fixed
Inductor L_SLCR20K_RF
Circular spiral RF inductor
y
y
y
Pcell
Bond Pad PAD_RF
Bond Pad
y
y
y
Fixed
RF Resistor
Capacitor
RF Capacitor MIMCAPM_RF Diode
BJT PNP_V50X50_MM
UMC Confidential
60 Ver. B04_PB
UM180FDKMFC000000A_B Varactor VARDIOP_RF VARMIS_18_RF
P+/Nwell RF diode varactor 1.8V N+/Nwell RF MIS varactor
y y
y y
y y
Pcell Pcell
23.1 MOS FORMAL PARAMETERS l (gate length in microns)
Device
min
N_18_MM N_BPW_18_MM N_33_MM N_BPW_33_MM N_LV_18_MM N_LV_33_MM N_ZERO_18_MM N_ZERO_33_MM
180n 180n 340n 340n 240n 500n 300n 500n
Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules
P_18_MM P_33_MM P_LV_18_MM P_LV_33_MM
180n 340n 240n 500n
Design Rules Design Rules Design Rules Design Rules
Value Got from Design Rule #
max
Value Got from
4.14Aa 4.14Aa 4.14Ab 4.14Ab 4.7Aa 4.9A 4.8A 4.7Ab
50u 50u 50u 50u 50u 50u 50u 50u
Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model
4.14Ba 4.14Bb 4.4A 4.5A
50u 50u 50u 50u
Spectre model Spectre model Spectre model Spectre model
w (gate width in microns)
Device
min
Value Got from
max
Value Got from
N_18_MM N_BPW_18_MM N_33_MM N_BPW_33_MM N_LV_18_MM N_LV_33_MM N_ZERO_18_MM N_ZERO_33_MM
240n 240n 240n 240n 240n 800n 240n 800n
Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model
100u 100u 100u 100u 100u 100u 100u 100u
Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model
P_18_MM P_33_MM P_LV_18_MM P_LV_33_MM
240n 240n 240n 800n
Spectre model Spectre model Spectre model Spectre model
100u 100u 100u 100u
Spectre model Spectre model Spectre model Spectre model
UMC Confidential
61 Ver. B04_PB
UM180FDKMFC000000A_B
Fingers (number of fingers)
Device
min
Value Got from
max
Value Got from
N_18_MM N_BPW_18_MM N_33_MM N_BPW_33_MM N_LV_18_MM N_LV_33_MM N_ZERO_18_MM N_ZERO_33_MM
1 1 1 1 1 1 1 1
Default Default Default Default Default Default Default Default
100 100 100 100 100 100 100 100
PDK standard PDK standard PDK standard PDK standard PDK standard PDK standard PDK standard PDK standard
P_18_MM P_33_MM P_LV_18_MM P_LV_33_MM
1 1 1 1
Default Default Default Default
100 100 100 100
PDK standard PDK standard PDK standard PDK standard
UMC Confidential
62 Ver. B04_PB
UM180FDKMFC000000A_B
23.2 RF MOS FORMAL PARAMETERS Device Name
N_L18W500_18_RF N_L34W500_33_RF N_PO7W500_18_RF N_PO7W500_33_RF P_L18W500_18_RF P_L34W500_33_RF P_PO7W500_18_RF P_PO7W500_33_RF
Formal Parameters l (Length) min
Value Got from
max
Value Got from
180.0n 340.0n 200n 340.0n 180.0n 340.0n 200n 340.0n
Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model
180.0n 340.0n 500n 800n 180.0n 340.0n 500n 800n
Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model
Value Got from
max
Value Got from
Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model
5u 5u 5u 5u 5u 5u 5u 5u
Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model
Device Name w (Finger Width) min N_L18W500_18_RF N_L34W500_33_RF N_PO7W500_18_RF N_PO7W500_33_RF P_L18W500_18_RF P_L34W500_33_RF P_PO7W500_18_RF P_PO7W500_33_RF
5u 5u 5u 5u 5u 5u 5u 5u
Device Name nf (Finger Number) min N_L18W500_18_RF N_L34W500_33_RF N_PO7W500_18_RF N_PO7W500_33_RF P_L18W500_18_RF P_L34W500_33_RF P_PO7W500_18_RF P_PO7W500_33_RF
UMC Confidential
5 5 7 7 5 5 7 7
Value Got from
max
Value Got from
Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model
21 21 7 7 21 21 7 7
Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model
63 Ver. B04_PB
UM180FDKMFC000000A_B
23.3 RESISTOR FORMAL PARAMETERS r (resistance in Ohms)
Device RSND_MM RSPD_MM RNPPO_MM RNNPO_MM RSNWELL_MM RNHR1000_MM RNND_MM RNPD_MM RM1_MM RM1_MM RM3_MM RM4_MM RM5_MM RM6_MM
min 168.000m 168.000m 21.1085 5.11481 31.376 43.263 2.39596 4.73918 2.82975m 2.1545m 2.1545m 2.1545m 2.1545m 2.16275m
Value Got from
Design Rule #
max
Value Got from
Design Rule #
Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation
Calc.1 Calc.1 Calc.1 Calc.1 Calc.1 Calc.5 Calc.1 Calc.1 Calc.2 Calc.2 Calc.2 Calc.2 Calc.2 Calc.2
33.3107K 33.3107K 2.62455M 1.35984M 6.19403K 7.56992M 291.817K 484.5K 6.41667 4.42857 4.42857 4.42857 4.42857 1.86364
Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation
Calc. 3 Calc. 3 Calc. 3 Calc. 3 Calc. 3 Calc. 6 Calc. 3 Calc. 3 Calc.4 Calc.4 Calc.4 Calc.4 Calc.4 Calc.4
w (width In microns)
Device RSND_MM RSPD_MM RNPPO_MM RNNPO_MM RSNWELL_MM RNHR1000_MM RNND_MM RNPD_MM RM1_MM RM1_MM RM3_MM RM4_MM RM5_MM RM6_MM
min 240n 240n 180n 180n 1.5u 180n 240n 240n 240n 280n 280n 280n 280n 440n
UMC Confidential
Value Got from
Design Rule #
Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules
4.1Aa 4.1Ab 4.14Aa 4.14Ba 4.2Ab 4.14Aa 4.1Aa 4.1Ab 4.20A 4.22A 4.24A 4.26A 4.28A 4.31A
max 20u 20u 20u 20u 20u 20u 20u 20u 20u 20u 20u 20u 20u 20u
Value Got from PDK Standard PDK Standard PDK Standard PDK Standard PDK Standard PDK Standard PDK Standard PDK Standard PDK Standard PDK Standard PDK Standard PDK Standard PDK Standard PDK Standard
64 Ver. B04_PB
UM180FDKMFC000000A_B
Note: Calc.1
( Salicided sheet resistance ) * ( minL + deltaL ) / ( maxW + deltaW ) + 2 * ( Non-salicided sheet resistance ) / ( maxW + deltaW )
Calc.2
( Salicided sheet resistance ) * ( minL ) / ( maxW )
Calc.3
( Salicided sheet resistance ) * ( maxL + deltaL ) / ( minW + deltaW ) + 2 * ( Non-salicided sheet resistance ) / ( minW + deltaW)
Calc.4
( Salicided sheet resistance ) * ( maxL ) / ( minW )
Calc.5
( Salicided sheet resistance ) * ( minL -0.4um ) / ( maxW + deltaW ) + 2 * ( Non-salicided sheet resistance ) / ( maxW + deltaW )
Calc.6
( Salicided sheet resistance ) * ( maxL -0.4um ) / ( minW + deltaW ) + 2 * ( non-salicided sheet resistance ) / ( minW + deltaW )
UMC Confidential
65 Ver. B04_PB
UM180FDKMFC000000A_B
23.4 RF RESISTOR FORMAL PARAMETERS Device Name
Formal Parameters r (Resistance)
min RNHR_RF RNNPO_RF RNPPO_RF
972.1002 136.6264 467.7584
Value Got from Calculation Calculation Calculation
Value Got from
max 10.52856K 1.205465K 3.710338K
Calculation Calculation Calculation
Device Name w (Width) min RNHR_RF RNNPO_RF RNPPO_RF
2u 2u 2u
Value Got from Spectre model Spectre model Spectre model
max 10u 10u 10u
Value Got from Spectre model Spectre model Spectre model
Device Name l (Length) min RNHR_RF RNNPO_RF RNPPO_RF
2u 2u 2u
UMC Confidential
Value Got from Spectre model Spectre model Spectre model
max 100u 100u 100u
Value Got from Spectre model Spectre model Spectre model
66 Ver. B04_PB
UM180FDKMFC000000A_B
23.5 CAPACITOR FORMAL PARAMETERS c (capacitance In Farads)
Device MIMCAPS_MM NCAP_MM PCAP_MM
Value Got from Design Rule #
min N/E 1.8618f 1.8618f
Design Rules Design Rules
N/E 3.3011p 3.3011p
Dim.1 Dim.1
Value Got from
max
Design Rules Design Rules
Design Rule #
Dim.2 Dim.2
l (length in Metres)
Device MIMCAPS_MM NCAP_MM PCAP_MM
Value Got from Design Rule #
min 1.84u 180n 180n
Design Rules Design Rules Design Rules
Dim.3 4.14Aa 4.14Ba
max
Value Got from
100u 20u 20u
Spectre model Spectre model Spectre model
W (width in Metres)
Device MIMCAPS_MM NCAP_MM PCAP_MM
Value Got from
min 1.84u 440n 440n
Dim.3 Dim.4 Dim.5
MIMCAPS_MM NCAP_MM PCAP_MM
UMC Confidential
100u 20u 20u
Value Got from Spectre model Spectre model Spectre model
(number of Fingers)
Fingers
Device
max
Value Got from
min
1 1
max
Default Default
Value Got from
50 PDK Standard 50 PDK Standard
67 Ver. B04_PB
UM180FDKMFC000000A_B
Note: Dim.1
minW * minL * ( Area Capacitance ) + 2 * ( minW + minL ) * ( Fringe Capacitance )
Dim.2
maxW * maxL * ( Area Capacitance ) + 2 * ( maxW + maxL ) * ( Fringe Capacitance )
Dim.3
( minWidth of VI5 ) + 2 * ( MMC enclosure of VI5 ) 4.30A
4.29D
Dim.4
( MinWidth of contact ) + 2 * ( Diffusion enclosure of Contact ) 4.19A 4.19G
Dim.5
( MinWidth of contact ) + 2 * ( Diffusion enclosure of Contact ) 4.19A 4.19F
UMC Confidential
68 Ver. B04_PB
UM180FDKMFC000000A_B
23.6 RF CAPACITOR FORMAL PARAMETERS Device Name
MIMCAPM_RF
Formal Parameters c (Capacitance) min
Value Got from
max
Value Got from
103.00f
Calculation
5.047p
Calculation
Device Name
MIMCAPM_RF
l (Length(Y)) min
Value Got from
max
Value Got from
10u
Spectre model
70u
Spectre model
w (Width(X)) min
Value Got from
max
Value Got from
10u
Spectre model
70u
Spectre model
Device Name
MIMCAPM_RF
Device Name
MIMCAPM_RF
nx (Multi Square X) min
Value Got from
max
Value Got from
1
Spectre model
7
Spectre model
ny (Multi Square Y) min
Value Got from
max
Value Got from
1
Spectre model
7
Spectre model
Device Name
MIMCAPM_RF
UMC Confidential
69 Ver. B04_PB
UM180FDKMFC000000A_B
23.7 INDUCTOR FORMAL PARAMETERS Device Name
L_SLCR20K_RF
Formal Parameters l (Inductance) min
Value Got from
max
Value Got from
567.9646p
Calculation
14.27438n
Calculation
Device Name
L_SLCR20K_RF
d (Diameter) min
Value Got from
max
Value Got from
126u
Spectre model
238u
Spectre model
w (Width) min
Value Got from
max
Value Got from
6u
Spectre model
20u
Spectre model
Device Name
L_SLCR20K_RF Device Name
n (Turn Number) min
Value Got from
max
Value Got from
1.5
Spectre model
5.5
Spectre model
L_SLCR20K_RF
23.8 BOND PAD FORMAL PARAMETERS Device Name index
PAD_RF
UMC Confidential
min
Value Got from
max
Value Got from
1
Spectre model
5
Spectre model
70 Ver. B04_PB
UM180FDKMFC000000A_B
23.9 VARACTOR FORMAL PARAMETERS Formal Parameters c (C(zero bias)) min
Device Name
VARDIOP_RF VARMIS_18_RF
406.32f N/A
Value Got from
max
Value Got from
Calculation
1.62528p N/A
Calculation
Device Name c (Cmax) min VARDIOP_RF VARMIS_18_RF
N/A 1.030819p
Value Got from
max
Value Got from
Calculation
N/A 5.154096p
Calculation
Device Name nf (Finger Number) min VARDIOP_RF VARMIS_18_RF
23.10
Value Got from 30 24
Spectre model Spectre model
max 120 120
Value Got from Spectre model Spectre model
BIPOLAR FORMAL PARAMETERS
The bipolar devices have fixed layouts and do not have any formal editable parameters.
23.11
DIODES FORMAL PARAMETERS
The diode devices have fixed layouts and do not have any formal editable parameters.
UMC Confidential
71 Ver. B04_PB
UM180FDKMFC000000A_B
24 DEVICE DATASHEETS
24.1 N_18_MM – 1.8 volt NMOS Transistor
Spectre Netlist Spectre Model Name = “n_18_mm” NM0 (D G S B) n_18_mm w=2u l=180.0n as=9.8e-13 ad=9.8e-13 ps=4.98u \ pd=4.98u m=(1)*(1)
HspiceS Netlist HspiceS Model Name = “N_18_MM” MNM0 D G S B N_18_MM L=180E-9 W=2E-6 AD=980E-15 AS=980E-15 PD=4.98E-6 +PS=4.98E-6 M=+1.00000000E+00
DIVA LVS Netlist DIVA Device Name = “N_18_MM” ; N_18_MM Instance /NM0 = auLvs device M0 d N_18_MM D G S B (p D S) i 0 N_18_MM D G S B " L 180e-9 W 2e-6 M 1.0 "
CDL Netlist CDL Device Name = “N_18_MM” MMN0 D G S B N_18_MM W=2u L=180.0n M=1
UMC Confidential
72 Ver. B04_PB
UM180FDKMFC000000A_B
Assura Netlist Assura auLvs Device Name = “N_18_MM” C N_18_MM MOS DRAIN B
GATE B
SOURCE B
SUBSTRATE B ;;
* 4 pins * 4 nets * 0 instances i MN0 N_18_MM D G S B ; L 1.8e-07 W 2e-06 effW 2e-06 ;
UMC Confidential
73 Ver. B04_PB
UM180FDKMFC000000A_B
Width
N_18_MM (diagrammatic layout)
Length
Device Layers Layer
Color and Fill
DIFF NPLUS PO1 CONT ME1 SYMBOL (MMSYMBOL)
Device Derivation Device
Layer Derivation
Recognition
DIFF AND NPLUS CONTAINS PO1
G
PO1
D
DIFF AND NPLUS NOT PO1
S
DIFF AND NPLUS NOT PO1
B
Substrate
LVS Comparison Parameter
Calculation
Length
PO1 intersecting DIFF (illustrated above)
Width
PO1 inside DIFF (illustrated above)
UMC Confidential
74 Ver. B04_PB
UM180FDKMFC000000A_B * S and D are PERMUTABLE
UMC Confidential
75 Ver. B04_PB
UM180FDKMFC000000A_B
24.2 P_18_MM – 1.8 volt PMOS Transistor
Spectre Netlist Spectre Model Name = “p_18_mm” PM0 (D G S B) p_18_mm w=2u l=180.0n as=9.8e-13 ad=9.8e-13 ps=4.98u \ pd=4.98u m=(1)*(1)
HspiceS Netlist HspiceS Model Name = “P_18_MM” MPM0 D G S B P_18_MM L=180E-9 W=2E-6 AD=980E-15 AS=980E-15 PD=4.98E-6 +PS=4.98E-6 M=+1.00000000E+00
DIVA LVS Netlist DIVA Device Name = “P_18_MM” ; P_18_MM Instance /PM0 = auLvs device M0 d P_18_MM D G S B (p D S) i 0 P_18_MM D G S B " L 180e-9 W 2e-6 M 1.0 "
CDL Netlist CDL Device Name = “P_18_MM” MPM0 D G S B P_18_MM W=2u L=180.0n M=1
UMC Confidential
76 Ver. B04_PB
UM180FDKMFC000000A_B
Assura Netlist Assura auLvs Device Name = “P_18_MM” c P_18_MM MOS DRAIN B
GATE B
SOURCE B
SUBSTRATE B ;;
* 4 pins * 4 nets * 0 instances i MP0 P_18_MM D G S B ; W 2e-06 effW 2e-06 L 1.8e-07;
UMC Confidential
77 Ver. B04_PB
UM180FDKMFC000000A_B
Width
P_18_MM (diagrammatic layout)
Length
Device Layers Layer
Color and Fill
NWEL DIFF PPLUS PO1 CONT ME1 SYMBOL (MMSYMBOL)
Device Derivation Device
Layer Derivation
Recognition
NWEL AND DIFF AND PPLUS CONTAINS PO1
G
PO1
D
NWEL AND DIFF AND PPLUS NOT PO1
S
NWEL AND DIFF AND PPLUS NOT PO1
B
NWEL
LVS Comparison Parameter
Calculation
Length
PO1 intersecting DIFF (illustrated above)
Width
PO1 inside DIFF (illustrated above)
UMC Confidential
78 Ver. B04_PB
UM180FDKMFC000000A_B * S and D are PERMUTABLE
UMC Confidential
79 Ver. B04_PB
UM180FDKMFC000000A_B
24.3 N_33_MM – 3.3 volt NMOS Transistor
Spectre Netlist Spectre Model Name = “n_33_mm” NM0 (D G S B) n_33_mm w=2u l=340.0n as=1.28e-12 ad=1.28e-12 ps=5.28u \ pd=5.28u m=(1)*(1)
HspiceS Netlist HspiceS Model Name = “N_33_MM” MNM0 D G S B N_33_MM L=340E-9 W=2E-6 AD=1.28E-12 AS=1.28E-12 PD=5.28E-6 +PS=5.28E-6 M=+1.00000000E+00
DIVA LVS Netlist DIVA Device Name = “N_33_MM” ; N_33_MM Instance /NM0 = auLvs device M0 d N_33_MM D G S B (p D S) i 0 N_33_MM D G S B " L 340e-9 W 2e-6 M 1.0 "
CDL Netlist CDL Device Name = “N_33_MM” MMN0 D G S B N_33_MM W=2u L=340.0n M=1
UMC Confidential
80 Ver. B04_PB
UM180FDKMFC000000A_B
Assura Netlist Assura auLvs Device Name = “N_33_MM” C N_33_MM MOS DRAIN B
GATE B
SOURCE B
SUBSTRATE B ;;
* 4 pins * 4 nets * 0 instances i MN0 N_33_MM D G S B ; W 2e-06 effW 2e-06 L 3.4e-07;
UMC Confidential
81 Ver. B04_PB
UM180FDKMFC000000A_B
Width
N_33_MM (diagrammatic layout)
Length
Device Layers Layer
Color and Fill
DIFF NPLUS PO1 CONT TG ME1 SYMBOL (MMSYMBOL)
Device Derivation Device
Layer Derivation
Recognition
DIFF AND NPLUS AND TG CONTAINS PO1
G
PO1
D
DIFF AND NPLUS AND TG NOT PO1
S
DIFF AND NPLUS AND TG NOT PO1
B
Substrate
LVS Comparison Parameter
Calculation
Length
PO1 intersecting DIFF (illustrated above)
Width
PO1 inside DIFF (illustrated above)
UMC Confidential
82 Ver. B04_PB
UM180FDKMFC000000A_B * S and D are PERMUTABLE
UMC Confidential
83 Ver. B04_PB
UM180FDKMFC000000A_B
24.4 P_33_MM – 3.3 volt PMOS Transistor
Spectre Netlist Spectre Model Name = “p_33_mm” PM0 (D G S B) p_33_mm w=2u l=340.0n as=1.28e-12 ad=1.28e-12 ps=5.28u \ pd=5.28u m=(1)*(1)
HspiceS Netlist HspiceS Model Name = “P_33_MM” MPM0 D G S B P_33_MM L=340E-9 W=2E-6 AD=1.28E-12 AS=1.28E-12 PD=5.28E-6 +PS=5.28E-6 M=+1.00000000E+00
DIVA LVS Netlist DIVA Device Name = “P_33_MM” ; P_33_MM Instance /PM0 = auLvs device M0 d P_33_MM D G S B (p D S) I 0 P_33_MM D G S B " L 340e-9 W 2e-6 M 1.0 "
CDL Netlist CDL Device Name = “P_33_MM” MPM0 D G S B P_33_MM W=2u L=340.0n M=1
UMC Confidential
84 Ver. B04_PB
UM180FDKMFC000000A_B
Assura Netlist Assura auLvs Device Name = “P_33_MM” c P_33_MM MOS DRAIN B
GATE B
SOURCE B
SUBSTRATE B ;;
* 4 pins * 4 nets * 0 instances i MP0 P_33_MM D G S B ; effW 2e-06 L 3.4e-07 W 2e-06;
UMC Confidential
85 Ver. B04_PB
UM180FDKMFC000000A_B
Width
P_33_MM (diagrammatic layout)
Length
Device Layers Layer
Color and Fill
NWEL DIFF PPLUS TG PO1 CONT ME1 SYMBOL ( MMSYMBOL)
Device Derivation Device
Layer Derivation
Recognition
NWEL AND DIFF AND PPLUS AND TG CONTAINS PO1
G
PO1
D
NWEL AND DIFF AND PPLUS AND TG NOT PO1
S
NWEL AND DIFF AND PPLUS AND TG NOT PO1
B
NWEL
UMC Confidential
86 Ver. B04_PB
UM180FDKMFC000000A_B
LVS Comparison Parameter
Calculation
Length
PO1 intersecting DIFF (illustrated above)
Width
PO1 inside DIFF (illustrated above) * S and D are PERMUTABLE
UMC Confidential
87 Ver. B04_PB
UM180FDKMFC000000A_B
24.5 N_LV_18_MM – 1.8 volt low vt NMOS Transistor
Spectre Netlist Spectre Model Name = “n_lv_18_mm” NM0 (D G S B) n_lv_18_mm w=2u l=240.0n as=9.8e-13 ad=9.8e-13 ps=4.98u \ pd=4.98u m=(1)*(1)
HspiceS Netlist HspiceS Model Name = “N_LV_18_MM” MNM0 D G S B N_LV_18_MM L=240E-9 W=2E-6 AD=980E-15 AS=980E-15 PD=4.98E-6 PS=4.98E-6 M=+1.00000000E+00
DIVA LVS Netlist DIVA Device Name = “N_LV_18_MM” ; N_LV_18_MM Instance /NM0 = auLvs device M0 d N_LV_18_MM D G S B (p D S) i 0 N_LV_18_MM D G S B " L 240e-9 W 2e-6 M 1.0 "
CDL Netlist CDL Device Name = “N_LV_18_MM” MMN0 D G S B N_LV_18_MM W=2u L=240.0n M=1
UMC Confidential
88 Ver. B04_PB
UM180FDKMFC000000A_B
Assura Netlist Assura auLvs Device Name = “N_LV_18_MM” C N_LV_18_MM MOS DRAIN B
GATE B
SOURCE B
SUBSTRATE B ;;
* 4 pins * 4 nets * 0 instances i MN0 N_LV_18_MM D G S B ; W 2e-06 effW 2e-06 L 2.4e-07;
UMC Confidential
89 Ver. B04_PB
UM180FDKMFC000000A_B Width
N_LV_18_MM (diagrammatic layout)
Length
Device Layers Layer
Color and Fill
DIFF NPLUS PO1 CONT VT (VTNL) ME1 SYMBOL (MMSYMBOL)
Device Derivation Device
Layer Derivation
Recognition
DIFF AND NPLUS AND VTNL CONTAINS PO1
G
PO1
D
DIFF AND NPLUS AND VTNL NOT PO1
S
DIFF AND NPLUS AND VTNL NOT PO1
B
Substrate
LVS Comparison Parameter
Calculation
Length
PO1 intersecting DIFF (illustrated above)
Width
PO1 inside DIFF (illustrated above)
UMC Confidential
90 Ver. B04_PB
UM180FDKMFC000000A_B * PLUS and MINUS are PERMUTABLE
UMC Confidential
91 Ver. B04_PB
UM180FDKMFC000000A_B
24.6 P_LV_18_MM – 1.8 volt low vt PMOS Transistor
Spectre Netlist Spectre Model Name = “p_lv_18_mm” PM0 (D G S B) p_lv_18_mm w=2u l=240.0n as=980e-15 ad=980e-15 ps=4.98u \ pd=4.98u m=(1)*(1)
HspiceS Netlist HspiceS Model Name = “P_LV_18_MM” MPM0 D G S B P_LV_18_MM L=240E-9 W=2E-6 AD=980E-15 AS=980E-15 PD=4.98E-6 PS=4.98E-6 M=+1.00000000E+00
DIVA LVS Netlist DIVA Device Name = “P_LV_18_MM” ; P_LV_18_MM Instance /PM0 = auLvs device M0 d P_LV_18_MM D G S B (p D S) i 0 P_LV_18_MM D G S B " L 240e-9 W 2e-6 M 1.0 "
CDL Netlist CDL Device Name = “P_LV_18_MM” MPM0 D G S B P_LV_18_MM W=2u L=240.0n M=1
UMC Confidential
92 Ver. B04_PB
UM180FDKMFC000000A_B
Assura Netlist Assura auLvs Device Name = “P_LV_18_MM” c P_LV_18_MM MOS DRAIN B
GATE B
SOURCE B
SUBSTRATE B ;;
* 4 pins * 4 nets * 0 instances i MP0 P_LV_18_MM D G S B ; W 2e-06 effW 2e-06 L 2.4e-07;
UMC Confidential
93 Ver. B04_PB
UM180FDKMFC000000A_B
Width
P_LV_18_MM (diagrammatic layout)
Length
Device Layers Layer
Color and Fill
NWEL DIFF PPLUS VT (VTPL) PO1 CONT ME1 SYMBOL (MMSYMBOL)
Device Derivation Device
Layer Derivation
Recognition
NWEL AND DIFF AND PPLUS AND VTPL CONTAINS PO1
G
PO1
D
NWEL AND DIFF AND PPLUS AND VTPL NOT PO1
S
NWEL AND DIFF AND PPLUS AND VTPL NOT PO1
B
NWEL
UMC Confidential
94 Ver. B04_PB
UM180FDKMFC000000A_B
LVS Comparison Parameter
Calculation
Length
PO1 intersecting DIFF (illustrated above)
Width
PO1 inside DIFF (illustrated above) * PLUS and MINUS are PERMUTABLE
UMC Confidential
95 Ver. B04_PB
UM180FDKMFC000000A_B
24.7 N_LV_33_MM – 3.3 volt low vt NMOS Transistor
Spectre Netlist Spectre Model Name = “n_lv_33_mm” NM0 (D G S B) n_lv_33_mm w=2u l=500.0n as=1.28e-12 ad=1.28e-12 ps=5.28u \ pd=5.28u m=(1)*(1)
HspiceS Netlist HspiceS Model Name = “N_LV_33_MM” MNM0 D G S B N_LV_33_MM L=500E-9 W=2E-6 AD=1.28E-12 AS=1.28E-12 PD=5.28E-6 PS=5.28E-6 M=+1.00000000E+00
DIVA LVS Netlist DIVA Device Name = “N_LV_33_MM” ; N_LV_33_MM Instance /NM0 = auLvs device M0 d N_LV_33_MM D G S B (p D S) i 0 N_LV_33_MM D G S B " L 500e-9 W 2e-6 M 1.0 "
CDL Netlist CDL Device Name = “N_LV_33_MM” MMN0 D G S B N_LV_33_MM W=2u L=500.0n M=1
UMC Confidential
96 Ver. B04_PB
UM180FDKMFC000000A_B
Assura Netlist Assura auLvs Device Name = “N_LV_33_MM” C N_LV_33_MM MOS DRAIN B
GATE B
SOURCE B
SUBSTRATE B ;;
* 4 pins * 4 nets * 0 instances i MN0 N_LV_33_MM D G S B ; W 2e-06 effW 2e-06 L 5e-07;
UMC Confidential
97 Ver. B04_PB
UM180FDKMFC000000A_B
Width
N_LV_33_MM (diagrammatic layout)
Length
Device Layers Layer
Color and Fill
DIFF NPLUS PO1 CONT VTNHL TG ME1 SYMBOL (MMSYMBOL)
Device Derivation Device
Layer Derivation
Recognition
DIFF AND NPLUS AND TG AND VTNHL CONTAINS PO1
G
PO1
D
DIFF AND NPLUS AND TG AND VTNHL NOT PO1
S
DIFF AND NPLUS AND TG AND VTNHL NOT PO1
B
Substrate
UMC Confidential
98 Ver. B04_PB
UM180FDKMFC000000A_B
LVS Comparison Parameter
Calculation
Length
PO1 intersecting DIFF (illustrated above)
Width
PO1 inside DIFF (illustrated above) * S and D are PERMUTABLE
UMC Confidential
99 Ver. B04_PB
UM180FDKMFC000000A_B
24.8 P_LV_33_MM – 3.3 volt low vt PMOS Transistor
Spectre Netlist Spectre Model Name = “p_lv_33_mm” PM0 (D G S B) p_lv_33_mm w=2u l=500.0n as=1.28e-12 ad=1.28e-12 ps=5.28u \ pd=5.28u m=(1)*(1)
HspiceS Netlist HspiceS Model Name = “P_LV_33_MM” MPM0 D G S B P_LV_33_MM L=500E-9 W=2E-6 AD=1.28E-12 AS=1.28E-12 PD=5.28E-6 PS=5.28E-6 M=+1.00000000E+00
DIVA LVS Netlist DIVA Device Name = “P_LV_33_MM” ; P_LV_33_MM Instance /PM0 = auLvs device M0 d P_LV_33_MM D G S B (p D S) I 0 P_LV_33_MM D G S B " L 500e-9 W 2e-6 M 1.0 "
CDL Netlist CDL Device Name = “P_LV_33_MM” MPM0 D G S B P_LV_33_MM W=2u L=500.0n M=1
UMC Confidential
100 Ver. B04_PB
UM180FDKMFC000000A_B
Assura Netlist Assura auLvs Device Name = “P_LV_33_MM” c P_LV_33_MM MOS DRAIN B
GATE B
SOURCE B
SUBSTRATE B ;;
* 4 pins * 4 nets * 0 instances i MP0 P_LV_33_MM D G S B ; effW 2e-06 L 5e-07 W 2e-06;
UMC Confidential
101 Ver. B04_PB
UM180FDKMFC000000A_B
Width
P_LV_33_MM (diagrammatic layout)
Length
Device Layers Layer
Color and Fill
NWEL DIFF PPLUS VTPHL TG PO1 CONT ME1 SYMBOL (MMSYMBOL)
Device Derivation Device
Layer Derivation
Recognition
NWEL AND DIFF AND PPLUS AND TG AND VTPHL CONTAINS PO1
G
PO1
D
NWEL AND DIFF AND PPLUS AND TG AND VTPHL NOT PO1
S
NWEL AND DIFF AND PPLUS AND TG AND VTPHL NOT PO1
B
NWEL
UMC Confidential
102 Ver. B04_PB
UM180FDKMFC000000A_B
LVS Comparison Parameter
Calculation
Length
PO1 intersecting DIFF (illustrated above)
Width
PO1 inside DIFF (illustrated above) * S and D are PERMUTABLE
UMC Confidential
103 Ver. B04_PB
UM180FDKMFC000000A_B
24.9 N_ZERO_18_MM – 1.8 volt zero vt NMOS transistor
Spectre Netlist Spectre Model Name = “n_zero_18_mm” NM0 (D G S B) n_zero_18_mm w=2u l=300.0n as=9.8e-13 ad=9.8e-13 ps=4.98u \ pd=4.98u m=(1)*(1)
HspiceS Netlist HspiceS Model Name = “N_ZERO_18_MM” MNM0 D G S B N_ZERO_18_MM L=300E-9 W=2E-6 AD=980E-15 AS=980E-15 PD=4.98E-6 PS=4.98E-6 M=+1.00000000E+00
DIVA LVS Netlist DIVA Device Name = “N_ZERO_18_MM” ; N_ZERO_18_MM Instance /NM0 = auLvs device M0 d N_ZERO_18_MM D G S B (p D S) i 0 N_ZERO_18_MM D G S B " L 300e-9 W 2e-6 M 1.0 "
CDL Netlist CDL Device Name = “N_ZERO_18_MM” MMN0 D G S B N_ZERO_18_MM W=2u L=300.0n M=1
UMC Confidential
104 Ver. B04_PB
UM180FDKMFC000000A_B
Assura Netlist Assura auLvs Device Name = “N_ZERO_18_MM” C N_ZERO_18_MM MOS DRAIN B
GATE B
SOURCE B
SUBSTRATE B ;;
* 4 pins * 4 nets * 0 instances i MN0 N_ZERO_18_MM D G S B ; W 2e-06 effW 2e-06 L 3e-07;
UMC Confidential
105 Ver. B04_PB
UM180FDKMFC000000A_B Width
N_ZERO_18_MM (diagrammatic layout)
Length
Device Layers Layer
Color and Fill
DIFF NPLUS PO1 CONT VTNI ME1 SYMBOL ( MMSYMBOL)
Device Derivation Device
Layer Derivation
Recognition
DIFF AND NPLUS AND VTNI CONTAINS PO1
G
PO1
D
DIFF AND NPLUS AND VTNI NOT PO1
S
DIFF AND NPLUS AND VTNI NOT PO1
B
Substrate
LVS Comparison Parameter
Calculation
Length
PO1 intersecting DIFF (illustrated above)
Width
PO1 inside DIFF (illustrated above)
UMC Confidential
106 Ver. B04_PB
UM180FDKMFC000000A_B •
24.10
PLUS and MINUS are PERMUTABLE
N_ZERO_33_MM – 3.3 volt zero vt NMOS Transistor
Spectre Netlist Spectre Model Name = “n_zero_33_mm” NM0 (D G S B) n_zero_33_mm w=2u l=500.0n as=1.28e-12 ad=1.28e-12 ps=5.28u \ pd=5.28u m=(1)*(1)
HspiceS Netlist HspiceS Model Name = “N_ZERO_33_MM” MNM0 D G S B N_ZERO_33_MM L=500E-9 W=2E-6 AD=1.28E-12 AS=1.28E-12 PD=5.28E-6 PS=5.28E-6 M=+1.00000000E+00
DIVA LVS Netlist DIVA Device Name = “N_ZERO_33_MM” ; N_ZERO_33_MM Instance /NM0 = auLvs device M0 d N_ZERO_33_MM D G S B (p D S) i 0 N_ZERO_33_MM D G S B " L 500e-9 W 2e-6 M 1.0 "
CDL Netlist CDL Device Name = “N_ZERO_33_MM” MMN0 D G S B N_ZERO_33_MM W=2u L=500.0n M=1
UMC Confidential
107 Ver. B04_PB
UM180FDKMFC000000A_B
Assura Netlist Assura auLvs Device Name = “N_ZERO_33_MM” C N_ZERO_33_MM MOS DRAIN B
GATE B
SOURCE B
SUBSTRATE B ;;
* 4 pins * 4 nets * 0 instances i MN0 N_ZERO_33_MM D G S B ; W 2e-06 effW 2e-06 L 5e-07;
UMC Confidential
108 Ver. B04_PB
UM180FDKMFC000000A_B
Width
N_ZERO_33_MM (diagrammatic layout)
Length
Device Layers Layer
Color and Fill
DIFF NPLUS PO1 CONT VT (VTNL) TG ME1 SYMBOL (MMSYMBOL)
Device Derivation Device
Layer Derivation
Recognition
DIFF AND NPLUS AND TG AND VTNL CONTAINS PO1
G
PO1
D
DIFF AND NPLUS AND TG AND VTNL NOT PO1
S
DIFF AND NPLUS AND TG AND VTNL NOT PO1
B
Substrate
UMC Confidential
109 Ver. B04_PB
UM180FDKMFC000000A_B
LVS Comparison Parameter
Calculation
Length
PO1 intersecting DIFF (illustrated above)
Width
PO1 inside DIFF (illustrated above) * S and D are PERMUTABLE
UMC Confidential
110 Ver. B04_PB
UM180FDKMFC000000A_B
24.11 N_BPW_18_MM – 1.8 volt triple-well NMOS Transistor
Spectre Netlist Spectre Model Name = “n_bpw_18_mm” NM0 (D G S B) n_bpw_18_mm w=2u l=180.0n as=9.8e-13 ad=9.8e-13 ps=4.98u \ pd=4.98u m=(1)*(1)
HspiceS Netlist HspiceS Model Name = “N_BPW_18_MM” MNM0 D G S B N_BPW_18_MM L=180E-9 W=2E-6 AD=980E-15 AS=980E-15 PD=4.98E-6 PS=4.98E-6 M=+1.00000000E+00
DIVA LVS Netlist DIVA Device Name = “N_BPW_18_MM” ; N_BPW_18_MM Instance /NM0 = auLvs device M0 d N_BPW_18_MM D G S B (p D S) i 0 N_BPW_18_MM D G S B " L 180e-9 W 2e-6 M 1.0 "
CDL Netlist CDL Device Name = “N_BPW_18_MM” MMN0 D G S B N_BPW_18_MM W=2u L=180.0n M=1
UMC Confidential
111 Ver. B04_PB
UM180FDKMFC000000A_B
Assura Netlist Assura auLvs Device Name = “N_BPW_18_MM” C N_BPW_18_MM MOS DRAIN B
GATE B
SOURCE B
SUBSTRATE B ;;
* 4 pins * 4 nets * 0 instances i MN0 N_BPW_18_MM D G S B ; W 2e-06 effW 2e-06 L 1.8e-07;
UMC Confidential
112 Ver. B04_PB
UM180FDKMFC000000A_B Width
N_BPW_18_MM (diagrammatic layout)
Length
Device Layers Layer
Color and Fill
NWEL DIFF NPLUS PO1 CONT TWEL ME1 SYMBOL ( MMSYMBOL)
Device Derivation Device
Layer Derivation
Recognition
DIFF AND NPLUS AND TWEL CONTAINS PO1
G
PO1
D
DIFF AND NPLUS AND TWEL NOT PO1
S
DIFF AND NPLUS AND TWEL NOT PO1
B
TWEL
LVS Comparison Parameter
Calculation
Length
PO1 intersecting DIFF (illustrated above)
Width
PO1 inside DIFF (illustrated above)
UMC Confidential
113 Ver. B04_PB
UM180FDKMFC000000A_B
* PLUS and MINUS are PERMUTABLE
UMC Confidential
114 Ver. B04_PB
UM180FDKMFC000000A_B
24.12 N_BPW_33_MM – 3.3 volt triple-well NMOS Transistor
Spectre Netlist Spectre Model Name = “n_bpw_33_mm” NM0 (D G S B) n_bpw_33_mm w=2u l=340.0n as=1.28e-12 ad=1.28e-12 ps=5.28u \ pd=5.28u m=(1)*(1)
HspiceS Netlist HspiceS Model Name = “N_BPW_33_MM” MNM0 D G S B N_BPW_33_MM L=340E-9 W=2E-6 AD=1.28E-12 AS=1.28E-12 PD=5.28E-6 PS=5.28E-6 M=+1.00000000E+00
DIVA LVS Netlist DIVA Device Name = “N_BPW_33_MM” ; N_BPW_33_MM Instance /NM0 = auLvs device M0 d N_BPW_33_MM D G S B (p D S) i 0 N_BPW_33_MM D G S B " L 340e-9 W 2e-6 M 1.0 "
CDL Netlist CDL Device Name = “N_BPW_33_MM” MMN0 D G S B N_BPW_33_MM W=2u L=340.0n M=1
UMC Confidential
115 Ver. B04_PB
UM180FDKMFC000000A_B
Assura Netlist Assura auLvs Device Name = “N_BPW_33_MM” C N_BPW_33_MM MOS DRAIN B
GATE B
SOURCE B
SUBSTRATE B ;;
* 4 pins * 4 nets * 0 instances i MN0 N_BPW_33_MM D G S B ; W 2e-06 effW 2e-06 L 3.4e-07;
UMC Confidential
116 Ver. B04_PB
UM180FDKMFC000000A_B
Width
N_BPW_33_MM (diagrammatic layout)
Length
Device Layers Layer
Color and Fill
NWEL DIFF NPLUS PO1 CONT TWEL TG ME1 SYMBOL (MMSYMBOL)
Device Derivation Device
Layer Derivation
Recognition
DIFF AND NPLUS AND TG AND TWEL CONTAINS PO1
G
PO1
D
DIFF AND NPLUS AND TG AND TWEL NOT PO1
S
DIFF AND NPLUS AND TG AND TWEL NOT PO1
B
TWEL
UMC Confidential
117 Ver. B04_PB
UM180FDKMFC000000A_B
LVS Comparison Parameter
Calculation
Length
PO1 intersecting DIFF (illustrated above)
Width
PO1 inside DIFF (illustrated above) * S and D are PERMUTABLE
UMC Confidential
118 Ver. B04_PB
UM180FDKMFC000000A_B
24.13
RSPD_MM – P+ diffused resistor w/ salicide
NOTE: Dog-bone configurations are permitted. NOTE: If: 0.24um
View more...
Comments
