# Tutorial 7

May 7, 2018 | Author: tutulkar | Category: Field Effect Transistor, Mosfet, Semiconductor Devices, Amplifier, Electronic Circuits

#### Description

TUTORIAL 7

Theoretical Questions: Q1.

Explain on the basic operation of the n-channel JFET. Draw the drain characteristics of the mentioned JFET type and denote the important parameters on the graph.

Q2.

Explain why the JFET is called a unipolar device. Your explanation must be based on the n-channel or p-channel device which is biased to operate as an amplifier.

Q3.

What is one advantage of FET over BJT?

Q4.

What is the main advantage of using self-biasing in a JFET amplifier circuit? Draw the self-biasing circuit.

Q5.

State the three basic configurations of the JFET circuit. Compare and give brief  description on the circuits’ voltage gain, input and output impedances. State the main application for each configuration.

Q6.

Describe in detail, with the help of appropriate illustrations, the operation of the n-channel E-MOSFET under the following biasing conditions: drain and source are grounded, no biasing voltage at the gate drain and source are grounded, small positive voltage at the gate small positive voltage at the gate, small positive voltage at the drain and source small positive voltage at the gate, V DS increased from the value in (c)

(a) (b) (c) (d) Q7.

Draw the schematic of the p-channel E-MOSFET in its typical operation. Explain on the drain and transfer characteristics of this circuit.

Q8.

Draw the cross section and the drain characteristics of an n-channel E-MOSFET at the different biasing condition specified below:

(i)

VGS < VGS(th) and VDS > 0

(ii)

VGS > VGS(th) and VDS > VDS(sat)

(iii)

VGS > VGS(th) and VDS = VDS(sat)

(iv)

VGS > VGS(th) and VDS > VDS(sat)

Q9.

versus sus VDS curve for an ideal n-channel E-MOSFET (NMOS). Label Draw the ID ver the operating mode regions and write the I D expression for each region.

1

Q10. Q11.

With the help of illustrations, explain briefly on the operation of the DE and E MOSFETs as amplifiers and comment on the differences. For the circuit shown below, (a)give detailed explanation on the reason why ID will decrease with the increment of  VGG at a fixed VDD . (b)what will happen if  VGG = VGS(off) ? RD ID

VDD

VGG

Q12.

How is the drain current controlled in the n-channel JFET? Use illustrations to help you in giving your explanations.

Calculations: Q1.

The JFET in the following diagram has the following characteristics, IDSS = 5mA and V GS(off) = -3V . Determine VGSQ and VO if  (a) VG = 0 V (b) VG =10 V

RD 3 kΩ

RS

VG

8 kΩ

2

Vo

Q2.

Given the drain to ground voltage is equivalent to 5 V for the circuit below. Calculate ID , VGS , VDS and VS for this circuit. +VDD 9V

Q3.

R1

RD

10 MΩ

4.7 kΩ

R2

RS

2.2MΩ

3.3 kΩ

Calculate the voltage gain and the input and output impedances for the common source circuit shown below. R GS =1000 MΩ, g m = 4000 μS and rds = 80 k Ω . Determine the voltage gain if C 2 is absent. VDD RD 4.7 kΩ

C3

R Supply C 1

vs

vi

vo

RG 390 kΩ

RS 2.7 kΩ

Q4.

RL 68 kΩ

C2

The JFET in the following diagram has V p = -3 V and IDSS = 9 mA . Calculate the value of all the resistors so that VG =5 V,I D = 4mA and V D =11V . The design has 0.05 mA flowing through the voltage divider.

3

R G1

RD

R G2

RS

Q5.

The gate current can be ignored for the JFET in the circuit below. If  VDD = -20 V, IDSS =10 mA, IDQ = 8 mA, V GS(off) = 4 V, R S = 0 Ω andR D =1.5 k Ω , determine

(i) (ii)

VGG and VDSQ VDD RD

C3

+

C1

+ vi

vo

RG RS

VGG

-

-

Q6.

(a) (b) (c)

For the circuit shown below, R G >> R S1,R S2 , I DSS =10 mA, V GS(off) = -4 V, V DD =15 V, V DSQ =10 V and V GSQ = -2 V. Determine: VS RS1 RS2

4

VDD

ii

CC CC iL

RG

R S1

v in

R S2

CS

Q7.

RL

vL

VS

(a)Self-biasing is implemented on the following JFET circuit. Assume that the gate current can be neglected (I G = 0). Show that if VDD > 0, VGS < 0. This condition will enable correct device biasing.   DD =15 V and V DSQ = 7 V , calculate I DQ and VGSQ. (b)If  R D = 3 kΩ,R S = 1 kΩ, V VDD

RD

RG

RS

Q8.

Referring to the following circuits, determine the DE MOSFET’s mode of  operation (depletion, enhancement or zero). Give explanation to your answer. Assume R G is very large that the current flowing through it can be neglected resulting in VRG ≈ 0 .

5

+VDD

+VDD

RD

RD

RG RG

RS

(a)

(b)

+VDD

-VDD

RD

RD

RG

RS

(c)

Q9.

(d)

The JFET in the following circuit has V p = -3 V. If V S = -1 V when the device is in its pinched-off region, calculate I DSS. VSS

1mA VS = -1 V

VDD

6

Q10.

For a JFET that is operating at V GS = -1 V, has Vp = -2 V and IDSS = 8 mA, determine the variation required in the V GS to increase the I D by 0.4 mA. What is the variation required in the V GS to reduce the I D by 0.4 mA from the same initial value. Why is the variation in the V GS different for both cases? What is the JFET type? Give explanations for your answers.

Q11.

For

the

circuit

shown

below,

VGS(off) = -2 V and K = 2 m A/V 2 .

Given

2

IDSS = K [ VGS(off) ] . Neglecting the VDS effect on ID in the pinched-off region (also

known as the constant current region or saturation region), calculate the voltage at the source of the transistor. Determine the operation mode of the device. Give two reasons for your answer. 5V

2 mA

Q12.

(a)Determine the voltages at the terminal, the transconductance and the voltage gain for the following DE-MOSFET circuit. Given: gain, A v = gm x RD, gm0 = 2000 μmho, VGS(off) = -4 V and I DSS = 4 mA. (b)Determine the transistor’s mode of operation, i.e. whether it is in depletion or enhancement mode. Based on the results from the calculation in (a), give two reasons for your answer. 11 V

R1

RD

100MΩ

1k Ω v out

v in

R2 10 MΩ

7

Q13.

Each of the transistor in the circuit below has VGS(th) = 2 V, μ nC ox = 20 μA/V 2, λ = 0 and L 1 = L 2 =10 μm . Find the value of R and the required gate width for Q 1 and Q2 to obtain the voltages and current as shown in the diagram.

Q2

Q1

Q14. In the common source amplifier of the circuit below, let -3 R D = 3 kΩ, g m = 2 × 10 S and rds = 30 k Ω . Using the simplified, low-frequency small-

signal equivalent circuit, find an expression for the voltage-gain ratio A v = v o / v in and then evaluate A v . VDD

RD

vi

RG

RS

8

CS

Q15.

E-MOSFETs are normally found operating as switches in digital ICs. Below is a typical switching circuit. Determine the waveform v out for the shown v in. Use the given drain characteristics to help you in your calculations. Repeat if R is changed to 10 k Ω. VDD = 20 V

R = 4.7 kΩ

+

v out

+

10 0

v in

-

Q16.

(i) (ii)

Fixed biasing can be implemented on the E-MOSFET as shown in the diagram below. The drain characteristic of the E-MOSFET is included. R 1 = 60 kΩ, R 2 = 40 k Ω, R D = 3 k Ω, V DD = 15 V. Assume I G = 0. Calculate VGSQ. Determine VDSQ and IDQ from the drain characteristic. VDD

RD

R1

R2

9