TSMC 4 0 Design Flow Diagram

TSMC Hierarchical Design Flow Diagram

TSMC Hierarchical Design Flow Diagram / TSMC Reference Flow Release 3.0

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Prototyping

Netlist, Timing Constraint, Size

Hierarchical Timing Closure

budgeting (PT) RC Correlation(FE->PC)

RC Correlation (StarRCXT->Apollo->FE)

flattened prototyping (FE)

Fullchip Verification

full chip verification: IR analysis (Voltage Storm) DRC LVS (Calibre) Formal Verification (Formality, Verplex) xtalk (CeltIc)

block frame view and pdb generation(APO) block preCTS implementation (PC): placement, timing optimization block timing model generation

floorplanning (FE) top preCTS implementation (PC): placement, timing optimization top level trial route (APO)

IR drop analysis (MarsRail)

hierarchical prototyping (FE)

top/block implementation (APO): CTS, track assign, SDF

APO: Apollo FE: First Encounter NDC: Nautilus DC PC: Physical Compiler PT: PrimeTime

RC Correlation (APO->PC) block/top post CTS implementation (PC) block/top detail route (APO): double via, xtalk, antenna

characterizing timing-violated blocks(PT)

fullchip STA (PT, StarRCXT, NDC)

TSMC Hierarchical Design Flow Diagram / TSMC Reference Flow Release 3.0

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Prototyping original netlist timing constraint (sdc) timing library(.lib) standard cell library(.cdump) technology file

initial floorplan (I/O, critical macro placement)

Amoeba Place

RC Correlation (StarRCXT->Apollo->FE)

flattened prototyping (FE)

saved initial placement

Fullchip Verification

design import

save place

original netlist timing constraint (sdc) timing library(.lib) standard cell library(.cdump) technology file

congestion repair loop

Netlist, Timing Constraint, Size

Hierarchical Timing Closure

load placement, load routing create fences (shaping, resizing)

saved initial placement and routing

specify partition macro placement refinement

trial route saved initial routing

design import

CTS

Amoeba place

trial route

save route power planning

Extract RC

no congestion OK?

trial route

yes

Timing Analysis

CTS

IPO

trial route

floorplan file(.fp) placement file(.place) netlist(.v)

save floorplan save placement save netlist

IR drop analysis (MarsRail)

timing repair loop

Extract RC

Timing Analysis

IPO

hierarchical prototyping (FE) no

commit partition

congestion repair loop

top level trial route (APO)

feed-through buffer insertion, refine placement, trial route

Is Timing Met?

timing repair loop

floorplanning (FE)

no

yes Save Partition

top level route

Congestion OK?

no

Partitioned netlist, constraint, floorplan

Is Timing Met? yes

yes

TSMC Hierarchical Design Flow Diagram / TSMC Reference Flow Release 3.0

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Prototyping

Netlist, Timing Constraint, Size

RC Correlation (StarRCXT->Apollo->FE)

Hierarchical Timing Closure

1. partitioned netlist 2. partitioned timing constraint 3. standard cell library 4. macro library 5. timing library

Fullchip Verification

modify top level floorplan

Design Import Load Floorplan Macro Placement AmoebaPlace CTS

Partitioned Floorplan (.fp)

TrialRoute

flattened prototyping (FE)

no

congestion OK? yes

floorplanning (FE)

Extract RC Timing Analysis

top level trial route (APO)

IPO no

Is timing met?

IR drop analysis (MarsRail)

hierarchical prototyping (FE) (Block Level)

yes

Netlist PDEF

Save netlist Save Placement

SPEF Setload

Extract RC

SDF

Delay Calculation

Create Stamp Model

TSMC Hierarchical Design Flow Diagram / TSMC Reference Flow Release 3.0

PT:Budgeting RC Correlation

Model Definition Model Data

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Prototyping

Netlist, Timing Constraint, Size

RC Correlation (StarRCXT->Apollo->FE)

Hierarchical Timing Closure

1. Standard Cell Library 2. Timing Library 3. Technology file

top level trial route (APO)

IR drop analysis (MarsRail)

Design Import Load Floorplan AmoebaPlace CTS

Stamp Models of Each Partition

Trial Route congestion OK?

flattened prototyping (FE)

floorplanning (FE)

Fullchip Verification

1.Macro Libraries of Each Partition (.cdump) 2.Top Level Netlist 3.Top Level Timing Constraints

Top Level Floorplan

hierarchical prototyping (FE) (Top Level)

TSMC Hierarchical Design Flow Diagram / TSMC Reference Flow Release 3.0

no

yes Extract RC Timing Analysis IPO no

Is timing met? yes Save netlist Save Partition

Netlist

Extract RC

SPEF Setload

Delay Calculation

SDF

Save IO File (pin locations)

.tdf

PT:Budgeting RC Correlation

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Hierarchical Timing Closure

Prototyping

Fullchip Verification

budgeting (PT) RC Correlation(FE->PC)

PC • netlist • timing constraint

block frame view and pdb generation(APO) block level preCTS implementation (PC): placement, timing optimization

design import

PC .SPEF

write boundary parasitics

PC .SDF

remove SDF on boundary

block timing model extraction top level preCTS implementation (PC): placement, timing optimization top/block level implementation (APO): CTS, track assign, SDF

1.boundary net transition time 2.boundary capacitance

load boundary parasitics

RC Correlation(APO->PC)

extract timing model

block/top post CTS implementation (PC) block/top detail route (APO): double via, xtalk, antenna

characterizing timing-violated blocks (PT)

PC

fullchip STA (PT, StarRCXT, NDC)

TSMC Hierarchical Design Flow Diagram / TSMC Reference Flow Release 3.0

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Hierarchical Timing Closure

Prototyping

budgeting (PT)

Fullchip Verification

Create Lib (Ref = Std) FE • netlist(simplified) • floorplan script • tdf files • Timing constraints (Clock information only)

RC Correlation(FE->PC)

block frame view and pdb generation(APO) block level preCTS implementation (PC): placement, timing optimization

NetlistIn

load floorplan script metal_case.pl

Make Macro

block timing model extraction

Load Timing Constraint

top level preCTS implementation (PC): placement, timing optimization

.CLF

top/block level implementation (APO): CTS, track assign, SDF

Dump LEF (dumpLibLEF.scm)

lef2plib

.LEF

PLIB

Create Timing Model

RC Correlation(APO->PC)

.CLF with clock port capacitance, clock port subtype, port direction

Read PLIB Load Timing CLF

write PDB

PDB

block/top post CTS implementation (PC) block/top detail route (APO): double via, xtalk, antenna

characterizing timing-violated blocks (PT)

APO CTS PC

fullchip STA (PT, StarRCXT, NDC)

TSMC Hierarchical Design Flow Diagram / TSMC Reference Flow Release 3.0

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Hierarchical Timing Closure

Prototyping

budgeting (PT)

Fullchip Verification

Block level

Top level

Create Lib (RefLib = Std)

Create Lib (RefLib = Std cell, generated pdb library)

RC Correlation(FE->PC) NetlistIn

block frame view and pdb generation(APO)

Load floorplan script block level preCTS implementation (PC): placement, timing optimization

PC netlist .pdef

metal_case.pl

FE 1.floorplan script 2.power plan script 3.tdf

Load power plan script Load timing constraints

FE timing constraint (clock information only)

block timing model extraction

top level preCTS implementation (PC): placement, timing optimization

pdef_pc2apo.pl

Read PDEF (readPDEF3.scm) Purge clock net/ default TranDelay

top/block level implementation (APO): CTS, track assign, SDF RC Correlation(APO->PC)

CTS related files

Report skew

Define Synchronous Pin

Dump PDEF (dumpPDEF3.scm)

block/top post CTS implementation (PC) block/top detail route (APO): double via, xtalk, antenna

CTS

pdef_apo2pc.pl

*.hvout

Hierarchical Netlist Out characterizing timing-violated blocks (PT)

sdf_apo2pc.pl Write SDF/Setload

fullchip STA (PT, StarRCXT, NDC)

TSMC Hierarchical Design Flow Diagram / TSMC Reference Flow Release 3.0

*_cts_fixed.pdef

dc_apo2pc.pl

PC

*_cts_fixed.sdf *_cts_fixed.dc

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Prototyping

Hierarchical Timing Closure

Fullchip Verification

budgeting (PT)

Block level

Top level

RC Correlation(FE->PC)

Create Lib (RefLib = Std)

Create Lib (RefLib = Std cell, generated pdb library)

block frame view and pdb generation(APO) block level preCTS implementation (PC): placement, timing optimization

NetlistIn

PC netlist .pdef

block timing model extraction

top level preCTS implementation (PC): placement, timing optimization top/block level implementation (APO): CTS, track assign, SDF

Load power plan script

metal_case.pl

FE 1.floorplan script 2.power plan script 3.tdf

Read PDEF Define Synchronous Pin (Top level only) APO CTS related files generated after CTS

preRoute CTS Route Xtalk reduction route

RC Correlation(APO->PC)

Antenna-fixing route

block/top post CTS implementation (PC)

block/top detail route (APO): double via, xtalk, antenna

Load floorplan script

characterizing timing-violated blocks (PT)

Dump PDEF (dumpPDEF3.scm)

pdef_apo2pc.pl

Write SDF/Setload

dc_apo2pc.pl

Write SPEF

sdf_apo2pc.pl

*_cts_fixed.pdef *_cts_fixed.sdf

PC

*_cts_fixed.dc *_route.SPEF

STA

fullchip STA (PT, StarRCXT, NDC)

TSMC Hierarchical Design Flow Diagram / TSMC Reference Flow Release 3.0

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