Trkm 10dc12r Datasheet b

TRKM-10DC12R Master Controller

Power System Controllers Master and Slave Configuration

Features ·

Digital Signal Processors (DSP) based with Bel Firmware

·

Provides power up and power down sequencing

·

Fault detection and reporting

·

Analog input monitoring

·

Voltage margining via closed loop trim

·

Comparator function

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I2C, SMBus, or PMBus compatible serial interface

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Configurable through serial interface, Customizable through software

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Programmed parameters saved in non-volatile memory

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Intelligent configuration capability

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Power-down data log for identifying fault conditions

·

Boot loader for in-system upgrading

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3V3 logic levels

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Master/slave configuration for support of large power systems

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100-pin 12mm x 12mm TQFP package (master)

Applications ·

Data storage servers

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Networking

·

Telecommunications

Description These on board power system controllers provide a cost effective high performance solution for controlling, monitoring, and sequencing multiple Point of Load (PoL) converters on system boards. The sequencers use a digital signal processor (DSP) engine and Bel’s firmware to implement a portfolio of board level control features typically required in a multiple voltage power system. The master and slave part configuration allows control of large power systems, either on one system board or separate boards with minimal I/O required between the parts. The TRKM-10DC12R master device can perform active trim control and monitoring of up to 8 analog PoL converters and enable and monitor an additional 30 digital PoLs, VRMs, or other analog inputs. The use of analog multiplexers is required on some of these inputs. There are 17 enable signals that are configurable for controlling how the converters are enabled. Figure 1 provides a block diagram of the master/slave system.

Bel Power 2400 Computer Drive Westborough, MA 01581 belpower.com Rev. B

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TRKM-10DC12R

Power System Controllers

Master Controller

Master and Slave Configuration

Digital I/Os Enable, Margin Up/Down, Reset In, Power Good Out, Reset Out, etc.

Master Power System Controller Analog Voltage Monitoring

Digital I/O Control

(analog inputs)

MUX select for additional analog voltages

External Reference Vin Monitor Additional Analog Voltages to Monitor APoL Vout Monitors

I2C Clock

Main Engine

I2C Engine

Active Trim Control

APoL Trim PWMs

Vin Trim

(PWM outputs) Trim Circuit

Data

APoL Converters Vout

Internal Flash

Sequence Up/Down Control

(board configuration data, fault log)

(digital outputs)

Enable

GND

PIF Enables

Slave Part Communication SPI

Digital I/O (Enable, Power Good)

(SS, Clock, MOSI, MISO)

Master Part Communication

Analog Voltage Monitoring

Digital I/Os

Digital I/O Control Margin Up/Down, Reset In, Reset Out , etc .

(analog inputs)

APoL Vout Monitors

Clock

I2C Data

External Reference Vin Monitor Additional Analog Voltages to Monitor

I2C Engine

Main Engine

Active Trim Control (PWM outputs)

APoL Trim PWMs Trim Trim Circuit

Sequence Up/Down Control

Internal Flash (board configuration data , fault log )

(digital outputs)

Vin

APoL Converters

Vout

Enable GND

PIF Enables

Slave Power System Controller

Figure 1

Functional Block Diagram Bel Power 2400 Computer Drive Westborough, MA 01581 belpower.com Rev. B

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TRKM-10DC12R

Power System Controllers

Master Controller

Master and Slave Configuration

Theory of Operation Each part is individually configured to define the rail parameters and sequencing order of the voltages for which each controller is responsible. Board ID inputs are used to define specific boards so that single code releases can be deployed across different system configurations. Though the controllers function independently, their operation is integrated through digital I/O handshaking to handle enabling and fault detection of the slave controller. When the main controller is enabled, it then enables and monitors the slave controller like it handles other rails. That is, it asserts the slave enable signal, delays for the configured time, and then monitors the slave digital power good signal. If a fault occurs on the slave, the master also faults off (if so configured) with the fault log indicating the slave fault. SPI communication between the master and slave allows the system host controller a single point of contact to query and manage the controllers. The system host controller communicates with the master using I2C. If the system host accesses rails that are managed by the slave, the master passes through the commands to the slave through the SPI communication between the two parts. The master-slave communication also provides slave fault log details to the master. There is also an I2C interface in the slave which is used for system boot loading and debugging. The remainder of this document provides details of the master device.

I/O Assignment Summary I/O Type Analog Input Digital Input

Quantity 31 14

Signals Vin, APoLs 1-8, DPoLs 1-21, Analog Board ID Enable, Mfg Mode, Margin (2), Alt Volt Select, VNN VID (2), Reset (2), Board ID (3), Slave Power Good, VR Hot

Digital Output

23

Power Good, Warning, Slave Enable, Mux Sel, IO PIF/OV Trip, Reset A, PoL Enables (17)

PWM Trim External Reference I2C Communication SPI Communication Power

8 2 2 3 15

APoLs 1-8 VREF-, VREF+ I2C Data, I2C Clock SDO, SDI, SCK, (SS not used) VDD, VSS, AVDD, AVSS, VCAP/VDDCORE

Programming

1

MCLR, (PGD, PGC shared)

I/O Definitions Pin # 1 2 3 4 5

Signal Description APoL 1 Trim VDD DPoL 17 Monitor DPoL 18 Monitor Analog Board ID

I/O Type or Function PWM Trim Power Analog Input Analog Input Analog Input

5V Tolerant Y N N N N Bel Power 2400 Computer Drive Westborough, MA 01581 belpower.com

Rev. B

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TRKM-10DC12R Master Controller Pin # 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Signal Description DPoL 4 Monitor DPoL 5 Monitor DPoL 6 Monitor DPoL 7 Monitor Board ID 0 Board ID 1 Board ID 2 MCLR Warning VSS VDD Enable/Board Seated DPoL 8 A/B Monitor DPoL 9 A/B Monitor APoL 5 Monitor APoL 4 Monitor APoL 3 Monitor APoL 2 Monitor APoL 1 Monitor Vin Monitor APoL 6 Monitor APoL 7 Monitor VREFVREF+ AVDD AVSS APoL 8 Monitor DPoL 19 Monitor DPoL 20 Monitor DPoL 21 Monitor VSS VDD Slave Enable APoL 2 Trim APoL 3 Trim VR Hot DPoL 1 Monitor DPoL 2 Monitor DPoL 3 Monitor VSS VDD Slave Power Good Power Good

Power System Controllers Master and Slave Configuration I/O Type or Function Analog Input Analog Input Analog Input Analog Input Digital Input Digital Input Digital Input Programming Digital Output Power Power Digital Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input External Reference External Reference Power Power Analog Input Analog Input Analog Input Analog Input Power Power Digital Output PWM Trim PWM Trim Digital Input Analog Input Analog Input Analog Input Power Power Digital Input Digital Output

5V Tolerant N N N N N N N Y N N N Y N N N N N N N N N N N N N N N N N N N N Y Y Y N N N N N N Y Y Bel Power 2400 Computer Drive Westborough, MA 01581 belpower.com

Rev. B

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TRKM-10DC12R Master Controller Pin # 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

Signal Description AVS Selection Manufacturing Mode (Margin Enable) APoL 4 Trim APoL 5 Trim PCH Reset Not used VDD VNN VID 1 VNN VID 0 Enable Output 1 Enable Output 2 Enable Output 3 Enable Output 4 VDD Enable Output 5 Enable Output 6 VSS Reset In Enable Output 7 Enable Output 8 I2C Data I2C Clock Enable Output 9 APoL 6 Trim Margin High / PGD Input for ICD Margin Low / PGC Input for ICD VSS APoL 7 Trim APoL 8 Trim Enable Output 15 Enable Output 10 IO PIF Enable / OVP Trip Enable Output 16 Enable Output 17 Reset A Output Enable Output 11 VCAP/VDDCORE VDD Enable Output 12 Enable Output 13 Enable Output 14 Analog Voltage Mux Select DPoL 10 A/B Monitor

Power System Controllers Master and Slave Configuration I/O Type or Function Digital Input Digital Input PWM Trim PWM Trim Digital Input Not used Power Digital Input Digital Input Digital Output Digital Output Digital Output Digital Output Power Digital Output Digital Output Power Digital Input Digital Output Digital Output I2C Communication I2C Communication Digital Output PWM Trim Digital Input Digital Input Power PWM Trim PWM Trim Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output Power Power Digital Output Digital Output Digital Output Digital Output Analog Input

5V Tolerant Y Y Y Y Y Y N N N Y Y Y Y N N N N Y Y Y Y Y Y Y N N N Y Y Y Y Y Y Y N N N N Y Y Y Y N Bel Power 2400 Computer Drive Westborough, MA 01581 belpower.com

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TRKM-10DC12R Master Controller Pin # 92 93 94 95 96 97 98 99 100

Signal Description DPoL 11 A/B Monitor DPoL 12 A/B Monitor DPoL 13 A/B Monitor SDO SDI SCK DPoL 14 A/B Monitor DPoL 15 A/B Monitor DPoL 16 A/B Monitor

Power System Controllers Master and Slave Configuration I/O Type or Function Analog Input Analog Input Analog Input SPI Communication SPI Communication SPI Communication Analog Input Analog Input Analog Input

5V Tolerant N N N Y Y Y N N N

The voltage on 5V tolerant digital input pins can exceed VDD as indicated in the Absolute Maximum Ratings section. 5V tolerant digital output pins can be configured with the open-drain feature which allows the generation of outputs higher than VDD by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification defined in the Electrical Specifications.

Signal Definitions Signal Analog Board ID Analog Voltage Mux Select

Type Analog Input Digital Output

APoL Monitor

Analog Input

APoL Trim

PWM Output

AVS Selection

Digital Input

Board ID

Digital Input

DPoL Monitor

Analog Input

Enable Outputs

Digital Output

Enable/Board Seated

Digital Input

I2C Clock

I2C Communications

I2C Data

I2C

Definition Analog voltage for specifying unique board ID. See Board ID below. Selection signal for analog voltage monitor multiplexers. This signal shall be routed to the select input of the analog voltage multiplexers. When this signal is low the controller reads the A voltages. When it is high it reads the B voltages. Analog PoL output voltage monitor (must be scaled using attenuating resistors if voltage exceeds reference voltage). PWM outputs for actively trimming the analog PoLs to their desired set points. See Using the PWM Trim Outputs below. When asserted the alternate voltage limits will be used for converters configured for dual set-points. Any analog POL converters configured for dual set-points will be trimmed to the alternate set-point. When de-asserted the normal voltage set-points and limits will be used. These three digital inputs along with the Analog Board ID define a board identification number for controlling which board specific configuration data is loaded. Digital PoL, VRM, or other voltage monitor (must be scaled using attenuating resistors if voltage exceeds reference voltage). Enable signal for the APoL, DPoL, or VRM converters. The actual assignment of which converters are enabled by each output is configurable. Asserted during sequence up and de-asserted during sequence down. When asserted the board is sequenced up if the input voltage is valid. When de-asserted the board is sequenced down. This function can be overridden as defined in the separate interface document. Synchronous serial clock input/output for I2C communication. Since this is an I2C slave device, the master drives the clock. Clock stretching may occur if necessary according to the I2C specification. Synchronous serial bi-directional data line for I2C communication. Bel Power 2400 Computer Drive Westborough, MA 01581 belpower.com Rev. B

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TRKM-10DC12R Master Controller Signal IO PIF Enable / OVP Trip

Type Communications Digital Output

Manufacturing Mode

Digital Input

Margin High Margin Low MCLR*

Digital Input Digital Input Programming

PGC PGD Power Good

Programming Programming Digital Output

Reset In Reset Out

Digital Input Digital Output

SCK

Slave Enable

SPI Communications SPI Communications SPI Communications Digital Output

Slave Power Good

Digital Input

Vin Monitor

Analog Input

VNN VID VR Hot Warning

Digital Input Digital Input Digital Output

AVDD

Power

AVSS VCAP/VDDCORE

Power Power

SDI SDO

Power System Controllers Master and Slave Configuration Definition If this pin is configured as the IO PIF Enable, it is the enable signal for the IO PIF circuit. Asserted during sequence up and de-asserted during sequence down. If an OVP fault is detected (any monitored output voltage is greater than the power good upper limit), the IO PIF Enable is de-asserted first at power down. If no OVP fault occurs, the IO PIF Enable is de-asserted last at power down. If this pin is configured as OVP Trip, it is asserted when an OVP fault is detected (any monitored output voltage is greater than the power good upper limit). Enable signal for the hardware margin signals. When asserted the margin high/low inputs will cause the analog PoLs to be margined to their configured high/low margin values. See Manufacturing mode above. See Manufacturing mode above. Master Clear (Reset) input. This pin is an active-low Reset to the device. Clock input pin for in-circuit programming. Data I/O pin for in-circuit programming. Asserted after the configured power good delay after all of the outputs have been sequenced up and are operating within their configured power good limits. De-asserted prior to sequencing down due to a fault or commanded to do so. When asserted, causes Reset outputs to assert. Asserted when Reset In is asserted. De-asserted when any outputs in configured reset masks are outside of power good limits. Reset outputs can also be controlled by PMBus commands. Serial communications clock signal from master to slave. Serial communications data signal between master and slave (connect master SDI to slave SDO). Serial communications data signal between master and slave (connect master SDO to slave SDI). Output signal from master to enable the slave. When asserted, the slave will then sequence up the rails it controls. When de-asserted, the slave will sequence down the rails it controls. Input signal from the slave to the master to indicate the power good state of the rails that the slave monitors. System input voltage monitor (must be scaled using attenuating resistors if voltage exceeds reference voltage). Digital inputs for controlling set point associated with VNN PoL. When asserted, the configured VR Hot action occurs. This output is asserted when any of the monitored output voltages are less than their configured warning lower limit or greater than their configured warning upper limit. Positive supply (filtered VDD) for analog modules. See Powering the Sequencer below. Analog ground reference. See Powering the Sequencer below. Core decoupling capacitor. See Powering the Sequencer below. Bel Power 2400 Computer Drive Westborough, MA 01581 belpower.com Rev. B

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TRKM-10DC12R

Power System Controllers

Master Controller

Master and Slave Configuration

Signal VDD

Type Power

VSS

Power

VREF-

External Reference External Reference

VREF+

Definition Positive supply (3.3V) for peripheral logic and I/O pins. See Powering the Sequencer below. Ground reference for logic and I/O pins. See Powering the Sequencer below. Analog voltage reference (low) input. Analog voltage reference (high) input.

Powering the Sequencer VDD Core C8 2.2 uF 10v X5R

D1 BAT54

+12Vin

In R1 20 Ohm 1206

+12Vin Return

C1 1000uF 25V

C2 1uF 16v X5R

Microchip P/N MCP1702T-3302I/MB or Equivalent

VDD

Out

3V3 Output LDO

C4 1uF 16v X5R

GND R2 4.64 Ohm

C5 1uF 16v X5R

C6 1uF 16v X5R

C7 1uF 16v X5R

VSS

AVDD C3 2.2 uF 10v X5R AVSS R3 1 Ohm

Figure 2

VDD Interface

Figure 2 is a schematic of the typical VDD interface to the sequencer ICs. A Microchip LDO, P/N MCP1702T3302I/MB, is used to produce the 3.3V VDD supply to the DSP. This device is in a SOT89 package and in most applications will be sufficient in size to handle the power dissipation when powering the circuit from a 12V source. Capacitors C4, C5, C6, and C7 are the decoupling capacitors and they should be located directly across each pair of VDD and VSS pins on the IC. The device has a VDD core pin which is used to decouple the internally generated core voltage. Capacitor C8 is the decoupling capacitor for the VDD core. This decoupling capacitor should be a low ESR ceramic capacitor and can be as large as 10uF. Capacitor C3 is the decoupling capacitor for the analog VDD (AVDD) and it should be located directly across the AVDD and AVSS pins on the IC. Resistor R2 in combination with C3 provides a filter for the analog VDD. Resistor R3 is intended to separate AVSS from VSS. Capacitor C2 is the input decoupling capacitor for the LDO and it should be connected directly across the LDO’s input and ground pins. Capacitor C1 is used as a hold up capacitor. Its purpose is to hold up the supply voltage to the LDO and maintain a Bel Power 2400 Computer Drive Westborough, MA 01581 belpower.com Rev. B

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TRKM-10DC12R Master Controller

Power System Controllers Master and Slave Configuration

stable VDD for a short period after the +12Vin source is removed. The Schottky diode D1 prevents C1 from being discharged after +12Vin is removed. Resistor R1 is used to protect D1 during the inrush event associated with the application of the +12Vin. The single pulse peak current rating for a typical BAT54 diode is approximately 600mA. If the rise time of the +12V source is slow enough to limit the peak charging current into C1 it is possible to eliminate R1. Assuming a 40mA current draw C1 will provide approximately 188 us of hold up time per uF of capacitance.

Monitoring via ADC Channels The imbedded ADC channels are converted as 12-bit results with full scale equal to a chosen reference. The device is intended to be powered from a 3V3 source and can be configured to use this source as the ADC reference or to use an externally provided reference. Closed loop margining and set point adjustments always use the entire 12-bit result to trim the output voltages to specified values. Monitored voltages are reported via I2C communication using PMBus data formats as defined in the separate communication manual. The voltage range reported is determined by the entered set points. Any monitored output that is greater than the ADC reference or that can be margined above this reference should have a voltage divider to limit the maximum input to the corresponding ADC channel to a value equal or less than the ADC reference. Monitored voltages below the chosen ADC reference do not require this voltage divider. A four sample moving average is used to filter the ADC results. In most cases this will eliminate the need for external filtering. The input voltage (Vin) monitoring channel requires a voltage divider so that Vin maximum is scaled to a value less than the maximum value of the ADC reference.

Connecting the Control and Monitor Signals The three primary control interface signals to the attached PoL converters are an enable signal, a voltage monitoring signal, and trim control signal. The Monitoring signals are labeled and the trim signals are labeled . The APoL converters are enabled with an Enable Output signal, which may be shared with other converters.

Communication with the Device Serial communication is achieved via an I2C bus. The communication protocol is derived from the PMBus command set and is defined in a separate communications manual. The communications manual (TRKM-10DC12R Protocol) also define the protocol for device programming via embedded boot loader software. The parameters and voltage readings for each PoL converter or analog input can be accessed using PMBus page mode as described in the communications manual.

Bel Power 2400 Computer Drive Westborough, MA 01581 belpower.com Rev. B

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TRKM-10DC12R

Power System Controllers

Master Controller

Master and Slave Configuration

Absolute Maximum Ratings Parameter Ambient temperature under bias Storage temperature Voltage on VDD with respect to VSS Voltage on any pin that is not 5V tolerant, with respect to VSS Voltage on any 5V tolerant pin with respect to VSS when VDD ≥ 3.0V Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V Maximum current out of VSS pin Maximum current into VDD pin Maximum current sourced/sunk by any I/O pin Maximum current sunk by all ports Maximum current sourced by all ports

Limits -40°C to +85°C -65°C to +150°C -0.3V to +4.0V -0.3V to (VDD + 0.3V) -0.3V to +5.5V -0.3V to 3.6V 300 mA 250 mA 4 mA 200 mA 200 mA

Electrical Specifications Parameter Input Voltage Range Input Current (100-pin master) Logic Low Input Level

Symbol VDD

VIL

VSS

Logic High Input Level

VIH

0.7*VDD

Logic Low Output Level Logic High Output Level VDD Rise Rate Capacitance I/O Pin to GND I2C Bus Capacitance PWM Series Resistor Margin PWM Frequency Reference Input Program Flash Memory Cell Endurance

Min 3.0

IDD

VOL VOH SVDD CIO CB RPWM FPWM VREFH EP

Typ 3.30

Max 3.6

Units VDC

44

66

mA

0.2*VDD VDD 5.3 0.4

VDC VDC

2.4 1 50 400 1 15 AVSS + 2.5 10,000

AVDD

VDC VDC V/ms pF pF kΩ kHz

Notes Typical is at 3.3V, 25C, 40 MIPS Max is at 3.3V, 85C, 40 MIPS Non 5V tolerant pins 5V tolerant pins VDD = 3.3V, IOL ≤ 3.0mA VDD = 3.3V, IOH ≥ -3.0mA 0 to 3.0V in 3ms SCL and SDA External Series Resistor

VDC E/W cycles

Bel Power 2400 Computer Drive Westborough, MA 01581 belpower.com Rev. B

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TRKM-10DC12R

Power System Controllers

Master Controller

Master and Slave Configuration

Mechanical Outline

Bel 100-pin 12x12x1mm TQFP Sequencer 100-Lead Plastic Thin-Quad Flatpack, 12x12x1mm Body Units Millimeters Dimension Units Min Nom Number of Leads N 100 Lead Pitch e 0.40 BSC Leads per side n1 25 Overall Height A Molded Package Thickness A2 0.95 1.00 Standoff A1 0.05 Foot Length L 0.45 0.60 Footprint L1 1.00 REF Foot Angle 0˚ 3.5˚ f Overall Width E 14.00 BSC Overall Length D 14.00 BSC Molded Package Width E1 12.00 BSC Molded Package Length D1 12.00 BSC Lead Thickness c 0.09 Lead Width b 0.13 0.18 Mold Draft Angle Top 11˚ 12˚ a Mold Draft Angle Bottom 11˚ 12˚ b

Max

1.20 1.05 0.15 0.75 7˚

0.20 0.23 13˚ 13˚

Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Champers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only.

Bel Power 2400 Computer Drive Westborough, MA 01581 belpower.com Rev. B

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TRKM-10DC12R Master Controller

Power System Controllers Master and Slave Configuration

Revision History Date

Revision

Change Detail

2015-3-13

A

First preliminary draft.

2015-04-23

B

Updated I/O definitions on pins 33, 34, 35, 41, 56, 57, 73, 74, 78, 81, 82, and 83.

Errata Refer to TRKM-10DC12R Errata document for additional information specific to each code release.

RoHS Compliance Complies with the European Directive 2002/95/EC, calling for the elimination of lead and other hazardous substances from electronic products.

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