Trka 10da14r Datasheet d

Power System Sequencer TRKA-10DA14R February 10, 2014

Bel Power Inc., a subsidiary of Bel Fuse Inc.

On Board Power System Controller

RoHS Compliant

Rev. D

Features •

Digital Signal Processor (DSP) Based with Bel Firmware

•

Provides Power Up and Power Down Sequencing Logic

•

Stand Alone or Command Based Feature Set

•

Fault Detection and Reporting

•

100-Pin 12mm x 12mm TQFP package

•

I2C, SMBus, or PMBus compatible serial interface options

•

Configurable through serial interface, Customizable through software

•

3V3 logic levels

•

Voltage Margining via Closed Loop Trim

•

Analog Input Monitoring

•

Comparator function

•

Programmed parameters saved in non-volatile memory

•

Intelligent configuration capability

•

Power-down data log for identifying fault conditions

•

Boot loader for in-system upgrading

Applications •

Data Storage Servers

•

Networking

•

Telecommunications

Description This on board power system controller provides a cost effective high performance solution for controlling, monitoring, and sequencing multiple Point of Load (PoL) converters on a system board. The sequencer uses a digital signal processor (DSP) engine and Bel’s firmware to implement a portfolio of board level control features typically required in a multiple voltage configuration. This device can perform active trim control and monitor up to 10 PoL converters and enable and monitor up to 18 digital PoL or VRM converters (some of the enable signals are shared), and monitor two additional analog inputs. Figure 1 provides a block diagram of the device.

Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com

1

Power System Sequencer TRKA-10DA14R

Bel Power Inc., a subsidiary of Bel Fuse Inc.

February 10, 2014 Digital I/Os Margin Up/Down, Reset In, Power Good Out, Warning Out, Reset Out, etc.

External Reference Vin Monitor

Analog Voltage Monitoring

DPoL, VRM, or Other voltages to monitor APoL Vout Monitors

Digital I/O Control

Main Engine

Active Trim Control

PWM Output

I2C

APoL Converters 1 of 10

I2C Engine

Clock

Trim

Vout

Data Enable

Sequence Up/Down Control

DPoL or VRM Enables

Power System Controller

Figure 1 Functional Block Diagram I/O Assignment Summary I/O Type Analog Input

Quantity 32

Digital Input

12

Digital Output

25

PWM Trim

10

External Reference I2C Communication Power Programming

2 2 14 3

Signals Vin, APoLs (10), DPoLs (38), Analog x Monitor, Analog y Monitor, Analog ID Mfg Mode, Board ID (3), Enable, Margin (2), Thermal (2), Resets (2), Alternate Voltage Set-point Control APoL Enables (8), DPoL Enable (11), IO PIF Enable / OVP Trip, Alert/Warning, Power Good, Reset or Comparator Out (3) 8 Hardware PWM outputs for APoLs 1-8 2 PWM outputs implemented using timer interrupts for APoLs 9 and 10. VREF-, VREF+ I2C Data, I2C Clock VDD, VSS, AVDD, AVSS, VCAP/VDDCORE MCLR*, PGD, PGC

Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com

2

Power System Sequencer TRKA-10DA14R February 10, 2014

Bel Power Inc., a subsidiary of Bel Fuse Inc.

I/O Definitions Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

Pin Name RG15 VDD AN29 AN30 AN31 AN16 AN17 AN18 AN19 RG6 RG7 RG8 MCLR* RG9 VSS VDD RA0 AN20 AN21 AN5 AN4 AN3 AN2 AN1 AN0 AN6 AN7 VREFVREF+ AVDD AVSS AN8 AN9 AN10 AN11 VSS VDD RA1 RF13 RF12 AN12 AN13 AN14 AN15 VSS VDD RD14 RD15 RF4 RF5 RF3 RF2 RF8

Signal Description DPoL 14 Enable 3V3 VDD Analog x Monitor Analog y Monitor Analog ID DPoL 6 Monitor DPoL 7 Monitor DPoL 8 Monitor DPoL 9 Monitor Board ID 0 Board ID 1 Board ID 2 CMD Reset/Vpp Alert/Warning Logic Ground 3V3 VDD Enable/Board Seated DPoL 10 Monitor DPoL 11 Monitor APoL 5 Monitor APoL 4 Monitor APoL 3 Monitor APoL 2 Monitor APoL 1 Monitor Vin Monitor APoL 6 Monitor APoL 7 Monitor Analog Ground 3V00 External Reference Filtered VDD Analog Ground APoL 8 Monitor APoL 9 Monitor APoL 10 Monitor DPoL 1 Monitor Logic Ground 3V3 VDD APoL 1 Enable Margin Low Margin High DPoL 2 Monitor DPoL 3 Monitor DPoL 4 Monitor DPoL 5 Monitor Logic Ground 3V3 VDD Thermal Trip Power Good Alternate Voltage Set-point Control Manufacturing Mode (Margin Enable) DPoL 18 Enable DPoL 17 Enable PCH Reset

I/O Type or Function Digital Output Power Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Digital Input Digital Input Digital Input Programming Digital Output Power Power Digital Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input External Reference External Reference Power Power Analog Input Analog Input Analog Input Analog Input Power Power Digital Output Digital Input Digital Input Analog Input Analog Input Analog Input Analog Input Power Power Digital Input Digital Output Digital Input Digital Input Digital Output Digital Output Digital Input

5V Tolerant Y

Y Y Y Y Y Y

Y Y Y

Y Y Y Y Y Y Y

Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com

3

Power System Sequencer TRKA-10DA14R February 10, 2014 Pin 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

Pin Name RF7 RF6 SDA1 SCL1 RA2 RA3 RA4 RA5 VDD RC12 RC15 VSS RA14 RA15 RD8 RD9 RD10 RD11 OC1 PGD2 PGC2 VSS OC2 OC3 OC4 RD12 RD13 OC5 OC6 OC7 OC8 VCAP/VDDCORE VDD RF0 RF1 RG1 RG0 AN22 AN23 AN24 AN25 RG14 RG12 RG13 AN26 AN27 AN28

Bel Power Inc., a subsidiary of Bel Fuse Inc. Signal Description APoL 10 Trim APoL 9 Trim I2C Data I2C Clock APoL 2 Enable APoL 3 Enable APoL 4 Enable APoL 5/6 Enable 3V3 VDD Reset B / Analog Y Comparator Out Reset C Out Logic Ground Reset In Reset A Out APoL 10 Enable DPoL 1-4 Enable DPoL 5/9 Enable DPoL 6/10 Enable APoL 1 Trim Program Data Program Clock Logic Ground APoL 2 Trim APoL 3 Trim APoL 4 Trim DPoL 7/11 Enable IO PIF Enable / OVP Trip APoL 5 Trim APoL 6 Trim APoL 7 Trim APoL 8 Trim Core Decoupling Capacitor 3V3 VDD DPoL 15 Enable DPoL 16 Enable APoL 7/8 Enable APoL 9 Enable DPoL 12 Monitor DPoL 13 Monitor DPoL 14 Monitor DPoL 15 Monitor DPoL 13 Enable VR Hot DPoL 8/12 Enable DPoL 16 Monitor DPoL 17 Monitor DPoL 18 Monitor

I/O Type or Function Digital Output Digital Output I2C Communication I2C Communication Digital Output Digital Output Digital Output Digital Output Power Digital Output Digital Output Power Digital Input Digital Output Digital Output Digital Output Digital Output Digital Output PWM Trim Programming Programming Power PWM Trim PWM Trim PWM Trim Digital Output Digital Output PWM Trim PWM Trim PWM Trim PWM Trim Power Power Digital Output Digital Output Digital Output Digital Output Analog Input Analog Input Analog Input Analog Input Digital Output Digital Input Digital Output Analog Input Analog Input Analog Input

5V Tolerant Y Y Y Y Y Y Y Y

Y Y Y Y Y Y Y

Y Y Y Y Y Y Y Y Y Y Y Y Y

Y Y Y

The voltage on 5V tolerant digital input pins can exceed VDD as indicated in the Absolute Maximum Ratings section. 5V tolerant digital output pins can be configured with the open-drain feature which allows the generation of outputs higher than VDD by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification defined in the Electrical Specifications.

Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com

4

Power System Sequencer TRKA-10DA14R

Bel Power Inc., a subsidiary of Bel Fuse Inc.

February 10, 2014

Signal Definitions Signal VDD

Type Power

VSS

Power

AVDD

Power

AVSS

Power

VCAP/VDDCORE

Power

MCLR*

Programming

PGD PGC I2C Clock

Programming Programming I2C

I2C Data

I2C

VREF+ VREFAlternate Voltage Set-point Control

External Reference External Reference Digital Input

Board ID (0-2)

Digital Input

Enable/Board Seated

Digital Input

Manufacturing Mode

Digital Input

Margin High Margin Low Reset In Thermal Trip VR Hot IO PIF Enable / OVP Trip

Digital Input Digital Input Digital Input Digital Input Digital Input Digital Output

Definition Positive supply (3.3V) for peripheral logic and I/O pins. See Powering the Sequencer below. Ground reference for logic and I/O pins. See Powering the Sequencer below. Positive supply (filtered VDD) for analog modules. See Powering the Sequencer below. Analog ground reference. See Powering the Sequencer below. Core decoupling capacitor. See Powering the Sequencer below. Master Clear (Reset) input. This pin is an active-low Reset to the device. Data I/O pin for programming communication. Clock input pin for programming communication. Synchronous serial clock input/output for I2C communication. Since this is a slave device, the master drives the clock. Clock stretching may occur if necessary according to the I2C specification. Synchronous serial bi-directional data line for I2C communication. Analog voltage reference (high) input. Analog voltage reference (low) input. When asserted the alternate voltage limits will be used for converters configured for dual set-points. Any analog POL converters configured for dual set-points will be trimmed to the alternate set-point. When de-asserted the normal voltage set-points and limits will be used. These three digital inputs along with the Analog Board ID define a board identification number for controlling which board specific configuration data is loaded. When asserted the board is sequenced up if the input voltage is valid. When de-asserted the board is sequenced down. This function can be overridden as defined in the separate interface document. Enable signal for the hardware margin signals. When asserted the margin high/low inputs will cause the analog PoLs to be margined to their configured high/low margin values. See Manufacturing mode above. See Manufacturing mode above. When asserted, causes Reset A-C to assert. When asserted, the configured thermal trip action occurs. When asserted, the configured VR Hot action occurs. If this pin is configured as the IO PIF Enable, it is the enable signal for the IO PIF circuit. Asserted during sequence up and de-asserted during sequence down. If an OVP fault is detected (any monitored output voltage is greater than the power good upper limit), the IO PIF Enable is de-asserted first at power down. If no OVP fault occurs, the IO PIF Enable is de-asserted last at power down.

Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com

5

Power System Sequencer TRKA-10DA14R

Bel Power Inc., a subsidiary of Bel Fuse Inc.

February 10, 2014 Signal

Type

APoL Enables (8)

Digital Output

Alert/Warning

Digital Output

DPoL Enable (11)

Digital Output

Power Good

Digital Output

Reset Out (A-C)

Digital Output

Analog Y Comparator Output

Digital Output

APoL Trim (1-10)

PWM Output

Definition If this pin is configured as OVP Trip, it is asserted when an OVP fault is detected (any monitored output voltage is greater than the power good upper limit). Enable signal for the 10 analog PoL converters. Note that some of the enables are shared. Asserted during sequence up and de-asserted during sequence down. If this pin is configured for the Alert function, then this output is asserted when an I2C error occurs. If this pin is configured for the Warning function, then this output is asserted when any of the monitored output voltages are less than their configured warning lower limit or greater than their configured warning upper limit. Enable signal for the 18 digital PoL or VRM converters. Note that some of the enables are shared. Asserted during sequence up and de-asserted during sequence down. If the corresponding analog input is configured as a comparator then this enable signal is used as the comparator output instead of enabling/disabling the converter during sequence up/down. Asserted after the configured power good delay after all of the outputs have been sequenced up and are operating within their configured power good limits. De-asserted prior to sequencing down due to a fault or commanded to do so. Asserted when Reset In is asserted. De-asserted when any outputs in configured reset masks are outside of power good limits. Reset outputs can also be controlled by PMBus commands. If pin 63 (RC12) is configured for Analog Y Comparator then this signal is the output of the Analog Y Comparator function. PWM outputs for actively trimming the analog PoLs to their desired set points. See Using the PWM Trim Outputs below. The trim PWMs for APoLs 1-8 are hardware based. The PWM output duty cycle will remain fixed even when the controller is performing long operations (such as flash memory erases and writes).

APoL Monitor (1-10)

Analog Input

Analog Board ID Analog X Monitor

Analog Input Analog Input

Analog Y Monitor

Analog Input

The PWM outputs for APoLs 9 and 10 are implemented using timers. The PWM output is suspended during long operations (such as flash memory erases and writes). During these intervals the output is tri-stated, so the trim circuit should have a pull-up to set the trim voltage to as close to the desired voltage as possible to reduce glitches on the PoL output. Analog PoL output voltage monitor (must be scaled using attenuating resistors if voltage exceeds reference voltage). See Board ID above. Analog X monitor (must be scaled using attenuating resistors if voltage exceeds reference voltage). Analog Y monitor (must be scaled using attenuating

Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com

6

Power System Sequencer TRKA-10DA14R

Bel Power Inc., a subsidiary of Bel Fuse Inc.

February 10, 2014 Signal

Type

DPoL Monitor (1-18)

Analog Input

Vin Monitor

Analog Input

Definition resistors if voltage exceeds reference voltage). Digital PoL, VRM, or other voltage monitor (must be scaled using attenuating resistors if voltage exceeds reference voltage). System input voltage monitor (must be scaled using attenuating resistors if voltage exceeds reference voltage).

Powering the Sequencer VDD Core C8 2.2 uF 10v X5R

D1 BAT54

+12Vin R1 20 Ohm 1206

+12Vin Return

In C1 1000uF 25V

C2 1uF 16v X5R

Microchip P/N MCP1702T-3302I/MB or Equivalent

VDD

Out

3V3 Output LDO

C4 1uF 16v X5R

GND R2 4.64 Ohm

C5 1uF 16v X5R

C6 1uF 16v X5R

C7 1uF 16v X5R

VSS

AVDD C3 2.2 uF 10v X5R AVSS R3 1 Ohm

Figure 2 VDD Interface Figure 2 is a schematic of the typical VDD interface to the sequencer IC. A Microchip LDO, P/N MCP1702T3302I/MB, is used to produce the 3.3V VDD supply to the DSP. This device is in a SOT89 package and in most applications will be sufficient in size to handle the power dissipation when powering the circuit from a 12V source. Capacitors C4, C5, C6, and C7 are the decoupling capacitors for the DSP and they should be located directly across each pair of VDD and VSS pins on the DSP IC. The device has a VDD core pin which is used to decouple the internally generated core voltage. Capacitor C8 is the decoupling capacitor for the VDD core. This decoupling capacitor should be a low ESR ceramic capacitor and can be as large as 10uF. Capacitor C3 is the decoupling capacitor for the analog VDD (AVDD) and it should be located directly across the AVDD and AVSS pins on the DSP IC. Resistor R2 in combination with C3 provides a filter for the analog VDD. Resistor R3 is intended to separate AVSS from VSS. Capacitor C2 is the input decoupling capacitor for the LDO and it should be connected directly across the LDO’s input and ground pins. Capacitor C1 is used as a hold up capacitor. Its purpose is to hold up the supply voltage to the LDO and maintain a stable VDD for the DSP for a short period after the +12Vin source is removed. This would be desired if a short communication stream is required during power down or if storing system data to EE memory is required during power down. The Schottky diode D1 Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com

7

Power System Sequencer TRKA-10DA14R

Bel Power Inc., a subsidiary of Bel Fuse Inc.

February 10, 2014

prevents C1 from being discharged after +12Vin is removed. Resistor R1 is used to protect D1 during the inrush event associated with the application of the +12Vin. The single pulse peak current rating for a typical BAT54 diode is approximately 600mA. If the rise time of the +12V source is slow enough to limit the peak charging current into C1 it is possible to eliminate R1. Assuming a 40mA current draw by the DSP C1 will provide approximately 188 us of hold up time per uF of capacitance.

Using the PWM Trim Outputs +Sense

+Vin

Zf

Ry

Zi

TRIM Rx

-

Rz

+Vout

PWM

E/A

+ Reference

Figure 3A. +Sense

+Vin

Zf Zi

+Vout

PWM

E/A

+ TRIM Rx

Ry

Reference

Figure 3B. +Sense

+Vin

Zf Zi

PWM

E/A Reference

TRIM

+Vout

+

uController or Equivalent

Figure 3C. Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com

8

Power System Sequencer TRKA-10DA14R

Bel Power Inc., a subsidiary of Bel Fuse Inc.

February 10, 2014

The drawings in figure 3 show the three most common trim methods used in PoL converters. In all of these schemes a power conversion stage contains a PWM device that receives a control voltage from an error amplifier. The error amplifier (E/A) compares a scaled version of the output voltage to a reference. The output voltage of the converter module is simply the reciprocal of the scaling factor multiplied by the reference value. The output voltage can be adjusted by changing this scaling factor (Figure 3A) or by modifying the reference (Figures 3B, C). The most common trim method is shown in figure 3A. The popularity of this method stems from the fact that most highly integrated PWM control IC’s have an internal reference that is not accessible and cannot be controlled externally. In this scheme the output is scaled by adding a resistor from the trim pin to ground. This modifies the feedback divider and moves the output voltage to a higher value. The output can also be modified by superimposing an offset voltage on the feedback divider by connecting a voltage source to the trim pin through a resistor. Either of these two approaches will move the output voltage to a new value. The common characteristic of modules with this trim scheme is that a lower value trim resistor to ground will cause a higher output voltage or a larger voltage superimposed on the trim pin will cause Vout to decrease. Some PoL converters incorporate the trim scheme shown in figure 3B. With this method the feedback ratio is kept constant and the reference value is modified to move the output voltage. The common characteristic of modules with this trim scheme is that a lower value trim resistor to ground will cause a lower output voltage and a larger voltage superimposed on the trim pin will cause Vout to increase. The method shown in figure 3C is occasionally used. This is similar to the method in figure 3B except the modification of the reference is mapped through a device such as a microcontroller. This is the least common of the 3 methods and requires the vendor’s data sheet to determine the trim characteristic because the micro controller can map the reference in many different ways. PoL Vout or VDD

VTrim Ripple VTrim Average Margin PWM

PoL Trim Pin

Ra 3V3

Ca

Rb Ca

0

Margin PWM

PoL Trim Pin

Ra

Rb

3V3 VTrim Average

0

VTrim Ripple

Figure 4B

Figure 4A

The power sequencer has the ability to do independent closed loop trim and closed loop margining of the output voltage for each PoL controlled by the device. Each PoL’s output voltage is monitored and by an analog to digital converter (ADC) in a continuous loop. In firmware the most recent measured output voltage is compared against the desired value and the PoL’s output is adjusted by delivering a trim value to the corresponding PoL’s trim pin. This trim voltage is created from a digital PWM output and an external low pass filter. Each digital PWM is labeled where n indicates a specific converter which corresponds to the monitoring channel labeled with the same “n” value. The external low pass filter creates a DC value from the PWM signal which is then delivered to each PoL converter through a range limiting resistor. Figure 4 shows the typical circuits used to interface the sequencers Margin PWM signals to PoL converters. In each of the circuits shown Ra and Ca construct a low pass filter while Rb is used to limit the trim range. The effective trim voltage is equal to the Margin PWM duty cycle multiplied by VDD and is controllable in 1024 steps from 0 to VDD. The effective trim resistor value is equal to Ra + Rb. Ra and Ca are chosen to reduce the trim voltage ripple. Typical values for Ra and Ca are 1K for Ra and 0.22uF to 1uF for Ca. Rb is used to limit the control range and should be selected based on the desired control range and the trim equation for the PoL. Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com

9

Power System Sequencer TRKA-10DA14R February 10, 2014

Bel Power Inc., a subsidiary of Bel Fuse Inc.

This trim equation is usually available from the PoL manufactures data sheet. The sequencer learns the trim direction by making a minor adjustment to the Margin PWM and then determining the direction that Vout moves based on this stimulus. Once the trim direction is known it knows whether increment or decrement the TRIM PWM value until the desired Vout is achieved. The accuracy of the active trim is a function of the ADC accuracy which is mostly controlled by accuracy of the applied reference to the sequencers Vref pins. Either circuit in Figure 4 will work with any of the trim methods shown in Figure 3. When interfacing to PoL modules that use the trim method in Figure 3A the circuit in Figure 4B is the optimum interface configuration. By connecting the filter capacitor Ca to the PoL’s Vout or to a positive voltage reference the effective of filtering the Margin PWM signal remains intact. With this method there will not be a discharged capacitor connected to ground that could cause the PoL’s output to overshoot during power up as this capacitor becomes charged. In the case that the circuit in figure 4A is used with the trim configuration in Figure 3B the sequencer will precharge the capacitor before enabling the PoL converter and then decrement the Margin PWM to achieve the desired Vout. This requires additional start up time during system initialization. When interfacing to PoL converters of the type shown in Figure 3B the interface circuit in figure 4A is optimum.

Monitoring Via ADC Channels The imbedded ADC channels are converted as 10 or 12 bit results with full scale equal to a chosen reference. The device is intended to be powered from a 3V3 source and can be configured to use this source as the ADC reference or to use an externally provided reference. Closed loop margining and set point adjustments always use the entire 10 or 12 bit result to trim the output voltages to specified values. Monitored voltages are reported via I2C communication using PMBus data formats as defined in the separate communication manual. The voltage range reported is determined by the entered set points. Any monitored output that is greater than the ADC reference or that can be margined above this reference should have a voltage divider to limit the maximum input to the corresponding ADC channel to a value equal or less than the ADC reference. Monitored voltages below the chosen ADC reference do not require this voltage divider. A four sample moving average is used to filter the ADC results. In most cases this will eliminate the need for external filtering. The input voltage (Vin) monitoring channel requires a voltage divider so that Vin maximum is scaled to a value less than the maximum value of the ADC reference.

Connecting the Control and Monitor Signals The three primary control interface signals to the attached PoL converters are an enable signal, a voltage monitoring signal, and trim control signal. The enable signals are labeled . The Monitoring signals are labeled . The trim signals are labeled . Each APoL converter is required to share the corresponding enable, monitor, and trim signals. The installed firmware assumes that the connections are made this way when controlling system.

Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com

10

Power System Sequencer TRKA-10DA14R

Bel Power Inc., a subsidiary of Bel Fuse Inc.

February 10, 2014

Communication with the Device Serial communication is achieved via an I2C bus. The communication protocol is derived from the PMBus command set and is defined in a separate communications manual. The communications manual (TRKA10DA14R Protocol) also defines the protocol for device programming via embedded boot loader software. The parameters and voltage readings for each PoL converter or analog input can be accessed using PMBus page mode. Figure 5 shows the page assignments.

Page 0 Not Used

Hard Coded I2C Address

Page 1-10 APoL1-10 Set Point Control Scaling Margin Limits PGD/Warning Limits Voltage Reads

I2C Engine I2C Bus

& Page Switch

Page 11-28 DPoL1-18 Scaling PGD/Warning Limits Voltage Reads

Page 29-30 Analog x-y Scaling PGD/Warning Limits Voltage Reads

Figure 5 I2C Communication Page Assignment

Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com

11

Power System Sequencer TRKA-10DA14R

Bel Power Inc., a subsidiary of Bel Fuse Inc.

February 10, 2014

Absolute Maximum Ratings Ambient temperature under bias ........................................................................................................... -40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant with respect to VSS ...................................................... -0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD ≥ 3.0V..................................................... -0.3V to +5.6V Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V....................................................... -0.3V to 3.6V Voltage on VDDCORE with respect to VSS ................................................................................................ 2.25V to 2.75V Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ............................................................................................................................. 250 mA Maximum output current sunk by any I/O pin ...........................................................................................................4 mA Maximum output current sourced by any I/O pin ......................................................................................................4 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports ..................................................................................................................200 mA

Electrical Specifications Parameter Input Voltage Range

Symbol VDD

Min

Typ

Max

3.0

3.30

3.6

Units VDC

46

55

mA

0.2*VDD VDD 5.5 0.4

VDC

Input Current

IDD

Logic Low Input Level

VIL

VSS

Logic High Input Level

VIH

0.7*VDD

VOL VOH SVDD

2.4 0.03

Logic Low Output Level Logic High Output Level VDD Rise Rate Capacitance I/O Pin to GND I2C Bus Capacitance PWM Series Resistor Margin PWM Frequency Reference Input Program Flash Memory Cell Endurance

VDC VDC VDC V/mS

CIO

50

pF

CB RPWM FPWM Vref

400

AVSS + 1.7

EP

10,000

pF kΩ kHz VDC E/W cycles

1 10

AVDD

Notes Typical is at 3.3V, 25C, 20 MIPS. Max is at 3.3V, 85C, 20 MIPS Non 5V tolerant pins 5V tolerant pins VDD = 3.3V VDD = 3.3V, IOH = -3.0mA 0 to 3.0V in 100mS SCl and SDA External Series Resistor

Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com

12

Power System Sequencer TRKA-10DA14R February 10, 2014

Bel Power Inc., a subsidiary of Bel Fuse Inc.

Mechanical Outline

Bel 100-pin 12x12x1mm TQFP Sequencer Figure 6A 100-Lead Plastic Thin-Quad Flatpack, 12x12x1mm Body Units Millimeters Dimension Units Min Nom Number of Leads N 100 Lead Pitch e 0.40 BSC Leads per side n1 25 Overall Height A Molded Package Thickness A2 0.95 1.00 Standoff A1 0.05 Foot Length L 0.45 0.60 Footprint L1 1.00 REF Foot Angle 0˚ 3.5˚ φ Overall Width E 14.00 BSC Overall Length D 14.00 BSC Molded Package Width E1 12.00 BSC Molded Package Length D1 12.00 BSC Lead Thickness c 0.09 Lead Width b 0.13 0.18 Mold Draft Angle Top 11˚ 12˚ α Mold Draft Angle Bottom 11˚ 12˚ β

Max

1.20 1.05 0.15 0.75 7˚

0.20 0.23 13˚ 13˚

Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Champers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only.

Figure 6B Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com

13

Power System Sequencer TRKA- 10DA14R

Bel Power Inc., a subsidiary of Bel Fuse Inc.

February 10, 2014

Revision History Date

Revision

Changes Detail

Approval

2012-11-12

A

First preliminary draft.

S. Moore

2012-11-15

B

Added OVP Trip function.

S. Moore

2012-12-27

C

Added Analog Y Comparator output function.

S. Moore

2014-2-10

D

Added information about 5V tolerant pins.

S. Moore

Errata Refer to TRKA-10DA14R Errata document for additional information specific to each code release.

RoHS Compliance Complies with the European Directive 2002/95/EC, calling for the elimination of lead and other hazardous substances from electronic products.

©2014 Bel Fuse Inc. Specifications subject to change without notice.

14 CORPORATE

FAR EAST

EUROPE

Bel Fuse Inc. 206 Van Vorst Street Jersey City, NJ 07302 Tel 201-432-0463 Fax 201-432-9542 www.belfuse.com

Bel Fuse Ltd. 8F/ 8 Luk Hop Street San Po Kong Kowloon, Hong Kong Tel 852-2328-5515 Fax 852-2352-3706 www.belfuse.com

Bel Fuse Europe Ltd. Preston Technology Management Centre Marsh Lane, Suite G7, Preston Lancashire, PR1 8UD, U.K. Tel 44-1772-556601 Fax 44-1772-888366 www.belfuse.com