Tele controlled steper motor Thesis

CHAPTER 1 Introduction 1.1 Introduction to Microcontrollers

Every day human’s life is associated with an electrical/electronics mechanical work field, which plays a wide variety role in the world to make ease of work load to the human being. Although the man is responsible for the presence of all these fields, he could not trace the speed of these fields. This is the main hint for these fields to kick out the human beings and come into existence. However, as the man is the master for each of this universe, he gained command on all these fields to solve his problems. In this way, the Microcontrollers became necessary to help human being. Now a day’s all industrial applications involved with microprocessors or microcontrollers. These are very popular today. Typical microcontroller is a true computer on a chip.Like microprocessor, microcontroller is a general purpose device, but one that is meant to read data, performs limited calculations. The prime use of microcontroller is to control the operation of a machine using a fixed program that is stored in ROM and that does not change over the life time of system. For this project, the user needs to interface the microcontroller with the DTMF receiver.the DTMF is one, which will recognize the ring signal and gives out binary equivalent of the incoming signal. According to the program written into the microcontroller, it fallows the data coming out from the DTMF and enable or disable the buffers.

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1.2 Introduction to DTMF Receiver The DTMF is dual tone multi frequency used in telecommunications for dialing. There are 8 tones of low audio band, and 4 tones of high audio band. One from each band is added together to generate a dual tone. We can make 16 tones totally however 10 tones are sufficient for dialing digits 0…9. In this project, to receive the pass code and control codes sent by the user we have this dtmf transceiver circuit. After answering the call, if a tone is received this IC 8870 will detect it and give the code to the microcontroller.

1.3 Introduction to Assembly Language Programming An assembly language program consists of, among other things, a series of lines of assembly language instructions. An assembly language instruction consists of a mnemonic, optionally followed by one or two operands. The operands are the data items being manipulated, and the mnemonics are the commands to the CPU, telling it what to do with those items. An assembly language instruction consists of 4 fields: [Label:]

mnemonic

[operand]

[comment]

Brackets indicate that a field is optional and not all lines have them. Brackets should not be typed in: 1.The label field allows the program to refer to a line of code by name. The label field cannot exceed a certain number of characters. 2.The assembly language mnemonic and operand fields together perform the real work of the program and accomplish the tasks for which the program was written. ADD

A, B

MOV

A, #67

ADD and MOV are mnemonics which produce opcodes."A,B" and "A,#67"

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are the operand. 3. The comment field begins with a semicolon comment indicator ";" comments may be at the end of a line or on a line by themselves. The assembler ignores comments, but they are indispensable to programmers. Although comments are optional, it is recommended that they be used to describe the program in order to make it easier for someone else to read and understand.

Assembling and Running an 89C51 Program

Steps to create an executable assembly language program are as follows:1. First we use an editor to type in a program. Many excellent editors or word processors are available that can be used to create arid/or edit the program. Widely used editor is MS-DOS edit program. Editor must be able to produce an ASCII file. For many assemblers, the file names follow the usual DOS conventions but the source file has the extension "asm" or "src", depending on which assembler you are using. 2. The" asm" source file containing the program code created in step one is fed to an 89c51 assembler. The assembler converts the instructions into machine code. The assembler will produce an object file and list file. The extension for object file is "obj" while extension for list file is "1st". 3. Assemblers require a third step called linking. The link program takes one or more object files and produces an absolute file with extension "abs". This abs file is used by 89c51 trainers that have a monitor program.

1.4 Introduction to Project 3

When you forget to OPEN/CLOSE the doors, or to switch OFF our electrical home appliances, to switch ON alarm for industrial protection etc., To OPEN/CLOSE the doors and to ON/OFF all these equipment automatically we need the domestic automation. Every one of knowingly/unknowingly forgets to OPEN/CLOSE the doors and to switch ON/OFF the electrical devices when we leave the hose or an office. So what a person does is: One way to go back to his home and do the operation. If he has to travel a long distance it will be bit difficult to come back. The best way to operate the appliances with in seconds by a remote device such as telephone which is done by our project. As now-a-day telecommunication network is expanding to every where, all are using telecommunication network as a medium to transfer data, voice etc. Here, for this project telephone is the medium to transfer the data from any where. This is one of the best ways to control the appliances which is cost effective and can be afford by a common man.

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CHAPTER 2 AT89C51 Microcontroller The micro controller generic part number actually includes a whole family of micro controllers that have numbers ranging from 8031 to 8751 and are available in N-Channel Metal Oxide Silicon (NMOS) and Complementary Metal Oxide Silicon (CMOS) construction in a variety of package types.

2.1 Features 1Compatible with MCS 51 Products 24 Kbytes of In System Reprogrammable Flash Memory Endurance: 1,000 write/Erase Cycles 3Fully Static Operation: 0 Hz to 24 MHz 4Three Level Program Memory Lock 5Programmable Serial Channel 6Low Power Idle and Power Down Modes 7Eight-bit CPU with registers A (accumulator) and B 8Sixteen bit program counter (PC) and data pointer (DPTR) 9Eight bit program status word (PSW) 10Eight bit stack pointer (SP) 11Internal ROM or EPROM of 0 to 4K 12Internal RAM of 128 bytes 13Four register banks, each containing eight registers 14Sixteen bytes, which may be addressed at the bit level 15Eighty bytes of general-purpose data memory 16Thirty-two input/output pins arranged as four 8-bit ports:P0-P3 17Two 16-bit timer/counters: T0 and T1 18Full duplex serial data receiver/transmitter: SBUF 19Control registers: TCON, TMOD, SCON, PCON, IP and IE 20Two external and three internal interrupt sources

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21Oscillator and clock circuits

2.2 Description The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4Kbytes of Flash Programmable and Erasable Read Only Memory (PEROM). The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed insystem or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. The AT89C51 provides the following standard features: 4 Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, five vector two-level interrupt architecture, a full duplex serial port, and on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.

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2.3 pin Description

Fig.2.1 Pin diagram of 89C51

Fig.2.2 Block diagram of 89C51 Micro controller

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Port 0 Port 0 is an 8-bit open drain bi-directional I/O port. As an output port each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification. Port 1 Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 1 also receives the low-order address bytes during Flash programming and program verification. Port 2 Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits during Flash programming.

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Port 3 Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 also serves the functions of various special features. Table 2.1 Alternative Use of Port 3

RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.

ALE/PROG Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC 9

instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the micro controller is in external execution mode. PSEN Program Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP External access enables. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.

XTAL1 Input to the inverting oscillator amplifier and input to the internal lock operating circuit.

XTAL2 Output from the inverting oscillator amplifier.

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven. There are no requirements on the duty cycle of the external clock signal, since the

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input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.

Fig.2.3 Oscillator Connections

Note: c1, c2 = 30 pF =40pF

10 pF for crystals 10pF for ceramic Resonators

Fig.2.4 Internal Architecture of 89C51

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2.4 Idle Mode In Idle mode, the CPU puts itself to sleep while the entire on chip Peripherals remain active. The mode is invoked by software. The content of the on-chip AM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hard-ware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.

2.4.1 Power down Mode In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.

2.5 Program Memory Lock Bits On the chip are three lock bits which can e left un-programmed (U) or can be programmed (P) to obtain the additional features listed in the Table 2.2 below. When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the

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latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.

2.6 Program Counter and Data Pointer The 89C51 contains two 16-bit registers the programs counter (PC) and the data pointer (DPTR), Each is used to hold the address of a byte in memory. The PC is the only register that does not have an internal address. The DPTR is under the control of program instructions and can be specified by its 16-bit name, DPTR, or by each individual byte name, DPH and DPL. DPTR does not have a single internal address; DPH and DPL are each assigned an address.

2.7 A and B Registers The 89C51 contains 34 general purpose, working, registers. Two of these, registers A and B, hold results of many instructions, particularly math and logical operations, of the 89C51 CPU. The other 32 are arranged as part of internal RAM in four banks, B0-B3, of eight registers. The A register is also used for all data transfers between the 89c51 and any external memory. The B register is used for with the A register for multiplication and division operations.

2.8 Flags and the Program Status Word (PSW) Flags may be conveniently addressed, they are grouped inside the program status word (PSW) and the power control (PCON) registers. The 89C51 has four math flags that respond automatically to the outcomes of math operations and three generalpurpose user flags that can be set to 1 or cleared to 0 by the programmer as desired. The math flags include Carry (C), Auxiliary Carry (AC), Overflow (OV), and Parity (P). User flags are named F0, F0 and GF1; they are general-purpose flags that may be used by the programmer to record some event in the program.

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Table 2.2 Functions of PSW

2.9 Internal Memory The 89C51 has internal RAM and ROM memory for the functions. Additional memory can be added externally using suitable circuits. This has a Hardware architecture, which uses the same address, in different memories, for code and data.

2.9.1 Internal RAM The 128-byte internal RAM is organized into three distinct areas  Thirty two bytes from address 00H to 1FH that make up 32 working registers organized four banks of eight registers each. The four register banks are numbered 0 to 3 and are made up of eight registers named R0 to R7. Each register can be addressed by name or by its RAM address. Thus R0 of bank 3 is R0 (if bank 3 is currently selected) or address 18H (whether bank 3 is selected or not). Bits RS0 and RS1 in the PSW determine which bank of registers is currently in use at any time when the

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program is running. Register banks not selected can be used as a generalpurpose RAM. Bank0 is selected on reset.  A bit addressable area of 16 bytes occupies RAM byte addresses 20H to 2FH, forming a total of 128 addressable bits. An addressable bit may be specified by its bit address of 00H to 7FH, or 8 bits may form any byte address form 20H to 2FH.  A general-purpose RAM area above the bit area, from 30H to 7FH, addressable as bytes.

Internal RAM Organization

Fig.2.5 Internal RAM Organization 15

2.9.2 Internal ROM The 89C51 is organized so that data memory and program code memory can be in two entirely different physical memory entities. Each has the same address ranges. Program addresses higher than 0FFFH, which exceeds the internal ROM capacity, will cause the 89C51 to automatically fetch code bytes from external program memory. Code bytes can also be fetched exclusively from an external memory by connecting the external access pin to ground.

2.10 Special Function Register (SFR) Memory Special Function Registers (SFRs) are areas of memory that control specific functionality of the 89C51 processor. For example, four SFRs permit access to the 89C51’s 32 input/output lines. Another SFR allows a program to read or write to the 89C51’s serial port. Other SFRs allow the user to set the serial baud rate, control and access timers, and configure the 89C51’s interrupt system.

2.10.1 Special function registers SFRs are accessed as if they were normal Internal RAM. The only difference is that Internal RAM is from address 00H through 7FH whereas SFR registers exist in the address range of 80H through FFH. Each SFR has an address (80H through FFH) and a name. Although the address range 80h through FFH offers 128 possible addresses, there are only 21 SFRs in a standard 89C51. All other addresses in the SFR range (80h through FFH) are considered invalid. Writing to or reading from these registers may produce undefined values or behaviour. The following table lists the symbols, names and addresses of the 89C51 SFR.

SFR Description There are four I/O ports of 8 bits each for a total of 32 I/O lines. The four ports are called P0, P1, P2 and P3.

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SP (stack pointer) This is the stack pointer of the micro controller. This SFR indicates where the next value to be taken from the stack will be read from in Internal RAM. Pushing a value onto the stack, the value will be written to the address of SP + 1. That is to say, if SP holds the value 07h, a PUSH instruction will push the value onto the stack at address 08h. This SFR is modified by all instructions that modify the stack, such as PUSH, POP, and LCALL, RET, RETI, and whenever interrupts are provoked by the micro controller. The SP SFR, on start up, is initialized to 07h. This means the stack will start at 08h and start expanding upward in internal RAM. Since alternate register bans 1, 2, and 3 as well as the user bit variables occupy internal RAM from addresses 08h through 2Fh, it is necessary to initialize SP in program to some other value such as 2F, using the alternate register banks and/or bit memory.

DPL / DHL (Data pointer low / high) The SFRs DPL and DPH work together to represent a 16-bit value called the Data Pointer. The data pointer is used in operations regarding external RAM and some instructions involving code memory. Since it is an unsigned two-byte integer value, it can represent values from 0000H to FFFFH (0 through 65,535 decimal). DPTR is really DPH and DPL taken together as a 16-bit value. For example, to push DPTR onto the stack first push DPL and then DPH. Additionally, there is an instruction to “increment DPTR.” On executing this instruction, the two bytes are operated upon as a 16-bit value. However, there is no instruction to decrement DPTR.

PCON (Power control) The Power Control SFR is used to control the 89C51’s power control modes. Certain operation modes of the 89C51 allow the 89C51 to go into a type of “sleep” mode that requires much less power. These modes of operation are controlled through PCON. Additionally, one of the bits in PCON is used to double the effective baud rate of the 89C51’s serial port.

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TCON (Timer control) The Timer Control SFR is used to configure and modify the way in which the 89C51’s two timers operate. This SFR controls whether each of the two timers is running or stopped and contains a flag to indicate that each timer has overflowed. Additionally, some non-timer related bits are located in the TCON SFR. These bits are used to configure the way in which the external interrupts are activated.

TMOD (Timer mode) The Timer Mode SFR is used to configure the mode of operation of each of the two timers. Using this SFR the program may configure each timer to be a 16-bit timer, an 8-bit auto reload timer, a 13-bit timer, or two separate timers. Additionally, the program may configure the timers to only count when an external pin is activated or to count “events” that are indicated on an external pin.

TL0 / TH0 (Timer 0 low / high) These two SFRs, taken together, represent timer 0. Their exact behavior depends on how the timer is configured in the TMOD SFR; however, these timers always count up. Increment in value is configurable.

TL1 / TH1 (Timer 1 low / high) These two SFRs, taken together, represent timer 1. Their exact behavior depends on how the timer is configured in the TMOD SFR; however, these timers always count up. Increment in value is configurable.

SCON (Serial control) The Serial Control SFR is used to configure the behavior of the 89C51’s onboard serial port. This SFR controls the baud rate of the serial port, whether the serial port is activated to receive data, and also contains flags that are set when a byte is successfully sent or received. To use the 89C51’s on-board serial port, it is generally necessary to initialize the following SFRs: SCON, TCON, and TMOD.

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This is because SCON controls the serial port. However, in most cases the program will wish to use one of the timers to establish the serial port’s baud rate. In this case, it is necessary to configure timer 1 by initializing TCON and TMOD.

SBUF (Serial control) The Serial Buffer SFR is used to send and receive data via the on-board serial port. Any value written to SBUF will be sent out the serial port’s TXD pin. Likewise, any value, which the 89C51 receive via the serial port’s RXD pin, will be delivered to the user program via BUF. In other words, when written to SBUF serves as the output port and when read from as an input port.

IE (Interrupt enable) The Interrupt Enable SFR is used to enable and disable specific interrupts. The low 7 bits of the SFR are used to enable/disable the specific interrupts, where as the highest bit is used to enable or disable ALL interrupts. Thus, if the high bit of IE is 0 all interrupts are disabled regardless of whether an individual interrupt is enabled by setting a lower bit. Table 2.3 Functions of Special Function Registers

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2.11 IP (Interrupt priority) The Interrupt Priority SFR is used to specify the relative priority of each interrupt. On the 89C51, an interrupt may either be of low (0) priority or high (1) priority. An interrupt, may only interrupt, interrupts of lower priority. For example, configure the 89C51 so that all interrupts are of low priority except the serial interrupt, the serial interrupt will always be able to interrupt the system, even if another interrupt is currently executing. However, if a serial interrupt is executing no other interrupt will be able to interrupt the serial interrupt routine since the serial interrupt routine has the highest priority. The 89c51 operations that do not use the internal 128-byte RAM addresses from 00H to 7FH are done by a group of specific internal registers, each called a Special Function register, which may be addressed much like internal RAM, using addresses from 80h to FFH. PC is not part of the SFR and has no internal RAM address

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CHAPTER 3 DTMF Signalling 3.1 Introduction DTMF stands for “Dual Tone Multi Frequency” (also called Touch Tone or Tel Touch) and during the 25 years has steadily gaining ground at the expense of the traditional dial pulse signaling employed in the older telephone sets. Many years ago, the engineers at Bell labs figured out that the dial pulse system was not the best for long distances, reliability, using over microwave systems and so on. Their research showed that you could use tones to represent the digits that the person was dialing. You could have a single separate tone for each digit, but there is always a chance that a random sound will be on the same frequency and trip up the system. So, they reasoned, if you have 2 tones to represent a digit, then a false is less likely to occur. This is the basis for Dual Tone in the DTMF. Now, if you have two tones for each digit, and there are 12 keys on the telephone, (0-9,*, #) then you will need 24 tones. If you remember, most of the tones at that time were being generated with coils and capacitors instead of solid state IC’s like they are today. If you didn’t mind a telephone in the size of a Breadbox, the 24tones theory would work just fine. However, most people wanted a phone that looked like a phone and did not cotton to the idea of talking into a loaf of bread.

3.2 Generation of DTMF Signals The Engineers came up with the idea of row and column tones. That means that you think of your telephone keypad as a grid. Every button is positioned at the intersection of horizontal row and vertical column. Each row has a single tone, and each column has a single tone. When you press a button, you generate both the row and column tones i.e. 2 tones.

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Each button will have at least one different from any other keys. Using a normal keypad layout with the same 12 buttons, you now need only 7 tones, not 24. Table 3.1 A Row and Column Grid 1

2

3

697HZ

4

5

6

770HZ

7

8

9

852HZ

0 1209HZ

941HZ

1336HZ

1477HZ

When you press digit 1 on your phone you generate the tones 1209Hz and 697Hz. If you press digit 2, you will now generate the tones 1209Hz that would complete a digit 1, and a 1336 Hz that would complete a digit 2. While the Engineers were working on this, they decided to throw in a few more “special purpose “tone groups. You don’t normally see these on telephones, but they are alive, well and being used for communication signaling. For lack of imagination, the Engineers called four of the “extra” digits “A, B, C, and D”. These all use the same row frequencies as a standard keypad, but they have a special column tone. Table 3.2 Row and column Grid with Special Purpose Tones 1

2

3

A

697HZ

4

5

6

B

770HZ

7

8

9

C

852HZ

1477H

D 1633H

941HZ

1209H

0 1336H

Z

Z

Z

Z

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The special codes are very useful for preventing a standard telephone from being used to control remote devices, and can give override status when used correctly in a two-way radio system.

3.3 DTMF Receiver Development More than 25 years ago the need for an need for an improved method for transferring dialing information through the telephone network was recognized. The main disadvantages of the dialing system (which makes the phone generate a member of ON-OFF pulses corresponding to the digit dialed by the user) are:  The mechanical make and break of the circuit is difficult and closely to implement through a computer or other electronic device. Some sort of electromechanical relay is needed.  The actual time to dial the complete number is fairly long and in fact depends on the specific number being dialed. For the example, consider dialing the following 2 numbers at 1 pulse/sec with 0.5 sec between numbers. 345 takes: 0.3+0.5+0.4+0.5+0.5 = 2.2sec. 789 takes: 0.7+0.5+0.8+0.5+0.9 = 3.4 sec. This problem is due to two reasons. First, the inter-office lines are tied up for a long time with just passing digits. Second, the length of the time is uncertain and depends on the number sequence itself. This means that the receiving circuitry must be prepared for a variety of time spans and these capability necessities an inefficient and costly design of circuitry.

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 These make/break pulses can’t really be used for any other purpose. Once the numbers are dialed and the call established, any opening or closing of the loop may be confused with hanging up the phone. The use of dial pulse for any type of signal, such as to active equipment at the receiver end is impractical.  The dial pulses suffer severe distortion over long wire loops.  The dial pulses require a dc path through the communication channel.

3.4 Advantages of DTMF Signalling The main advantages of the DTMF tone dialing system are  The time to send a complete number is greatly reduced. A 3-digit phone number takes only 1.25 sec regardless of the digits, using 0.25 sec value for tone and inter tone duration. A 7-digit number can be sending in 3.25 sec so that the phone circuits are tied up for much less duration with the dialing information.  The time to send a number is the same regardless of the actual digits themselves. For example all 7-digit numbers take the same time and so on. As a result the receiver circuitry is much easier to design.  The tones can be used for signaling purposes, once the dialing is over. The phone system is designed to ignore any and all frequencies within the frequency band that the voice uses. Since the circuitry designed to take some specific action once the call is established may accidentally be tripped by the user’s voice. The tones can therefore be used to turn on equipment or send a coded message to the system at the other end. This is in contrast to pulse dialing in which the phone system is designed to look

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at all times for the opening of the loop to the phone, since this indicates that the phone has been hung up.  Circuitry to send tones is easier to build with modern ICs and much easier to control with computers or other electronic equipment when compared to pulse dialing systems. This means tone dialing is more compatible with modern systems and automatic unattended operations.  The other important advantages are: 1) Convenience 2) Efficiency 3) High reliability in transmission of signals 4) Better performance 5) Small system size 6) Lower power cost due to LSI implementation 7) Lower power consumption due to CMOS technology 8) Existence of complementary technologies such as voice synthesizer The main reasons that have accelerated the conversion of dial Pulse signaling equipment to tone dialing are:  Increase in competition between DTMF receiver manufacturers.  Switch to MOS/LSI technology, thus taking advantage of semiconductor pricing curves.  Acceptance by telephone companies of newer technologies and reduction of procurement cycle.  Emergence of new application for DTMF signaling.  The additional revenue available on the DTMF line quickly amortizes the cost of DTMF installation.

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CHAPTER 4 HARDWARE SETUP 4.1 Block Diagram

Fig.4.1 Block Diagram

4.2 Design and Development Stage 1

getting 5V supply

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Connecting 230v supply to a step-down transformer and bringing it to 12v. The transformer output is rectified using a full wave rectifier and this rectified A.C voltage is feed as input to 7805 regulator. 7805 1st pin ------input 2nd pin ----ground 3rd pin -----output 3rd pin i.e. the output is connected as input supply to various ICs used in the circuit. Check Now the power is switched on and the 3rd pin of 7805 is checked for 5v supply with the help of a multimeter. Stage 2

Ring detection

The telephone line voltage is feed to abridge rectifier. the rectifier output is filtered and by using a potentiometer we obtain voltage below 5v. This line voltage is feed as negative input to the comparatorLM393 6th pin. To the positive input we fed voltage i.e. obtained by connecting 5v supply to the potentiometer. This is connected to the 7th pin of the LM339 comparator. High signal at 1st pin of LM393 indicates no ring and a low signal indicates ring tone on a telephone line. Check Initially we check whether the comparator out put i.e.1st pin is a high signal or not. Stage 3

DTMF Signal Detection

The telephone line is connected as input to the DTMF decoder IC CM8870. The telephone line is connected to the second pin of the IC .Crystal oscillator of 3.578M H.Z is connected to seventh and eight pins .Supply voltage is given to tenth pin, 4 bit BCD output is produced at pins 11 to 14 .Fifteen pin is also an output and is 27

called STD (delay steering).If Std is high then it indicates presence of valid BCD code on the output lines. Check

all the BCD code output lines are checked for high signal.

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STAGE 4

Microcontrollers

The outputs from ring sensor and DTMF decoder are fed to microcontroller. We use port 0 and port2.ring sensor output is fed to P0.5 pin. DTMF output is fed to pins P0.0 to p0.3.std signal is fed to P0.4 pin P0.7 pin is connected to a relay that shifts the telephone from ring mode to voice mode. Similarly pins P1.2to P1.4 all are connected to relay driving circuits. And stepper motor is connected to P2.1 to P2.4A high signal on these pins switches on the relay and a low signal turns off the relay.18 and19 pins are connected to 2 terminals of the oscillators the oscillator terminals are connected to two 33pf capacitors the other capacitor terminals are shorted and grounded. Check The pins 18 and19 of 89c51 are checked the clock pulse with help of an oscillator.

4.3 Comparator LM393 A comparator as its name implies compares a signal voltage on one input of an op amp with a known voltage called the reference voltage on the other input. In its simplest form, it is nothing more than an open loop op amp, with two analog inputs and a digital out put. The output may be positive or negative saturation voltage depending on which input is the larger. Comparators are used in circuits such as digital interfacing, Schmitt triggers, discriminator, voltage-level detectors, and oscillators.

Basic Comparator An op amp is used as a comparator. A fixed reference voltage Vref of 2.5v is applied to the positive input, and the other time varying signal voltage Vin is applied to the negative input. Because of this arrangement, the circuit is called the INVERTING COMPARATOR. When Vin is less than Vref, the output voltage Vo is at

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+Vsat (approximately-Vee) because the +Vsat (approximately+Vee). Thus Vo changes from one saturation voltage at the negative input is higher than that at the positive input. On the other hand, when Vin >Vref, the positive input becomes positive with respect to the negative input, and Vo goes to level to another whenever Vin=Vref, as shown in fig. in short the comparator is a type of analog to digital converter. At any given time the Vo waveform shows whether Vin is greater or lesser than Vref. The comparator is some times also called as VOLTAGE LEVEL DETECTOR because, for a desired value of Vref the voltage level of the input Vin can be detected.

General Description The LM393 series consists of four independent precision voltage comparators with an offset voltage specification as low as 2 mV max for all four comparators. These were designed specifically to operate from a single power supply over a wide range of voltages. Operation from split power supplies is also possible and the low power supply current drain is independent of the magnitude of the power supply voltage. These comparators also have a unique characteristic in that the input common mode voltage range includes ground, even though operated from a single power supply voltage. Application areas include limit comparators, simple analog to digital converters, pulse, square wave and time delay generators, Clock timers, multi vibrators and high voltage digital logic gates. The LM393 is a distinct advantage over standard comparators.

Fig.4.2 Pin Connection of LM 393 30

Fig.4.3 Inverting Comparator with Hysteresis

(Vcc R1)  V ref = (Rref+R1) 

R3 = R1 // Rref // R2

(R1 // Rref) [Vo (max)-Vo (min)]  Vh= R1 // Rref + R2 

R2 > Rref // R1

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Features  Wide supply voltage range  LM139/139A Series 2 to 36 VDC or ± 1 to ±18 VDC  LM2901:2to36 VDC or± 1 to± 14 VDC  LM3302:2 to 28 VDC or± 1 to ± 14  Very low supply current drain (0.8mA) independent of supply voltage.  Low input biasing current:25nA  Low input offset current: ± 5nA  Offset voltage : ± 3mV  Input common –mode voltage range includes GND.  Differential input voltage range equal to the power supply voltage.  Low out put saturation voltage: 250mV at 4mA.  Output voltage compatible with TTL, DTL, ECL, MOS and CMOS logic systems.

Advantages  High precision comparators  Reduced VOS drift over temperature  Eliminates need for dual supplies  Allows sensing near GND  Compatible with all forms of logic  Power drain suitable for battery operation

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Absolute Maximum Ratings of LM393 Table 4.1 Absolute Maximum Ratings of LM393 Supply Voltage, V+

36VDC or ±18VDC

Differential input voltage

36VDC

Input Voltage

-0.3 VDC to +36VDC

Input Current (Vin