Technical Systems Engineering Director in Irvine CA Resume James Mayer

James Mayer, MSEE Technical Leader Principal Systems Engineer

714.306.2037 ~ [email protected]

Leadership Qualities Proven team leadership skills combined with exceptional ability to manage multiple projects, tasks and priorities concurrently, and in timely manner. Superior communicator and spokesperson with ease in presenting in front of clients, senior executives and/or large audiences of engineers. Skilled in organizing, motivating, and inspiring teams of experts to excel in tasks involving high expectations in engineering environment. Top Secret Clearance (exp. 2012) Technical Summary Solid technical background combined with exceptional business skills in analyzing, testing and managing design, development, documentation, maintenance and configuration management, in wide variety of multi-million dollar systems in complex multivendor environments. Skilled in large and small businesses, as well as commercial entities and government defense contractors. Core Competencies Team Building & Leadership Multi-Million Dollar Project Management Technical Presentations – Large & Small Audiences Program Management – Face & Voice of Company Specialties Hardware/Software Development Digital Communications Design Firmware Development Systems Engineering

Process Optimization Proposal Development Innovative Problem Solver Multi-Million Dollar Monthly Budget

Rapid Prototyping Satellite Payloads Digital Signal Processing Wireless Network Design

Embedded Communications Requirements Development MS Project, Excel, Word, PowerPoint, DOORS

Select Career Accomplishments st Directed 10 individuals in 1 -of-its-kind ad-hoc wireless system to serve Army (both hardware and software development) that directly led to 8 successful networking units and customer demonstrations ($14M/monthly budget). Previous hardware vendor was able to connect 3 elements and Intel Corp. was able to connect 5 elements. Led technical team in smooth transition of 4 technologies into phase III SBIR prime contractor programs. Coordinated transition plan agreements between prime contractors and small businesses. Received commendation from US Air Force. Principal contributor to Internal Design Review, Preliminary Design Review, and Critical Design Review processes and worked 1on-1 with consulting team in development of Engineering Model to demonstrate digital payload for advanced satellite communication system. Compiled report and presented in front >400 scientists from Hughes, Aerospace Corporation, and MIT/Lincoln Labs on hardware design/implementation of engineering model for digital satellite demodulator payload. Pr o f es s ion a l Exp er i en c e TECHNICAL PROJECT MANAGER DIRECTV INC., El Segundo, CA 2012 – 2013  Project Manager for Consumer STB SW Engineering and Broadcast Systems. Provided status, delivered support, and aided in execution of Conditional Access Management Center (CAMC) tasks involving Unix to Linux application migration and database server upgrades. Provided technical support/guidance in executing development and test of new features for NDS STBs, and addressing problem reports. Coordinated/supported actions between NDS and DirecTV.  Worked with senior management in introducing work plans and developing schedules. Generated/maintained schedules among team leaders. Provided motivation/support to meet schedule commitments via weekly meetings and technical exchanges. Assisted in managing team that oversaw all NDS STBs operational support. Tracked, researched, and resolved program issues for Broadcast Systems/STB SW. Monitored progress and prioritized actions to support SW release dates.

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James Mayer, MSEE ~ 714.306.2037 ~ [email protected]

PRINCIPAL SYSTEMS ENGINEER, SE&I Payload-to-Terminal ICD Project Lead LinQuest Corp., Los Angeles, CA 2007 – 2011 Consulting and communications engineering company serving federal agencies and industrial customers. Scope of responsibility: supervised 6 lead engineers on development team. Reported directly to CTO. Objective: to further develop requirements document on new technology describing Payload-to-Terminal communications between satellite and user terminal, requiring consensus of >300 engineers in strategy and details of every operation.  Led development of Interface Control Document (ICD) addressing Layer 1, 2 & 3 functions for payload-to-terminal communications in TSAT (cutting-edge military satellite system). Directed activities for Information Assurance, Acq/Trk, Network, AEHF compatibility, PHY layer, and advanced communication link.  Established priorities and guided development with >300 engineers contributing to ICD contents.  Conducted analysis/risk assessments; recommended risk mitigation strategies. Top level requirements defined in Technical Requirements Document and Air Force illustrations, and flowed down where it was ultimately entered into DOORS database. Impact!!  Led technical team in overcoming complex technical challenges in smooth transition of 4 technologies into phase III SBIR prime contractor programs. Coordinated transition plan agreements between prime contractors and small businesses.  Increased requirements document completion 80% during project tenure. Streamlined development processes and improved productivity through effective reporting, prioritization and customer weekly communications. Received commendation from United States Air Force for successful efforts.  Developed method of requiring supporting lead at each contractor to achieve continuity and ensure ownership of tasks. Method served essential in project progressing at faster rate. LEAD SYSTEMS PROJECT ENGINEER General Dynamics, Advanced Information Systems Division, Anaheim Hills, CA 2003 – 2007 US defense contractor with last year’s profit of $564M serving defense industry in IS and combat systems areas. Scope of responsibility: directed 10 individuals in both hardware and software development. $14M/monthly budget. Reported to Program Manager and Site Program Director. st Objective: to program direct development of 1 of its kind ad-hoc wireless system to serve Army. Tasked with working with customer in establishing approach, direction, and funding to support requirement.  Scheduled, planned, directed and procured all engineering resources for development of scalable, self-configuring ad-hoc sensor-embedded communications network project.  Provided research/direction for technologies/routing protocols to be used in development of heterogeneous embedded sensor network. Led rewrite/reengineer /testing of software algorithms to achieve customer’s goals. Impact!!  Defined, established and met project goals and milestones for team that directly led to 8 successful networking units and customer demonstrations. Previously hardware vendor was able to connect 3 elements and Intel Corp. was able to connect 5 elements. Project so successful hardware vender offered to buy business.  Developed customized WLAN hardware solution for Xilinx FPGA-based wireless card from existing Verilog RTL implementation and ARM processor.  Received 4 General Dynamics Achievement Awards. DSP FIRMWARE ENGINEER Intel Corp., Network Connectivity Division, Irvine, CA 2000 – 2003 $40B semiconductor house serving computing and communications industries in worldwide markets. Scope of responsibility: team member of 3. Reported to Program Manager. Objective: development of algorithms and firmware for echo canceller for VoIP media gateway.  Originally hired by Vxtel 2000 (grew to 160 employee during tenure), then acquired by Intel 2001.  Oversaw full approval of patent application for ‘Echo Canceller with Doubletalk and Channel Impulse Response Adaptation.’ Team partnership with co-team located in India. Task involved experimentation of algorithms, testing, and rework to improve performance measures. Additionally, traveled frequently to Japan to support potential customer of (NEC) in efforts of analyzing echo canceller. Impact!!  Successfully developed firmware for echo canceller for IXS1000 media gateway as part of VoP (Voice-over-Packet) program for embedded DSP group. Page 2

James Mayer, MSEE ~ 714.306.2037 ~ [email protected]

DSP FIRMWARE ENGINEER, Intel Corp. Continued:  Achieved carrier-class status and higher rating than other commercially-deployed echo cancellers at AT&T.  British Telecom analyzed echo canceller and compared it to other commercially available echo cancellers proving ours achieved performance measures exceeding other echo cancellers.  Won Intel Division Recognition Award from President of Network Connectivity Div. for echo canceller efforts. DIGITAL PROCESSOR PAYLOAD DESIGN / VERIFICATION ENGINEER Hughes Space & Communications Co., Los Angeles, CA 1996 – 2000 Primary products were commercial and government satellites serving US government/military market. Scope of responsibility: supervised 10 engineers from ASIC design team, subsystems team, and systems engineering team in design development with high level of authority due to results gained from algorithm study. Reported to Program Manager. Objective: to come up with design that not only met customer’s requirements but in simplest design (i.e. fewest number of digital ASIC gates).  Designed/implemented hardware design of engineering model for digital satellite demodulator payload. Compile presentations based on findings for Preliminary Design Review, Internal Design Review, and Critical Design Review, presenting in front >400 scientists from Hughes, Aerospace Corporation, and MIT/Lincoln Labs.  Researched requirements, architectural design and development of DSP algorithms for digital demodulator and detector for low-power CMOS technology for MILSATCOM.  Led subsystem team and ASIC design team in mapping top-level requirements to low-level hardware design for secure Frequency-Hopped Spread Spectrum (FHSS) anti-jam satellite communication system.  Designed innovative DSP technique for processing multiple channels in bandwidth-limited frequency plan; created behavioral fixed-point models in SPW, MATLAB and C.  Constructed VHDL test benches for ASIC design team to facilitate single-design RTL verification and multi-design verification utilizing ModelSim.  Integrated requirements of systems engineering team with ASIC design team. Simplified algorithms for ASIC design team and translated requirements into set of hardware elements. Participated in testing ASIC models against golden C model to ensure superior performance. Impact!!  Significantly saved ASIC design team time in design and testing; project remained on schedule and with completion of designs in allotted time.  Developed algorithm to process bandlimited channel frequency plan that was ASIC design efficient in cost savings and in development/testing.  Received numerous Hughes Achievement Awards during this program. Pr o f es s ion a l D ev e lo p m en t Education Master of Science - Electrical Engineering / University Of Southern California Bachelor of Science, Electrical Engineering / University Of California Honors Certificate of Commendation, U.S. Air Force General Dynamics Achievement Award (x4) Intel Division Recognition Award Clearance Top Secret Clearance (exp. 2012)

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James Mayer, MSEE ~ 714.306.2037 ~ [email protected]