SystemVerilog for e Experts Janick Bergeron

SystemVerilog for e Experts— Understanding the Migration Process

Janick Bergeron Synopsys Scientist May 2006

©2006 Synopsys, Inc.

Abstract This document identifies the major differences between the e language as defined by the IEEE P1647/ D6 draft standard and the SystemVerilog language as defined by the IEEE Std. 1800™ 2005 standard. It explains the semantics of those differences and, where relevant, presents how similar functionality can be obtained using SystemVerilog. The document concludes that any verification environment based on e could easily and efficiently be implemented in SystemVerilog.

Introduction Like any modern programming language, e and SystemVerilog have much in common. Both provide enumerated types, have a for-loop statement and support object-oriented programming. And being verification languages, both support constrained randomization, functional coverage and interfacing to a design under verification. Finally, both languages have recently become IEEE standards. Despite having so much in common, these two languages differ significantly in certain critical areas. In terms of industry support and momentum, SystemVerilog is without a doubt the choice for the vast majority of the market with all major EDA vendors supporting, or pledging support for, the language. e is currently supported by just one major EDA vendor. Various user surveys have also shown a clear preference for SystemVerilog as the preferred language for future designs. In technical terms, the two languages have major differences that may require users to take a slightly different approach to testbench coding. The main focus of this document is to identify and explain these differences, and to describe how functionality similar to e can be obtained using SystemVerilog.

HDL References In e, a hardware description language (HDL) signal can be accessed without any prior reference or declaration by simply specifying its hierarchical name between single quotes: if (‘~/top.dut.blk_a.status_reg’ != 0) ...

SystemVerilog, being an extension of Verilog, has similar arbitrary access to any HDL signal through crossmodule references, either absolute or relative: if (top.dut.blk_a.status_reg != 0) ...

However, SystemVerilog cross-module references cannot be runtime expressions: they must be literal references, whereas an e HDL reference can contain a string expression that is evaluated at runtime. Similarly, the root path of a relative HDL reference is specified by the hdl_path() of the unit containing the reference. This feature is used to define the path and name of the interface signals a transactor is connected to. module top; reg tx_clk_0, tx_clk_1, tx_clk_2, tx_clk_3; reg [3:0] txd_0, txd_1, txd_2, txd_3; reg txe_0, txe_1, txe_2, txe_3; ... endmodule

©2006 Synopsys, Inc.



unit mii_bfm { tx_clk: string; txd : string; tx_en : string; ... event txc: rise(‘(tx_clk)’) @sim; ... send(fr: eth_frame) @txc is { ... ‘(txd)’