Solution For All Problems in Chapter 9

 

SOLUTION FOR PROBLEMS IN CHAPTER 9 : MSI LOGIC CIRCUITS 9-1 : Refer to Figure 9-3 Determine the levels at each decoder output for the following sets of input conditions :

a. Input nput : All All LOW LOW  output : All HIGH  b. Input : LOW except E3= HIGH  output : O’3=LOW c. Input Input : All All inputs inputs HIGH HIGH exce except pt E’1=E E’1=E’2= ’2=LOW LOW  Output : All HIGH d. Inpu Inputt : All All HIGH HIGH  Output : All LOW 9-3 : For a 74LS138, what input conditions will produce the following outputs :

a.  b. c. d.

Outp Output ut : LOW LOW at O’6 O’6  Input : E3E’2E’1 = 100, [A]=110 (MSB) Output : LOW at O’3  Input : E3E’2E’1 = 100, [A]=011 (MSB) Outp Output ut : LOW LOW at O’5 O’5  Input : E3E’2E’1 = 100, [A]=101 (MSB) Output Output : LOW LOW at O’0 O’0 and and O’7, O’7, simult simultane aneous ously ly  Input : E3E’2E’1 = 100, [A]= 111 (MSB)

9-4 : Show how to use 74LS138s to form a 1-of-16 decoder :

  Inputs A, B, C are used to select which output on either decoder will be at logic “1” (HIGH) and input Dis used with the enable input to select which encoder either the first or second will output the “1”. However, there is a limit to the number of inputs that can be used for one particular decoder, because as n increases, the number of AND gates required to produce an output also becomes larger resulting in the fanout of the gates used to drive d rive them becoming large. This type of active-“HIGH” decoder can be implemented using just Inverters, ( NOT Gates ) and AND gates. It is convenient to use an AND gate as the basic decoding element for the output because it produces a “HIGH” or  logic “1” output only when all of its inputs are logic “1”. But some binary binary decoders decoders are constructed constructed using NAND NAND gates gates instead instead of AND gates for their decoded output, output, since NAND gates are cheaper to produce than AND’s as they require fewer transistors to implement within their design. The use of gates the decoding element, results inan aninverted active-“LOW” output while the rest willlike be “HIGH”. AsNAND a NAND gateasproduces the AND operation with output, the NAND decoder looks this with its inverted truth table.

 

9.5: Figure 9-70 shows how a decoder can be used in the generation of control signals . Assume that s RESET pulse has occurred at time t0, and determine the CONTROL waveform for 32 clock pulses :

9.8 : Consider the waveform signals to the 74LS138 as follow :

in Figure 9-72 . Apply these

A A0, B A1, C A2, D E3 9-13 : Drill question : For each item, indicate whether it is referring to a decoder or an encoder :

(a),(b): Decoder ;

(c),(d),(e) : Encoder

9-15: Apply the signals sign als of Figure 9-72 to the inputs input s of a 74147 as follo follows ws : A D A’ A’1 1: 9-16: 9-24: 9-25: 9-27: 9-29: 9-31: 9-35: 9-36: 9-37: 9-38: 9-39: 9-41: 9-43: 9-44: 9-56: 9-57:

A’7, B

A’4, C

A’2,

 

9-58 9-62: