Download Siemens Simatic S 7 300 - 400 -Statement List for S7-300 and S7-400...
Preface, Contents Product Overview
1
Structure and Components of Instructions and Statements
2
Adressing
3
Accumulator Operations and Address Register Instructions
4
Bit Logic Instructions
5
Timer Instructions
6
Counter Instructions
7
Load and Transfer Instructions
8
Integer Math Instructions
9
SIMATIC S7 Statement List (STL) for S7-300 and S7-400 Programming Reference manual
This reference manual is part of the documentation package with the order number 6ES7810-4CA04-8BR0
10/98 C79000-G7076-C565 Release 01
Floating-Point Math Instructions
10
Comparison Instructions
11
Conversion Instructions
12
Word Logic Instructions
13
Shift and Rotate Instructions
14
Data Block Instructions
15
Jump Instructions
16
Program Control Instructions
17
Appendix Glossary, Index
Safety Guidelines
!
!
!
This manual contains notices which you should observe to ensure your own personal safety, as well as to protect the product and connected equipment. These notices are highlighted in the manual by a warning triangle and are marked as follows according to the level of danger:
Danger indicates that death, severe personal injury or substantial property damage will result if proper precautions are not taken.
Warning indicates that death, severe personal injury or substantial property damage can result if proper precautions are not taken.
Caution indicates that minor personal injury or property damage can result if proper precautions are not taken.
Note draws your attention to particularly important information on the product, handling the product, or to a particular part of the documentation.
Correct Usage
!
Note the following:
Warning This device and its components may only be used for the applications described in the catalog or the technical description, and only in connection with devices or components from other manufacturers which have been approved or recommended by Siemens. This product can only function correctly and safely if it is transported, stored, set up, and installed correctly, and operated and maintained as recommended.
Trademarks
SIMATIC, SIMATIC HMI
and SIMATIC NET are registered trademarks of SIEMENS AG.
Third parties using for their own purposes any other names in this document which refer to trademarks might infringe upon the rights of the trademark owners.
Copyright Siemens AG 1998 All rights reserved
Disclaimer of Liability
The reproduction, transmission or use of this document or its contents is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved.
We have checked the contents of this manual for agreement with the hardware and software described. Since deviations cannot be precluded entirely, we cannot guarantee full agreement. However, the data in this manual are reviewed regularly and any necessary corrections included in subsequent editions. Suggestions for improvement are welcomed.
Siemens AG Bereich Automatisierungs- und Antriebstechnik Geschaeftsgebiet Industrie-Automatisierungssysteme Postfach 4848, D-90327 Nuernberg
Siemens Aktiengesellschaft
Siemens AG 1998 Technical data subject to change. C79000-G7076-C565
Statement List (STL) for S7-300/S7-400
Preface
Purpose
This manual is your guide to creating user programs in the Statement List programming language STL. The manual also includes a reference section that describes the syntax and functions of the language elements of STL.
Audience
This manual is intended for S7 programmers, operators, and maintenance/service personnel. A working knowledge of automation procedures is essential.
Scope of the Manual
This manual is valid for release 5.0 of the STEP 7 programming software package.
Compliance with Standards
STL corresponds to the “Instruction List” language defined in the International Electrotechnical Commission’s standard IEC 1131-3, although there are substantial differences with regard to the operations. For further details, refer to the table of standards in the STEP 7 file NORM_TBL.WRI.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
iii
Preface
Requirements
To use this Statement List manual effectively, you should already be familiar with the theory behind S7 programs which is documented in the online help for STEP 7. The language packages also use the STEP 7 standard software, so you should be familiar with handling this software and have read the accompanying documentation.
Documentation
Purpose
Order Number
STEP 7 Basic Information with
Basic information for technical per- 6ES7810-4CA04-8BA0 Working with STEP 7 V5.0, Getting Started sonnel describing the methods of implementing control tasks with Manual STEP 7 and the S7-300/400 proProgramming with STEP 7 V5.0 grammable controllers. Configuring Hardware and Communication Connections, STEP 7 V5.0
From S5 to S7, Converter Manual STEP 7 Reference with
Ladder Logic (LAD)/Function Block Diagram (FBD)/Statement List (STL) for S7-300/400 manuals
Standard and System Functions for S7-300/400
Online Helps
Provides reference information and 6ES7810-4CA04-8BR0 describes the programming languages LAD, FBD and STL and standard and system functions extending the scope of the STEP 7 basic information.
Purpose
Order Number
Help on STEP 7
Basic information on programming and configuraing hardware with STEP 7 in the form of an online help.
Reference helps on STL/LAD/FBD
Context-sensitive reference informa- Part of the STEP 7 Stantion. dard software.
Reference help on SFBs/SFCs
Part of the STEP 7 Standard software.
Reference help on Organization Blocks
Accessing the Online Help
You can display the online help in the following ways:
Context-sensitive help about the selected object with the menu command Help > Context-Sensitive Help, with the F1 function key, or by clicking the question mark symbol in the toolbar.
Help on STEP 7 via the menu command Help > Contents. References
iv
References to other documentation are indicated by reference numbers in slashes /.../. Using these numbers, you can check the exact title in the References section at the end of the manual.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Preface
SIMATIC Customer Support Online Services
The SIMATIC Customer Support team offers you substantial additional information about SIMATIC products via its online services:
General current information can be obtained: – on the Internet under http://www.ad.siemens.de/simatic/html_00/simatic – via the Fax-Polling number 08765-93 02 77 95 00
Current product information leaflets and downloads which you may find useful are available: – on the Internet under http://www.ad.siemens.de/support/html_00/ – via the Bulletin Board System (BBS) in Nuremberg (SIMATIC Customer Support Mailbox) under the number +49 (911) 895-7100. To dial the mailbox, use a modem with up to V.34 (28.8 Kbps) with the following parameter settings: 8, N, 1, ANSI; or dial via ISDN (x.75, 64 Kbps).
Additional Assistance
If you have other questions, please contact the Siemens representative in your area. The addresses are listed, for example, in catalogs and in Compuserve (go autforum). Our SIMATIC Basic Hotline is also ready to help:
in Nuremberg, Germany – Monday to Friday 07:00 to 17:00 (local time): telephone: +49 (911) 895–7000 – or E-mail:
[email protected]
in Johnson City (TN), USA – Monday to Friday 08:00 to 17:00 (local time): telephone: +1 423 461–2522 – or E-mail:
[email protected]
in Singapore – Monday to Friday 08:30 to 17:30 (local time): telephone: +65 740–7000 – or E-mail:
[email protected] The SIMATIC Premium Hotline is available round the clock worldwide with the SIMATIC card (telephone: +49 (911) 895-7777).
Courses for SIMATIC Products
Siemens offers a number of training courses to introduce you to the SIMATIC S7 automation system. Please contact your regional training center or the central training center in Nuremberg, Germany for details: Telephone: +49 (911) 895-3154.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
v
Preface
Questionnaires on the Manual and Online Help
vi
To help us to provide the best possible documentation for you and future STEP 7 users, we need your support. If you have any comments or suggestions relating to this manual or the online help, please complete the questionnaire at the end of the manual and send it to the address shown. Please include your own personal rating of the documentation.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Contents Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iii
1
Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-1
2
Structure and Components of Instructions and Statements . . . . . . . . . . . . . . . .
2-1
2.1
Structure of a Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-2
2.2
Meaning of the CPU Register in Statements . . . . . . . . . . . . . . . . . . . . . . . . .
2-10
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1
3.1
Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2
3.2
Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2
3.3
Memory Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3
3.4
Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-6
3.5
Area-Internal Register Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . .
3-7
3.6
Area-Crossing Register Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . .
3-11
Accumulator Operations and Address Register Instructions . . . . . . . . . . . . . . . .
4-1
4.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-2
4.2
ENT and LEAVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3
4.3
Incrementing and Decrementing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6
4.4
+AR1 und +AR2: Adding a Constant to Address Register 1 or Address Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7
Bit Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-1
5.1
Boolean Bit Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-2
5.2
Bit Logic Instructions and Relay Coil Circuit . . . . . . . . . . . . . . . . . . . . . . . . . .
5-6
5.3
Evaluating Conditions Using And, Or, and Exclusive Or . . . . . . . . . . . . . . .
5-10
5.4
Nesting Expressions and And before Or . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-14
5.5
Instructions for Transitional Contacts: FP, FN . . . . . . . . . . . . . . . . . . . . . . . .
5-16
5.6
Output of Boolean Logic String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-20
5.7
Set and Reset Instructions: S and R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-21
5.8
Assign Instruction (=) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-24
5.9
Negating, Setting, Clearing, and Saving the RLO . . . . . . . . . . . . . . . . . . . . .
5-26
3
4
5
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
vii
Contents
6
7
8
9
10
viii
Timer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-1
6.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-2
6.2
Location of a Timer in Memory and Components of a Timer . . . . . . . . . . .
6-3
6.3
Loading, Starting, Resetting, and Enabling a Timer . . . . . . . . . . . . . . . . . . .
6-5
6.4
Timer Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-7
6.5
Address Locations and Ranges for Timer Instructions . . . . . . . . . . . . . . . . .
6-17
6.6
Choosing the Right Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-18
Counter Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-1
7.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-2
7.2
Setting, Resetting, and Enabling a Counter . . . . . . . . . . . . . . . . . . . . . . . . . .
7-3
7.3
Couting Up and Counting Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-5
7.4
Loading a Count Value as Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-6
7.5
Loading a Count Value in Binary Coded Decimal Format . . . . . . . . . . . . . .
7-7
7.6
Counter Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-8
7.7
Address Locations and Ranges for Counter Instructions . . . . . . . . . . . . . . .
7-10
Load and Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-1
8.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-2
8.2
Loading and Transferring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-3
8.3
Reading the Status Word or Transferring to the Status Word . . . . . . . . . . .
8-6
8.4
Loading Times and Counts as Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-7
8.5
Loading Times and Counts in Binary Coded Decimal Format . . . . . . . . . .
8-9
8.6
Loading and Transferring between Address Registers . . . . . . . . . . . . . . . .
8-11
8.7
Loading Data Block Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-12
Integer Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-1
9.1
Four-Function Math . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-2
9.2
Adding an Integer to Accumulator 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-6
Floating-Point Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-1
10.1
Four-Function Math . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-2
10.2
Forming the Absolute Value of a Floating-Point Number . . . . . . . . . . . . . . .
10-6
10.3
Extended Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-7
10.4
Forming the Square / Square Root of a Floating-Point Number . . . . . . . . .
10-9
10.5
Forming the Natural Logarithm of a Floating-Point Number . . . . . . . . . . . . 10-11
10.6
Forming the Exponential Value of a Floating-Point Number . . . . . . . . . . . . 10-12
10.7
Forming Trigonometric Functions on Angles Acting as Floating-Point Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Contents
11
12
13
14
15
16
Comparison Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-1
11.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-2
11.2
Comparing Two Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3
11.3
Comparing Two Floating-Point Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-5
Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12-1
12.1
Converting Binary Coded Decimal Numbers and Integers . . . . . . . . . . . . .
12-2
12.2
Converting 32-Bit Floating-Point Numbers to 32-Bit Integers . . . . . . . . . . .
12-8
12.3
Reversing the Order of Bytes within Accumulator 1 . . . . . . . . . . . . . . . . . . . 12-13
12.4
Forming Complements and Negating Floating-Point Numbers . . . . . . . . . 12-14
Word Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13-1
13.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13-2
13.2
16-Bit Word Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13-3
13.3
32-Bit Word Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13-6
Shift and Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14-1
14.1
Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14-2
14.2
Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14-6
Data Block Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15-1
15.1
Opening Data Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15-2
15.2
Swapping Data Block Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15-2
15.3
Loading Data Block Lengths and Numbers . . . . . . . . . . . . . . . . . . . . . . . . . .
15-3
Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-1
16.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-2
16.2
Unconditional Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-3
16.3
Conditional Jump Instructions Founded on Result of Logic Operation . . .
16-4
16.4
Conditional Jump Instructions Founded on BR, OV, or OS Bits of the Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-5
Conditional Jump Instructions Based on Result in the CC 1 and CC 0 Bits of the Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-6
Loop Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-8
Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17-1
17.1
Parameter Assignment when Calling FCs and FBs . . . . . . . . . . . . . . . . . . .
17-2
17.2
Calling Functions and Function Blocks with CALL . . . . . . . . . . . . . . . . . . . .
17-3
17.3
Calling Functions and Function Blocks with CC and UC . . . . . . . . . . . . . . .
17-7
17.4
Working with Master Control Relay Functions . . . . . . . . . . . . . . . . . . . . . . . . 17-10
17.5
Master Control Relay Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
17.6
Ending Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16
16.5 16.6 17
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
ix
Contents
A
Alphabetical Listing of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A-1
A.1
Listing with (German) SIMATIC and International Mnemonics . . . . . . . . . .
A-2
A.2
Alphabetical Listing with International Names . . . . . . . . . . . . . . . . . . . . . . . .
A-12
Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B-1
B.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B-2
B.2
Bit Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B-3
B.3
Timer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B-7
B.4
Counter and Comparison Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B-10
B.5
Integer Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B-12
B.6
Word Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B-14
C
Source Files - Examples and Reserved Keywords . . . . . . . . . . . . . . . . . . . . . . . . .
C-1
D
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-1
B
x
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Glossary-1
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index-1
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Product Overview
1
What is Statement List?
Statement List (STL) is a textual programming language that can be used to create the code section of logic blocks. Its syntax for statements is similar to assembler language and consists of instructions followed by addresses on which the instructions act.
The Programming Language STL
Of all the programming languages with which you can program S7 controllers, STL is the closest to the machine code MC7 of the S7 CPU. This means that by using it to program S7 controllers, you can optimize the run time and the use of memory. The programming language STL has all the necessary elements for creating a complete user program. It contains a comprehensive range of instructions. A total of over 130 different basic instructions and a wide range of addresses are available. Functions and function blocks allow you to structure your STL program clearly.
The Programming Package
The STL programming package is an integral part of the STEP 7 Standard Software. This means that following the installation of your STEP 7 software, all the editor functions, compiler functions and test/debug functions for STL are available to you. Using STL, you can create your own user program as follows:
With the Incremental Editor. The input of the local data structure is made easier with the help of table editors.
With a source file in the Text Editor. Text input is made easier with the help of block templates. There are three programming languages in the standard software, STL, FBD, and LAD. You can switch from one language to the other almost without restriction and choose the most suitable language for the particular block you are programming. If you write programs in LAD or FBD, you can always switch over to the STL representation. If you convert LAD programs into FBD programs and vice versa, program elements that cannot be represented in the destination language are displayed in STL.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
1-1
1-2
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Structure and Components of Instructions and Statements
2
Chapter Overview
Page
Section
Description
2.1
Structure of a Statement
2.2
Meaning of the CPU Register in Statements
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
2-2 2-10
2-1
Structure and Components of Instructions and Statements
2.1
Structure of a Statement
Components of a Statement
With reference to structure, an instruction statement belongs to either one of the following two basic groups (see also Figure 2-1):
A statement made up of an instruction alone (for example, NOT, see Section 5.9)
A statement made up of an instruction and an address (see Tables 2-1 through 2-5, and Table 2-9)
Statement group 1 Instruction alone Figure 2-1
Address of an Instruction
Statement group 2 Instruction + address
Basic Groups of Statements
The address of an instruction indicates a constant or the location where the instruction finds a value (data object) on which to perform an operation. The address can have a symbolic name or an absolute designation. The address can point to any of the following items (see also Tables 2-1 through 2-9):
A constant, the value of a timer or counter, or an ASCII character string to be loaded into accumulator 1 (for example, L +27, see Table 2-1)
A bit in the status word of the programmable logic controller (for example, A UO, see Table 2-2)
A symbolic name (for example, A Motor.On, see Table 2-3) A data block and a location within the data block area (for example, L DB4.DBD10, see Table 2-4)
A function (FC), function block (FB), integrated system function (SFC), or integrated system function block (SFB) and the number of the function or block (see Table 2-5)
An address identifier and a location within the memory area that is indicated by the address identifier (for example, A I 1.0, or A I [AR1,P#4.3], see Table 2-9) Tables 2-1 through 2-9 show various statements that each include an instruction with an address.
2-2
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Structure and Components of Instructions and Statements
Constant Values
Table 2-1 shows how you can use a constant value as the address of an instruction. Table 2-1
Addresses That Point to a Value or Character String Statement
Instruction
Address
D Description i i
Constant
Locations in the Status Word
L
+27
L
’END’
Load the integer 27 into accumulator 1. Load the ASCII characters ’END’ into accumulator 1.
The address of a statement list instruction can refer to one or more bits in the status word of the programmable logic controller (see Section 2.2). The instruction checks and reacts to the signal state of a single bit in the status word (for example, A BR) or interprets the bit combination in two of the bits (for example, A UO). Table 2-2
Addresses That Refer to a Bit in the Status Word Statement
Instruction
Address
Description
Bit in the Status Word A
BR
The 1 or 0 in bit 8 of the status word is included in a Boolean logic combination.
A
UO
The instruction interprets the bit combination that it finds in bits CC 1 and CC 0 of the status word to see if a certain condition has been fulfilled. For example, a combination of 1 and 1 indicates “unordered,” that is, one of the values in a floating-point operation was not a valid floating-point number.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
2-3
Structure and Components of Instructions and Statements
Symbolic Name
Table 2-3 shows how you use a symbolic name as the address of an instruction. You can only use symbolic names in STL statements once you have declared them: shared symbolic names should be entered in the symbol table and local names in a block. Table 2-3
Addresses That Point to a Symbolic Name Statement
Instruction
Address
D Description i i
Symbol
A Data Block and a Location within the Data Block
A
Motor.On
Perform an And logic operation on the bit whose symbolic name is “Motor.On”. In this case, the symbolic name “Motor.On” can only represent a bit in the data block (D) area of memory or element of a structure “MOTOR” .
L
SPEED
Load the byte, word, or double word value, whose symbolic name is SPEED, into accumulator 1 .
Table 2-4 shows how you use a data block and a location within the data block as the address of an instruction. Table 2-4
Addresses That Point to a Data Block and a Location within the Data Block Statement
Instruction
Address
Description Descr pt on
Data Block and Location
2-4
L
DB4.DBD10
A
DB10.DBX4.3
Load data double word DBD10 from data block DB4 into accumulator 1. Perform an And logic operation on data bit DBX4.3 from data block DB10.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Structure and Components of Instructions and Statements
FCs, FBs, SFCs, and SFBs
Table 2-5 shows how you use a function (FC), function block (FB), integrated system function (SFC), or integrated system function block (SFB) and the number of the function or block as the address of an instruction. Table 2-5
Addresses That Point to a Function, Function Block, System Function, or System Function Block Statement
Instruction
Address D Description i ti
FC, FB, SFC, SFB and Number
Address Identifiers
CALL
FB10, DB10
CALL
SFC43
Call function block FB10 with instance data block DB10. Call integrated system function SFC43.
Some addresses include an address identifier and a location within the memory area indicated by the address identifier. An address identifier can be one of the following three basic types (see Tables 2-6 through 2-8):
An address identifier that indicates the memory area and the size of a data object in that area as follows (see Table 2-6): – The memory area in which an instruction finds a value (data object) on which to perform an operation (for example, “I” for the process image input area of memory) – The size of the value (data object) on which the instruction is to perform its operation (for example, B for “byte,” W for “word,” and D for “double word”)
An address identifier that indicates a memory area but no size of a data object in that area (for example, an identifier that indicates the area T for “timer,” C for “counter,” or DB or DI for “data block,” plus the number of that timer, counter, or data block, see Table 2-7)
An address identifier that indicates the size of a data object but no memory area. The memory area is encoded in the memory location that follows the address identifier (see Table 2-8).
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
2-5
Structure and Components of Instructions and Statements
Table 2-6
Address Identifier That Indicates Memory Area and Size of Data Object
Type of Addressing
Instruction
Address Identifier Memory Area
Direct
A
I
Direct
L
I
Memory indirect
A
I
Memory indirect
L
I
Area-internal register indirect
A
I
Area-internal register indirect
T
L
Table 2-7
Memory Location
Size of Data Object (If no size is indicated, a bit is implied.) 0.0 B
10 [MD2]
B
[DID4] [AR1, P#4.3]
D
[AR2, P#53.0]
Address Identifier That Indicates Memory Area, but No Size of Data Object Instruction
Address Identifier: Memory Area
Number or Location of Number
Direct
OPN
DB
5
Direct
SP
T
7
Memory indirect
OPN
DB
[LW2]
Memory Indirect
S
C
[MW44]
Type of Addressing
Table 2-8
Address Identifier That Indicates Size of Data Object, but No Memory Area Instruction
Type of Addressing
Area-crossing register indirect
A
Area-crossing register indirect
L
Table 2-9
Size of Data Object (If no size is indicated, a bit is implied.)
Memory Location
[AR1, P#4.3] B
[AR1, P#100.0]
Addresses That Include Address Identifier and Location Statement
Instruction
2-6
Address Address Identifier
Location in Memory Area or Register
A
I
1.0
A
I
[MD2]
L
C
1
D Description i ti
Perform an And logic operation on input bit 1.0. Perform an And logic operation on the input bit whose exact location is in memory double word MD2. Load the count value of counter 1 into accumulator 1.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Structure and Components of Instructions and Statements
Working with Word or Double Word as Data Object
If you are working with an instruction whose address identifier indicates a memory area of your programmable logic controller and a data object that is either a word or a double word in size (see Table 2-6), you need to be aware of the fact that the memory location is always referenced as a byte location. This byte location is the number of the most significant byte within the word or double word. For example, the address in the statement shown in Figure 2-2 references four successive bytes in memory area M, starting at byte 10 (MB10) and going through byte 13 (MB13).
Statement: L MD10 Address identifier
Figure 2-2
Byte location
Example of Memory Location Referenced as Byte Location
Figure 2-3 illustrates data objects of the following sizes:
Double word: memory double word MD10 Word: memory words MW10, MW11, and MW13 Byte: memory bytes MB10, MB11, MB12, and MB13 When you use absolute addresses that are a word or a double word in width, make sure that you do not create any byte assignments that overlap.
15
015
0
MW10 MB10
MW12 MB11
MB12
MB13 LSB
MSB 31
Figure 2-3
Memory Areas and their Functions
MW11 1615 MD10
0
Referencing a Memory Location as a Byte Location
Most addresses in STL refer to memory areas. The following table lists the memory areas and describes the function of each area.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
2-7
Structure and Components of Instructions and Statements
Table 2-10
Memory Areas and Their Functions Access to Area
Name of Area
Function Funct on of Area
via Units of the Following Size:
Abbrev.
Process image input
At the beginning of the scan cycle, the operating system reads the inputs from the process and records the values in this area. The program can use these values in its cyclic processing.
Input bit Input byte Input word Input double word
I IB IW ID
Process image output
During the scan cycle, the program calculates output values and places them in this area. At the end of the scan cycle, the operating system reads the calculated output values from this area and sends them to the process outputs.
Output bit Output byte Output word Output double word
Q QB QW QD
Bit memory
This area provides storage for interim results calculated in the program.
Memory bit Memory byte Memory word Memory double word
M MB MW MD
I/O: external input
This area enables your program to have direct access to input and output modules (that is, peripheral inputs and outputs).
Peripheral input byte Peripheral input word Peripheral input double word
PIB PIW PID
Peripheral output byte Peripheral output word Peripheral output double word
PQB PQW PQD
I/O: external output Timer
Timers are function elements of STL programming. This area provides storage for timer cells. In this area, clock timing accesses time cells to update them by decrementing the time value and timer instructions access time cells.
Timer (T)
T
Counter
Counters are function elements of STL programming. This area provides storage for counters. Counter instructions access them here.
Counter (C)
C
Data block
This area contains data that can be accessed from any block. If you need to have two different data blocks open at the same time, you can open one with the statement “OPN DB” and one with the statement “OPN DI”. In this way, the CPU can distinguish which of the two data blocks your program wants to access while both data blocks are open. While you can use the “OPN DI” statement to open any data block, the principal use of this statement is to open instance data blocks that are associated with function blocks (FBs) and system function blocks (SFBs). For more information on FBs, SFBs, and instance data blocks, see the STEP 7 Online Help.
Data block opened with the statement “OPN DB”:
Data bit Data byte Data word Data double word
DIX DIB DIW DID
This area contains temporary data that is used within a logic block (OB, FB, or FC). These data are also called dynamic local data. They serve as an intermediate buffer. When the logic block is finished, these data are lost. The data are contained in the local data stack (L stack).
Temporary local data bit Temporary local data byte Temporary local data word Temporary local data double word
L LB LW LD
Local data
2-8
Data bit Data byte Data word Data double word
DBX DBB DBW DBD
Data block opened with the statement “OPN DI”:
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Structure and Components of Instructions and Statements
Table 2-11 lists the maximum address ranges for various memory areas. For the address range possible with your CPU, refer to the technical data of the CPU. For an explanation of the functions of the memory areas, see Table 2-10. Table 2-11
Memory Areas and Their Address Ranges Access to Area
Name of Area
via Units of the Following Size:
Abbrev.
M i Maximum Address Add Range R
Process image input
Input bit Input byte Input word Input double word
I IB IW ID
0.0 to 65,535.7 0 to 65,535 0 to 65,534 0 to 65,532
Process image output
Output bit Output byte Output word Output double word
Q QB QW QD
0.0 to 65,535.7 0 to 65,535 0 to 65,534 0 to 65,532
Bit memory
Memory bit Memory byte Memory word Memory double Word
M MB MW MD
0.0 to 255.7 0 to 255 0 to 254 0 to 252
I/O: external input
Peripheral input byte Peripheral input word Peripheral input double word
PIB PIW PID
0 to 65,535 0 to 65,534 0 to 65,532
I/O: external output
Peripheral output byte Peripheral output word Peripheral output double word
PQB PQW PQD
0 to 65,535 0 to 65,534 0 to 65,532
Timer
Timer (T)
T
0 to 255
Counter
Counter (C)
C
0 to 255
Data block
Data block opened with the statement “OPN DB”:
DBX DBB DBW DBD
0.0 to 65,535.7 0 to 65,535 0 to 65, 534 0 to 65,532
DIX DIB DIW DID
0.0 to 65,535.7 0 to 65,535 0 to 65, 534 0 to 65,532
L LB LW LD
0.0 to 65,535.7 0 to 65,535 0 to 65, 534 0 to 65,532
Data bit Data byte Data word Data double word Data block opened with the statement “OPN DI”: Data bit Data byte Data word Data double word Local data
Temporary local data bit Temporary local data byte Temporary local data word Temporary local data double word
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
2-9
Structure and Components of Instructions and Statements
2.2
Meaning of the CPU Register in Statements
Accumulators
The two 32-bit accumulators are general purpose registers that you use to process bytes, words, and double words. You can load constants or values from the memory as addresses into the accumulator and perform logic operations on them. You can also transfer the result of an operation from accumulator 1 to a memory location. Figure 2-4 identifies the areas of an accumulator. The stack mechanism for accumulator administration is as follows:
A load instruction always acts on accumulator 1 and saves the old contents to accumulator 2.
A transfer instruction does not change the accumulators (with the exception of instructions TAR1 and TAR2).
The TAK instruction swaps the contents of accumulators 1 and 2. For information on accumulator administration for math instructions, see Section 9.1.
31
24 High byte
23
16 Low byte
High word Figure 2-4
15
8 7 High byte
Accumulator (1 or 2)
0 Low byte
Low word
Areas of an Accumulator
Nesting Stack
The nesting stack is a storage area that is one byte wide. This storage area is used by the nesting instructions A(, O(, X(, AN(, ON(, XN(. These instructions save the current result of logic operation (RLO) to the nesting stack and start a new logic string. The nesting stack can accommodate seven entries. A nesting stack entry consists of the RLO, BR, and OR bits of the status word, and a function code to indicate which of the Boolean logic operations is to be used (A, AN, O, ON, X, or XN). The “)” instruction closes a nesting expression by performing the following functions:
Fetches an entry from the nesting stack Restores the OR and BR bits Defines the new RLO by logically combining the current RLO (that is, the RLO from the expression nested in parentheses) with the RLO of the stack entry according to the function code (see Section 5.4)
2-10
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Structure and Components of Instructions and Statements
Figure 2-5 shows the structure of an entry in the nesting stack. Below Figure 2-5 you can see an explanation of the bits in the nesting stack byte.
Figure 2-5
27
26
0
0
25
24
23
22
21
20
BR
RLO
OR Function code
Structure of an Entry in the Nesting Stack
The nesting stack byte contains the following bits (see Figure 2-5):
Non-assigned bits (bits 7 and 6 with signal state “0”) The stored binary result (BR) The stored result of logic operation (RLO) The stored OR bit in the functions A( and AN( Zero is stored in all other functions
The function code (in bits 2, 1 and 0) Function code With the help of the function code, the instruction “)” defines the function which is to be used for the combination of the current RLO (that is the RLO from the expression nested in parentheses) with the RLO of the nesting stack entry. Table 2-12 shows the bit combinations of the function code for each function type: Table 2-12
Function Codes of Nesting Stack Byte
Instruction
Function Code 2
Function Code 1
Function Code 0
A(
0
0
0
AN(
0
0
1
O(
0
1
0
ON(
0
1
1
X(
1
0
0
XN(
1
0
1
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
2-11
Structure and Components of Instructions and Statements
Nesting Stack with Entries and Pointer The nesting stack and the nesting stack pointer must be stored either in the interrupt stack or they must be fetched from it, when the batches change. The number in the nesting stack pointer indicates the number of entries available in the nesting stack (see Figure 2-6). 15
7 Nesting stack entry 7
Nesting stack entry 6
Nesting stack entry 5
Nesting stack entry 4
Nesting stack entry 3
Nesting stack entry 2
Nesting stack entry 1
Nesting stack pointer
Figure 2-6
Status Word
Rising addresses
Structure of a Nesting Stack with Entries and Pointer
The status word contains bits that you can reference in the address of bit logic and word logic instructions. Figure 2-7 shows the structure of the status word. The sections that follow the figure explain the significance of bits 0 through 8. 215...
Figure 2-7
First Check
0
...29
28
27
26
BR
CC 1 CC 0
25 OV
24 OS
23
22
OR
STA
21 RLO
20 FC
Structure of the Status Word
Bit 0 of the status word is called the first-check bit (FC bit, see Figure 2-8). The signal state of 0 in the FC bit indicates that, following this point in your program, the next logic instruction begins a new logic string. (The bar over the FC indicates that it is negated.) Each logic instruction checks the signal state of the FC bit as well as the signal state of the location it addresses. If the FC bit is 0, the instruction stores the result of the signal state check in the result of logic operation bit of the status word (RLO bit, see next section) and sets the FC bit to 1. This process is called a first check (see Figure 2-8 and Section 5.6). If the signal state of the FC bit is equal to 1, an instruction combines the result of its signal state check on the contact it addresses with the value stored in the previous RLO bit (see Figure 2-8). A string of logic instructions always ends with an output instruction (S, R, or =, see Sections 5.7 and 5.8), a jump instruction related to the result of logic operation (JC, see Section 16), or one of the nesting instructions A(, O(, X(, AN(, ON(, or XN( (see Section 5.4). Such an output, jump instruction, or nesting instruction resets the FC bit to 0 (see Figure 2-8).
2-12
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Structure and Components of Instructions and Statements
Result of Logic Operation
Bit 1 of the status word is called the RLO bit (RLO stands for “result of logic operation,” see Figure 2-7). This bit stores the result of a bit logic instruction or math comparison. For example, the second instruction in a string of bit logic instructions checks the signal state of a contact and produces a result of 1 or 0. Then the instruction combines this result with the value stored in the RLO bit of the status word according to the principles of Boolean logic (see First Check above and Chapter 5). The result of this logic operation is stored in the RLO bit of the status word, replacing the former value in the RLO bit. Each subsequent instruction in the string performs a logic operation on two values: the result produced when the instruction checks the contact, and the current RLO. You can set the RLO to 1 unconditionally by using the SET instruction; you can reset the RLO to 0 unconditionally by using the CLR instruction. You can use a Boolean bit logic instruction on a first check to assign the state of the contents of a Boolean bit memory location to the RLO. You can use the RLO to trigger jump instructions.
Statement List Program
Signal State Result of Check of Input (I) or Output (Q)
RLO Bit
FC Bit
Explanation
0
FC bit = 0 indicates that next instruction begins logic string
A I 1.0
1
1
1
1
Result of first check is stored in RLO bit. FC bit is set to 1.
AN I 1.1
0
1
1
1
Result of check is combined with previous RLO according to AND truth table. FC bit remains 1.
= Q 4.0
1
0
RLO is assigned to output coil. FC bit is reset to 0.
Figure 2-8
Status Bit
Effect of Signal State of FC Bit on Logic Instructions
The status bit (STA bit) stores the value of a bit that is referenced. The status of a bit instruction that has read access to the memory (A, AN, O, ON, X, XN) is always the same as the value of the bit that this instruction checks (the bit on which it performs its logic operation). The status of a bit instruction that has write access to the memory (S, R, =) is the same as the value of the bit to which the instruction writes or, if no writing takes place, the same as the value of the bit that the instruction references. The status bit has no significance for bit instructions that do not access the memory. Such instructions set the status bit to 1 (STA=1). The status bit is not checked by an instruction. It is interpreted during program test (program status) only.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
2-13
Structure and Components of Instructions and Statements
OR Bit
The OR bit is needed if you use the O instruction to perform a logical AND before OR operation. An AND function may contain the following instructions: A, AN A(, AN(, ), and NOT. The OR bit shows these instructions that a previously executed AND function has supplied the value 1, thus forestalling the result of the logical OR operation. Any other bit-processing command resets the OR bit (see Section 5.4).
Overflow Bit
The overflow bit (OV bit) indicates a fault. It is set by a math instruction or a floating-point comparison instruction after a fault occurs (overflow, illegal operation, illegal floating-point number). This bit is set according to the result of the next math instruction or comparison instruction.
Stored Overflow Bit
The stored overflow bit (OS bit) is set together with the OV bit when a fault occurs. Because the OS bit remains set after the fault has been eliminated, it stores the OV bit status and indicates whether or not a fault occurred in one of the previously executed instructions. The following commands reset the OS bit: JOS (jump after stored overflow), the block call commands, and the block end commands.
Condition Code 1 and Condition Code 0
The CC 1 and CC 0 bits (condition codes) provide information on the following results or bits:
Result of a math operation Result of a comparison Result of a digital operation Bits that have been shifted out by a shift or rotate command Tables 2-13 through 2-18 list the significance of CC 1 and CC 0 after your program executes certain instructions. Table 2-13
CC 1 and CC 0 after Math Instructions, without Overflow
CC 1
CC 0
Explanation
0
0
Result = 0
0
1
Result < 0
1
0
Result > 0
Table 2-14
2-14
CC 1 and CC 0 after Integer Math Instructions, with Overflow
CC 1
CC 0
Explanation
0
0
Negative range overflow in +I and +D
0
1
Negative range overflow in I and D Positive range overflow in +I, –I, +D, –D, NEGI, and NEGD
1
0
Positive range overflow in I, D, /I, and /D Negative range overflow in +I, –I, +D, and –D
1
1
Division by 0 in /I, /D, and MOD
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Structure and Components of Instructions and Statements
Table 2-15
CC 1 and CC 0 after Floating-Point Math Instructions, with Overflow
CC 1
CC 0
0
0
Gradual underflow
0
1
Negative range overflow
1
0
Positive range overflow
1
1
Invalid floating-point number
Table 2-16
Explanation
CC 1 and CC 0 after Comparison Instructions
CC 1
CC 0
0
0
Accumulator 2 = accumulator 1
0
1
Accumulator 2 < accumulator 1
1
0
Accumulator 2 > accumulator 1
1
1
Accumulator 1 or accumulator 2 is an invalid floating-point number
Table 2-17
Explanation
CC 1 and CC 0 after Shift and Rotate Instructions
CC 1
CC 0
0
0
Last bit shifted out = 0
1
0
Last bit shifted out = 1
Table 2-18
Explanation
CC 1 and CC 0 after Word Logic Instructions
CC 1
CC 0
0
0
Result = 0
1
0
Result 0
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Explanation
2-15
Structure and Components of Instructions and Statements
Binary Result Bit
The binary result bit (BR bit) forms a link between the processing of bits and words. It is an efficient means of interpreting the result of a word operation as a binary result and integrates this result in a binary logic string. Viewed in this way, the BR bit represents a machine-internal memory bit to which the RLO is saved prior to a word operation that changes the RLO, so that the RLO will be available again after the operation to continue the interrupted bit string. For example, the BR bit makes it possible for you to write a function block (FB) or a function (FC) in statement list (STL) and then call the FB or FC from ladder logic (LAD, see the Reference Manual /233/). When writing a function block or function that you want to call from LAD, no matter whether you write the FB or FC in STL or LAD, you are responsible for managing the BR bit. The BR bit corresponds to the enable output (ENO) of a LAD box. You should use the SAVE instruction (in STL, see Section 5.9) or the –––(SAVE) coil (in LAD) to store an RLO in the BR bit according to the following criteria:
Store an RLO of 1 in the BR bit for a case where the FB or FC is executed without error.
Store an RLO of 0 in the BR bit for a case where the FB or FC is executed with error You should program these instructions at the end of the FB or FC so that these are the last instructions that are executed in the block. When you call a system function block (SFB) or a system function (SFC) in your program, the SFB or SFC indicates whether the CPU was able to execute the function with or without errors by providing the following information in the binary result bit:
If an error occurred during execution, the BR bit is 0. If the function was executed with no error, the BR bit is 1.
2-16
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3
Addressing Chapter Overview
Section
Description
Page
3.1
Immediate Addressing
3-2
3.2
Direct Addressing
3-2
3.3
Memory Indirect Addressing
3-3
3.4
Address Registers
3-6
3.5
Area-Internal Register Indirect Addressing
3-7
3.6
Area-Crossing Register Indirect Addressing
3-11
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
3-1
Addressing
3.1
Immediate Addressing
Description
With immediate addressing, the address is coded directly in the instruction; that is, it directly follows the value with which the instruction is to work (for example, Load). An instruction can also provide its own value (for example, SET, see Table 3-1). Table 3-1
Examples
3.2
Immediate Addressing Description
Example SET
Set the RLO to 1.
OW W#16#A320
Or Word.
L 27
Load the integer value 27 into accumulator 1.
L ’ABCD’
Load the ASCII characters ABCD into accumulator 1.
L B#(100,12)
Load the two bytes 100 and 12 into accumulator 1.
L C#0100
Load the BCD value 0000 into accumulator 1.
Direct Addressing
Description
An instruction that uses direct addressing has the following two-part address that indicates the location of the value that the instruction is going to process:
An address identifier (for example, “IB” for “input byte”) An exact location within the memory area that is indicated by the address identifier The address points directly to the location of the value. Table 3-2
Examples
3-2
Direct Addressing Example
Description
A I 0.0
Perform an AND logic operation on input bit I 0.0.
S L 20.0
Set the local data bit L 20.0.
= M 115.4
Assign the RLO to memory bit M 115.4
L IB0
Load input byte IB0 into accumulator 1.
L MW64
Load memory word MW64 into accumulator 1.
T DBD12
Transfer the contents from accumulator 1 into data double word DBD12.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Addressing
3.3
Memory Indirect Addressing
Description
An instruction that uses memory indirect addressing has the following two-part address that indicates the location of the value that the instruction is going to process:
An address identifier (for example, “IB” for “input byte”) One of the following pointers: – A word that contains the number of a timer (T), counter (C), data block (DB), function (FC), or function block (FB) – A double word that contains the exact location of a value within the memory area that is indicated by the address identifier The address indicates the location of the value or number indirectly via the pointer. This word or double word can be in one of the following areas:
Bit memory (M) Data block (DB) Instance data block (DI) Local data (L) The advantage of memory indirect addressing is that you can modify the statement address dynamically during program execution.
Using the Right Syntax
When working with a memory indirect address that is stored in the data block area of memory, first you must open the data block by using the Open a Data Block (OPN) instruction. Then you can use the data word or data double word as an indirect address, as shown in the following example: OPN DB10 L IB [DBD20]
Examples Table 3-3 Memory Indirect Addressing
Example
Description
A I [MD2] or A I [anna]
Perform an And logic operation on the input bit whose exact location is in memory double word MD2 or in the location designated by “anna” in the symbol table, as a reference to MD2.
= DIX [DBD2]
Assign the RLO bit to the instance data bit whose exact location is in data double word DBD2.
OPN DB [LW2]
Open the data block whose data block number is located in local word LW2.
O Q [LD3] or O Q [boxcar]
Perform an Or logic operation on the output bit that is located in a local data double word LD3 or in a local TEMP variable designated as “boxcar.”
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
3-3
Addressing
Pointer Format
There are two possible pointer formats: word and double word. The abbreviation for a pointer in word format ends in W (for example, DBW). Figure 3-1 shows the pointer format for a word. The abbreviation for a double word format ends in D (for example, DBD). Figure 3-2 shows the pointer format for a double word.
15.. ..8 nnnn nnnn
7.. ..0 nnnn nnnn
Bits 0 to 15 (nnnn nnnn nnnn nnnn): number (range 0 to 65,535) of a timer (T), counter (C), data block (DB), function (FC), or function block (FB)
Figure 3-1
Word Pointer Format for Memory Indirect Addressing
The following two examples show how to work with the word pointer format:
STL
Explanation
L +5 T MW2 OPN DB[MW2]
Load the value 5 as an integer into accumulator 1. Transfer the contents of accumulator 1 to memory word MW2. Open data block 5.
STL
Explanation
OPN L T A
3-4
DB10 +20 DBW10 T[DBW10]
Open data block DB10. Load the value 20 as an integer into accumulator 1. Transfer the contents of accumulator 1 to data word DBW10 Check the signal state of timer T 20.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Addressing
31.. ..24 23.. ..16 15.. ..8 0000 0000 0000 0 bbb bbbb bbbb
7.. bbbb b
..0 xxx
Bits 3 to 18 (bbbb bbbb bbbb bbbb): byte number (range 0 to 65,535) of the addressed byte Bits 0 to 2 (xxx): bit number (range 0 to 7) of the addressed bit
Figure 3-2
Double Word Pointer Format for Memory Indirect Addressing
Note If you access a byte, word, or double word, be sure that the bit number of your pointer is 0.
The following two examples show you how to work with the double word pointer format:
STL
Explanation
L
P#8.7
T
MD2
Load 2#0000 0000 0000 0000 0000 0000 0100 0111 (binary value) into accumulator 1. Store the exact location 8.7 in memory double word MD2.
A I [MD2] = Q [MD2]
The controller checks input bit I 8.7 and assigns its signal state to output bit Q 8.7.
STL
Explanation
L
P#8.0
T
MD2
L IB [MD2] T MW [MD2]
Load 2#0000 0000 0000 0000 0000 0000 0100 0000 (binary value) into accumulator 1. Store the exact location 8 in memory double word MD2. The controller loads input byte IB8 and transfers the contents to memory word MW8. The exact location 8 comes from memory double word MD2.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
3-5
Addressing
3.4
Address Registers
Explanation
Some types of indirect addressing in statement list programming require the use of certain registers in the CPU. These registers are described below.
Address Registers 1 and 2
Address registers 1 and 2 (AR1 and AR2) are 32-bit registers that accept an area-internal or area-crossing pointer for commands that use register-indirect addressing (see Sections 3.5 and 3.6).
Pointers
Pointers are used in register-indirect addressing (see Sections 3.5 and 3.6). The following two types are available:
Area-internal: used for area-internal access to bits, bytes, words, and double words in memory areas P, I, Q, M, DBX, DIX, and L
Area-crossing: used for area-crossing access to bits, bytes, words, and double words in memory areas P, I, Q, M, DBX, DIX, and L
3-6
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Addressing
3.5
Area-Internal Register Indirect Addressing
Description
An instruction that uses area-internal register indirect addressing has the following two-part address that indicates the memory location of the value that the instruction is going to process:
An address identifier (for example, “LD” for “local data double word,” see Table 2-6)
An address register and a pointer to specify byte and bit. The byte and bit indicate an offset, which, when added to the contents of the register, indicate the memory location of the value that the instruction is to process. The address points to the memory location of the value indirectly via the address register plus offset. A statement that uses area-internal register indirect addressing does not change the value in the address register.
Calculating the Memory Location of the Address
The address of an instruction points to the value that the instruction is going to process. Where area-internal register indirect addressing is concerned, the address points to the memory location of the value indirectly via the address register plus offset. Figure 3-3 shows how you calculate the memory location for the address of the Assign (=) instruction in the following statement: = Q [AR1, P#1.1]
Byte
+
Bit
Contents of address register AR1: 8.7
byte 8, bit 7
Offset P#:
byte 1, bit 1
1.1
Memory location:
output byte Q 10.0
bytes: 9, bits: 8 (= 1 byte) (9 bytes + 1 byte = 10 bytes)
Figure 3-3
Calculating the Memory Location of Output Q [AR1, P#1.1]
You calculate the memory location of the address by adding the byte portion of the contents of the address register to the byte portion of the offset pointer and by adding the bit portion of the contents of the address register to the bit portion of the offset pointer. You calculate the byte portion of the memory location using decimal math and the bit portion using octal math (8 bits = 1 byte). There can be a carry between the bit and byte portions.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
3-7
Addressing
Table 3-4
Examples
Area-Internal Register Indirect Addressing Example
Description
A I [AR1, P#4.3]
Perform an And logic operation on the input bit whose memory location is calculated by the contents of address register AR1 plus 4 bytes, plus 3 bits.
= DIX [AR2, P#0.0]
Assign the RLO bit to the instance data bit whose memory location is in address register AR2.
L IB [AR1, P#100.0]
Load the input byte whose memory location is calculated by the contents of address register AR1 plus 100 bytes into accumulator 1.
T LD [AR2, P#56.0]
Transfer the contents of accumulator 1 into local data double word LD whose memory location is calculated by the contents of address register AR2 plus 56 bytes. With reference to addressing local data, please read the Warning below.
!
Warning Possible overwriting of the data that is used by the compiler. When you use absolute addressing to access temporary local data, there is no guarantee that there will be no conflict between the data used by the compiler and the local data that you are attempting to access by means of absolute addressing. It is possible that you overwrite some of the data that the compiler uses. (For example, the compiler uses local data for transferring formal parameters.) Local data that the compiler needs are attached to the symbolic data that are defined by the person doing the programming. When accessing temporary local data, you are advised to choose symbolic addressing over absolute addressing.
3-8
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Addressing
Pointer Format
Area-internal register indirect addressing has only one possible pointer format: double word. This double word contains an address encoded as a bit address. The abbreviation for a double word format ends in D (for example, DBD). Figure 3-4 shows the pointer format for a double word.
31.. ..24 23.. ..16 15.. ..8 7.. 0000 0000 0000 0 bbb bbbb bbbb bbbb b
..0 xxx
Bit 31 = 0 to indicate area-internal register indirect addressing Bits 3 to 18 (bbbb bbbb bbbb bbbb): byte number (range 0 to 65,535) of the addressed bit Bits 0 to 2 (xxx): bit number (range 0 to 7) of the addressed bit Figure 3-4
Double Word Pointer Format for Area-Internal Register Indirect Addressing
Note If you access a byte, word, or double word, be sure that the bit number of your pointer is 0.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
3-9
Addressing
The following two examples show you how to work with the double word pointer format:
STL L
Explanation P#8.7
Load a double word pointer to bit address location 8.7 into accumulator 1.
LAR1
Store a double word pointer to bit address location 8.7 in address register AR1.
A I [AR1, P#0.0]
The CPU adds the offset (P#0.0) to the contents of address register AR1 (8.7) and uses this address as the location of an And bit logic instruction. The contents of AR1 remain unchanged.
= Q [AR1, P#1.1]
The CPU assigns the result of the And bit logic operation (RLO) to an address (Q 10.0). The CPU calculates this address by adding the contents of address register AR1 (8.7) and the offset (P#1.1).
STL
Explanation
L
P#8.0
Load a double word pointer to bit address location 8.0 into accumulator 1.
LAR2
Store a double word pointer to bit address location 8.0 in address register AR2.
L IB [AR2, P#2.0]
The CPU loads input byte IB10 into accumulator 1.
T MW [AR2, P#200.0]
The CPU transfers the contents of accumulator 1 to memory word MW208. The location 208 comes from 8 (AR2) plus 200 (offset), which is 208.
3-10
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Addressing
3.6
Area-Crossing Register Indirect Addressing
Description
An instruction that uses area-crossing register indirect addressing has the following two-part address that indicates the memory location of the value that the instruction is going to process:
An address identifier that indicates the size of a data object (for example, “B” for “byte,” see Table 2-8). The memory area is indicated in bits 24, 25, and 26 of the address register.
An address register and a pointer that indicate an offset which, when added to the contents of the address register, indicates the memory location of the value that is to be processed by the instruction. The pointer is indicated by P#byte.bit. The address points to the memory location of the value indirectly via the address register plus offset. A statement that uses area-crossing register indirect addressing does not change the value in the address register.
Calculating the Memory Location of the Address
The address of an instruction points to the value that the instruction is going to process. Where area-crossing register indirect addressing is concerned, the address points to the memory location of the value indirectly via the address register plus offset. Figure 3-5 shows how you calculate the memory location for the address of the Assign (=) instruction in the following statement: = [AR1, P#1.1]
Byte
+
Bit
Contents of address register AR1: 8.7
byte 8, bit 7
Offset P#:
byte 1, bit 1
1.1
Memory location:
byte 10.0
bytes: 9, bits: 8 (= 1 byte) (9 bytes + 1 byte = 10 bytes)
Figure 3-5
Calculating the Address [AR1, P#1.1]
You calculate the memory location of the address by adding the byte portion of the contents of the address register to the byte portion of the offset pointer and by adding the bit portion of the contents of the address register to the bit portion of the offset pointer. You calculate the byte portion of the memory location using decimal math and the bit portion using octal math (8 bits = 1 byte). There can be a carry between the bit and byte portions.
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3-11
Addressing
Example
Table 3-5 provides examples of area-crossing register indirect addressing. The address must contain an additional area identification in bits 24, 25, and 26 of the pointer. The addressed information is in the address register. Table 3-5
Area-Crossing Register Indirect Addressing Description
Example A [AR1, P#4.3]
Perform an And logic operation on the bit whose memory location is calculated by the contents of address register AR1, plus 4 bytes plus 3 bits. The memory area of the bit is indicated in bits 24, 25, and 26 of address register AR1.
= [AR2, P#0.0]
Assign the RLO bit to the bit whose memory location is in address register AR2. The memory area of the bit is indicated in bits 24, 25, and 26 of address register AR2.
L B [AR1, P#100.0]
Load into accumulator 1 the byte whose memory location is calculated in address register AR1 plus 100 bytes. The memory area of the byte is indicated in bits 24, 25, and 26 of address register AR1.
T D [AR2, P#56.0]
Transfer the contents of accumulator 1 into the double word whose memory location is calculated by the contents of address register AR2 plus 56 bytes. The memory area of the double word is indicated in bits 24, 25, and 26 of address register AR2.
Table 3-6 lists the binary code in bits 24, 25, and 26 of the pointer that identifies the area. Table 3-6
Area Identification for Area-Crossing Register Indirect Addressing
Area Identification (Memory Area)
Binary Contents of Bits 26, 25, and 24
P
(I/O, external inputs and outputs)
000
I
(process-image input)
001
Q
(process-image output)
010
M
(bit memory)
011
DBX (data block)
100
DIX (data block)
101
(previous local data, that is, the local data of the previous incompleted block)
3-12
111
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Addressing
Pointer Format
Area-crossing register indirect addressing has only one possible pointer format: double word. The abbreviation for a double word format ends in D (for example, DBD). Figure 3-6 shows the pointer format for a double word.
31.. ..24 23.. 1000 0rrr 0000 0
..8 7.. 3.. ..16 15.. ..0 bbb bbbb bbbb bbbb b xxx
Bit 31 = 1 to indicate area-crossing register indirect addressing Bits 24, 25, and 26 (rrr): area identification (memory area, see Table 3-6) Bits 3 to 18 (bbbb bbbb bbbb bbbb): byte number (range 0 to 65,535) of the addressed bit Bits 0 to 2 (xxx): bit number (range 0 to 7) of the addressed bit Figure 3-6
Double Word Pointer Format for Area-Crossing Register Indirect Addressing
Note If you access a byte, word, or double word, be sure that the bit number of your pointer is 0. You cannot access local data using area-crossing register indirect addressing!
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
3-13
Addressing
The following two examples show you how to work with the double word pointer format:
STL L
Explanation P#I 8.7
Load a double word pointer to bit address location I 8.7 into accumulator 1.
LAR1
Store a double word pointer to bit address location I 8.7 in address register AR1.
L P#Q 8.7
Load a double word pointer to bit address location Q 8.7 into accumulator 1.
LAR2
Store a double word pointer to bit address location Q 8.7 in address register AR2.
A [AR1, P#0.0]
The CPU adds the contents of address register AR1 (P#I 8.7) and the offset (P#0.0) and uses the address pointed to by the result (I 8.7) as the address of an And bit logic instruction. The contents of AR1 remain unchanged.
= [AR2, P#1.1]
STL L
The CPU assigns the result of the And bit logic operation (RLO) to an address (Q 10.0). The CPU calculates this address by adding the contents of address register AR2 (P#Q 8.7) and the offset (P#1.1) and dereferencing the pointer. The contents of AR2 remain unchanged.
Explanation P#I 8.0
Load a double word pointer to bit address location I 8.0 into accumulator 1.
LAR2
Store a double word pointer to bit address location I 8.0 in address register AR2.
L P#M 8.0
Load a double word pointer to bit address location M 8.0 into accumulator 1.
LAR1
Store a double word pointer to bit address location M 8.0 in address register AR1.
L B [AR2, P#2.0]
The CPU loads input byte IB10.
T W [AR1, P#200.0]
The CPU transfers the contents to memory word MW208. Input byte 10 comes from 8 (AR2) plus 2 (offset). Memory word 208 comes from 8 (AR1) plus 200 (offset), which is 208.
3-14
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Accumulator Operations and Address Register Instructions
4
Chapter Overview
Page
Section
Description
4.1
Overview
4-2
4.2
ENT and LEAVE
4-3
4.3
Incrementing and Decrementing
4-6
4.4
+AR1 und +AR2: Adding a Constant to Address Register 1 or Address Register 2
4-7
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
4-1
Accumulator Operations
4.1
Overview The following instructions are available to you for handling the contents of one or both accumulators: Mnemonic
Instruction
Explanation
TAK
Toggle Accumulator 1 with Accumulator 2
This instruction exchanges the contents of accumulator 1 with the contents of accumulator 2.
PUSH with 2 ACCUs
Accumulator 1 to Accumulator 2 This instruction copies the contents of accumulator 1 to accumulator 2.
POP with 2 ACCUs
Accumulator 2 to Accumulator 1 This instruction copies the contents of accumulator 2 to accumulator 1.
PUSH with 4 ACCUs
Copy ACCU 3 to ACCU 4, ACCU 2 to ACCU 3, ACCU 1 to ACCU 2
This instruction copies the contents of accumulator 3 to accumulator 4, the contents of accumulator 2 to accumulator 3 and the contents of accumulator 1 to accumulator 2.
POP with 4 ACCUs
Copy ACCU 2 to ACCU 1, ACCU 3 to ACCU 2, ACCU 4 to ACCU 3
This instruction copies the contents of accumulator 2 to accumulator 1, the contents of accumulator 3 to accumulator 2 and the contents of accumulator 4 to accumulator 3.
ENT
Enter accumulator stack
This instruction copies the contents of accumulator 3 to accumulator 4 and the contents of accumulator 2 to accumulator 3.
LEAVE
Leave accumulator stack
This instruction copies the contents of accumulator 3 to accumulator 2 and the contents of accumulator 4 to accumulator 3.
INC
Increment Accumulator 1
This instruction increases the contents of the low byte of the low word of accumulator 1 by the 8-bit constant that is indicated in the instruction statement. The constant can be in the range of 0 to 255.
DEC
Decrement Accumulator 1
This instruction decreases the contents of the low byte of the low word of accumulator 1 by the 8-bit constant that is indicated in the instruction statement. The constant can be in the range of 0 to 255.
+AR1, +AR2
Add Accumulator 1 to Address Register
This instruction adds the contents of the low word of accumulator 1 to address register 1 or 2.
+AR1 P#Byte.Bit, +AR2 P#Byte.Bit
Add Constant to Address Register
This instruction adds a constant to the contents of address register 1 or 2.
BLD
Program Display Instruction
”This instruction does not carry out any function and does not influence the status bits. The instruction is only relevant to the programming device (PG) when a program is displayed. The address is the ID of the instruction BLD and is generated by the programming device.”
NOP 0
Null Instruction 0
NOP 1
Null Instruction 1
”These instructions do not carry out any function, nor do they influence the contents of the status word. The instructions NOP 1 and NOP 0 are required for decompiling. The instruction code contains a bit pattern with either 16 zeroes or 16 ones.”
For information on reversing the order of bytes in accumulator 1, see Section 12.3.
4-2
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Accumulator Operations
4.2
ENT and LEAVE
Description
With the instructions ENT (Enter Accumulator Stack) and LEAVE (Leave Accumulator Stack) you can carry out the following functions:
The instruction ENT copies the contents of Accumulator 3 to Accumulator 4 and the contents of Accumulator 2 to Accumulator 3. If you program the ENT instruction directly before a load instruction, it SHIFTS Accumulator 2 and Accumulator 3 further in the stack.
The instruction LEAVE copies the contents of Accumulator 3 to Accumulator 2 and the contents of Accumulator 4 to Accumulator 3. If you program the LEAVE instruction directly before a shift and rotate instruction, which combines accumulators, then the LEAVE instruction will function like a math operation.
ENT
Figure 4-1 shows how the ENT instruction works.
ENT
ACCU 4 31
0 I
II
III
ACCU 4 31
IV
0 V
ACCU 3 0 VI
VII
0 IX
ACCU 2 XI
Figure 4-1
XII
0 IX
ACCU 1
X
XI
XII
ACCU 1 0
XIV
XI
31
XII
31 XIII
X
ACCU 2 0
X
VIII
31
VIII
31 IX
VII
ACCU 3
31 V
VI
XV
XVI
31 XIII
0 XIV
XV
XVI
Copying the contents of Accumulator 3 to Accumulator 4 and the contents of Accumulator 2 to Accumulator 3 in the ENT instruction ENT
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
4-3
Accumulator Operations
LEAVE
Figure 4-2 shows how the LEAVE instruction works.
ACCU 4
31
0 I
II
ACCU 4
LEAVE
31 III
0 I
IV
ACCU 3 0 VI
VII
0 I
VIII
XI
XII
V
ACCU 1
Figure 4-2
Example
IV
0 VI
VII
VIII
XV
XVI
ACCU 1
31
0 XIV
III
31
0
XIII
II
ACCU 2
31 X
IV
31
ACCU 2 IX
III
ACCU 3
31 V
II
XV
31
XVI
XIII
0 XIV
Copying the contents of Accumulator 3 to Accumulator 2 and the contents of Accumulator 4 to Accumulator 3 in the LEAVE instruction
The following program extract shows the use of the ENT instruction. The floating points in the data double words DBD0 and DBD4 should be added together. The sum should then be divided by the difference of the floating points of the data double words DBD8 and DBD12.
DBD16 =
DBD0 + DBD4 DBD8 – DBD12
The quotient of the above division should be stored in DBD16. In this example, the purpose of the ENT instruction is to take the interim result (DBD0+DBD4), which is located in Accumulator 2 and save it in Accumulator 3. The subtraction command (-R) copies the interim result back to Accumulator 2 following the subtraction.
4-4
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Accumulator Operations
STL
Explanation
L
DBD0
L
DBD4
+R
L
DBD8
ENT L
DBD12
–R
/R T
DBD16
Load the value from data double word DBD0 in ACCU1 (the value must be in floating-point format). Copy the value from ACCU1 to ACCU2.Load the value from data double word DBD4 in ACCU1 (the value must be in floating-point format). Add the contents of ACCU1 and ACCU2 as floating-point numbers (32 bits, IEEE-FP) and store the result in ACCU1. Copy the value from ACCU1 to ACCU2. Load the value from data double word DBD8 to ACCU1. Copy the contents of ACCU3 to ACCU4. Copy the contents of ACCU2 (interim result) to ACCU3. Copy the contents of ACCU1 to ACCU2. Load the contents from data double word DBD12 to ACCU1. Subtract the contents of ACCU1 from the contents of ACCU2. Store the result in ACCU1. Copy the contents of ACCU3 to ACCU2. Divide the contents of ACCU 2 by the contents of ACCU1. Save the quotient in ACCU1. Transfer the result (ACCU1) to the data double word DBD16.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
4-5
Accumulator Operations
4.3
Incrementing and Decrementing
Description
You can use the Increment Accumulator 1 (INC) and Decrement Accumulator 1 (DEC) instructions to perform the following functions:
INC increases the contents of the low byte of the low word of accumulator 1 by the 8-bit constant that is indicated in the instruction statement. The constant can be in the range of 0 to 255.
DEC decreases the contents of the low byte of the low word of accumulator 1 by the 8-bit constant that is indicated in the instruction statement. The constant can be in the range of 0 to 255. The CPU always executes the INC and DEC instructions, regardless of the result of logic operation. These instructions do not affect the RLO nor do they change any of the bits in the status word. Note These instructions are not suitable for 16-bit or 32-bit math because no carry is made from the low byte of the low word of accumulator 1 to the high byte of the low word of accumulator 1. For 16-bit or 32-bit math, use the +I or +D instruction, respectively.
Example
The following sample program provides an example of how the INC instruction works within a loop triggered by a conditional jump.
STL
Explanation
Body of a loop operation
M1:
4-6
L T L INC T . . L 0). The FC bit determines the result of logic operation (RLO):
If FC is 0, the result of the state check will remain unchanged and will be stored in the RLO (start of a logic string).
If FC is 1, the result of the state check will be combined with the logic instruction (A, O, X) according to the truth table and will be stored in the RLO.
Truth Table at the Start of a Boolean Logic String
The result of logic operation can be determined with the help of the following truth table: Instruction
Status of Address
Result in RLO
And
0 1
0 1
And Not
0 1
1 0
Or
0 1
0 1
Or Not
0 1
1 0
Exclusive Or
0 1
0 1
Exclusive Or Not
0 1
1 0
Mnemonic A AN O ON X XN
5-2
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Bit Logic Instructions
Truth Table within the Boolean Logic String
After the second Boolean bit operation the RLO can be established with the help of the following table: Instruction
RLO Before Instruction
Status of Address
Result in RLO
And
0 0 1 1
0 1 0 1
0 0 0 1
And Not
0 0 1 1
0 1 0 1
0 0 1 0
Or
0 0 1 1
0 1 0 1
0 1 1 1
Or Not
0 0 1 1
0 1 0 1
1 0 1 1
Exclusive Or
0 0 1 1
0 1 0 1
0 1 1 0
Exclusive Or Not
0 0 1 1
0 1 0 1
1 0 0 1
Mnemonic A
AN
O
ON
X
XN
Addresses of Basic Functions (A, AN, O, ON, X, XN)
The address of an instruction can be a bit, a timer or a counter. The instruction accesses the contact with one of these addressing types: The address identifier and the address within the memory area defined by the address identifier (see Tables 5-1 and 5-3). Bit, timer or counter transferred as parameter (see Table 5-4). Conditions, expressed in bits of the status word (see Table 5-8).
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
5-3
Bit Logic Instructions
Table 5-1
Addresses: Direct and Indirect Addressing Maximum Address Range According to Addressing Type
Address ID
Direct
I Q
0.0 to 65,535.7
[DBD] [DID] [LD] [MD]
0 to 65,532
M
0.0 to 65,535.7
[DBD] [DID] [LD] [MD]
0 to 65,532
0.0 to 65,535.7
[DBD] [DID] [LD] [MD]
0 to 65,532
DBX DIX L
Table 5-2
Memory Indirect
[AR1, P#byte.bit] 0.0 to 8,191.7 [AR2, P#byte.bit] [AR1, P#byte.bit] 0.0 to 8,191.7 [AR2, P#byte.bit] [AR1, P#byte.bit] 0.0 to 8,191.7 [AR2, P#byte.bit]
Addresses: Area-Crossing Register Indirect Addressing Address Identifier1
Maximum Address Range [AR1, P#byte.bit] [AR2, P#byte.bit]
I, Q, M, DBX, DIX, or L 1
Register Indirect, Area-Internal
0.0 to 8,191.7
The memory area is encoded in pointer bits 24, 25, and 26 (see Section 3.6).
Table 5-3
Addresses: Timers and Counters Maximum Address Range According to Addressing Type
Address Ident Identifier f er
Direct
T C
Table 5-4
0 to 65,535
Symbolic name
5-4
[DBW] [DIW] [LW] [MW]
0 to 65,534
Address: Bit, Timer, or Counter Transferred as Parameter
Address
Table 5-5
Memory Indirect
Address Parameter Format A bit, timer, or counter transferred as parameter
Addresses of Boolean Bit Logic Instructions: Bits of the Status Word
Memory Area or Reference to a Location
Bits of the Status Word
>0, =0, 0, ==0, 3
Seg. 3
LIST:
Load destination: 0 = Jump to SEG0 1 = Jump to SEG1 2 = Jump to GEM 3 = Jump to SEG3 >3 = Jump to LIST
Jump distributor with length of four
SEG0: Program Segment 0 JU Common Program
COMM
SEG1: Program Segment 1 JU
End
COMM
SEG3: Program Segment 3 COMM: Common Program
Figure 16-1
Controlling the Flow of Logic Control Using the Jump to List Instruction JL
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16-3
Logic Control Instructions
16.3 Conditional Jump Instructions Founded on Result of Logic Operation Description
The following jump instructions interrupt the flow of logic in your program based on the result of logic operation (RLO) produced by the previous instruction statement:
Jump If RLO = 1 (JC) Jump If RLO = 0 (JCN) Jump If RLO = 1 with BR (JCB): The RLO is saved in the BR bit of the status word.
Jump If RLO = 0 with BR (JNB): The RLO is saved in the BR bit of the status word. Irrespectively of the jump, the following status word bits are described: OR :=0 STA :=1 RLO :=1 FC :=0
Start
I 1.0 = 1 and I 1.1 = 1?
No RLO=1
Program Section B Yes RLO=0 Erase MB10
IF RLO=0
A
I1.0
A
I1.1
JCN COMM L
0
T
MB10
COMM:
Section B
Common Program
Common Program
End
Figure 16-2
16-4
Controlling the Flow of Logic Control Using the Jump If RLO = 0 Instruction JCN
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Logic Control Instructions
16.4 Conditional Jump Instructions Founded on BR, OV, or OS Bits of the Status Word Description
The following jump instructions interrupt the flow of logic in your program based on the signal state of a bit in the status word (see Section 2.2). Jump If BR = 1 with BR (JBI) or Jump If BR = 0 (JNBI) Jump If OV = 1 ( JO) or Jump If OS = 1 (JOS) The JBI and JNBI instructions reset the OR and FC bits of the status word to 0 and set the STA bit to 1. The JOS instruction resets the OS bit to 0. Start
Reset OS Bit
JOS ODEL ODEL:
Calculate =+–
L
MW12
L
MW14
+
I
L
MW16
–
I
T
MW10
Reset OS Bit
Calculate
Overflow stored?
Yes
JOS SECC*
Section C No
JPZ SECB
Erase Result 0
Yes
SECB:
No
L
+10
T
MW20
JU
COMM
L
+17
T
MW30
JU
COMM
L
0
T
MW10
Section A
Section B
Section A
Section B
= 10
= 17
SECC:
Section C
COMM: Common Program Common Program
End Figure 16-3
* In this case, do not use the JO instruction. The JO instruction would check only the previous – I instruction if an overflow occurred.
Controlling the Flow of Logic Control Using the Jump If OS = 1 Instruction JOS, JP
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16-5
Logic Control Instructions
16.5 Conditional Jump Instructions Based on Result in the CC 1 and CC 0 Bits of the Status Word
Description
The following jump instructions interrupt the flow of logic in your program based on the result of a calculation:
Jump If Zero (JZ) Jump If Not Zero (JN) Jump If Plus (JP, that is, greater than zero) Jump If Minus (JM, that is, less than zero) Jump If Minus or Zero (JMZ, that is, less than or equal to zero) Jump If Plus or Zero (JPZ, that is, greater than or equal to zero, see Figure 16-4)
Jump If Unordered (JUO, that is, if one of the numbers in a floating-point math operation is not a valid floating-point number)
CC 1 and CC 0 in the Status Word
The status word bits CC 1 and CC 0 are described, irrespectively of the result of the previous operation. The signal states of the CC 1 and CC 0 bits of the status word indicate the conditions shown in Table 16-1. Table 16-1
Relationship of CC 1 and CC 0 to Conditional Jump Instructions
Signal State
16-6
Result of Calculat Calculation on
Jump Instruct Instruction on Tr Triggered ggered
0
=0
JZ
1 or 0
0 or 1
0
JN
1
0
>0
JP
0
1
=0
JPZ
0 or 0
0 or 1
=0?
Yes
SECB:
No
L
+10
T
MW20
JU
COMM
L
+17
T
MW30
JU
COMM
L
0
T
MW10
Section A
Section B Section A
Section B
= 10
= 17
SECC:
Section C
COMM: Common Program Common Program
End
Figure 16-4
* In this case, do not use the JO instruction. The JO instruction would check only the previous – I instruction if an overflow happened.
Controlling the Flow of Logic Control Using the Jump If Plus or Zero Instruction JPZ
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
16-7
Logic Control Instructions
16.6 Loop Control
Description
You can use the Loop (LOOP) instruction to call a program segment multiple times (see Figure 16-5). The Loop instruction decrements the low word of accumulator 1 by 1. Then the value in the low word of accumulator 1 is tested. If it is not 0, a jump is executed to the label indicated in the address of the Loop instruction; otherwise the next instruction is executed.
Providing a Label as Address
You provide the Loop instruction with a label so it knows the point to which it should return in the program. For example, the Loop instruction in the program shown in Figure 22-5 has the label NEXT as its address. This label tells the instruction to return to the statement T MB10 in th program. At this point, the program processes Section A. The Loop instruction returns to the label as many times as you tell it to. You provide this information in the low word of accumulator 1. One way to do this is to set up a loop counter and load it into the accumulator.
Start
Initialize Loop Counter
Program Section A
NEXT:
L
+5
T
MB10
Initialize Loop Counter
Section A Decrement Loop Counter by 1 L
MB10
LOOP NEXT Yes
Loop Counter 0? No End
Figure 16-5
16-8
Using the Loop Instruction to Call a Program Segment Multiple Times
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Logic Control Instructions
Setting Up a Loop Counter
You provide the Loop instruction with a value that indicates how many times you want LOOP to call a particular program segment. The Loop instruction interprets the loop counter as a WORD data type. Table 16-2 provides information about the two possible formats for a loop counter. Table 16-2
Using the Loop Instruction Efficiently
Possible Format for a Loop Counter
Value Type
Value Range
Data Type
Memory Area
Integer
1 to 65,535 (positive value only)
WORD
I, Q, M, D, L
Word
W#16#0001 to W#16#FFFF
WORD
I, Q, M, D, L
In order to avoid running a loop more times than is necessary, you need to be aware of the following characteristics of the Loop instruction:
If you initialize the loop counter with a 0, the loop is executed 65,535 times.
You should avoid initializing the loop counter with a negative number.
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16-9
Logic Control Instructions
16-10
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Program Control Instructions Chapter Overview
Section
Description
17 Page
17.1
Parameter Assignment when Calling FCs and FBs
17-2
17.2
Calling Functions and Function Blocks with CALL
17-3
17.3
Calling Functions and Function Blocks with CC and UC
17.4
Working with Master Control Relay Functions
17-10
17.5
Master Control Relay Instructions
17-11
17.6
Ending Blocks
17-16
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
17-7
17-1
Program Control Instructions
17.1 Parameter Assignment when Calling FCs and FBs
Terms
When calling blocks that require parameters the terms formal parameters and actual parameters play an important role. A formal parameter is a parameter whose name and data type are assigned and declared (for example, as INPUT, OUTPUT parameters) when the block is created. When a block is called in the Incremental Editor (for example CALL SFC31), STEP 7 automatically displays a list of all the formal parameters. The next step is to assign actual parameters to the formal parameters. An actual parameter is a parameter which functions and function blocks use during the actual run time of the user program. The following diagram shows the call of SFC31 “QRY_TINT” (Query Time-of-Day Interrupt) in STL. STL Representation
CALL SFC 31 OB_NO := 10 RET_VAL:= MW 22 STATUS := MW 100
Actual parameters Formal parameters
17-2
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Program Control Instructions
17.2 Calling Functions and Function Blocks with CALL
Description
You can use the Call (CALL) instruction to call functions (FCs) and function blocks (FBs) that you have created for your program or that you have received as standard functions and standard function blocks from Siemens. The Call instruction calls the FC or FB that you indicate as an address regardless of the result of logic operation or any other condition. When you use the Call instruction to call a function block, you must supply the function block with an instance data block (instance DB) or declare it as a local instance. The instance data block stores all the static variables and actual parameters of the function block. If you need information on how to program a function or a function block, or how to work with their parameters, see the STEP 7 Online Help.
Formal Parameters and Actual Parameters
When calling a function (FC) or a function block (FB), you must assign corresponding actual parameters to the declared formal parameters.
Specifying the Actual Parameters
The actual parameters used when a function (FC) or function block (FB) is called are generally specified symbolically. Absolute addressing of actual parameters is possible only for an address whose maximum size is a double word (for example, I 1.0, MB2, QW4, ID0).
The actual parameter that is specified when a function block is called must have the same data type as the formal parameter.
When you call a function, all formal parameters must be supplied with actual parameters. You only need to declare the actual parameters when these are different to the parameters of the previous call (actual parameters remain stored in the instance data block after the processing of the function block has been completed). When you call a function block, the Call instruction copies one of the following items into the instance data block of the function block, depending on the data type of the actual parameter and on the declaration of the formal parameter (IN, OUT, IN_OUT):
The value of the actual parameter A pointer to the address of the actual parameter A pointer to the L stack of the calling block where the value of the actual parameter has been buffered
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17-3
Program Control Instructions
Calling an FB with Instance DB and Block Parameters
The call can take place once the following details are entered:
The name of the function block The name of the instance data block and The parameters (if the actual parameter is a data block, the complete absolute address must always be specified, for example DB1.DBW2). The call uses either with an absolute or a symbolic address. Absolute Call: CALL FBx,DBy (pass parameters); x = block number y = data block number Symbolic Call: CALL fbname,datablockname (pass parameters); fbname = symbolic block name datablockname = symbolic data block name
Examples
The following example shows the call of function block FB40 with instance data block DB41. In this example, the formal parameters have the following data types: IN1: BOOL IN2: WORD OUT1: DWORD
STL
Explanation
CALL IN1:=
FB40,DB41 I1.0
IN2:=
MW2
OUT1:=
MD20
L
MD20
Call of FB40 with instance data block DB41. IN1 (formal parameter) is supplied with I 1.0 (actual parameter). IN2 (formal parameter) is supplied with MW2 (actual parameter). OUT1 (formal parameter) is supplied with MD20 (actual parameter). With this instruction, the program accesses the formal parameter OUT1.
The following example shows the call of function block FB50 with instance data block DB51. In this example, the formal parameters have the following data types: IN10: BOOL OUT11: STRUCT V1: BOOL V2: INT END_STRUCT
17-4
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Program Control Instructions
STL CALL IN10:=
Explanation FB50,DB51 I1.0
OUT11:= ACTPA11
Call of FB50 with instance data block DB51. IN10 (formal parameter) is supplied with I 1.0 (actual parameter). Here it is not possible to specify an absolute actual parameter (for example, MW10) because the formal parameter OUT11 was defined as a structure. Instead, the symbolic actual parameter ACTPA11 is specified. Please note that ACTPA11 has the same structure as the formal parameter OUT11.
Access to the values of the structure OUT11 in FB50 would be made as follows:
STL A L
Explanation OUT11.V1 OUT11.V2
Calling Multiple Instances
Perform an AND logic operation on the bit OUT11.V1. Load word OUT11.V2 into accumulator 1.
The call can take place once the following details are entered:
The instance name (= name of a static variable of the type FB z) and The Parameters The call always has a symbolic designation. CALL Instance Name (pass parameters);
STL
Explanation
FUNCTION_BLOCK FB 11 Source file VAR loc_inst : FB 10; Declaration of a multiple instance with data type FB10 END_VAR BEGIN NETWORK CALL #loc_inst ( Call of the multiple instance with syntax in_bool := M Parameter pass 0.0); (in_bool in this case is a variable declared in FB10)
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17-5
Program Control Instructions
Calling an FC with Block Parameters
The call can take place once the following details are entered:
The name of the fucntion block and The parameters The call is addressed either with an absolute or a symbolic name. Absolute Call: CALL FCx (pass parameters); x = block number Symbolic Call: CALL fcname (pass parameters); fcname = symbolic block name
Example
The following example shows the call of function FC80 with block parameters. In this example, the formal parameters have the following data types: INC1: BOOL INC2: INT OUT: WORD
STL
Explanation
CALL FC80 INC1:= M 1.0
Call FC80. INC1 (formal parameter) is supplied with M 1.0 (actual parameter). INC2 (formal parameter) is supplied with IW2 (actual parameter). OUT (formal parameter) is supplied with QW4 (actual parameter).
INC2:= IW2 OUT:=
QW4
Calling an FC That Delivers a Return Value
17-6
You can create a function (FC) that delivers a return value (RET_VAL). For example, if you want to create a floating-point math function, you can use this return value as an output for the result of your function. When you call this function in your program, you provide the output “RET_VAL” with a double word location to accommodate the 32-bit result of your floating-point math function.
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Program Control Instructions
17.3 Calling Functions and Function Blocks with CC and UC
Description
You can use the following instructions to call functions (FCs) and function blocks (FBs) that you have created for your program in the same way as using the Call instruction. Using these instructions, you cannot transfer parameters.
Conditional Call (CC): Calls the function or function block that you indicate as an address if the result of logic operation is 1.
Unconditional Call (UC): Calls the function or function block that you indicate as an address regardless of the result of logic operation or any other condition. It is not possible for function blocks which are called with either a CC or a UC instruction to have associated data blocks.
Addressing Format
A CC or UC instruction can call a function (FC) or a function block (FB) using direct or memory indirect addressing or via an FC or FB transferred as a parameter (see Tables 17-1 and 17-2). The address is FC plus the number of the FC. Table 17-1 FC or FB Part of Address FC FB
Table 17-2
Addresses of CC and UC Instructions: Direct and Indirect Addressing Maximum Range of Address Number according to Addressing Type Direct
0 to 65,535
Name of the formal parameter or a symbolic name
Example
[DBW] [DIW] [LW] [MW]
0 to 65,534
Addresses of CC and UC Instructions: FC Transferred as Parameter Address
1
Memory Indirect
Parameter Data Types BLOCK_FC 1 BLOCK_FB 1
Parameters of type BLOCK_FC or BLOCK_FB cannot be used with the CC command in FCs and FBs.
To call an FC that you had created and given the number 12, you would use one of the following instructions, depending on whether you want the call to be conditional or not: CC FC12 (Call FC12 if the RLO is 1.) UC FC12 (Call FC12 no matter what the RLO is.)
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17-7
Program Control Instructions
Assigning Actual Parameters
Table 17-3
Depending on the data type there are various ways to assign actual parameters to the formal parameters when you call a function or a function block. The following table is compiled according to the length of the data type.
Assigning Actual Parameters
Data Type of Formall Parameter F P t
BOOL (Bit)
Example of Assigning an Actual Parameter Direct Input (Value) TRUE
Input of a Shared Data Element M 100.0
Symbolic Input1 #OK_BIT
I 0.0 Q 0.0 DBX 3.0 BYTE (Byte)
B#16#1F
MB 100
#TYP_BYTE
IB 0 QB 0 CHAR
’K’
DBB 1
#TYP_CHAR
WORD (Word)
W#16#1F12
MW 100
#TYP_WORD
2#0001_1111_0001_0010
IW 0
C#32
QW 0
B#(5,25)
DBW 2
INT (Integer)
27
#TYP_INT
–25 S5TIME (S5 Time)
S5T#10MS
#TYP_S5_TIME
DATE (IEC Date)
D#1995–12–24
#TYP_DATE
DWORD (Double Word)
DW#16#FFFF_0F02
MD 100
2#0001_1111_0001_0010_0001 _1111_0001_0010
ID 0
B#(5,4,59,8)
#TYP_DWORD
QD 0 DBD 4
DINT (Double Integer)
L#170
REAL (FloatingPoint Number)
1.23
#TYP_REAL
TIME (IEC Time)
T#20MS
#TYP_TIME
TIME_OF_DAY (IEC Time-of-Day)
TOD#23:59:12.3
#TYP_TOD
17-8
#TYP_DINT
L#-350
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Program Control Instructions
Table 17-3
Assigning Actual Parameters, continued
Data Type of Formal Parameter
Example of Assigning an Actual Parameter Direct Input (Value)
DATE_AND_TIME (IEC Date and Time)
Not possible
ANY (Data type of any type and size)
P#M0.0 BYTE20
Input of a Shared Data Element
Symbolic Input1 #TYP_8_BYTE
(Variable must be declared, for example, temporary variable)
20 bytes 2 ... ... from bit memory 0.0 3
E 0.0
#TYP_ANYTYP
MB 5
(Declaration of arrays and structures)
AW 2
Prefix for ANY pointer
(Use of any STEP 7 shared addresses possible)
P#DB58.DBX16.0 BYTE14 14 bytes 2 ... ... in DB58 from data bit 16.0 3 Prefix for ANY pointer 1
2 3
Prerequisite: In the case of shared data, the name (= symbol) must be declared in the symbol table before it can be used as an actual parameter. In the case of local data, the name (= symbol) must be declared in the declaration table of the block before it can be used as an actual parameter. Local data symbols must be preceded by a hash #. Length specification can include elementary data types, for example BOOL, BYTE, WORD or DWORD or complex types, for example DATE_AND_TIME. Always enter a bit address; in length specifications enter 0 as the bit address (exception: BOOL).
Conditional Call in STL
In order to call an SFC conditionally, you can follow a sequence similar to the following:
STL
Explanation
A #OK_BIT_MEMORY JCNB m001 CALL SFC 28 OB_NO := 10 SDT := #OUT_TIME_DATE PERIOD := W#16#1201 RET_VAL := MW 200 m001: A BR = M 202.3
Condition for the call If the condition is not fulfilled (RLO=0), the call of the SFC is jumped and the RLO in the status bit is saved.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Check status bit BR
17-9
Program Control Instructions
17.4 Working with Master Control Relay Functions
Description
The Master Control Relay (MCR) is an American relay ladder logic master switch for energizing and de-energizing power flow (current path). A de-energized current path corresponds to an instruction sequence that writes a zero value instead of the calculated value, or, to an instruction sequence that leaves the existing memory value unchanged. Operations triggered by the following bit logic and transfer instructions are dependent on the MCR:
= S R T (used with byte, word, or double word) The T instruction used with byte, word, or double word, and the = instruction write a 0 to the memory if the MCR is 0. The S and R instructions leave the existing value unchanged. Table 17-4
Operations Dependent on MCR and How They React to Its Signal State
Signal State of MCR 0
1
17-10
=
S or R
T
Writes 0
Does not write
Writes 0
(Imitates a relay that falls to its quiet state when voltage is removed)
(Imitates a latching relay that remains in its current state when voltage is removed)
(Imitates a component that, on loss of voltage, produces a value of 0)
Normal execution
Normal execution
Normal execution
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Program Control Instructions
17.5 Master Control Relay Instructions
Overview
You can use the following statements to implement a master control relay:
Description: MCRA, MCRD
MCRA
Activate MCR Area
MCRD
Deactivate MCR Area
MCR(
Save RLO in MCR Stack, Begin MCR Area
)MCR
End MCR Area
The following instructions activate or deactivate an MCR area, that is, they specify which instructions in your program depend on the MCR (see also Figure 17-1):
Activate MCR Area: MCRA Deactivate MCR Area: MCRD The instructions that are programmed between the MCRA and the MCRD statements depend on the signal state of the MCR bit. The instructions that are programmed outside an MCRA-MCRD sequence do not depend on the signal state of the MCR bit. If an MCRD instruction is missing, the instructions programmed between an MCRA instruction and a BEU instruction depend on the MCR bit (see Figure 17-1). You must program the MCR dependency of functions (FCs) and function blocks (FBs) in the blocks themselves, that is, if such a function or function block is called from an MCRA-MCRD sequence, all the commands within that sequence are not automatically dependent on the MCR bit. To make the instructions in a called block dependent on the MCR bit, you must use the MCRA instruction in the block that is called.
!
Danger Never use the MCR instruction as an emergency off or personnel safety device.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
17-11
Program Control Instructions
ÀÀÀÀÀÀ ÀÀÀÀÀÀ ÀÀÀÀÀÀ ÀÀÀÀÀÀ ÀÀÀÀÀÀ ÀÀÀÀÀÀ OB1
MCRA
ÀÀÀÀÀÀ ÀÀÀÀÀÀ ÀÀÀÀÀÀ ÀÀÀÀÀÀ ÀÀÀÀÀÀ ÀÀÀÀÀÀ FBx
ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ FCy
MCRA
MCRA
ÀÀÀÀÀÀ ÀÀÀÀÀÀ ÀÀÀÀÀÀ ÀÀÀÀÀÀ ÀÀÀÀÀÀ MCRD
CALL FBx
MCRA
CALL FCy
ÀÀÀÀÀÀ ÀÀÀÀÀÀ ÀÀÀÀÀÀ MCRD
BEU
BEU
Instructions do not depend on the MCR bit Instructions depend on the MCR bit
Figure 17-1
17-12
Activating and Deactivating a Master Control Relay Area
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Program Control Instructions
Description: MCR(, )MCR
The following instructions turn the Master Control Relay function on and off:
Save RLO in MCR Stack, Begin MCR: MCR( End MCR: )MCR You can nest MCR( and )MCR instructions. The maximum nesting depth is eight, that is, you can have a maximum of eight MCR( instructions in sequence before you insert an )MCR instruction. You must program an equal number of MCR( and )MCR instructions (see Figure 17-3). When MCR( instructions are nested, the MCR bit of the deeper nesting levels is formed. To form this MCR bit, the MCR( instruction combines the current RLO with the current MCR bit according to the And truth table. The )MCR instruction terminates a nesting level by restoring the MCR bit from the higher level. The )MCR instruction of the highest level sets the MCR bit to 1. If you use MCR( and )MCR in your program, you must always use them in pairs.
Example
Figure 17-2 shows how to implement a Master Control Relay. If the MCR bit is 1, then the MCR contact is closed. The signal states of outputs Q 4.0 and Q 4.1 are calculated according to the signal state of inputs I 1.0 to I 1.3 and their logic combinations. If the MCR bit is 0, then the MCR contact is opened. The outputs Q 4.0 and Q 4.1 are reset to 0, regardless of the signal states of inputs I 1.0 to I 1.3.
STL
Relay Logic Diagram
MCRA A I 2.0 MCR( O I 1.0 O I 1.1 = Q 4.0 A I 1.2 A I 1.3 = Q 4.1 )MCR MCRD
Power rail
MCR contact
I 2.0
I 1.0
I 1.2 I 1.3
Q 4.0
Q 4.1
MCR coil Master Control Relay implemented with the MCR( and )MCR instructions
Figure 17-2
I 1.1
Area which is controlled by the MCR (Master Control Relay), implemented with MCRA and MCRD instructions
Implementation of a Master Control Relay
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
17-13
Program Control Instructions
Figure 17-3 shows the nesting application of the instructions.
STL
MCRA A I 1.1 MCR ( A I 1.2 MCR ( A I 1.3 MCR (
S M 1.0 )MCR
S M 1.1 )MCR
Signal State
Result of Check
RLO
1
1
1
1
1
1
0
0
0
MCR Bit of Level 1 2 3
1 1 1 1
*
0 0 0 0 0
This bit (M 1.0) remains unchanged regardless of any previous logic string because the MCR bit = 0. 1 1 1 1
This bit (M 1.1) is changed due to the previous logic string and the function of the S instruction because the MCR = 1.
**
1 1 1 1
)MCR MCRD
*
The MCR bit of the deeper nesting level is formed. To form this MCR bit, the MCR( instruction combines the current RLO with the MCR bit of the current nesting level according to the And truth table.
**
When the )MCR instruction ends a nesting level, the instruction restores the MCR bit of the next higher level.
Figure 17-3
17-14
Nesting Application of MCR Instructions
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Program Control Instructions
Important Notes on Using MCR Functions Take care with blocks in which the Master Control Relay was activated with MCRA:
If the MCR is deactivated, the value 0 is written by all assignments in program segments between (MCR).
The MCR is deactivated if the RLO was =0 before an (MCR, =, , =, , =, Accumulator 4, Accumulator 2 ---> Accumulator 3
4-3
EXP
EXP
Exponential Value of a Floating-Point Number (32-Bit IEEE FP) to Base E
FN
FN
Edge Negative
5-17
FP
FP
Edge Positive
5-16
FR
FR
Enable Counter (Free, FR C 0 to C 255)
6-5
FR
FR
Enable Timer (Free, FR T 0 to T 255)
7-3
INC
INC
Increment Accumulator 1
4-6
INVD
INVD
Ones Complement Double Integer (32-Bit)
12-14
INVI
INVI
Ones Complement Integer (16-Bit)
12-14
ITB
ITB
Integer (16-Bit) to BCD
12-5
ITD
ITD
Integer (16-Bit) to Double Integer (32-Bit)
12-6
L
L
Load
8-3
L
L
Load Length of Shared Data Block into Accumulator 1 (L DBLG)
8-12 15-2
L
L
Load Number of Shared Data Block into Accumulator 1 (L DBNO)
8-12
L
L
Load Length of Instance Data Block into Accumulator 1 (L DILG)
8-12 15-2
L
L
Load Number of Instance Data Block into Accumulator 1 (L DINO)
8-12 15-2
L
L
Load Status Word into Accumulator 1 (L STW)
8-6
L
L
Load Current Timer Value into Accumulator 1 as Integer (where the number of the current timer can be in the range of 0 to 255, for example: L T 32)
8-7
L
L
Load Current Counter Value into Accumulator 1 as Integer (where the number of the current counter can be in the range of 0 to 255, for example: L C 15)
7-6 8-8
LAR1
LAR1
Load Address Register 1 from Accumulator 1 (if no address is indicated)
8-11
LAR1
LAR1
Load Address Register 1 from ... (from address indicated)
8-11
LAR1
LAR1
Load Address Register 1 from Address Register 2 (LAR1 AR2)
8-11
LAR1
LAR1
Load Address Register 1 with Double Integer (32-Bit, LAR1 P#area byte.bit)
8-11
LAR2
LAR2
Load Address Register 2 from Accumulator 1 (if no address is indicated)
8-11
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
10-12
A-3
Alphabetical Listing of Instructions
Table A-1
Alphabetical Listing with the SIMATIC and the International Mnemonic Abbreviations, cont.
SIMATIC Abbreviation
International Abbreviation
Name
Page No.
LAR2
LAR2
Load Address Register 2 from ... (from address indicated)
8-11
LAR2
LAR2
Load Address Register 2 with Double Integer (32-Bit, LAR2 P#area byte.bit)
8-11
LC
LC
Load Current Counter Value into Accumulator 1 as BCD (where the number of the current counter can be in the range of 0 to 255, for example: LC C 15)
8-9
LC
LC
Load Current Timer Value into Accumulator 1 as BCD (where the number of the current timer can be in the range of 0 to 255, for example: LC T 32)
7-7 8-9
LEAVE
LEAVE
Accumulator 3 ---> Accumulator 2, Accumulator 4 ---> Accumulator 3
4-3
LN
LN
Natural Logarithm of a Floating-Point Number (32-Bit IEEE FP)
LOOP
LOOP
Loop
MCR(
MCR(
Save RLO in MCR Stack, Begin MCR
17-11
)MCR
MCR)
Restore RLO, End MCR
17-11
MCRA
MCRA
Activate MCR Area
17-11
MCRD
MCRD
Deactivate MCR Area
17-11
MOD
MOD
Division Remainder Double Integer (32-Bit)
9-5
NEGD
NEGD
Twos Complement Double Integer (32-Bit)
12-14
NEGI
NEGI
Twos Complement Integer (16-Bit)
12-14
NEGR
NEGR
Negate Real Number
12-14
NOP 0
NOP 0
Null Operation 0
NOP 1
NOP 1
Null Operation 1
4-2
NOT
NOT
Negate RLO
5-26
O
O
Or
5-10
O(
O(
Or with Nesting Open
5-14
OD
OD
Or Double Word (32-Bit)
13-6
ON
ON
Or Not
5-8
ON(
ON(
Or Not with Nesting Open
5-14
OW
OW
Or Word (16-Bit)
13-3
POP
POP
Accumulator 1 Accumulator 2
4-2
R
R
Reset
5-22
R
R
Reset Counter (where the current counter can have a number in the range of 0 to 255, for example: R C 15)
6-5
R
R
Reset Timer (where the current timer can have a number in the range of 0 to 255, for example: R T 32)
7-4
RLD
RLD
Rotate Left Double Word (32-Bit)
14-8
RLDA
RLDA
Rotate Accumulator 1 Left via CC 1 (32-Bit)
14-6
A-4
10-11 16-8
4-2
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Alphabetical Listing of Instructions
Table A-1
Alphabetical Listing with the SIMATIC and the International Mnemonic Abbreviations, cont.
SIMATIC Abbreviation
International Abbreviation
Name
Page No.
RND
RND
Round
RND+
RND+
Round to Upper Double Integer
12-10
RND-
RND-
Round to Lower Double Integer
12-11
RRD
RRD
Rotate Right Double Word (32-Bit)
14-8
RRDA
RRDA
Rotate Accumulator 1 Right via CC 1 (32-Bit)
14-6
S
S
Set
5-21
S
S
Set Counter Preset Value (where the current counter can have a number in the range of 0 to 255, for example: S C 15)
7-3
SA
SF
Off-Delay Timer
6-15
SAVE
SAVE
Save RLO in BR Register
5-26
SE
SD
On-Delay Timer
6-11
SET
SET
Set RLO (= 1)
5-26
SI
SP
Pulse Timer
6-7
SIN
SIN
Sine of a Floating-Point Number (32-Bit IEEE FP)
10-7
SLD
SLD
Shift Left Double Word (32-Bit)
14-2
SLW
SLW
Shift Left Word (16-Bit)
14-2
SPA
JU
Jump Unconditional
16-3
SPB
JC
Jump if RLO = 1
16-4
SPBB
JCB
Jump if RLO = 1 with BR
16-4
SPBI
JBI
Jump if BR = 1
16-4
SPBIN
JNBI
Jump if BR = 0
16-4
SPBN
JCN
Jump if RLO = 0
16-4
SPBNB
JNB
Jump if RLO = 0 with BR
16-4
SPL
JL
Jump to Labels
16-3
SPM
JM
Jump if Minus
16-6
SPMZ
JMZ
Jump if Minus or 0
16-6
SPN
JN
Jump if Not 0
16-6
SPO
JO
Jump if OV = 1
16-5
SPP
JP
Jump if Plus
16-6
SPPZ
JPZ
Jump if Plus or 0
16-6
SPS
JOS
Jump if OS = 1
16-5
SPU
JUO
Jump if Unordered
16-6
SPZ
JZ
Jump if 0
16-6
SQR
SQR
Square of a Floating-Point Number (32-Bit IEEE PF)
10-9
SQRT
SQRT
Square Root of a Floating-Point Number (32-Bit IEEE PF)
10-9
SRD
SRD
Shift Right Double Word (32-Bit)
14-3
SRW
SRW
Shift Right Word (16-Bit)
14-2
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
12-9
A-5
Alphabetical Listing of Instructions
Table A-1
Alphabetical Listing with the SIMATIC and the International Mnemonic Abbreviations, cont.
SIMATIC Abbreviation
International Abbreviation
Name
Page No.
SS
SS
Retentive On-Delay Timer
6-13
SSD
SSD
Shift Sign Double Integer (32-Bit)
14-4
SSI
SSI
Shift Sign Integer (16-Bit)
14-4
SV
SE
Extended Pulse Timer
6-9
T
T
Transfer
8-3
T
T
Transfer Accumulator 1 to Status Word (T STW)
8-6
TAD
CAD
Change Byte Sequence in Accumulator 1 (32-Bit)
12-13
TAK
TAK
Toggle Accumulator 1 with Accumulator 2
4-2
TAN
TAN
Tangent of a Floating-Point Number (32-Bit IEEE FP)
10-7
TAR
CAR
Exchange Address Register 1 with Address Register 2
8-11
TAR1
TAR1
Transfer Address Register 1 to Accumulator 1 (if no address is indicated)
8-11
TAR1
TAR1
Transfer Address Register 1 to ... (to address indicated)
8-11
TAR1
TAR1
Transfer Address Register 1 to Address Register 2 (T AR1 AR2)
8-11
TAR2
TAR2
Transfer Address Register 2 to Accumulator 1 (if no address is indicated)
8-11
TAR2
TAR2
Transfer Address Register 2 to ... (to address indicated)
8-11
TAW
CAW
Change Byte Sequence in Accumulator 1 (16-Bit)
TDB
CDB
Exchange Shared Data Block and Instance Data Block
TRUNC
TRUNC
Truncate
U
A
And
5-10
U(
A(
And with Nesting Open
5-14
UC
UC
Unconditional Call
17-7
UD
AD
And Double Word (32-Bit)
13-6
UN
AN
And Not
5-8
UN(
AN(
And Not with Nesting Open
5-14
UW
AW
And Word (16-Bit)
13-3
X
X
Exclusive Or
5-10
X(
X(
Exclusive Or with Nesting Open
5-14
XN
XN
Exclusive Or Not
5-8
XN(
XN(
Exclusive Or Not with Nesting Open
5-14
XOD
XOD
Exclusive Or Double Word (32-Bit)
13-6
XOW
XOW
Exclusive Or Word (16-Bit)
13-3
ZR
CD
Counter Down
7-5
ZV
CU
Counter Up
7-5
A-6
12-13 15-2 12-12
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Alphabetical Listing of Instructions
Table A-2 provides an alphabetical listing of the mnemonic abbreviations of the statement list instructions. Next to each international abbreviation are the equivalent (German) SIMATIC abbreviation, the full international name and the page on which the instruction is explained. Table A-2
Alphabetical Listing with the International and the SIMATIC Mnemonic Abbreviations
International Abbreviation
SIMATIC Abbreviation
Name
Page No.
+
+
Add Integer Constant (8, 16, 32-Bit)
15-6
=
=
Assign
11-24
)
)
Nesting Closed
11-14
+AR1
+AR1
Add Accumulator 1 to Address Register 1
10-7
+AR2
+AR2
Add Accumulator 1 to Address Register 2
10-7
+D
+D
Add Accumulator 1 and Accumulator 2 as Double Integer (32-Bit)
15-2
-D
-D
Subtract Accumulator 1 from Accumulator 2 as Double Integer (32-Bit)
15-2
*D
*D
Multiply Accumulator 1 by Accumulator 2 as Double Integer (32-Bit)
15-2
/D
/D
Divide Accumulator 2 by Accumulator 1 as Double Integer (32-Bit)
15-2
==D
==D
Compare Double Integer (32-Bit) >, =, , =, , =, Accumulator 4, Accumulator 2 ---> Accumulator 3
10-3
EXP
EXP
Exponential Value of a Floating-Point Number (32-Bit IEEE FP) to base E
16-12
FN
FN
Edge Negative
11-17
FP
FP
Edge Positive
11-16
FR
FR
Enable Counter (Free, FR C 0 to C 255)
12-5
FR
FR
Enable Timer (Free, FR T 0 to T 255)
13-3
INC
INC
Increment Accumulator 1
10-6
INVD
INVD
Ones Complement Double Integer (32-Bit)
18-14
INVI
INVI
Ones Complement Integer (16-Bit)
18-14
ITB
ITB
Integer (16-Bit) to BCD
18-5
ITD
ITD
Integer (16-Bit) to Double Integer
18-6
JBI
SPBI
Jump if BR = 1
22-4
JC
SPB
Jump if RLO = 1
22-4
JCB
SPBB
Jump if RLO = 1 with BR
22-4
JCN
SPBN
Jump if RLO = 0
22-4
JL
SPL
Jump to Labels
22-3
JM
SPM
Jump if Minus
22-6
JMZ
SPMZ
Jump if Minus or 0
22-6
JN
SPN
Jump if Not 0
22-6
JNB
SPBNB
Jump if RLO = 0 with BR
22-4
A-8
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Alphabetical Listing of Instructions
Table A-2
Alphabetical Listing with the International and the SIMATIC Mnemonic Abbreviations, cont.
International Abbreviation
SIMATIC Abbreviation
Name
Page No.
JNBI
SPBIN
Jump if BR = 0
22-4
JO
SPO
Jump if OV = 1
22-5
JOS
SPS
Jump if OS = 1
22-5
JP
SPP
Jump if Plus
22-5
JPZ
SPPZ
Jump if Plus or 0
22-6
JU
SPA
Jump Unconditional
22-3
JUO
SPU
Jump if Unordered
22-6
JZ
SPZ
Jump if 0
22-6
L
L
Load
14-3
L
L
Load Length of Shared Data Block into Accumulator 1 (L DBLG)
14-12 21-2
L
L
Load Number of Shared Data Block into Accumulator 1 (L DBNO)
14-12
L
L
Load Length of Instance Data Block into Accumulator 1 (L DILG)
14-12 21-2
L
L
Load Number of Instance Data Block into Accumulator 1 (L DINO)
14-12 21-2
L
L
Load Status Word into Accumulator 1 (L STW)
14-6
L
L
Load Current Timer Value into Accumulator 1 as Integer (where the number of the current timer can be in the range of 0 to 255, for example: L T 32)
14-7
L
L
Load Current Counter Value into Accumulator 1 as Integer (where the number of the current counter can be in the range of 0 to 255, for example: L C 15)
13-6 14-8
LAR1
LAR1
Load Address Register 1 from Accumulator 1 (if no address is indicated)
14-11
LAR1
LAR1
Load Address Register 1 from ... (from address indicated)
14-11
LAR1
LAR1
Load Address Register 1 from Address Register 2 (LAR1 AR2)
14-11
LAR1
LAR1
Load Address Register 1 with Double Integer (32-Bit, LAR1 P#area byte.bit)
14-11
LAR2
LAR2
Load Address Register 2 from Accumulator 1 (if no address is indicated)
14-11
LAR2
LAR2
Load Address Register 2 from ... (from address indicated)
14-11
LAR2
LAR2
Load Address Register 2 with Double Integer (32-Bit, LAR2 P#area byte.bit)
14-11
LC
LC
Load Current Counter Value into Accumulator 1 as BCD (where the number of the current counter can be in the range of 0 to 255, for example: LC C 15)
14-9
LC
LC
Load Current Timer Value into Accumulator 1 as BCD (where the number of the current timer can be in the range of 0 to 255, for example: LC T 32)
13-7 14-10
LEAVE
LEAVE
Accumulator 3 ---> Accumulator 2, Accumulator 4 ---> Accumulator 3
10-3
LN
LN
Natural Logarithm of a Floating-Point Number (32-Bit IEEE FP)
16-11
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
A-9
Alphabetical Listing of Instructions
Table A-2
Alphabetical Listing with the International and the SIMATIC Mnemonic Abbreviations, cont.
International Abbreviation
SIMATIC Abbreviation
Name
Page No.
LOOP
LOOP
Loop
22-8
MCR(
MCR(
Save RLO in MCR Stack, Begin MCR
23-11
MCR)
)MCR
Restore RLO, End MCR
23-11
MCRA
MCRA
Activate MCR Area
23-11
MCRD
MCRD
Deactivate MCR Area
23-11
MOD
MOD
Division Remainder Double Integer (32-Bit)
15-5
NEGD
NEGD
Twos Complement Double Integer (32-Bit)
18-14
NEGI
NEGI
Twos Complement Integer (16-Bit)
18-14
NEGR
NEGR
Negate Real Number (32-Bit IEEE FP)
18-14
NOP 0
NOP 0
Null Operation 0
10-2
NOP 1
NOP 1
Null Operation 1
10-2
NOT
NOT
Negate RLO
11-26
O
O
Or
11-10
O(
O(
Or with Nesting Open
11-14
OD
OD
Or Double Word (32-Bit)
19-6
ON
ON
Or Not
11-9
ON(
ON(
Or Not with Nesting Open
11-14
OPN
AUF
Open a Data Block
21-2
OW
OW
Or Word (16-Bit)
19-3
POP
POP
Accumulator 1 Accumulator 2
10-2
R
R
Reset
11-22
R
R
Reset Counter (where the current counter can have a number in the range of 0 to 255, for example: R C 15)
12-5
R
R
Reset Timer (where the current timer can have a number in the range of 0 to 255, for example: R T 32)
13-4
RLD
RLD
Rotate Left Double Word (32-Bit)
20-6
RLDA
RLDA
Rotate Accumulator 1 Left via CC 1 (32-Bit)
20-6
RND
RND
Round
18-9
RND+
RND+
Round to Upper Double Integer
18-10
RND-
RND-
Round to Lower Double Integer
18-11
RRD
RRD
Rotate Right Double Word (32-Bit)
20-8
RRDA
RRDA
Rotate Accumulator 1 Right via CC 1 (32-Bit)
20-6
S
S
Set
11-21
S
S
Set Counter Preset Value (where the current counter can have a number in the range of 0 to 255, for example: S C 15)
13-3
SAVE
SAVE
Save RLO in BR Register
11-26
A-10
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Alphabetical Listing of Instructions
Table A-2
Alphabetical Listing with the International and the SIMATIC Mnemonic Abbreviations, cont.
International Abbreviation
SIMATIC Abbreviation
Name
Page No.
SD
SE
On-Delay Timer
12-11
SE
SV
Extended Pulse Timer
12-9
SET
SET
Set RLO (= 1)
11-26
SF
SA
Off-Delay Timer
12-15
SIN
SIN
Sine of a Floating-Point Number (32-Bit IEEE FP)
16-7
SLD
SLD
Shift Left Double Word (32-Bit)
20-2
SLW
SLW
Shift Left Word (16-Bit)
20-2
SP
SI
Pulse Timer
12-7
SQR
SQR
Square of a Floating-Point Number (32-Bit IEEE PF)
16-9
SQRT
SQRT
Square Root of a Floating-Point Number (32-Bit IEEE PF)
16-9
SRD
SRD
Shift Right Double Word (32-Bit)
20-3
SRW
SRW
Shift Right Word (16-Bit)
20-2
SS
SS
Retentive On-Delay Timer
12-13
SSD
SSD
Shift Sign Double Integer (32-Bit)
20-4
SSI
SSI
Shift Sign Integer (16-Bit)
20-4
T
T
Transfer
14-3
T
T
Transfer Accumulator 1 to Status Word (T STW)
14-6
TAK
TAK
Toggle Accumulator 1 with Accumulator 2
10-2
TAN
TAN
Tangent of a Floating-Point Number (32-Bit IEEE FP)
16-7
TAR1
TAR1
Transfer Address Register 1 to Accumulator 1 (if no address is indicated)
14-11
TAR1
TAR1
Transfer Address Register 1 to ... (to address indicated)
14-11
TAR1
TAR1
Transfer Address Register 1 to Address Register 2 (T AR1 AR2)
14-11
TAR2
TAR2
Transfer Address Register 2 to Accumulator 1 (if no address is indicated)
14-11
TAR2
TAR2
Transfer Address Register 2 to ... (to address indicated)
14-11
TRUNC
TRUNC
Truncate
18-12
UC
UC
Unconditional Call
23-7
X
X
Exclusive Or
11-10
X(
X(
Exclusive Or with Nesting Open
11-14
XN
XN
Exclusive Or Not
11-9
XN(
XN(
Exclusive Or Not with Nesting Open
11-14
XOD
XOD
Exclusive Or Double Word (32-Bit)
19-6
XOW
XOW
Exclusive Or Word (16-Bit)
19-3
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
A-11
Alphabetical Listing of Instructions
A.2
Alphabetical Listing with International Names Table A-3 provides an alphabetical listing of the full international names of the statement list instructions. Next to each name is its international mnemonic abbreviation and the page on which the instruction is explained.
Table A-3
Statement List Instructions Arranged Alphabetically by International Full Name Name
Mnemonic Page No. Abbreviation
Absolute Value of a Real (32-Bit IEEE FP)
ABS
16-6
Accumulator 1 ---> Accumulator 2
PUSH
10-2
Accumulator 1 Accumulator 3
ENT
10-3
Accumulator 3 ---> Accumulator 4, Accumulator 2 ---> Accumulator 3, Accumulator 1 ---> Accumulator 2
PUSH
10-2
Activate MCR Area
MCRA
23-11
Add Accumulator 1 and Accumulator 2 as Double Integer (32-Bit)
+D
15-2
Add Accumulator 1 and Accumulator 2 as Integer (16-Bit)
+I
15-2
Add Accumulator 1 and Accumulator 2 as Real (32-Bit IEEE FP)
+R
16-2
Add Accumulator 1 to Address Register 1
+AR1
10-7
Add Accumulator 1 to Address Register 2
+AR2
10-7
Add Integer Constant (8, 16, 32-Bit)
+
15-6
And
A
11-10
And Double Word (32-Bit)
AD
19-6
And Not
AN
11-9
And Not with Nesting Open
AN(
11-14
And with Nesting Open
A(
11-14
And Word (16-Bit)
AW
19-3
Arc Cosine of a Floating-Point Number (32-Bit IEEE FP)
ACOS
16-7
Arc Sine of a Floating-Point Number (32-Bit IEEE FP)
ASIN
16-7
Arc Tangent of a Floating-Point Number (32-Bit IEEE FP)
ATAN
16-7
Assign
=
11-24
BCD to Double Integer (32-Bit)
BTD
18-4
BCD to Integer (16-Bit)
BTI
18-2
Block End Conditional
BEC
23-15
Block End Unconditional
BEU
23-15
Call
CALL
23-3
Change Byte Sequence in Accumulator 1 (16-Bit)
CAW
18-13
Change Byte Sequence in Accumulator 1 (32-Bit)
CAD
18-13
A-12
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Alphabetical Listing of Instructions
Table A-3
Statement List Instructions Arranged Alphabetically by International Full Name, continued Name
Mnemonic Page No. Abbreviation
Clear RLO (= 0)
CLR
11-26
Compare Double Integer (32-Bit) >, =, , =, , =, =I =
C 1 Q 4.0 C 1 Q 4.1 +50 C 1
Each pulse generated by photoelectric barrier 1 increases the count value of counter C 1 by one, thereby counting the number of packages going into the storage area. Each pulse generated by photoelectric barrier 2 decreases the count value of counter C 1 by one, thereby counting the packages that leave the storage area. If the count value is 0, the indicator lamp for “Storage area empty” comes on. If the count value is not 0, the indicator lamp for “Storage area not empty” comes on. If 50 is less than or equal to the count value, the indicator lamp for “Storage area 50% full” comes on.
Q 4.2 +90
If the count value is greater than or equal to 90, the indicator lamp for “Storage area 90% full” comes on.
Q 4.3 C 1 100
If the count value is greater than or equal to 100, the indicator lamp for “Storage area filled to capacity” comes on. (You could also use output Q 4.4 to lock conveyor belt 1.)
Q 4.4
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
B-11
Programming Examples
B.5
Integer Math Instructions
Solving a Math Problem
The following sample program (applicable for the S7-300 only) shows you how to use three integer math instructions, along with Load and Transfer, to produce the same result as the following equation: MD4 +
STL L L
IW0 DB5.DBW3
+15
I
L
MW2
/I
T
B-12
15
Explanation
+I
L
(IW0 ) DBW3) MW2
MD4
Load the value from input word IW0 into accumulator 1. Load the value from shared data word DBW3 of DB5 into accumulator 1. The old contents of accumulator 1 are shifted to accumulator 2. Add the contents of the low words of accumulators 1 and 2. The result is stored in the low word of accumulator 1. The contents of accumulator 2 and the high word of accumulator 1 remain unchanged. Load the constant value +15 into accumulator 1. The old contents of accumulator 1 are shifted to accumulator 2. Multiply the contents of the low word of accumulator 2 by the contents of the low word of accumulator 1. The result is stored in accumulator 1. The contents of accumulator 2 remain unchanged. Load the value from memory word MW2 into accumulator 1. The old contents of accumulator 1 are shifted to accumulator 2. Divide the contents of the low word of accumulator 2 by the contents of the low word of accumulator 1. The result is stored in accumulator 1. The contents of accumulator 2 remain unchanged. Transfer the final result to memory double word MD4. The contents of both accumulators remain unchanged.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Programming Examples
Figure B-7 shows the relationship of the program to the equation.
Accumulator 1
Accumulator 2
L
IW0
(IW0)
³
(Old contents)
L
DBW3
(DBW3) + ± (IW0) + (DBW3)
³
(IW0)
+I
L
+15
I
L
MW2
/I
T
MD4
15 ± [(IW0) + (DBW3)] 15
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
³
(IW0) + (DBW3)
(IW0) + (DBW3)
³
MW2 / ±
[(IW0) + (DBW3)] 15
(IW0 ) DBW3) MW2
15
(IW0 ) DBW3)
15
(IW0 ) DBW3) MW2
15
(IW0 ) DBW3)
15
MD4 +
Figure B-7
(IW0)
(IW0 ) DBW5) MW2
15
Relationship of Integer Math Statements to an Equation (S7-300)
B-13
Programming Examples
B.6
Word Logic Instructions
Heating an Oven
The operator of the oven shown in Figure B-8 starts the oven heating by pushing the start push button. The operator can set the length of time for heating by using the thumbwheel switches shown in the figure. The value that the operator sets indicates seconds in binary coded decimal (BCD) format. Table B-9 lists the components of the heating system and their corresponding absolute addresses used in the sample program that follows Figure B-8. Table B-9
Heating System Components and Corresponding Absolute Addresses System Component
Absolute Address in STL Program
Start push button
I 0.7
Thumbwheel for ones
I 1.0 to I 1.3
Thumbwheel for tens
I 1.4 to I 1.7
Thumbwheel for hundreds
I 0.0 to I 0.3
Heating starts
Q 4.0
Thumbwheels for setting BCD digits
ÎÎÎÎÎ ÎÎÎÎÎ
Oven
4 Heat Q 4.0
7....
...0
XXXX
0001
4
4
7... 1001
IB0
...0
Bits
0001
IW0
IB1
Bytes
Start push button I 0.7
Figure B-8
Using the Inputs and Outputs for the Time-Limited Heating Process
STL
Explanation
A T 1 = Q 4.0 BEC
If the timer is running, then turn on the heat.
L AW
IW0 W#16#0FFF
OW
W#16#2000
A SE BE
I 0.7 T 1
B-14
If the timer is running, then end processing here. This prevents timer T 1 from being restarted if the push button is pressed. Mask input bits I 0.4 through I 0.7 (that is, reset them to 0). The time value in seconds is in the low word of accumulator 1 in binary coded decimal format. Assign the time base as seconds in bits 12 and 13 of the low word of accumulator 1. Start timer T 1 as an extended pulse timer if the push button is pressed. End the program network.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
C
Source Files - Examples and Reserved Keywords
Definition
A keyword is a reserved identifier which cannot be used as a general identifier. To use a keyword as a global symbol it must be marked as scan cycle checkpoint (SCC). To use a keyword as a local symbol it must be marked with #.
Overview
Table C-1 lists all keywords reserved for STEP 7. Table C-1
Keywords Keywords
A
B
AB
BEGIN
AD
BIE
ANY
BLOCK_DB
AO
BLOCK_FB
AR1
BLOCK_FC
AR2
BLOCK_SDB
ARRAY
BOOL
AUTHOR
BYTE
AW
C
DATA_BLOCK
CALL
DATE
CHAR
DATE_AND_TIME
COUNTER
DB DBB DBD DBLG DBNO DBW DBX
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
C-1
Source Files – Examples and Reserved Keywords
Table C-1
Keywords, continued Keywords DI DIB DID DILG DINO DINT DIW DIX DT DWORD
E
FALSE
EB
FAMILY
ED
FB
END_Data_Block
FC
END_Function
FUNCTION
END_Function_Block
FUNCTION_BLOCK
END_Organization_Block END_Struct
I
END_System_Function
IB
END_System_Function_Block
ID
END_Type
INT
END_VAR
IW
EW
KA
L
KNOW_HOW_PROTECT
LB
KP
LD LW
C-2
M
NAME
MB
NETWORK
MD
NI
MW
NO
OB
PA
OF
PAB
ORGANIZATION_BLOCK
PAD
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Source Files – Examples and Reserved Keywords
Table C-1
Keywords, continued Keywords
OS
PAW
OV
PE PEB PED PEW PI PIB PID PIW PQ PQB PQD PQW POINTER
Q
READ_ONLY
QB
REAL
QD
RET_VAL
QW
S5T
T
S5TIME
TIME
SDB
TIME_OF_DAY
SFB
TIMER
SFC
TITLE
STANDARD
TOD
STRING
TRUE
STRUCT
TYPE
STW SYSTEM_FUNCTION SYSTEM_FUNCTION_BLOCK
UDT
VAR
UNLINKED
VAR_IN_OUT
UO
VAR_INPUT VAR_OUTPUT VAR_TEMP VERSION
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
C-3
Source Files – Examples and Reserved Keywords
Table C-1
Keywords, continued Keywords VOID
WORD
C-4
Z
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
D
References /30/
Getting Started: Working with STEP 7 V5.0
/70/
Manual: S7-300 Programmable Controller, Hardware and Installation
/71/
Reference Manual: S7-300, M7-300 Programmable Controllers Module Specifications
/72/
Instruction List: S7-300 Programmable Controller
/100/ Manual: S7-400/M7-400 Programmable Controllers, Hardware and Installation /101/ Reference Manual: S7-400/M7-400 Programmable Controllers Module Specifications /102/ Instruction List: S7-400 Programmable Controller /231/ Manual: Configuring Hardware and Communication Connections, STEP 7 V5.0 /233/ Reference Manual: Ladder Logic (LAD) for S7-300 and S7-400 Programming /234/ Manual: Programming with STEP 7 V5.0 /235/ Reference Manual: System Software for S7-300 and S7-400 System and Standard Functions /236/ Reference Manual: Function Block Diagram (FBD) for S7-300 and 400, Programming /250/ Manual: Structured Control Language (SCL) for S7-300/S7-400, Programming /251/ Manual: S7-GRAPH for S7-300 and S7-400, Programming Sequential Control Systems /252/ Manual: S7-HiGraph for S7-300 and S7-400, Programming State Graphs /253/ Manual: C Programming for S7-300 and S7-400, Writing C Programs /254/ Manual: Continuous Function Charts (CFC) for S7 and M7, Programming Continuous Function Charts /270/ Manual: S7-PDIAG for S7-300 and S7-400 “Configuring Process Diagnostics for LAD, STL, and FBD” /271/ Manual: NETPRO, “Configuring Networks” Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
D-1
References
/800/ DOCPRO Creating Wiring Diagrams (CD only) /801/ TeleService for S7, C7 and M7 Remote Maintenance for Automation Systems (CD only) /802/ PLC Simulation for S7-300 and S7-400 (CD only) /803/ Reference Manual: Standard Software for S7-300 and S7-400, STEP 7 Standard Functions, Part 2
D-2
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Glossary
A Absolute Addressing
In absolute addressing, the memory location of the address to be processed is given.
Accumulator
Accumulators are registers in the CPU which act as intermediate buffers for load, transfer, comparison, math, and conversion operations.
Actual Parameter
Actual parameters replace the formal parameters when function blocks (FBs) and functions (FCs) are called. Example: The formal parameter “Start” is replaced by the actual parameter “I3.6”.
Address
An address is part of a STEP 7 statement and specifies what the processor should execute the instruction on. Addresses can be absolute or symbolic.
Address Identifier
An address identifier is the part of the address which contains various data. The data can include elements such as a value itself (data object) or the size of a value with which the instruction can, for example, perform a logic operation. In the instruction statement “L IB10” IB is the address identifier (“I” indicates the memory input area and “B” indicates a byte in that area).
Address Register
The address register is part of the registers in the communication part of the CPU. They act as pointers for register indirect addressing (possible in STL).
Array
An array is a complex data type which consists of data elements of the same type. These data elements can be elementary or complex.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Glossary-1
Glossary
B Bit Result (BR)
The bit result is the link between bit and word-oriented processing. This is an efficient method to allow the binary interpretation of the result of a word instruction and to include it in a series of logic operations.
C Call Hierarchy
All blocks must be called first before they can be processed. The sequence and nesting of these calls within an organized block is called the call hierarchy.
Condition Codes CC 1 and CC 0
The CC 1 and CC 0 bits (condition codes) provide information on the following results or bits:
Result of a math operation Result of a comparison Result of a digital operation Bits that have been shifted out by a shift or rotate command CPU
A CPU (central processing unit) is the central module in a programmable controller in which the user program is stored and processed. It consists of an operating system, processing unit, and communication interfaces.
Current Path
Characteristic of the Ladder Logic programming language. Current paths contain contacts and coils. Complex elements (for example, math functions) can also be inserted into current paths in the form of “boxes.” Current paths are connected to power rails.
D Data Block (DB)
Glossary-2
Data blocks (DBs) are areas in a user program which store user data. There are shared data blocks which can be accessed by all logic blocks and there are instance data blocks which are associated with a certain function block (FB) call. In contrast to all other blocks, data blocks do not contain instructions.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Glossary
Data, Static
Static data are local data of a function block which are stored in the instance data block and, therefore, remain intact until the function block is processed again.
Data Type
A data type defines how the value of a variable or a constant should be used in the user program. In SIMATIC STEP 7 two data types are available to the user (IEC 1131–3):
Elementary data types Complex data types Data Type, Complex
Complex data types are created by the user with the data type declaration. They do not have their own name and cannot, therefore, be used again. They can either be arrays or structures. The data types STRING and DATE AND TIME are classed as complex data types.
Data Type, Elementary
Elementary data types are preset data types according to IEC 1131–3. Examples:
Data type “BOOL” defines a binary variable (“Bit”) Data type “INT” defines a 16-bit fixed-point variable.
Declaration
The declaration section is used for the declaration of the local data of a logic block when programming in the Text Editor.
Direct Addressing
In direct addressing, the address contains the memory location of a value which is to be used by the instruction. Example: The location Q4.0 defines bit 0 in byte 4 of the process-image output table.
F First Check Bit
First check of the result of logic operation.
Folder
Directory of the user interface of the SIMATIC Manager which can be opened and can hold other directories or objects.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Glossary-3
Glossary
Formal Parameter
A formal parameter is a placeholder for the actual parameter in logic blocks. In function blocks (FBs) and functions (FCs) the formal parameters are declared by the user, in system function blocks (SFBs) and system functions (SFCs) they are already available. When a block is called, formal parameters are assigned actual parameters, so the called block works with the current values. The formal parameters are classed as local data. They can be input, output, or in/out parameters.
Function (FC)
According to the International Electrotechnical Commission’s IEC 1131–3 standard, functions are logic blocks without a ‘memory’ (meaning they do not have static data). A function allows you to transfer parameters in the user program, which means they are suitable for programming frequently recurring, complex functions, such as calculations. Important: As a function has no memory, you must continue processing the calculated values directly after the function has been called.
Function Block (FB)
According to the International Electrotechnical Commission’s IEC 1131–3 standard, function blocks are logic blocks with a ‘memory’ (meaning they have static data). A function block allows you to transfer parameters in the user program, which means they are suitable for programming frequently recurring, complex functions, such as closed-loop control and operating mode selection. As a function block has a memory (instance data block), you can access its parameters (for example, outputs) at any time and at any point in the user program.
Function Block Diagram (FBD)
Function Block Diagram (FBD) is one of the programming languages in STEP 5 and STEP 7. FBD represents logic in the boxes familiar from Boolean algebra. In addition, complex functions (for example, math functions) can be represented in direct connection with the logic box. Programs created with FBD can also be translated into other programming languages (for example, Ladder Logic).
I Immediate Addressing
In immediate addressing, the address contains the value with which the instruction works. Example: L.27 means load constant 27 into accumulator.
Input, Incremental
Glossary-4
When a block is input incrementally, each line or element is checked immediately for errors (for example, syntax errors). If an error is detected, it is marked and must be corrected before programming is completed. Incremental input is possible in STL (Statement List), LAD (Ladder Logic), and FBD (Function Block Diagram).
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Glossary
Instance
An “instance” is the call of a function block. An instance data block is assigned to each call.
Instance Data Block (DB)
An instance data block stores the formal parameters and the static data of function blocks. An instance data block can be assigned to one function block call or a call hierarchy of function blocks.
Instruction
An instruction is part of a STEP 7 statement; it specifies what the processor should do.
K Keyword
Keywords are used when programming with source files to identify the start and end of a block and to select sections in the declaration section of blocks, the start of block comments and the start of titles.
L Ladder Logic (LAD)
Ladder Logic is a graphic programming language in STEP 5 and STEP 7. Its representation is standardized in compliance with DIN 19239 (international standard IEC 1131-1). Ladder Logic representation corresponds to the representation of relay ladder logic diagrams. In contrast to Statement List (STL), LAD has a restricted set of instructions.
Logic Block
Logic blocks are blocks within SIMATIC S7 that contain a part of the STEP 7 user program. In contrast, data blocks (DBs) only contain data. There are the following types of logic blocks: organization blocks (OBs), function blocks (FBs), functions (FCs), system function blocks (SFBs), and system functions (SFCs). Blocks are stored in the “Blocks” folder under the “S7 Program” folder.
Logic String
A logic string is that portion of a user program which begins with an FC bit that has a signal state of 0 and which ends when an instruction or event resets the FC bit to 0. When the CPU executes the first instruction in a logic string, the FC bit is set to 1. Certain instructions such as output instructions (for example, Set, Reset, or Assign) reset the FC bit to 0. See First Check Bit above.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Glossary-5
Glossary
M Master Control Relay
The Master Control Relay (MCR) is an American relay ladder logic master switch for energizing and de-energizing power flow (current path). A de-energized current path corresponds to an instruction sequence that writes a zero value instead of the calculated value, or, to an instruction sequence that leaves the existing memory value unchanged.
Memory Area
In SIMATIC S7 a CPU has three memory areas:
Load memory Work memory System memory Memory Indirect Addressing
A type of addressing in which the address of an instruction indicates the location of the value with which the instruction is to work.
Mnemonic Representation
Mnemonic representation is an abbreviated form for displaying the names of addresses and programming instructions in the program (for example, “I” stands for “input”). STEP 7 supports the international representation (based on the English language), and the SIMATIC representation (based on the German abbreviations of the instruction set and the SIMATIC addressing conventions).
N Nesting Stack
The nesting stack is a storage byte used by the nesting instructions A(, O(, X(, AN(, ON(, XN(. A total of eight bit logic instructions can be stacked.
Network
Networks subdivide LAD and FBD blocks into complete current paths and Statement List (STL) blocks into clear units.
O OR Bit
Glossary-6
The OR bit is needed if you perform a logical AND before OR operation. The OR bit shows these instructions that a previously executed AND function has supplied the value 1, thus forestalling the result of the logical OR operation. Any other bit-processing command resets the OR bit (see Section 5.4).
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Glossary
Overflow Bit
The status bit OV stands for overflow. An overflow can occur, for example, after a math operation.
P Pointer
You can use a pointer to identify the address of a variable. A pointer contains an identifier instead of a value. If you allocate an actual parameter type, you provide the memory address. With STEP 7 you can either enter the pointer in pointer format or simply as an identifier (for example, M 50.0). In the following example, the pointer format is shown with which data from M 50.0 is accessed: P#M50.0
Project
A project is a folder for all objects in an automation task, irrespective of the number of stations, modules, and how they are connected in networks.
R Reference Data
Reference data are used to check your S7 program and include the cross-reference list, the assignment lists, the program structure, the list of unused addresses, and the list of addresses without symbols.
Register Indirect Addressing
A type of addressing in which the address of an instruction indicates indirectly via an address register and an offset the memory location of the value with which the instruction is to work.
Result of Logic Operation (RLO)
The result of logic operation (RLO) is the result of the logic string which is used to process other binary signals. The execution of certain instructions depends entirely on their preceding RLO.
S S7 Program
A folder for blocks, source files, and charts for S7 programmable controllers. The S7 program also includes the symbol table.
Shared Data Block (DB)
A shared data block is a DB whose address is loaded in the DB address register when it is opened. It provides storage and data for all logic blocks (FCs, FBs, or OBs) that are being executed.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Glossary-7
Glossary
In contrast, an instance DB is designed to be used as specific storage and data for the FB with which it has been associated.
SIMATIC Manager
The SIMATIC Manager is the graphical user interface for SIMATIC users under Windows 95.
Source File
A source file (text file) is part of a program created either with a graphic or a text-oriented editor and is compiled into an executable S7 user program or the machine code for M7. An S7 source file is stored in the “Sources” folder under the “S7 program” folder.
Statement
A statement is the smallest independent part of a user program created in a textual language. The statement represents a command for the processor.
Statement List (STL)
Statement List (STL) is a textual representation of the STEP 7 programming language, similar to machine code. STL is the assembler language of STEP 5 and STEP 7. If you program in STL, the individual statements represent the actual steps in which the CPU executes the program.
Station
A station is a device which can be connected to one or more subnets; for example, the programmable controller, programming device, and operator station.
Status Bit
The status bit stores the value of a bit that is referenced. The status of a bit instruction that has read access to the memory (A, AN, O, ON, X, XN) is always the same as the value of the bit that this instruction checks (the bit on which it performs its logic operation). The status of a bit instruction that has write access to the memory (S, R, =) is the same as the value of the bit to which the instruction writes or, if no writing takes place, the same as the value of the bit that the instruction references. The status bit has no significance for bit instructions that do not access the memory. Such instructions set the status bit to 1 (STA=1). The status bit is not checked by an instruction. It is interpreted during program test (program status) only.
Status Word
The status word is part of the register of the CPU. It contains status information and error information which is displayed when specific STEP 7 commands are executed. The status bits can be read and written on by the user, the error bits can only be read.
STL Source File
A source file programmed in Statement List; corresponds to a source or text file.
Glossary-8
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Glossary
Stored Overflow Bit
The status bit OS stands for “stored overflow bit of the status word”. An overflow can take place, for example, after a math operation.
Symbol
A symbol is a name which can be defined by the user subject to syntax guidelines. After it has been declared (for example, as a variable, data type, jump label, block etc) the symbol can be used for programming and for operator interface functions. Example: Address: I 5.0, data type: BOOL, Symbol: momentary contact switch / emergency stop.
Symbol Table
A table in which the symbols of addresses for shared data and blocks are allocated. Examples: Emergency Stop (symbol) -I 1.7 (address) or closed-loop control (symbol) - SFB24 (block).
Symbolic Addressing
In symbolic addressing, the address being processed is designated with a symbol (as opposed to an absolute address).
System Function (SFC)
A system function is a function (without a memory) that is integrated in the S7 operating system and can, if necessary, be called from the STEP 7 user program like a function (FC).
System Function Block (SFB)
A system function block (SFB) is a function (with a memory) that is integrated in the S7 operating system and can, if necessary, be called from the STEP 7 user program like a function block (FB).
U User Data Types (UDTs)
User data types are special data structures which you can create yourself and use in the entire user program after they have been defined. They can be used like elementary or complex data types in the variable declaration of logic blocks (FCs, FBs, OBs) or as a template for creating data blocks with the same data structure.
User Program
The user program contains all the statements and declarations and all the data for signal processing which can be used to control a device or a process. It is part of a programmable module (CPU, FM) and can be structured with smaller units (blocks).
User Program Structure
The user program structure describes the call hierarchy of the blocks within an S7 program and provides an overview of the blocks used and their dependency.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Glossary-9
Glossary
V Variable Declaration
The variable declaration includes a symbolic name, a data type and, optionally, an initial value, an address and a comment.
Variable Declaration Table
The variable declaration table is used for declaring the local data of a logic block, when programming takes place in the Incremental Editor.
Variable Table (VAT)
The variable table is used to collect together the variables that you want to monitor and modify and set their relevant formats.
Glossary-10
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Index Symbols )MCR. See Restore RLO, End MCR instruction +. See Instructions, integer math, adding an integer to accumulator 1 +I. See Four-function math, Adding two 16-bit integers; Instructions, integer math, adding two 16-bit integers +R. See Floating-point math, Adding two floating-point numbers =. See Assign (=) instruction
A ABS. See Absolute value, forming the absolute value of a real (floating–point ) number Absolute addressing, practical application, B-4 Absolute value definition of, 10-6 forming the absolute value of a real (floating-point) number, 10-6 Accumulator 1 to Accumulator 2 (PUSH), 4-2 Accumulator 2 to Accumulator 1 (POP), 4-2 Accumulator operations and address register instructions, 4-2–4-6 Accumulator 1 to Accumulator 2 (PUSH), 4-2 Accumulator 2 to Accumulator 1 (POP), 4-2 Decrement Accumulator 1 (DEC), 4-6 Decrement Accumulator 1 (DEC), 4-6 Increment Accumulator 1 (INC), 4-6 Increment Accumulator 1 (INC), 4-6 Toggle ACCU 1 with ACCU 2, 4-2
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Accumulators adding a constant to an address register, 4-7 adding an integer to accumulator 1, 9-6 description of, 2-10 functions Accumulator 2 to Accumulator 1 (POP), 4-2 Decrement Accumulator 1 (DEC), 4-6 Increment Accumulator 1 (INC), 4-6 handling the contents of, 4-2–4-6 information interchange using Load and Transfer instructions, 8-2 loading the status word into, 8-6 operation of, 2-10 with comparison instructions, 11-2 with floating-point math instructions, 10-2–10-3 with integer math instructions, 9-2–9-3 with Load and Transfer instructions, 8-2 with word logic instructions, 13-2, 13-3, 13-6 operations Accumulator 1 to Accumulator 2 (PUSH), 4-2 Decrement Accumulator 1 (DEC), 4-6 Increment Accumulator 1 (INC), 4-6 reversing the order of bytes within accumulator 1 Change Byte Sequence in Accumulator 1, 16 bits (CAW) instruction, 12-13 Change Byte Sequence in Accumulator 1, 32 bits (CAD) instruction, 12-13 time value in, 6-4 Toggle ACCU 1 with ACCU 2, 4-2 Toggle the contents of, 4-2 transferring the contents of to the status word, 8-6
Index-1
Index
ACOS. See Secant Activate MCR Area (MCRA) instruction, 17-11–17-12 Actual parameter, 17-2, 17-3 Actual parameters, assignment, 17-8 AD. See And Double Word instruction Address assigning addresses to a Call (CALL) instruction, 17-3 bits of the status word as, 5-13 constants as, 13-2 description of, 2-2 label for a jump instruction, 16-2 label for a loop instruction, 16-2 of instructions Assign (=), 5-25 Conditional Call (CC), 17-7 counter, 7-10 Edge Negative (FN), 5-19 Edge Positive (FP), 5-19 Load (L) and Transfer (T), 8-3–8-5 Open a Data Block (OPN), 15-2 Reset (R), 5-23 Set (S), 5-23 Timer, 6-17 Unconditional Call (UC), 17-7 symbolic, 17-3 types address identifier and location, 2-5–2-6 constants, 2-3, 13-2 data block, 2-4 function (FC), 2-5 function block (FB), 2-5 location in status word, 2-3 symbolic, 2-4 system function (SFC), 2-5 system function block (SFB), 2-5 Address register, adding a real number to an address register, 4-7 Address registers, 3-6 loading and transferring between, 8-11–8-12
Index-2
Addressing absolute, 17-3, B-4 area-crossing register indirect, 3-11–3-14 area-internal register indirect, 3-7–3-9 constants, 2-3 direct, 3-2 immediate, 3-2 memory indirect, 3-3–3-5 pointer format area-crossing register indirect, 3-13–3-14 area-internal register indirect, 3-8 area–internal register indirect, 3-9–3-10 memory indirect, 3-4–3-5 ranges, 2-9 symbolic, 2-4, 17-3, B-3 And (A), using counters as bit operands, 7-2 And (A) instruction, 5-3 And before Or, 5-15–5-16 And Double Word (AD) instruction, 13-7–13-8 And Not (AN), using counters as bit operands, 7-2 And Not (AN) instruction, 5-3 And Word (AW) instruction, 13-4–13-5 combining accumulator and constant, 13-4–13-5 ANY, 17-9 Arc cosine (ACOS), 10-13–10-15 Arc sine (ASIN), 10-13–10-14 Arc tangent (ATAN), 10-13 Area-crossing register indirect addressing, 3-11–3-15 Area-internal register indirect addressing, 3-7–3-9 Areas of memory address ranges, 2-9 bit memory, 2-8 counter, 2-8 data block, 2-8 I/O (external I/O), 2-8 local data, 2-8 peripheral I/O. See Areas of memory, I/O (external I/O) process image input, 2-8 process image output, 2-8 timer, 2-8 ASIN. See Cosecant Assign (=) instruction, 5-20, 5-24–5-25 Assigning addresses to a Call (CALL) instruction, 17-3 ATAN. See Cotangent AW. See And Word instruction
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Index
B BCD to Double Integer (BTD) conversion instruction, 12-4 BCD to Integer (BTI) conversion instruction, 12-3–12-4 BCDF. See Errors, binary coded decimal conversion BEC. See Blocks, ending: Block End Conditional instruction Beginning a logic string, 2-12–2-13 BEU. See Blocks, ending: Block End Unconditional instruction Binary coded decimal (BCD) format loading a count in, 8-10 loading a time in, 8-9 Binary coded decimal (BCD) numbers converting, 12-2–12-9 structure of a BCD number converted from a 32-bit integer, 12-6 structure of a BCD number to be converted from integer, 12-5 structure of a BCD number to be converted to integer, 12-3 structure of a32-bit BCD number to be converted to double integer, 12-4 Binary result (BR), bit of status word, 2-16 Bit logic instructions, And (A), using counters as Boolean operands, 7-2 Bit logic Boolean, 5-2–5-12 practical applications, B-3–B-6
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Bit logic instructions, 5-2–5-5 And Not (AN), using counters as Boolean operands, 7-2 Assign (=), 5-20, 5-24–5-25 Clear RLO (CLR), 5-26–5-27 Edge Negative (FN), 5-16–5-19 Edge Positive (FP), 5-16–5-19 Exclusive Or (X), using counters as Boolean operands, 7-2 Exclusive Or Not (XN), using counters as Boolean operands, 7-2 Negate RLO (NOT), 5-26 Or (O), using counters as Boolean operands, 7-2 Or Not (ON), using counters as Boolean operands, 7-2 practical applications, B-3–B-6 Reset (R), 5-20, 5-21–5-23, 7-8–7-9 counter, 7-4 timer, 6-6 Save RLO in BR Register (SAVE), 5-26 Set (S), 5-20, 5-21–5-23 counter, 7-3, 7-8–7-9 Set RLO (SET), 5-26, 5-27 using counters as bit operands, 7-2 Bit memory area of memory, 2-8 address ranges, 2-9 Blocks, ending Block End Conditional (BEC) instruction, 17-16 Block End Unconditional (BEU) instruction, 17-16 Boolean bit logic, 5-2–5-12 And (A) instruction, 5-3 And Not (AN) instruction, 5-3 checking condition codes (CC 1 and CC 0), 2-14–2-15 checking for overflow, 5-12–5-13 nesting expressions, 5-14–5-15 output of logic string, 5-20 BR. See Binary result BTD. See BCD to Double Integer conversion instruction BTI. See BCD to Integer conversion instruction
Index-3
Index
C CAD. See Change Byte Sequence in Accumulator 1 conversion instruction, 32 bits CALL. See Call instruction Call instruction, 17-3–17-5 Calling a function that delivers a return value, 17-6 Calling a program segment multiple times, 16-8 CAW. See Change Byte Sequence in Accumulator 1 conversion instruction, 16 bits CC. See Conditional Call instruction CC 1 and CC 0. See Condition codes CD. See Count Down instruction CDB. See Exchange Shared DB and Instance DB instruction Change Byte Sequence in Accumulator 1 conversion instruction 16 bits (CAW), 12-13 32 bits (CAD), 12-13 Checking condition codes (CC 1 and CC 0), 2-14–2-15 Clearing RLO (CRL) instruction, 5-26–5-27 the result of logic operation, 5-26–5-27 CLR. See Clear RLO instruction Comparing two integers, 11-3–11-5 two real numbers, 11-5–11-6 Comparison instructions, 11-2–11-3 Compare Double Integer, 11-3–11-5 Compare Integer, 11-3–11-5 Compare Real Number, 11-5 criteria for comparisons, 11-2 operation of accumulators, 11-2 practical applications, B-10–B-11 Complements, forming, 12-14
Index-4
Condition codes (CC 1 and CC 0) as affected by Compare instructions, 11-4, 11-5 as affected by floating-point math instructions, 10-4 as affected by integer math instructions, 9-4 as affected by the shift and rotate instructions, 14-2 as affected by word logic instructions, 13-2 bits of status word, 2-14–2-15 instructions that evaluate CC 1 and CC 0, 11-6 relationship to conditional jump instructions, 16-6 Conditional Call (CC) instruction, 17-7 Conditional jump instructions Jump If BR = 0 (JNBI), 16-5 Jump If BR = 1 (JBI), 16-5 Jump If Minus (JM), 16-6 Jump If Minus or Zero (JMZ), 16-6 Jump If Not Zero (JN), 16-6 Jump If OS = 1 (JOS), 16-5 Jump If OV = 1 (JO), 16-5 Jump If Plus (JP), 16-6 Jump If Plus or Zero (JPZ), 16-6, 16-7 Jump If RLO = 0 (JCN), 16-4 Jump If RLO = 0 with BR (JNB), 16-4 Jump If RLO = 1 (JC), 16-4 Jump If RLO = 1 with BR (JCB), 16-4 Jump If Unordered (JUO), 16-6 Jump If Zero (JZ), 16-6 relationship of condition codes CC 1 and CC 0, 16-6
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Index
Constants adding an integer constant to accumulator 1, 9-6 as addresses of word logic instructions, 13-2, 13-4–13-7 Decrement Accumulator 1 by an 8-bit constant, 4-6 Decrementing Accumulator 1 by an 8-bit constant, 4-6 Incrementing Accumulator 1 by an 8-bit constant, 4-6 used as address, 2-3 Conversion instructions BCD to Double Integer (BTD), 12-4 BCD to Integer (BTI), 12-3–12-4 Change Byte Sequence in Accumulator 1 16 bits (CAW), 12-13 32 bits (CAD), 12-13 Double Integer to BCD (DTB), 12-6 Double Integer to Real (DTR), 12-7 Integer to BCD (ITB), 12-5 Integer to Double Integer (ITD), 12-6 Negate Real Number (NEGR), 12-14–12-15 Ones Complement Double Integer (INVD), 12-14 Ones Complement Integer (INVI), 12-14 overview of number conversion and rounding, 12-12 Round (RND), 12-9 Round to Lower Double Integer (RND–), 12-11 Round to Upper Double Integer (RND+), 12-10 Truncate (TRUNC), 12-12 Twos Complement Double Integer (NEGD), 12-14 Twos Complement Integer (NEGI), 12-14–12-15 Converting 32-bit floating-point numbers to 32-bit integers, 12-8–12-12 binary coded decimal numbers and integers, 12-2–12-9 numbers, 12-12 COS. See Cosine Cosine (COS), 10-13 Count Down (CD) instruction, 7-5 Count Up (CU) instruction, 7-5 Count value, format, 7-6–7-7
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Counters area of memory, 2-8 address ranges, 2-9 components, 7-2 count instructions, bit logic instructions, 7-2 count value, format, 7-6–7-7 definition of, 7-2 enabling, 7-4, 7-8–7-9 instructions used with counters, 7-2–7-9 bit logic, 5-22–5-23, 7-2 Count Down (CD), 7-2, 7-5 Count Up (CU), 7-2, 7-5 Enable (FR), 7-2, 7-4 Load Current Counter Value into Accumulator 1 as Binary Coded Decimal (LC), 7-2, 8-10 Load Current Counter Value into Accumulator 1 as Integer, 7-2 practical applications, B-10–B-11 Reset (R), 7-2, 7-4, 7-8–7-9 Set (S), 7-2, 7-3, 7-8–7-9 resetting, 7-2, 7-4, 7-8–7-9 setting, 7-2, 7-3, 7-8–7-9 types Count Down (CD), 7-2, 7-8–7-9 Count Up (CU), 7-2, 7-8–7-9 CPU, registers, 3-6–3-11 nesting stack, 2-10 operation of accumulators, 2-10 pointers, 3-6 status word, 2-12–2-16 time value in accumulator 1, 6-4 CU. See Count Up instruction
Index-5
Index
D Data block (DB) area of memory, 2-8 address ranges, 2-9 instance, 17-3 lengths and numbers, loading, 15-3–15-4 loading the length of a shared data block into accumulator 1 (L DBLG), 8-12, 15-3 loading the length of an instance data block into accumulator 1 (L DILG), 8-12, 15-3 loading the number of a shared data block into accumulator 1 (L DBNO), 8-12, 15-3–15-4 loading the number of an instance data block into accumulator 1 (L DINO), 8-12, 15-3 registers, exchanging, 15-2 Data block (DB) instructions Exchange Shared DB and Instance DB (CDB), 15-2 Load Length of Instance Data Block in Accumulator 1 (DILG), 15-3 Load Length of Shared Data Block in Accumulator 1 (DBLG), 15-3 Load Number of Instance Data Block in Accumulator 1 (DINO), 15-3 Load Number of Shared Data Block in Accumulator 1 (DBNO), 15-3–15-4 Open a Data Block (OPN), 15-2 Data types ANY, 17-9 for actual and formal parameters, 17-3 DBLG. See Load Length of Shared DB in Accumulator 1 instruction DBNO. See Load Number of Shared DB in Accumulator 1 instruction Deactivate MCR Area (MCRD) instruction, 17-11–17-12 DEC. See Decrement Accumulator 1 Decrement Accumulator 1 (DEC), 4-6 DILG. See Load Length of Instance DB in Accumulator 1 instruction DINO. See Load Number of Instance DB in Accumulator 1 instruction Direct addressing, 3-2 Double Integer to BCD (DTB) conversion instruction, 12-6 Double Integer to Real (DTR) conversion instruction, 12-7 Double integers, comparing two, 11-3–11-5 DTB. See Double Integer to BCD conversion instruction
Index-6
DTR. See Double Integer to Real conversion instruction
E Edge Negative (FN) instruction, 5-16–5-19 Edge Positive (FP) instruction, 5-16–5-19 Enable (FR) instruction counters, 7-4, 7-8–7-9 timers, 6-6 Enable output (ENO). See Binary result Ending blocks Block End Conditional (BEC) instruction, 17-16 Block End Unconditional (BEU) instruction, 17-16 Errors, binary coded decimal conversion (BCDF), 12-3, 12-4 Examples, practical applications of instructions, B-2–B-14 Exchange Shared DB and Instance DB (CDB) instruction, 15-2 Exchange the contents of accumulators, 4-2 Exclusive Or (X), using counters as Boolean operands, 7-2 Exclusive Or Not (XN), using counters as Boolean operands, 7-2 Exclusive Or Word (XOW) instruction, 13-3, 13-4–13-5 combining accumulator and constant, 13-4–13-5 EXP. See Exponential value to base E Exponential value to base E, EXP, 10-12 Extended Pulse Timer (SE), 6-5, 6-9–6-10
F FBs. See Function blocks FCs. See Functions First check (FC) bit of status word, 2-12–2-13 result of, 2-12
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Index
Floating-point math Adding two floating-point numbers (+R), 10-3, 10-4 instructions forming the absolute value of a real number (ABS), 10-6 overview of four-function math, 10-2 relationship to accumulators, 10-2–10-3 valid ranges of result, 10-4 Floating-point math, extended operations arc cosine (ACOS), 10-13–10-15 arc tangent (ATAN), 10-13 Floating-point math, extended math operations, arc sine (ASIN), 10-13–10-14 FN. See Edge Negative instruction Formal parameter, 17-2 Formal parameters, 17-3 Format count value, 7-6–7-7 time value, 6-4 Forming complements, 12-14 Four-function math, Adding two 16-bit integers (+I), 9-3 FP. See Edge Positive instruction FR. See Enable instruction Function (FC) as address of an instruction, 2-5 calling FCs with the Call (CALL) instruction, 17-3–17-5 calling FCs with the Conditional Call (CC) instruction, 17-7 calling FCs with the Unconditional Call (UC) instruction, 17-7 dependency on Master Control Relay (MCR), 17-11 Function block (FB) as address of an instruction, 2-5 calling FBs with the Call (CALL) instruction, 17-3–17-5 calling FBs with the Conditional Call (CC) instruction, 17-7 calling FBs with the Unconditional Call (UC) instruction, 17-7 dependency on Master Control Relay (MCR), 17-11
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
I I/O (external I/O) area of memory, 2-8 address ranges, 2-9 Image registers. See Process-image Immediate addessing, 3-2 INC. See Increment Accumulator 1 Increment Accumulator 1 (INC), 4-6 Instruction statement addressing constants, 2-3 symbolic, 2-4 structure of, 2-2–2-7 Instructions accumulator operation and address register, 4-2–4-6 alphabetical listing, international names, A-12–A-16 bit logic, practical applications, B-3–B-6 comparison, 11-2–11-8 criteria for comparison, 11-2 operation of accumulators, 11-2 practical applications, B-10–B-11 conversion, overview of number conversion and rounding, 12-12 counter, 7-2–7-13 practical applications, B-10–B-11 dependent on the Master Control Relay (MCR), 17-11 dependent on the Master control Relay (MCR), 17-10 floating-point math overview of four-function math, 10-2 relationship to accumulators, 10-2–10-3 valid ranges of results, 10-4 integer math overview of four-function math instructions, 9-2 practical applications, B-12–B-13 relationship to accumulators, 9-2–9-3 valid ranges of results, 9-4 jump, unconditional, 16-3–16-4 Load (L) and Transfer (T), 8-2–8-12 area-crossing indirect addressing, 8-5
Index-7
Index
byte, word, or double word as address, 8-5 definition of, 8-2 direct addressing, 8-4 immediate addressing, 8-3 indirect addressing, 8-4 information interchange, 8-2 loading and transferring between address registers (LAR and TAR), 8-11–8-12 loading bits of the status word into accumulator 1, 8-6 loading the status word into accumulator 1, 8-6 transferring the contents of accumulator 1 to the status word, 8-6 loading and transferring between address registers (LAR and TAR), 8-11–8-12 logic control, 16-2–16-11 See also Jump instructions Loop (LOOP), 16-8 providing a label as address, 16-8 using efficiently, 16-9 practical applications, B-2–B-14 program control, assigning addresses to a call, 17-3 rotate, 14-6–14-8 shift, 14-2–14-6 signed numbers, 14-4 unsigned numbers, 14-2–14-3 shift and rotate, 14-2–14-6 that evaluate the condition codes (CC 1 and CC 0), 9-4, 10-4 that evaluate the overflow bit (OV) of the status word, 9-4, 10-4 that evaluate the stored overflow bit (OS) of the status word, 9-4, 10-4 timer, 6-2–6-17 practical applications, B-7–B-10 Transfer (T). See Load (L) and Transfer (T) instructions word logic, 13-2–13-8 16-bit, 13-3–13-8 32-bit, 13-6–13-8 accumulator administration, 13-2, 13-3, 13-6 constants as addresses, 13-2 influence on status word bits, 13-2 practical applications, B-14 Instructions that affect the status word, 5-10 Integer math, adding a real to an address register, 4-7
Index-8
Integer math instructions adding an integer constant to accumulator 1, 9-6 adding two 16-bit integers (+I), 9-3 overview of four-function math instructions, 9-2 practical applications, B-12–B-13 relationship to accumulators, 9-2–9-3 valid ranges of results, 9-4 Integer to BCD (ITB) conversion instruction, 12-5 Integer to Double Integer (ITD) conversion instruction, 12-6 Integers adding to accumulator 1, 9-6 comparing two, 11-3–11-5 converting, 12-2–12-9 International names for instructions, alphabetical listing, A-12–A-16 International names of the statement list (STL) instructions, A-12 INVD. See Ones Complement Double Integer conversion instruction Inverting numbers bit by bit, 12-14 INVI. See Ones Complement Integer conversion instruction ITB. See Integer to BCD conversion instruction ITD. See Integer to Double Integer conversion instruction
J JBI. See Jump If BR = 1 instruction JC. See Jump If RLO = 1 instruction JCB. See Jump If RLO = 1 with BR instruction JCN. See Jump If RLO = 0 instruction JL. See Jump to List instruction JM. See Jump If Minus instruction JMZ. See Jump If Minus or Zero instruction JN. See Jump If Not Zero instruction JNB. See Jump If RLO = 0 with BR instruction JNBI. See Jump If BR = 0 instruction JO. See Jump If OV = 1 instruction JOS. See Jump If OS = 1 instruction JP. See Jump If Plus instruction JPZ. See Jump If Plus or Zero instruction JU. See Jump Unconditional instruction Jump If BR = 0 (JNBI) instruction, 16-5 Jump If BR = 1 (JBI) instruction, 16-5 Jump If Minus (JM) instruction, 16-6
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Index
Jump If Minus or Zero (JMZ) instruction, 16-6 Jump If Not Zero (JN) instruction, 16-6 Jump If OS = 1 (JOS) instruction, 16-5 Jump If OV = 1 (JO) instruction, 16-5 Jump If Plus (JP) instruction, 16-6 Jump If Plus or Zero (JPZ) instruction, 16-6, 16-7 Jump If RLO = 0 (JCN) instruction, 16-4 Jump If RLO = 0 with BR (JNB) instruction, 16-4 Jump If RLO = 1 (JC) instruction, 16-4 Jump If RLO = 1 with BR (JCB) instruction, 16-4 Jump If Unordered (JUO) instruction, 16-6 Jump If Zero (JZ) instruction, 16-6 Jump instructions, 16-3–16-10 condition based on BR, OV, or OS bit of status word, 16-5 condition based on result in condition code bits (CC 1 and CC 0) of status word, 16-6–16-7 condition based on result of logic operation (RLO), 16-4–16-5 conditional Jump If BR = 0 (JNBI), 16-5 Jump If BR = 1 (JBI), 16-5 Jump If Minus (JM), 16-6 Jump If Minus or Zero (JMZ), 16-6 Jump If Not Zero (JN), 16-6 Jump If OS = 1 (JOS), 16-5 Jump If OV = 1 (JO), 16-5 Jump If Plus (JP), 16-6 Jump If Plus or Zero (JPZ), 16-6, 16-7 Jump If RLO = 0 (JCN), 16-4 Jump If RLO = 0 with BR (JNB), 16-4 Jump If RLO = 1 (JC), 16-4 Jump If RLO = 1 with BR (JCB), 16-4 Jump If Unordered (JUO), 16-6 Jump If Zero (JZ), 16-6 label as address, 16-2 overview of, 16-2 unconditional, 16-3–16-4 Jump to List (JL), 16-3 Jump Unconditional (JU), 16-3 Jump to List (JL) instruction, 16-3 Jump Unconditional (JU) instruction, 16-3 JUO. See Jump If Unordered instruction JZ. See Jump If Zero instruction
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
K Keywords, definition, C-1
L L. See Load and Transfer instructions Label, as address of a jump or loop instruction, 16-2 LAR. See Loading and transferring between address registers LC. See Load Current Value into Accumulator 1 as Binary Coded Decimal LN. See Natural Logarithm Load (L) and Transfer (T) instructions, 8-2–8-12 See also Instructions, Load (L) and Transfer (T) area-crossing indirect addressing, 8-5 byte, word, or double word as address, 8-5 definition of, 8-2 direct addressing, 8-4 immediate addressing, 8-3 indirect addressing, 8-4 information interchange, 8-2 between modules and memory areas, 8-2 by way of the accumulator, 8-2 Load Current Counter Value into Accumulator 1 as Binary Coded Decimal (LC), 8-10 loading and transferring between address registers (LAR and TAR), 8-11–8-12 loading bits of the status word into accumulator 1, 8-6 loading the length of a shared data block into accumulator 1 (L DBLG), 8-12 loading the length of an instance data block into accumulator 1 (L DILG), 8-12 loading the number of a shared data block into accumulator 1 (L DBNO), 8-12 loading the number of an instance data block into accumulator 1 (L DINO), 8-12 loading the status into accumulator 1, 8-6 transferring the contents of accumulator 1 to the status word, 8-6 Load Current Value into Accumulator 1 as Binary Coded Decimal counter, 7-2 timer, 6-2
Index-9
Index
Load Length of Instance DB in Accumulator 1 (DILG) instruction, 15-3 Load Length of Shared DB in Accumulator 1 (DBLG) instruction, 15-3 Load Number of Instance DB in Accumulator 1 (DINO) instruction, 15-3 Load Number of Shared DB in Accumulator 1 (DBNO) instruction, 15-3–15-4 Loading a count value format, 7-6 in binary coded decimal (BCD) format (LC counter word), 8-10 in binary form (L counter word), 8-8 Loading a time value format, 6-3 in binary coded decimal (BCD) format (LC timer word), 8-9 in binary form (L timer word), 8-7 range, 6-5 Loading and transferring between address registers, 8-11–8-12 Loading data block lengths and numbers, 15-3–15-4 Loading the length of a data block into accumulator 1 instance data block (L DILG), 8-12 shared data block (L DBLG), 8-12 Loading the number of a data block into accumulator 1 instance data block (L DINO), 8-12 shared data block (L DBNO), 8-12 Local data, area of memory, 2-8 address ranges, 2-9 Logic control instructions, 16-2–16-11 See also Jump and Loop instructions Logic string beginning of, 2-12–2-13 definition of, 2-12–2-13 output of, 5-20 terminating, 5-20 Loop (LOOP) instruction, 16-8 label as address, 16-2, 16-8 using efficiently, 16-9
Master Control Relay (MCR) instructions, 17-10–17-15 See also Program control instructions nesting, 17-13–17-15 MCR functions, Important notes, 17-15 MCR(. See Save RLO in MCR Stack, Begin MCR instruction MCRA. See Activate MCR Area instruction MCRD. See Deactivate MCR Area instruction Memory areas address ranges, 2-9 bit memory, 2-8 counter, 2-8 data block, 2-8 I/O (external I/O), 2-8 local data, 2-8 process image input, 2-8 process image output, 2-8 timer, 2-8 Memory indirect addressing, 3-3–3-5 Multiplying a number by –1, 12-14
N Natural Logarithm (LN), 10-11 Negate Real Number (NEGR) conversion instruction, 12-14–12-15 Negate RLO (NOT) instruction, 5-26 Negating numbers, 12-14 Negating the result of logic operation, 5-26 Negative edge transitions, 5-16–5-19 NEGD. See Twos Complement Double Integer conversion instruction NEGI. See Twos Complement Integer conversion instruction NEGR. See Negate Real Number conversion instruction Nesting expressions, 5-14–5-17 And before Or, 5-15–5-16 Nesting stack, 2-10, 5-14 Normally closed contact, 5-7 Normally open contact, 5-6 NOT. See Negate RLO instruction
M Master Control Relay (MCR) dependency on, 17-10, 17-11 effect on Set (S) and Reset (R) instructions, 5-21–5-22, 17-10 implementation of, 17-13 Important notes, 17-15
Index-10
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Index
O Off-Delay Timer (SF), 6-5, 6-15–6-16 On-Delay Timer (SD), 6-5, 6-11–6-12 Ones Complement Double Integer (INVD) conversion instruction, 12-14 Ones Complement Integer (INVI) conversion instruction, 12-14 Open a Data Block (OPN) instruction, 15-2 Operand. See Address OPN. See Open a Data Block instruction OR, bit of status word, 2-14 Or (O), using counters as bit operands, 7-2 Or branch, nesting expressions, 5-14–5-17 Or Not (ON), using counters as bit operands, 7-2 Or Word (OW) instruction, 13-3, 13-4–13-5 combining accumulator and constant, 13-4–13-5 Order of processing And with Or instructions, 5-15–5-16 OS. See Stored overflow Output of a logic string, 5-20 OV. See Overflow Overflow (OV) as affected by comparing two real numbers, 11-5 as affected by floating-point math instructions, 10-4 as affected by integer math instructions, 9-4 as affected by the shift and rotate instructions, 14-2 as affected by word logic instructions, 13-2 bit of status word, 2-14
P Parallel branch, nesting expressions, 5-14–5-17 Parameters actual, 17-3 formal, 17-3 Pointer format area-crossing register indirect addressing, 3-13–3-14 area–internal register indirect addressing, 3-9 memory indirect addressing, 3-4–3-5 POP. See Accumulator 2 to Accumulator 1 Positive edge transitions, 5-16–5-19
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Process image input area of memory, 2-8 Process image output area of memory, 2-8 Process-image input area of memory, address ranges, 2-9 Process-image output area of memory, address ranges, 2-9 Processing order for And with Or instructions, 5-15–5-16 Program control instructions Activate MCR Area, 17-11–17-12 assigning addresses to a Call (CALL) instruction, 17-3 Block End Conditional (BEC), 17-16 Block End Unconditional (BEU), 17-16 Call (CALL), 17-3–17-5 Conditional Call (CC), 17-7 Deactivate MCR Area, 17-11–17-12 Master Control Relay (MCR) functions, 17-10–17-15 Restore RLO, End MCR: )MCR, 17-11–17-12, 17-13–17-14 Save RLO in MCR Stack, Begin MCR: MCR(, 17-11–17-12, 17-13–17-14 Unconditional Call (UC), 17-7 Programming, practical applications, B-2–B-14 Pulse Timer (SP), 6-5–6-6, 6-7–6-8 PUSH. See Accumulator 1 to Accumulator 2
R R. See Reset instruction Real number comparing two real numbers, 11-5 forming the absolute value, 10-6 Registers address, 3-6 CPU, 3-6–3-11 Exchange Shared DB and Instance DB (CDB) instruction, 15-2 exchanging data block registers, 15-2 image. See Process-image Reset (R) instruction, 5-20, 5-21–5-23 counters, 7-4, 7-8–7-9 timers, 6-6 Resetting a counter, 7-4 a timer, 6-6
Index-11
Index
Restore RLO, End MCR instruction: )MCR, 17-11–17-12, 17-13–17-14 Result of logic operation (RLO) bit of status word, 2-13 clearing, 5-26–5-27 instructions that do not affect the RLO, 4-6 negating, 5-26 relationship to Block End instructions, 17-16 saving, 5-26 setting, 5-26, 5-27 stored in nesting stack, 5-14 transitions of, 5-16–5-19 with Assign (=) instruction, 5-24–5-25 Retentive On-Delay Timer (SS), 6-5, 6-13–6-14 Return value, calling a function that delivers a return value, 17-6 Reversing the order of bytes within accumulator 1, 12-13 RLD. See Rotate instructions, Rotate Left Double Word RLDA. See Rotate instructions, Rotate Accumulator 1 Left via CC 1 RLO. See Result of Logic Operation RND. See Round conversion instruction RND+. See Round to Upper Double Integer conversion instruction RND–. See Round to Lower Double Integer conversion instruction Rotate instructions, 14-6–14-8 Rotate Accumulator 1 Left via CC 1 (RLDA), 14-8 Rotate Accumulator 1 Right via CC 1 (RRDA), 14-8 Rotate Left Double Word (RLD), 14-7–14-8 Rotate Right Double Word (RRD), 14-7 Round (RND) conversion instruction, 12-9 Round to Lower Double Integer (RND–) conversion instruction, 12-11 Round to Upper Double Integer (RND+) conversion instruction, 12-10 Rounding 32-bit floating-point numbers to double integers, 12-8–12-11 numbers, overview, 12-12 real numbers to double integers, 12-8–12-11 RRD. See Rotate instructions, Rotate Right Double Word RRDA. See Rotate instructions, Rotate Accumulator 1 Right via CC 1
Index-12
S S. See Set instruction S5 TIME time base, 6-4–6-5 time value, 6-3 SAVE. See Save RLO in BR Register instruction Save RLO in BR Register (SAVE) instruction, 5-26 Save RLO in MCR Stack, Begin MCR instruction: MCR(, 17-11–17-12, 17-13–17-14 Saving, the result of logic operation, 5-26 SD. See On–Delay Timer SE. See Extended Pulse Timer SET. See Set RLO instruction Set (S) instruction, 5-20, 5-21–5-23 counters, 7-3 Set RLO (SET) instruction, 5-26, 5-27 Setting a counter, 7-3, 7-8–7-9 the result of logic operation, 5-26, 5-27 SF. See Off–Delay Timer SFBs. See System function blocks SFCs. See System functions Shift and rotate instructions, 14-2–14-8 Shift instructions, 14-2–14-6 effect on condition codes CC 1 and CC 0 and on the Overflow bit(OV) of the status word, 14-2 method of operation, 14-2 Shift Left Double Word (SLD, 32 bits), 14-2 Shift Left Word (SLW, 16 bits), 14-2 Shift Right Double Word (SRD, 32 bits), 14-2, 14-3 Shift Right Word (SRW, 16 bits), 14-2 Shift Sign Double Integer (SSD, 32 bits), 14-4 Shift Sign Integer (SSI, 16 bits), 14-4 signed numbers, 14-4 unsigned numbers, 14-2–14-3 SIMATIC and International mnemonic abbreviations of the statement list (STL) instructions, A-2, A-7 SIN. See Sine Sine (SIN), 10-13 SLD. See Shift instructions, Shift Left Double Word SLW. See Shift instructions, Shift Left Word
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
Index
SP. See Pulse Timer SQR. See Square SQRT. See Square root Square (SQR), 10-9 Square root (SQRT), 10-9 SRD. See Shift instructions, Shift Right Double Word SRW. See Shift instructions, Shift Right Word SS. See Retentive On–Delay Timer SSD. See Shift instructions, Shift Sign Double Integer SSI. See Shift instructions, Shift Sign Integer STA. See Status, bit of status word Starting a logic string, 2-12–2-13 Starting a timer, 6-5 Statement. See Instruction statement Statement list (STL), 1-1 definition of, 1-1 Status (STA), bit of status word, 2-13 Status word binary result (BR) bit, 2-16 bits affected by floating-point math instructions, 10-4 bits affected by integer math instructions, 9-4 bits affected by the shift and rotate instructions, 14-2 condition code bits (CC 1 and CC 0), overflow bit (OV) as affected by word logic instructions, 13-2 condition code bits CC 1 and CC 0, relationship to conditional jump instructions, 16-6 condition codes (CC 1 and CC 0), 2-14–2-15 condition codes CC 1 and CC 0 after a Compare instruction, 11-4, 11-5 description of, 2-12–2-16 evaluation of 32-bit integer math result, 9-4 first check (FC) bit, 2-12–2-13 indication of valid range for integer math result, 9-4 instructions that affect the status word, 5-10 instructions that evaluate the bits of the status word, 11-6 OR bit, 2-14 overflow (OV) bit, 2-14 overflow bit (OV) after a Compare Real number instruction, 11-5 reading using the Load (L) instruction, 8-6
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
result of logic operation (RLO) bit, 2-13 status (STA) bit, 2-13 stored overflow (OS) bit, 2-14 stored overflow bit (OS) after a Compare Real number instruction, 11-5 transferring the contents of accumulator 1 to it, 8-6 STL instructions, alphabetical listing arranged by International full name, A-12–A-16 arranged by the International mnemonic abbreviations, A-7–A-11 arranged by the SIMATIC mnemonic abbreviations, A-2–A-11 Stored overflow (OS) as affected by floating-point math instructions, 10-4 as affected by integer math instructions, 9-4 bit of status word, 2-14 Stored overflow (OV), as affected by comparing two real numbers, 11-5 Structure of an instruction statement, 2-2–2-7 STW. See Status word Swapping, data block registers, 15-2 Symbolic addresses, 17-3 Symbolic addressing, 2-4, 17-3 practical example, B-3 System function blocks (SFBs), as address of an instruction, 2-5 System functions (SFCs), as address of an instruction, 2-5
T T. See Load and Transfer instructions TAK. See Toggle Accumulator 1 with Accumulator 2 TAN. See Tangent Tangent (TAN), 10-13 TAR. See Loading and transferring between address registers Terminating a logic string, 5-20 Terminating the scanning of a block, 17-16 Time base for S5 TIME, 6-4–6-5 Time resolution. See Time base for S5 TIME
Index-13
Index
Time value format in accumulator 1, 6-4 range, 6-3–6-4 syntax, 6-3 Timers area of memory, 2-8 address ranges, 2-9 components, 6-3–6-4 definition of, 6-2 enabling, 6-6 instructions used with, 6-2–6-17 instructions used with timers bit logic, 5-22–5-23 Enable (FR), 6-6 Extended Pulse Timer (SE), 6-5, 6-9–6-10 Off-Delay Timer (SF), 6-5, 6-15–6-16 On-Delay Timer (SD), 6-5, 6-11–6-12 practical applications, B-7–B-10 Pulse Timer (SP), 6-5–6-6, 6-7–6-8 Reset (R), 6-6 Retentive On-Delay Timer (SS), 6-5, 6-13–6-14 location in memory, 6-3 number supported, 6-3 resetting, 6-6 resolution. See Time base for S5 TIME starting, 6-5 time base for S5 TIME, 6-4–6-5 time value, 6-3 range, 6-3–6-4 syntax, 6-3 types, 6-2 Extended Pulse (SE), 6-2, 6-5, 6-9–6-10 Off-Delay (SF), 6-2, 6-5, 6-15–6-16 On-Delay (SD), 6-2, 6-5, 6-11–6-12 overview, 6-18 Pulse (SP), 6-2, 6-5–6-6, 6-7–6-8 Retentive On-Delay (SS), 6-2, 6-5, 6-13–6-14 Toggle Accumulator 1 with Accumulator 2. See TAK
Index-14
Toggle the contents of Accumulator 1 with Accumulator 2, 4-2 Transfer (T) instruction. See Load (L) and Transfer (T) instructions Transferring the contents of accumulator 1 to the status word, 8-6 Transitional contacts, 5-16–5-19 TRUNC. See Truncate conversion instruction Truncate (TRUNC) conversion instruction, 12-12 Twos Complement Double Integer (NEGD) conversion instruction, 12-14 Twos Complement Integer (NEGI) conversion instruction, 12-14–12-15
U UC. See Unconditional Call instruction Unconditional Call (UC) instruction, 17-7 Unconditional jump instructions Jump to List (JL), 16-3 Jump Unconditional (JU), 16-3
W Word logic instructions, 13-2–13-8 16-bit, 13-3–13-8 32-bit, 13-6–13-8 accumulator administration, 13-2, 13-3, 13-6 And Double Word (AD), 13-7–13-8 And Word (AW), 13-4, 13-5 Exclusive Or Word (XOW), 13-3 Or Word (OW), 13-3, 13-4 practical applications, B-14
X X. See Exclusive Or instruction XN. See Exclusive Or Not instruction
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
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Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
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Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
