Semiconductor Device Modelling

Department of Electrical and Electronic Engineering Imperial College London

EE 2.3: Semiconductor Modelling in SPICE Course homepage: http://www.imperial.ac.uk/people/paul.mitcheson/teaching

Paul D. Mitcheson [email protected] Room 1111, EEE

EE2.3 Semiconductor Modelling in SPICE / PDM – v1.4

1

1. Aims and Objectives 1.1. Course Aims • •

To show how SPICE solves circuit problems To explain the three main SPICE semiconductor models

1.2. Learning Objectives By the end of these lectures you should be able to: • Understand the internal operation of 3 types of simulation in SPICE • Know what the SPICE model parameters mean and how they relate to physical quantities • Appreciate the issue of simulation convergence and how the semiconductor models used try to improve convergence • Be able to use your own custom semiconductor models in SPICE (see study group sheet)

2. Syllabus • •

SPICE internals and algorithms SPICE semiconductor models Diode o o BJT MOSFET o

3. Problem Problem Sheet An exercise done in SPICE in the labs which gets you used to the SPICE model parameters, and shows you some of the dynamic effects of devices that you have seen the theory for in the first part of the course.

4. Recommended Recommended Reading This part of the devices course is relatively self contained. If, however, you you want to know more about SPICE, the following are good books:

• • •

“Semiconductor Device Modelling with SPICE” , Giuseppe Massobrio and Paolo Antognetti, McGraw-Hill Inc. “Inside SPICE, overcoming the obstacles of circuit simulation” , Ron Kielkowski, McGraw-Hill Inc. “SPICE for circuits and electronics using PSpice”, Muhammad H. Rashid, Prentice Hall

EE2.3 Semiconductor Modelling in SPICE / PDM – v1.4

2

1. Aims and Objectives 1.1. Course Aims • •

To show how SPICE solves circuit problems To explain the three main SPICE semiconductor models

1.2. Learning Objectives By the end of these lectures you should be able to: • Understand the internal operation of 3 types of simulation in SPICE • Know what the SPICE model parameters mean and how they relate to physical quantities • Appreciate the issue of simulation convergence and how the semiconductor models used try to improve convergence • Be able to use your own custom semiconductor models in SPICE (see study group sheet)

2. Syllabus • •

SPICE internals and algorithms SPICE semiconductor models Diode o o BJT MOSFET o

3. Problem Problem Sheet An exercise done in SPICE in the labs which gets you used to the SPICE model parameters, and shows you some of the dynamic effects of devices that you have seen the theory for in the first part of the course.

4. Recommended Recommended Reading This part of the devices course is relatively self contained. If, however, you you want to know more about SPICE, the following are good books:

• • •

“Semiconductor Device Modelling with SPICE” , Giuseppe Massobrio and Paolo Antognetti, McGraw-Hill Inc. “Inside SPICE, overcoming the obstacles of circuit simulation” , Ron Kielkowski, McGraw-Hill Inc. “SPICE for circuits and electronics using PSpice”, Muhammad H. Rashid, Prentice Hall

EE2.3 Semiconductor Modelling in SPICE / PDM – v1.4

2

5. Introduction You received an introduction to SPICE in the first year design project. Briefly, to remind you of the history and development of the software: SPICE (Simulation Program with Integrated Circuit Emphasis) is a well-known circuit simulator computer program which began with a mainframe program written at UC Berkeley by Lawrence  Nagel (and others) during his PhD. The SPICE solver or “engine” (the ( the core part of the program i.e. the part that solves the circuit equations) is free software but it is command line driven and is thus regarded as difficult to use. use. Consequently, several commercial commercial versions (mostly based on the 2G7 release of the Berkeley program [PSpice is based on 2G7]) are available which provide a graphical interface and up to date component libraries (models of commercially available semiconductor components provided by the semiconductor manufacturers). In this part of the course we will look briefly at the internal workings of SPICE, the semiconductor models that are used and how they relate to the device theory you have already studied.

6. How SPICE solves circuit bias points – a first stage of the simulation process Why do we care how SPICE works internally? Because when things go wrong with with a simulation, having some insight into the operation of the program helps you figure out how to make your simulation run and also allows you to use the program program in a more efficient way. We will look in detail at how SPICE solves DC bias point simulations and then look briefly at some other types of simulation. We do it this way because the DC type calculations are fundamental to the operation of the other types of simulation and (with the exception of transient simulations) it is easy to extend the DC analysis that SPICE does to the other types of analysis.

6.1. Overview for a simple resistive circuit SPICE firstly forms a set of nodal nodal equations for a circuit is it trying to solve. These are formed from the netlist. Let’s see with an example. Consider the following basic circuit:

I1

n0

n1

3

R1

n1

n2

5

R2

n0

n2

10

R3

n2

n3

5

R4

n0

n3

10

Figure 1 Simple circuit with current source excitaiton

Firstly, SPICE forms a set of nodal equations based on KCL:

−3+

V 1 − V 2 5

=0

EE2.3 Semiconductor Modelling in SPICE / PDM – v1.4

3

V 2

− V 1 5

V 3 − V 2

5

+

+

V 2 10 V 3

10

+

V 2

− V 3 5

=0

=0

Which are rearranged and written in matrix form:

⎡ 0.2 − 0.2 0 ⎤ ⎡V 1 ⎤ ⎡3⎤ ⎢− 0.2 0.5 − 0.2⎥ ⎢V  ⎥ = ⎢0⎥ ⎢ ⎥⎢ 2 ⎥ ⎢ ⎥ ⎢⎣ 0 − 0.2 0.3 ⎥⎦ ⎢⎣V 3 ⎥⎦ ⎢⎣0⎥⎦ Then, Gaussian elimination is used to form an upper triangular matrix which is solved using back substitution (first solve for V 3, then V 2, then V 1).

⎡0.2 − 0.2 0 ⎤ ⎡V 1 ⎤ ⎡3⎤ ⎢ 0 0.3 − 0.2⎥ ⎢V  ⎥ = ⎢3⎥ ⎢ ⎥⎢ 2 ⎥ ⎢ ⎥ ⎢⎣ 0 0 0.25 ⎥⎦ ⎢⎣V 3 ⎥⎦ ⎢⎣3⎥⎦ You can see that this matrix is very easy to solve on computer, no matter how big it is. In essence, SPICE always tries to solve for nodal voltages which satisfy KCL by forming an equation of the form:

[G]× [V ] = [ I ]  Note that the current matrix is known. For many equations, the entry in the current matrix will be zero – as KCL requires currents into a node sum to zero), but it will be non-zero if an active device, such as a current source, is present. In other words, the I matrix lists the current being actively injected  into each node. Changing the current source for a voltage source makes it harder to solve(!) because it does not fit into our nice simple framework quite so easily. You might initially think that we could reformulate the expressions in the form of:

[ R ]× [ I ] = [V ] And then do Gaussian elimination to solve for the current matrix Consider the circuit below and the equivalent nodal equations

− I 1 + V 2

V 1 − V 2

− V 1 5

V 3 − V 2 Figure 2 Simple circuit with voltage excitation

5

EE2.3 Semiconductor Modelling in SPICE / PDM – v1.4

+ +

5 V 2 10 V 3 10

=0

+

V 2

− V 3 5

=0

=0

4

Unfortunately we cannot form the matrix equations – the voltages at the nodes (other than n1) are not known – we do not know the [V] matrix in its entirety and thus cannot perform Gaussian elimination. Therefore, we would like to analyse circuits with current sources instead of voltage sources because the [I] matrix is always known, and we can therefore solve the circuit using Gaussian elimination. This is a special property about current excited circuits.

Remarkable but true!

So how do we cope with a voltage source in the circuit? After all, power supplies and batteries are voltage sources, not current sources!

Use a Norton Equivalent circuit. Although it is not always clear how to do this as we will now see…. It is clear that in the case of Figure 2, the voltage source and current source could easily be converted into a Norton equivalent source. But how can you do it with the circuit branches as shown below?

Figure 3 Tricky to convert to a Norton source?

Figure 4 Not really!

6.2. Automatic Construction of the Matrix Equations The above is all very well, but how do we construct the matrices from the netlist? We did it in the example above by:

• • • •

Taking the netlist Drawing the circuit Using KCL to write the nodal equations Writing those equations in a matrix form [G] × [V ] = [ I ]

That algorithm is quite hard to program into a computer! There must be a better way…. and indeed there is! EE2.3 Semiconductor Modelling in SPICE / PDM – v1.4

5

It’s called matrix construction by inspection and lets us go directly from the netlist to the matrix equation. This construction is done by using predefined element matrix templates which can be added together automatically as we step through the netlist – if the templates are designed properly. Each template consists of a conductance matrix of N by N, where N is the number of terminals on the device and an Nx1 voltage array and an Nx1 current array, in the usual form of [G] × [V ] = [ I ] . This means that the template conductance matrix for a resistor is 2x2, a BJT is 3x3 and a MOSFET (with separate body contact) is represented by a 4x4 conductance matrix. Let’s take the example of a resistor:

 Node 0  Node 1 col col − G R ⎤ ⎡  Node 0 row ⎡ G R

⎢− G ⎣  R

 Node 1 row

G R

⎤ ⎡ ⎤ ⎥⎢ ⎥ = ⎢ ⎥ ⎦⎣ ⎦ ⎣ ⎦

Conductance Array

Current Array

Voltage Array

And the example for a current source:

 Node 0  Node 1 col col  Node 0 row  Node 1 row

⎡ ⎢ ⎣

Conductance Array

⎤⎡ ⎥⎢ ⎦⎣

⎤ ⎡  I  ⎤ ⎥ = ⎢− I ⎥ ⎦ ⎣ ⎦

Current Array

Voltage Array

Let’s see how SPICE constructs the equations for our earlier circuit of Figure 1:

I1

n0

n1

3

R1

n1

n2

5

R2

n0

n2

10

R3

n2

n3

5

R4

n0

n3

10

EE2.3 Semiconductor Modelling in SPICE / PDM – v1.4

6

From the first line of the netlist, we have the current source definition: n0 n1 n0 n1

⎤ ⎡V 0 ⎤ ⎡− 3⎤ ⎥ ⎢V  ⎥ = ⎢ 3 ⎥ ⎦⎣ 1 ⎦ ⎣ ⎦

⎡ ⎢ ⎣

On reading the second line of the netlist we add the definition of R1:

⎡ ⎢ n1 ⎢ n2 ⎢⎣

n1

n0

n0

0.2

− 0.2

n2

⎤ ⎡V 0 ⎤ ⎡− 3⎤ − 0.2⎥⎥ ⎢⎢V 1 ⎥⎥ = ⎢⎢ 3 ⎥⎥ 0.2 ⎥⎦ ⎢⎣V 2 ⎥⎦ ⎢⎣ 0 ⎥⎦

Then on the third line we add R2: n0 0.1

n1

n2 − 0.1⎤ ⎡V 0 ⎤

⎡ ⎡− 3⎤ ⎢ ⎥⎢ ⎥ ⎢ ⎥ 0.2 − 0.2 V 1 = 3 n1 ⎢ ⎥⎢ ⎥ ⎢ ⎥ ⎢ ⎥⎦ ⎢⎣V 2 ⎥⎦ ⎢⎣ 0 ⎥⎦ 0 . 1 0 . 2 0 . 3 − − n2 ⎣

n0

On the fourth line add the R3 template:

n0 0.1

n1

n2 n3 − 0.1

⎡ ⎤ ⎡V 0 ⎤ ⎡− 3⎤ ⎢ ⎥ ⎢V  ⎥ ⎢ 3 ⎥ 0 .2 − 0 .2 n1 ⎢ ⎥⎢ 1 ⎥ = ⎢ ⎥ n2 ⎢− 0.1 − 0.2 0.5 − 0.2⎥ ⎢V 2 ⎥ ⎢ 0 ⎥ ⎢ ⎥⎢ ⎥ ⎢ ⎥ n3 ⎣ − 0.2 0.2 ⎦ ⎣V 3 ⎦ ⎣ 0 ⎦ n0

And finally add the last line and the R4 template: n0

n1

n2

n3

− 0.1 − 0.1⎤ ⎡V 0 ⎤ ⎡− 3⎤ ⎡ 0 .2 ⎥ ⎢V  ⎥ ⎢ 3 ⎥ n1 ⎢ 0.2 − 0.2 ⎢ ⎥⎢ 1 ⎥ = ⎢ ⎥ n2 ⎢− 0.1 − 0.2 0.5 − 0.2⎥ ⎢V 2 ⎥ ⎢ 0 ⎥ ⎥⎢ ⎥ ⎢ ⎥ n3 ⎢− 0.1 − 0.2 0.3 ⎦ ⎣V 3 ⎦ ⎣ 0 ⎦ ⎣ n0

EE2.3 Semiconductor Modelling in SPICE / PDM – v1.4

7

As we define V 0 as ground, our final matrix equation to solve is:

0 − 0.1 − 0.1⎤ ⎡ 0 ⎤ ⎡− 3⎤ ⎡ 0 .2 ⎢ 0 ⎥ ⎢V  ⎥ ⎢ 3 ⎥ 0.2 − 0.2 0 ⎢ ⎥⎢ 1 ⎥ = ⎢ ⎥ ⎢− 0.1 − 0.2 0.5 − 0.2⎥ ⎢V 2 ⎥ ⎢ 0 ⎥ ⎢ ⎥⎢ ⎥ ⎢ ⎥ ⎣− 0.1 0 − 0.2 0.3 ⎦ ⎣V 3 ⎦ ⎣ 0 ⎦

 Note that we can add the matrices because as we add components into the circuit, any additional  branch conductances appear in parallel with the existing elements – and conductances in parallel add up. Another nice reason to use the [G] × [V ] = [ I ]  instead of the [ R ]× [ I ] = [V ]  form!

But this equation by inspection is different from the one we derived using nodal analysis. Is it valid?

Use a Of course! Remove the first row and column (which you can do as the voltage was zero) and you have the same matrix as we started with.  Now we know how SPICE solves any resistive circuit bias point with both voltage and current sources. What about simulations with capacitors and inductors?

How are inductors and capacitors solved in a DC bias point simulation?

Simple - Capacitors are set open circuit and inductors to short circuit. So, what about solving for non-linear elements, like a diode, or BJT?

6.3. Solving circuits with non-linear elements Let’s look at a simple circuit with a diode present. What happens to the matrix equation that SPICE has to work with?  Non-linear elements, such as diodes, cannot be solved using the simple Gaussian elimination technique alone because we run into a problem. Consider the following circuit with just 1 unknown nodal voltage:

−5+

EE2.3 Semiconductor Modelling in SPICE / PDM – v1.4

V 1 2

+ Is exp

V 1 vt 

=0

8

This single nodal KCL equation is a transcendental  (meaning it is an equation involving terms other than simple polynomials which generally cannot be rearranged so that the variable becomes the subject of the equation) and thus the equation can only be solved numerically. If we tried to form this into our G*V=I form and solve the normal way we would get:

⎡

⎛   ⎞⎤

⎣

⎝  t  ⎠⎦

V  [0.5][V 1 ] = ⎢5 − I  s exp⎜⎜ 1 ⎟⎟⎥ V 

We do not need to make any Gaussian elimination operations to solve this – because there is only 1 node… But it is still not clear how to solve it because it is transcendental. We can solve it using the Newton-Raphson algorithm, with which you should be familiar. Let’s remind ourselves how this works. The Newton-Raphson algorithm is as follows: V n+1

= V n −

 F (V n )  F ' (V n )

Where V n+1 is the voltage at the next iteration and V n  is the voltage at the current iteration. This does not mean the voltage at node n or node n+1.

⎛ V 1 ⎞ ⎟⎟ − 0.5V 1 V  ⎝  t  ⎠

For the simple circuit above,  F (V 1 ) = 5 − I  s exp⎜⎜ Therefore we have:

V 1n +1

= V 1 −

⎛ V 1  ⎞ ⎟⎟ − 0.5V 1 V  ⎝  t   ⎠ ⎛ V 1  ⎞ ⎟⎟ − 0.5 exp⎜⎜ V  ⎝  t   ⎠

5 − I  s exp⎜⎜

n

− I  sV 1

n

n

n

n

Which is easy to solve on computer using a simple loop.

6.4. Bringing it all together So, in slightly a larger circuit, let’s see what happens: Firstly, all voltage sources are replaced with current sources to give a circuit that looks something like the example below:

Figure 5 Solve using Gaussian Elimination and Newton-Raphson

EE2.3 Semiconductor Modelling in SPICE / PDM – v1.4

9

The equations are: At node 1: 3+

V 2 − V 1 5

=0

At node 2: V 2

− V 1 5

+

⎛ V   ⎞ + I  s exp⎜⎜ 2 ⎟⎟ = 0 10 ⎝ V t  ⎠ V 2

Which can be formed into the following matrix equations (of course done in SPICE by inspection): 3 ⎡ ⎤ ⎡0.2 − 0.2⎤ ⎡V 1⎤ ⎢ V   ⎞ ⎥ ⎢0.2 − 0.3⎥ ⎢V 2⎥ = ⎢ I  s exp⎛  ⎜⎜ 2 ⎟⎟⎥ ⎣ ⎦⎣ ⎦ ⎝ V t  ⎠ ⎦ ⎣ To solve these matrix equations, SPICE first uses Gaussian elimination to form the following matrices: 3 ⎡ ⎤ ⎡0.2 − 0.2⎤ ⎡V 1⎤ ⎢ ⎥ ⎛   ⎞ ⎢ 0 − 0.1⎥ ⎢V 2⎥ = ⎢ I  s exp⎜⎜ V 2 ⎟⎟ − 3⎥ ⎣ ⎦⎣ ⎦ ⎝ V t  ⎠ ⎦ ⎣ Then, Newton-Raphson will be used to solve the transcendental equation for V 2, before back substitution is used to find V 1.  Now we have some idea of how SPICE can solve circuits of any combination of linear and nonlinear elements with both voltage and current source excitation.

You now know the basics of how SPICE solves operating point (static DC analysis) problems with R, L, C and non-linear elements. The topic of Newton-Raphson brings us nicely onto the next topic…

7. Simulation Convergence and Convergence Aids Anyone who has used SPICE in simulating anything other than very basic circuits will probably be familiar with those times during which the simulator does not converge. If you have not seen a non-convergence of a simulation yet, don’t worry, you will at some point! You may well have already encountered convergence problems in the first year design project. When SPICE fails to converge, the program stops with an error message about the voltages and currents that failed to converge.

EE2.3 Semiconductor Modelling in SPICE / PDM – v1.4

10

Given the high frequency at which you can encounter convergence issues when simulating circuits in SPICE, it may surprise you to know that SPICE was designed with the convergence issue in mind as it is a known problem with iterative solution methods (i.e. Newton-Raphson) used in the internals of the program.

7.1. Basic Convergence Parameters The iterative Newton-Raphson algorithm, if converging, produces more and more accurate estimates of a solution with each iteration. There is a trade-off here with the time taken to find a result and the accuracy of the result. In order to control this accuracy/time trade off, there are limits that must be set by the SPICE user for the accuracy of the simulations (or, as you have done up to now, you can simply accept the default values). The important parameters are: RELTOL – Fractional tolerance of voltages and currents VNTOL – Node voltage tolerance ABSTOL – Current branch tolerance ITL1 – The number of iterations allowed for a bias point calculation So far, VNTOL and RELTOL will make sense to you. We have seen SPICE always solves equations for the nodal voltages. RELTOL is the relative voltage (and current) tolerance for the node voltages, i.e.  if the voltage at each node in the simulation changes by less than RELTOL  percent of the absolute value from one iteration to the next, then the node voltages are said to have converged to the answer. This is fine unless the node voltages are very small. As the node voltages reduce, then RELTOL requires SPICE to converge to smaller and smaller absolute numbers. This is where VNTOL comes in. VNTOL is the absolute nodal voltage tolerance. If the node voltages change by less than VNTOL from iteration to iteration, the simulation is also said to have converged. Thus, once the node voltages converge to within the limits of one of these parameters (whichever has the larger tolerance), the simulation might be in a position to stop. SPICE 1 used only these two parameters to control the algorithm accuracy. However, non-linear devices (semiconductor devices!) can have very large changes in currents with only small changes in voltage. This means that even if the nodal voltages are converged to within tolerance, Kirchhoff’s current law may not have converged (i.e. the sum of currents into a junction may not be close to zero). Thus, SPICE 2 (on which all modern SPICE based simulators are based) introduced some basic parameters for tolerances on currents. RELTOL was expanded to cover maximum fractional changes in branch currents between iterations (as well as nodal voltages) and ABSTOL was introduces. ABSTOL, which is absolute branch current tolerance, is the maximum allowed absolute change in branch currents from one iteration to the next. There is also a limit on the total number of allowed iterations. This is controlled by the ITL1 parameter. Thus, the flow of the program is thus: 1. 2. 3. 4. 5. 6.

If number of iterations > ITL1, break Do Newton-Raphson iteration to solve for nodal voltages Check the solutions against VNTOL and RELTOL If solution not converged within parameters, goto 2, else goto 5. Check branch currents (known from the nodal voltages) against ABSTOL and RELTOL If not converged, goto 1 else finish

EE2.3 Semiconductor Modelling in SPICE / PDM – v1.4

11

7.2. Convergence Problems – An example Again, we are going to concentrate on the convergence problems for simple DC bias point simulations (although this type of convergence problem could very well also appear in a transient simulation). Let’s consider SPICE trying to solve the following simple circuit with a Newton-Raphson algorithm and see where we might run into trouble. We’ll do Newton-Raphson graphically to see how the  problems might arise.

 Newton-Raphson tries to find the intersection of the diode characteristic with the load line. Make sure you understand how the load line is drawn – you are probably used to drawing them for voltage excited series circuits but this is a current excited parallel circuit. We first pick a starting point for the iterations. Let’s choose somewhere around 1 V to start with. Graphically, the Newton-Raphson algorithm does the following:

• • •

Take a tangent to the diode curve at the starting point (this tangent is of course a small signal linearised model of the diode!) and see where that crosses the load line This voltage is the starting point for the next iteration Repeat

You can see how this iterates towards the solution in the diagrams below.

Figure 6 Initial guess

Figure 7 First iteration

EE2.3 Semiconductor Modelling in SPICE / PDM – v1.4

Figure 8 Second iteration

12

Imagine that the first guess had been at a lower voltage. Then the tangent at the second guess would be almost vertical and the algorithm can get stuck.

We can see that we are always going to have a problem with the Newton-Raphson algorithm whenever we have a very high value of conductance on an element (in this case the diode) because the time taken for convergence of the algorithm may be large, or if the gradient is steep enough, the algorithm may not converge at all, with the next iteration voltage being the same as the last, and potentially no where near the actual solution

V1 1 V1 2 ,V13

There will also be a problem if the algorithm ends up in the part of the curve where the conductance of the diode is too small – i.e. the slope of the graph is too shallow. We can see this because in the Newton-Raphson algorithm we will approach a divide by zero error as the derivative of the curve approaches zero. Graphically it means that the next guess at a node voltage will be very far from the actual answer- and back on a step part of the curve where we have long convergence times.

7.3. The GMIN Convergence Parameter This brings us to another more advanced convergence parameter you might find useful when using SPICE. This is a parameter called GMIN and is designed to stop divide by zero errors when simulating the exponentials of pn junctions, and to reduce the problem that an iteration may take the next voltage iteration far from the final solution. GMIN is a pure conductance and one is placed in  parallel with every pn junction implemented in SPICE.

Figure 9 pn junction with GMIN convergence parameter

This means that the slope of the exponential of the diode in reverse bias is at least equal to GMIN.

EE2.3 Semiconductor Modelling in SPICE / PDM – v1.4

13

In addition, GMIN is the minimum conductance allowed between any two neighbouring nodes in SPICE. If you set a resistance between two nodes with a conductance of less than GMIN, the simulator will not run.  Note that there may be certain circumstances where you have to reduce GMIN – the default value in SPICE is 1e-12. If the impedance of some components in your circuit are of this order of magnitude, although GMIN will aid convergence, it will potentially ruin the accuracy of your simulations. Think before you simulate! Essentially, if you have both a parallel GMIN with a pn junction, and a series resistance, simulating the resistance of the wires, the overall slope conductance is always kept within manageable levels so that the next iteration will neither be too far away from the previous guess (and possibly wildly inaccurate), or too close (long iteration times).

7.4. Setting the convergence parameters  Novice SPICE users would not necessarily think to change the default settings of the convergence  parameters. However, it is often worth thinking whether the defaults make sense for the simulation you are doing. For low voltage low  power work, they are almost always a good starting point (this is what SPICE was designed for). The default value of VNTOL is 1 μV. Do we really care about resolving voltages to 1 μV when simulating a 100 V power supply? Probably not. So how do  parameters?

we

set

these

In PSpice Capture, go to Simulation Profile|Options tab

convergence Figure 10 PSpice simulation options dialogue

Pspice|Edit

We have looked in some detail at the operation of the DC bias point analysis. We will look briefly now at the other types of simulation that SPICE can do.

7.1. DC sweep simulations The DC sweep simulation is an extension to the bias point simulation. In a DC sweep, the steady state solutions to a circuit are simulated for a range of DC voltages of a chosen voltage source in the circuit (which could be a power supply or an input to an amplifier etc). For the first voltage value to be simulated, SPICE solves the matrix equations in the normal way, doing iteration if non-linear elements are present. The outcome of this simulation is then used as the starting points for the nodal voltages for the first value in the DC sweep (if iterations were requires and thus a starting guess is required for the next DC step). The outcome of that simulation is then used for the starting point for the nodal voltages in the next value of the DC sweep etc. Problems can arise in convergence when a voltage changes particularly quickly.

EE2.3 Semiconductor Modelling in SPICE / PDM – v1.4

14

The DC sweep has a further convergence parameter associated with it – ITL2. This is the number of iterations that can be done at each step in the DC sweep,  i.e.  it provides the same function as ITL1 in the DC bias analysis.

7.1. AC Simulations So far, we have seen SPICE effectively solve linear and non-linear elements in DC simulations. Performing an AC simulation is not so different from a DC simulation. However, the AC SPICE simulation does not solve for non-linear elements – it does not have to perform Newton-Raphson. When you do an AC simulation in SPICE to get a bode plot of a circuit’s frequency response, the simulator makes linearised small-signal models of any non-linear devices. These are essentially the same models as you have seen in your analogue electronics courses and consist of (controlled) current and voltage sources and R, L and C. The component values are all constant during the simulation (which is necessary for the model to be linear of course) SPICE solves the nodal equations in almost exactly the same way as it would for a DC simulation – only now the program cannot set inductances to short circuits and capacitors to open circuit. They simply become complex impedances. Consequently, at each given frequency, SPICE solves the matrix equations of the form [G][I]=[V], where the matrices now become complex. One anomaly with the AC simulation therefore, is that if you simulate something like a closed loop opamp circuit with a gain of 100 and an AC input voltage of 10 V, the output will be shown as 1000 V (if we are below the G*BW product) even through the power supplies to the opamp might only be 15 V. This is the problem with a linear model. If you want to really see the exact  behaviour of a circuit, accurate at all voltages, then the best way to do it is with….

7.2. Large signal Transient Simulations These are the most complex type of simulation because they show the complete semiconductor models realistically at all operating points – the full non-linear models are used (as in a DC bias  point simulation – and therefore Newton-Raphson is heavily used), but in contrast to the DC bias  point simulations, capacitors and inductors cannot be set to open and short circuit respectively. SPICE therefore makes heavy use of numerical integration in these simulations. The exact detail of these simulations is however beyond the scope of this course for the time we have.

So, what models does SPICE use internally for its semiconductor devices and how do they relate to the understanding you already have of semiconductor devices? We will look at the three most common devices, the p-n diode, the BJT and the MOSFET. You have been shown small signal models of devices in other devices lectures and in your analogue courses. SPICE uses similar small signal device models when performing an AC analysis. In this  part of the course, however, we will be looking at the large signal models used by SPICE in a transient (time domain) analysis and how they relate to the device physics you have already learnt.

EE2.3 Semiconductor Modelling in SPICE / PDM – v1.4

15

8. Types of Model used in SPICE There are three types of semiconductor model used in SPICE. One is the DC static model, one is the small signal AC model and one is the large signal transient model. We will look here at the DC models and transient models. The small signal models are essentially the same as you have seen in your analogue courses. The DC models are effectively the transient models with capacitors open circuited and inductances shorted. We will thus look at the models by starting with the DC model and then build them into the transient models with the addition of capacitances to take into account the dynamic effects.

9. The SPICE Diode Model 9.1. DC Model You have already been shown the equations which describe the diode model, in both static and AC conditions. The simple DC equation you know is the well known Shockley equation, that is:

 I  D

⎡ ⎛ V  ⎞ ⎤ =  I  s ⎢exp⎜⎜ ⎟⎟ − 1⎥ ⎣ ⎝ V t  ⎠ ⎦

Where  I S   is the diode’s reverse saturation current, V   is the applied voltage bias, V t   is the thermal voltage (equal to kT/q which is about 25mV at room temperature) and  I  D is the current through the device. The simple DC model used in SPICE is very similar to the Shockley equation, with the addition of a  parameter n, and a convergence aid of a the GMIN parallel conductance (see Figure 11). The basic static diode model equation is thus:

 I  D

⎡ ⎛  V   ⎞ ⎤ ⎟⎟ − 1⎥ + V  D GMIN  =  I  s ⎢exp⎜⎜ nV  ⎣ ⎝  t  ⎠ ⎦

 I  D

⎡ ⎛  V   ⎞ ⎤ ⎟⎟ − 1⎥ =  I  ⎢exp⎜⎜ nV  ⎝   ⎠ ⎣ ⎦  s

t 

Figure 11 The SPICE diode model has a parallel conductance to aid convergence

The parameter n  is an ideality factor for the diode, known as the emission coefficient. It has a SPICE parameter called N (all SPICE parameters are given in capitals). So far we have assumed n EE2.3 Semiconductor Modelling in SPICE / PDM – v1.4

16

to be 1, and indeed, in a good diode it will almost be 1. This parameter will rise above 1 if there is significant recombination of carriers in the depletion layer. Therefore, n tends to be closer to 1 under high forward bias and more than 1 under small bias voltages because the depletion layer gets thinner as the forward bias is increased. The other SPICE parameter from this basic equation is IS. In order to allow faster simulations than this equation would provide, a simple approximation is made in moderate reverse bias. When V  D