Schematics-Huawei Lua l23
November 29, 2022 | Author: Anonymous | Category: N/A
Short Description
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Description
1 2 1 2 3 3 6 7 8 1 1 1 1 1 1 2 1 1 1 1 1 1 U U V V V U201-B T T T T T M S S S S S S S S S S S DVDD12_EMI DVSS S S S S S S S S S S S V V V V V V V V V V V DVDD12_EMI DVSS D D D D D D D D D D D
T11 R11 R2 G6 G7 G14 G17 G20 H10 M20 N11 A19 A26 B4 B10 E21 F6 B12 B14 B17 B22 B24 C4 C8 C11 C12 C16 C17 C18 C20 C21 C22 C23 C25 D4 D5 D7 D9 D11 D13 D15 D17 D21 D24 E5 E8 E10 E18 F18 P21 L10
DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS
A2 R24
VTCXO_PMU VIO18_PMU 2 1 1 C
VIO18_PMU
P T C V _M O X U
8 0 1 C F n 0 0 1
9 0 1 C F n 0 0 1
0 1 1 C
F n 0 0 1
F n 0 0 1
P _M 81U O V
3 4 1 C
4 4 1 C
1 5 1 C
F n 0 0 1
F n 0 0 1
F n 0 0 1
0 3 1 C
F u 7 . 4
Bottom cap/1st cap group
check MSDC1/2 IO power
AVDD18_MD
AE19
AVDD18_AP
AE22 AE18 A3
AVDD28_DAC DVDD18_PLLGP AVDD18_MEMPLL
AC21 AD22 AG26 V17 V18 AA18 AB19
AVSS18_MD AVSS18_MD AVSS18_MD AVSS18_AP AVSS18_AP AVSS18_AP
VMC_PMU VIO18_PMU VIO18_PMU
N12 N13 N14 N15 N16 N17 P14 R15 P15 R14 R13 R12 R16 R17 T14 T15 U15 U16 V15 V16
DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS
M15 N21 P10 P11 P12 P13 P16 P17 L18 M14 M13 M12
VIO18_PMU 5 2 1 C
5 1 1 C
F n 0 0 1
F u 0 . 1
6 1 1 C
7 1 1 C
3 2 1 C
2 2 1 C
7 2 1 C
8 2 1 C
F n 0 0 1
F n 0 0 1
F n 0 0 1
F n 0 0 1
F n 0 0 1
F n 0 0 1
VCCK
4 0 1 C
4 2 1 C
1 3 1 C
F n 0 0 1
F n 0 0 1
F n 0 0 1
0 4 1 C
2 5 F 1 C u 0 . 1
F u 0 . 1
9 2 1 C
6 3 1 C
F u 0 1
F u 0 1
Bottom cap
1st cap group
VCCK_VPROC
VPROC_PMU 6 5 1 C
7 5 1 C
8 5 1 C
F n 0 0 1
F n 0 0 1
F n 0 0 1
8 4 1 C
F u 0 . 1
5 5 1 C
F u 0 . 1
Bottom cap
2 3 1 C
3 3 1 C
4 3 1 C
F u 0 1
F u 0 1
F u 0 1
S U V B P _M
F n 0 0 1
F n 0 0 1
0 1 6 6 1 1 C F u C 0 . 1
F u 0 . 1
GND_ VPROC_ FB
[3 ]
HT1 [3 ]
To MT6323 GND_VPROC_FBpin To MT6323 VPROC_FBpin
HT2
(2)R107 &R103 must be close to 1st cap group. Ifyou want to removethem, please make sure the VPROC_FB/GND_VPROC_FBmust connect from 1st cap. grou p ofVPROC
VIO18_PMU
AVDD33_USB T24 AVDD18_USB P26 H4 H5 J5 J7 L4 M7 DVSS18_MIPITX M8 DVSS18_MIPITX DVSS18_MIPITX N3
4 5 1 C
(1)VPROC_BB, GNDpin of 1st cap group shou ld be laid differential pair with ground shielding remote sense to PMIC
DVDD18_MIPIIO G1
DVSS18_MIPIIO DVSS18_MIPIIO DVSS18_MIPIIO DVSS18_MIPIIO DVSS18_MIPITX
3 5 1 C
1st cap group
DVDD18_MIPITX L2
check MSDC1/2 IO power
C115 close to pin E1 (150mil) C125 close to pin G26 (150mil)
VPROC_ FB
AE21
AVSS18_AP AVSS18_WBG AVSS18_WBG
2 4 1 C F n 0 0 1
M V C P _U
VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC
AVSS18_MEMPLL AVSS33_USB
AF3 AG1
DVDD12_EMI
E1 V1 AD26 U25 G26 L26 Y26 D1 W1 AG13
R10 P9 L11 L12 L13 L14 L15 L16 L17 M10 M18 N10 N18 P18 R9 R18 T10 U10 VCCK V10 VCCK
AVSS18_MD AVSS18_MD AVSS18_MD AVSS18_MD AVSS18_MD AVSS18_MD AVSS18_MD AVSS18_MD AVSS18_MD AVSS18_MD AVSS18_AP AVSS18_AP
For low-power testing proposal. It can be cancel for cost-down proposal
1.2V IO for DDR2 H18 H16 H15 G9 G11 G13 G15 G16 G18 H8 E7 F7 F8 G8 H11 H13
VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK
AVSS18_WBG AVSS18_WBG AVSS18_WBG AVSS18_WBG AVSS18_WBG AVSS18_WBG AVSS18_WBG AVSS18_WBG AVSS18_WBG AVSS18_WBG AVSS18_WBG AVSS18_WBG
W20 U20 V20 V21 U21 W21 Y20 Y21 AA21 AB21 U17 U18
VIO18_PMU
DVDD28_MSDC1 DVDD28_MSDC2 DVDD28_BPI DVDD28_MD DVDD18_MSDC0 DVDD18_IO0 DVDD18_IO1 DVDD18_IO2 DVDD18_IO3 DVDD18_IO4
DVSS DVSS DVSS DVSS DVSS DVSS
AE5 V7 U7 W7 Y7 AB6 AB8 AC3 AC5 AC7 AD4 AE3
For low-power testing proposal. It can be cancelfor cost-down proposal
DVDD12_EMI DVDD12_EMI DVDD12_EMI DVDD12_EMI DVDD12_EMI DVDD12_EMI DVDD12_EMI DVDD12_EMI DVDD12_EMI DVDD12_EMI DVDD12_EMI DVDD12_EMI DVDD12_EMI DVDD12_EMI
VUSB_PMU VIO18_PMU
0 2 1 C F n 0 0 1
9 1 1 C
F u 0 . 1
1 1 1 C
3 1 1 C
F n 0 0 1
F n 0 0 1
For low-power testing proposal. It can be cancelfor cost-down proposal
For low-power testing proposal. It can be cancelfor cost-down proposal
S S S S S S S S S S S S S S S S S S S S V V V V V V V V V V D D D D D D D D D D
M _126T S 8D N E 503C L P 7+ 9O 4H W R B G U p¤
3 T H
MT6582
2 6 1 7 2 1 0 7 4 4 2 1 1 1 1 1 2 1 1 2 T M K M H J H H H V
C110 Close to MT6582 A2 should connect to C110.GND pin firsst, t, than connect to GNDby via
LUA-U23
TITLE: DOCUMENT NO.:
V1.3
REV:
01_MT6582_POWER
A1
SIZED:
Hardware DEPT.
DEPARTMENT: COMPANY:
DESIGNER:
Last Saved Date:
2015/12/7
SHEET:
1
OF
13
U201-D
For DDR3 ED29 ED24 ED31 ED28 ED30 ED27 ED25 ED26 ED20 ED22 ED23 ED21 ED17 ED19 ED18 ED16 ED13 ED11 ED12 ED15 ED10 ED8 ED9 ED14 ED4 ED5 ED7 ED6 ED2
C26 C24 A25 B25 B26 B23 A23 D25 A11 A14 A13 D12 A10 B13 C10 B11 D22 B20 D20 A22 C19 B19 A20 B21 B16 A17 B18 A16 B15
ED3 ED1 ED0
C15 D14 C14
RDQ31 RDQ30 RDQ29 RDQ28 RDQ27 RDQ26 RDQ25 RDQ24 RDQ23 RDQ22 RDQ21 RDQ20 RDQ19 RDQ18 RDQ17 RDQ16 RDQ15 RDQ14 RDQ13 RDQ12 RDQ11 RDQ10 RDQ9 RDQ8 RDQ7 RDQ6 RDQ5 RDQ4 RDQ3 RDQ2 RDQ1 RDQ0
[2 ,4 ] EVREF
F16
VREF
U201-A
[11]TX_BBIP [11]TX_BBIN [11]TX_BBQP [11]TX_BBQN
[11]RX_BBIP [11]RX_BBIN [11]RX_BBQP [11]RX_BBQN
AF22 AF21 AG20 AF20
UL_I_P UL_I_N UL_Q_P UL_Q_N
AG25 AG24 AG22 AG23
DL_I_P DL_I_N DL_Q_P DL_Q_N
BPI_BUS0 AB24
BPI_BUS2 BPI_BUS3 BPI_BUS4 BPI_BUS5 BPI_BUS6 BPI_BUS7 BPI_BUS8 BPI_BUS9 BPI_BUS10 BPI_BUS11 BPI_BUS12 BPI_BUS13 BPI_BUS14 BPI_BUS15
DVDD12_EMI
ASM_VCTRL_A[11,12] ASM_VCTRL_B [[11,12] 11,12] ASM_VCTRL_C [11,12] WG_GGE_PA_ENABLE[11,12]
BPI_BUS1 AB23 DVDD28_BPI AD25 AC24 AC23 AE25 AD24 AF16 AA17 AD16 AC16 AF15 AC17 AB17 AC15 Y15
2 K 2 . 8
W_ PA_ B1 _ EN [1 2 ] W_ PA_ B2 _ EN [1 2 ] W_PA_B5_EN W_PA_B8_EN [1 2 ] TD_PA_B40_EN SP3T_A SP3T_B
AF25 AE24
VBIAS APC
AE14
TXBPI
1
[2 ,4 ] EVREF 2
VM0 AG14 VM1 AF14
[11]DCOC_FLAG
F n 0 0 1
5 0 2 C
9 0 2 1 R
DVDD18_IO4
[1 1 ,1 2WG_GGE_PA_VRAMP ]
2
BSI_EN AD14 BSI_CLK Y14 BSI_DATA0 AB14 BSI_DATA1 AA14 BSI_DATA2 AC14
BSI-A_ EN BSI-A_ CK BSI-A_ DAT0 BSI-A_ DAT1 BSI-A_ DAT2
7 0 2 C
F n 0 0 1
6 0 2 C
0 1 1 2 R
[1 1 ] [1 1 ] [1 1 ] [1 1 ] [1 1 ]
2
2
K 2 . 8
VM 0 [1 2 ] VM1 [1 2 ]
F u 0 . 1
1
1
S N 37p+ G ¤9W O U 4H 501_2R L P D E 86T M C B
MT6582
0 5 2 P T
A1
RCS0_B B7 RCS1_B B6
ECS0 _ B [4 ] ECS1_B [4]
RCKE B5 RDQM0 RDQM1 RDQM2 RDQM3
D16 D18 D10 D23
RDQS0 RDQS1 RDQS2 RDQS3
F15 F17 F12 E20
ECKE [4 ]
EDQM0 [4] EDQM1 [4 ] EDQM2 [4 ] EDQM3 [4 ] EDQS0 [4 ] EDQS1 [4 ] EDQS2 [ 4] EDQS3 [4 ]
RDQS0_B E15 RDQS1_B E17 RDQS2_B E12 RDQS3_B F20
TP_MEMPLL
EDQS0 _ B [4 ] EDQS1 _ B [4 ] EDQS2 _ B [4 ] EDQS3 _ B [4 ]
RCLK0_B RCLK0
F9 E9
RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA8 RA9
B8 B9
EA0 EA1
D8 A8 A7 C7 A5 D6 C6 A4
EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9
REXTDN
B3
EDCLK K__ B [4 ] EDCLK [4 ]
1
R221
56T M P S p¤D C L 01E _2O R 8N 37G + 9U W 4H B
56_NF
MT6582
2
SCL0 [2 ,6 ] SDA0 [2 ,6 ] SCL1 [2 ,7 ] SDA1 [2 ,7 ] SCL2 [2 ,9 ,1 0 ] SDA2 [2 ,9 ,1 0 ]
U201-E
DTV_SPICS1 DTV_SPIDI DTV_SPIDO DTV_SPICLK
EINT11_HP [5]
EINT1 4 C _CTP_ TP_ RST EINT_ ACC [9 ] EINT16_MC1INSI
M M 2 8 . 0 2 0 - P P T T
URXD1
UTXD1 R202 R203
TP203 M 1 M 1 8 . 0 0 - 2 P P T T
GPIO_CHG_EN CHGFULL_EN CHGFULL_EN [1 0 ]
1K 1K
[6] UTXD0
0 0 D D X X T R U U
AF26
[11] CLK1_BB
2 2 Y W
U201-C
2 2 U V
VGP2_PMU
R213 R214 R215 2
9 0 2 C
VIO18_PMU
1
1 K 1 7 . 4
K 7 . 4
8 7 1 1 2 2 2 R 2 R
5.1K
RTC32K_CK
RTC32K_CK
1 1 D D X X T R U U
0 TESTMODE 0 FSOURCE_P NC
[3] WATCHDOG_B C N TP209 _ F n 0 TP210 0 1
TP211
AF11 R5 R4 N26
TESTMODE FSOURCE_P DVDD18_EFUSE WATCHDOG
AF12 AE12
JTCK JTDO
AG11
JTDI
537091N
637091N
USB_VRT
90 Ohm differential
[2 ,9 ,1 0 ]SCL2 [2 ,9 ,1 0 ]SDA2
[6] [6]
USB_DP USB_DM
[3] CHD_DP [3] CHD_DM
0 0 1 1 2 2 S O I K L A L A L A C M M C C D C D C D I_ _ I_ I_ S S S S S S P I P P S P S S S
1 1 T N I E
0 1 0 0 8 8 1 1 1 9 1 F G E C D E C A A A A A A A 4 5 6 7 8 9 0 1 1 1 1 1 1 2 T T T T T T T N I I N I N I N I N I N I N E E E E E E E
P25
USB_VRT
R26 R25
USB_DP USB_DM
N23 N24
2 1 1 1 2 2 2 R 2 R
[2 ,7 ] [2 ,7 ]
[3] BAT_ID_ADC [6] LCD_ID_ADC
SCL1 SDA1
2 0 2 C
3 0 2 C
F P 0 0 1
F P 0 0 1 REFP
VIO18_PMU
C204
MIPI_RDP2 MIPI_RDN2 MIPI_RDP3 MIPI_RDN3
K6 K5 L3 K3 K1 K2 J1 J2 G2 H2
RCP RCN RDP0 RDN0 RDP1 RDN1 RDP2_ RDN2_ RDP3_ RDN3_
[7] MIPI_RCP_A [7] MIPI_RCN_A [7] MIPI_RDP0_A [7] MIPI_RDN0_A [7] MIPI_RDP1_A [7] MIPI_RDN1_A
F5 G5 G4 G3 J3 H3
RCP_A_ RCN_A_ RDP0_A RDN0_A RDP1_A RDN1_A
MT6605 OSC_EN(SRCLKENAI) need to default low for MT6605 TESTMODEboot-str ap
N1
MIPI_VRT
LCM_RST U3 DSI_TE Y3 DISP_PWM AD9
CMMCLK B2 CMPCLK B1 CMDAT0 CMDAT1
LRSTB [6 ] LPTE [6 ] PWM [6 ]
R205
E2 F2
0 CMMCLK [7]
CMPCLK 1 0 2 C
SW_FM
SW_TV
F N
VRT
1 56T M P S p¤D C L 01E _2O R 8N 37G + 9U W 4H B
R204
SYSRSTB M25 SRCLKENAI SRCLKENA
SYSRST_B
GPIO12 GPIO13
DVDD28_MD
AUX_IN0 AUX_IN1 AUX_XP AUX_XM AUX_YP AUX_YM
AG19 AF19
REFP AVSS_REFN
F u 1 . 0
EINT0 EINT1 EINT2 EINT3 EINT4 EINT5 EINT6 EINT7 EINT8 EINT9 EINT10
3 2 1 0 T T T T K D A A A A L M D D D D C C _ _ _ _ _ _ 2 2 2 2 2 2 C C C C C C D D D D D D S S S S S S M M M M M M
3 2 1 0 T T T T K D A A A A L M D D D D C C _ _ _ _ _ _ 1 1 1 1 1 1 C C C C C C D D D D D D S S S S S S M M M M M M
[3 ] [3 ] [3 ] [3 ] [3]
AUD_CLK [3] AUD_ DAT_ MSO I [3 ] AUD_DAT_MOSI [3]
AG10 AF9
MT6582
[2 ,3 ]
F N
2
1.5K
Close to MT6582 C208 are for ESDehnhace proposal. It can be cancelfor cost-down proposal
GPIO1 2 [7 ] GPIO13 [7] SIM 1 _ SCLK L K [3 ] SIM1_SIO [3] SIM 1 _ SRST ST [3 ] [3] SIM2_SCLK SIM2_SIO [3] SIM 2 _ SRST ST [3 ]
W22 V22 AA24 V24 W25 Y25 AA23 AA26 AA25 Y23 Y22
GPIO_0 [5] EINT1 _ A [9 ] EINT2 _ CTP TP [6 ] EN I T3 _S D EINT4 _ SU UB_ B_ CM PDN
MIPI CSI IFPort
[ 8] [7 ] GPIO5_AUDIO_PA_EN[5] EINT6_SUB_CMRST EINT6_SUB_CMRST [7] [7] EINT7_NFC_VENB EINT8_NFC EINT9_MAINCAM_RST [7] EINT10_CMPDN [7]
PCM_CLK V23 PCM_RX V26 PCM_SYNC V25 PCM_TX U24
DVDD28_MSDC2 DVDD28_MSDC1
8 0 2 C
[3 ,1 1 ]
PM IC_ SPPI_ I_ CS PM IC_ SPPI_ I_ SCK PM IC_ SPPI_ I_ M ISO PM IC_ SPPI_ I_ M OSI E I NT _ P M IC
SIM1_SCLK L21 SIM1_SIO K23 SIM1_SRST L23 L20 SIM2_SCLK SIM2_SIO L24 SIM2_SRST K24
DVDD18_IO3
AF18 AG17 AF17 AG16
SRCLKENAI SRCLK E ENA NA
AUD_CLK_MOSI K26 AUD_DAT_MISO K25 AUD_DAT_MOSI J25
I2S_BCK I2S_LRCK I2S_DATA_IN
AC19 AD19
M24 N25
PWRAP_SPI0_CSN J23 PWRAP_SPI0_CK H23 PWRAP_SPI0_MI J24 PWRAP_SPI0_MO H22 PWRAP_INT H24
CHD_DP CHD_DM
V5 U5 W5
K 7 . 4
TP213
[2 ,3 ] SYSRST_B
GPIO93_DRVVBUS
0 0 1 1 2 2 L W L W L W O O O O O O C R C R C R P P P P P K K K P K K K
DVDD28_MD
VIO18_PMU
1 K 1 7 . 4
KCOL0 [1 0 ] KROW0
KCOL2 [10]
3 3 3 3 3 1 1 1 1 3 1 B C D E 1 A A A A A Y A
JTMS
37091N
+/-1%
2 2 3 3 D D D D X X X X T R T R U U U U
0 1 F A
TDP1 TDN1 TDP2 TDN2 TDP3 TDN3
MIPI_TDP1 MIPI_TDN1 MIPI_TDP2 MIPI_TDN2
RTC32K_CK
AF13
R201
Close to MT6582
L25
73091N
TP212
3 3 8 7 1 2 8 9 9 7 A B D E A A C C B D A A A A A A A A A A
3 3 2 2 T R
CLK26M
DVDD18_IO3 [3]
3 2 2 2 P P
P2 N2 P1 R1 N5 M5
[6] [6]
[7] [7] [7] [7]
KCOL1 [1 0 ] DTV_RST
1
TCP TCN TDP0 TDN0
MIPI_TCP MIPI_TCN MIPI_TDP0 MIPI_TDN0
[7] MIPI_RCP [7] MIPI_RCN [7] MIPI_RDP0 [7] MIPI_RDN0 [7] MIPI_RDP1 [7] MIPI_RDN1
[6 ]
EINT17_DTV
TP204
M3 M4 M1 M2
[6] [6] [6] [6]
ParallelCamera l Camera IFPort
RDP2 RDN2 RDP3 RDN3
CMDAT9 CMDAT8 CMDAT5 CMDAT4
R CP_A R CN_A R DP0_ A R DN0_A
CMDAT7 CMDAT6 CMVS YNC CMHS YNC
R DP1 _A R DN1_ A CMDAT1 CMDAT0
DVDD18_MSDC0
CMMCLK CMPCLK
7 6 5 4 3 2 1 0 T T T T T T T T K D B T A A A A A A A A L M S D D D D D D D D C C R _ _ _ _ _ _ _ _ _ _ _ 0 0 0 0 0 0 0 0 0 0 0 C C C C C C C C C C C D D D D D D D D D D D S S S S S S S S S S S M M M M M M M M M M M
CMDAT3 CMDAT2 CMDAT1 CMDAT0 CMMCLK CMPCLK
M _126T S 8D N E 503C L P 7+ 9O 4H W R B G U p¤
MT6582
1 K 1 7 . 4
K 7 . 4
0 9 2 1 2 2 2 R 2 R [2 ,6 ] [2 ,6 ]
SCL0 SDA0
C213 Close to MT6582 1 0 2 AF19 should T connect to C213.2 first, H than connect to GNDby via
2 1 5 6 7 3 T T T T R T
F N
F F N N
6 0 2 R
7 0 2 R
8 0 2 R
3 2 2 4 3 3 D C D E C E
2 3 4 4 6 5 3 2 6 4 5 2 2 2 2 2 2 2 2 2 2 2 F E F G E E G G D E G EM M C_ RST EMMC_CMD EM M C_ CLK EM M C_ DAT0 EM M C_ DAT1 EM M C_ DAT2 EM M C_ DAT3 EM M C_ DAT4 EMMC_DAT5 EM M C_ DAT6 EM M C_ DAT7
[4 ] [4] [4 ] [4 ] [4 ] [4 ] [4 ] [4 ] [4] [4 ] [4 ]
M C1 CM [8 ] MC1CK [8] M C1 DA0 [8 ] M C1 DA 1 [8 ] MC1DA2 [8] M C1 DA 3 [8 ]
LUA-U23
TITLE: DOCUMENT NO.:
V1.3
REV:
02_MT6582_BASEBAND
A1
SIZED:
Hardware DEPT.
DEPARTMENT: COMPANY:
DESIGNER:
Last Saved Date:
2015/12/7
SHEET:
2
OF
13
Before you select BJT , please take power dissipation into consideration. Referto MT6323 desig n notice U301
BGA145-5.8X5.8-0.4E0.25B(MT6323)
VBAT
Charger
2 1 3 F C u 0 . 1
R329 VCDT [3] 330K
0 9 8 7 1 4 1
3 4 2 F C u 0 . 1
R331
9 C C C C D D 8 0 5 I M P N P + T E F N R E W E B S G O P 2 3 6 5
CONNECTOR
ISENSE/BSTSNS 4mil differentialto Rsense
1 2 3 4
Rsense
ISENSE_R 5 2 . 0 8 0 0 R S
8 2 3 R
HT303
4mil
HT304
4mil
Differential
1 6 3 R
1
ACCDET
[11]CLK4_AUDIO
E1
CLK26M
CHR_LDO 6 1 3 C
500mW
2 0 3 C
F u 0 . 1
from VBAT to IC
BATSNS [3]
7 1 3 C
F P 0 0 1
ISINK0 ISINK1 ISINK2 ISINK3
DRIVER
AU_HPL [5,10] AU_HPR [5,10]
E9 C9 E10 C10
Please use inductor recommand by MTK
VPROC_PMU VPROC_PMU [1,3]
Referto MT 6323 design notice
BUCKOUTPUT
VPROC_SW
VPROC C14 VPROC D14 VPROC E14
L301
F N _ F u 7 . 4 3 3 3 C
0.68uh
(Battery connector
K 9 . 6 1
[2] EINT_PMIC
Close to PMIC
[2] AUD_DAT_MOSI [2] AUD_CLK [2] AUD_DAT_MISO
K 7 2
2 0 3 R V
1 0 3 R V
1 0 3 P T
5 3 3 R
VBAT VBAT [3,5,6,7,10,11,12] BAT_ON[3]
VBAT
[2] PMIC_SPI_SCK [2] PMIC_SPI_CS [2] PMIC_SPI_MOSI [2] PMIC_SPI_MISO
40mil
30mil(4milifVPAno use)
VBAT
20mil 1 6 1 2 0 0 0 0 3 0 D 0 0 2 1 1 2 8
[2,11] SRCLKENA [3] FCHR_ENB
n ot ice f orZen ers elect ion 80mil
R334,R335 must to be close to PMICAUXADC_REFpin
FCHR_ENB [3]
0 1 3 C
F u 2 2
0 3 3 C
VBAT
20mil 20mil 20mil
F N
VSYS_PMU
VBAT VBAT
20mil
CHRLDO
M2 A1 K4 A9 A7 N12
PWRKEY SYSRSTB RESETB FSOURCE INT EXT_PMIC_EN
E7 E8 B6
ALDO OUTPUT
ifbatteryNT Cis 47kohm, R334=61.9K, R335=100K Referto MT 6323 HWdesign notice
VIO18_PMU
VIO18_PMU [3,11] AUXADC_REF [11] AUXADC_TSX
BAT_ID_ADC [2] 1K
CL OSEB atconnector B ased on yoursystem level design , if
0 1 3 R V
better EOS performance is needed on your system, ple ase referto EOS performance enhance proposal
AUXADC_REF AUXADC_TSX 3 2 3 C
F u 0 1
F u 7 . 4
F u 0 1
1 0 3 C
0 5 3 C
3 0 3 C
F n 0 0 1
C322 must to be close to PMICAUXADC_TSXpin
4 0 3 C
F u 0 . 1
F F u u 0 0 1 1 6 0 9 3 0 C 3 C
F F u u 0 . . 0 7 81 1 0 0 3 3 C C
Connect TSX/XTALGND to AUXADC_GNDfirst than connect to main GND
2 0 3 T H
referto sys tem analog LDO performance improve proposal
GND_AUXADC [11]
2 2 3 F C u 0 . 1
2.2uh
VPA_PMU 2
H14
[1]
VPA for WCDMA
F u 2 . 2
1
VSYS_SW
L303
¿¿½üL305
0.68uh
VSYS_PMU
VA M3
SPI_CLK SPI_CSN SPI_MOSI SPI_MISO
DLDO OUTPUT
F13 F14 G13 A13
VBAT INPUT VBAT_VPROC VBAT_VPROC VBAT_VPROC VBAT_VPA
H13 P8 P6 P5 P2
VBAT_VSYS VBAT_LDOS3 VBAT_LDOS3 VBAT_LDOS2 VBAT_LDOS1
J14 M14
AVDD22_BUCK AVDD22_BUCK
VEMC_3V3_PMU
VM VRF18 VIO18 VIO28 VCN18 VCAMD VCAM_IO
J13 H11 L12 M4 J12 K14 L13
VEMC_3V3 VMC VMCH VUSB VSIM1 VSIM2 VGP1
P7 L6 P4 N6 P9 N9 L8
VA_PMU
VCN_2V8_PMU VTCXO_PMU VCAMA_PMU VCN_3V3_PMU VRTC C331 100nF
F u 1 . 4 0 5 3 C
1.0uF
3 5 3 C
DVDD12_EMI VRF18_PMU
F u 0 . 1
VIO18_PMU VIO28_PMU VCN18_PMU VCAMD_PMU VCAMD_IO_PMU VEMC_3V3_PMU VMC_PMU VMCH_PMU VUSB_PMU VSIM1_PMU VSIM2_PMU VGP1_PMU
VIBR M7 VGP2 N8 VGP3 L14 VCAM_AF N7
VIBR_PMU VGP3_PMU VCAM_AF_PMU
VGP2_PMU
DVDD18_DIG
A5
DVDD18_IO
C2 B1 B2
AUXADC_VREF18 F18 AUXADC_AUXIN_GPS AVSS28_AUXADC
VREF
AUXADC VREF
P14
BC1.1 GND_VREF N14
CHG_DM CHG_DP
[2] SIM1_SCLK [2] SIM1_SIO [2] SIM1_SRST
B5 M11 E6
SIM1_AP_SCLK SIMLS1_AP_SIO SIM1_AP_SRST
[2] SIM2_SCLK [2] SIM2_SIO [2] SIM2_SRST
C5 K11 D6
SIM2_AP_SCLK SIMLS2_AP_SIO SIM2_AP_SRST
SCLK1 SIO1 SRST1
M9 N11 M10
SIMLS1_SCLK SIMLS1_SIO SIMLS1_SRST
[8] SCLK2 [8] SIO2 [8] SRST2
K9 L11 K10
SIMLVS
[8] [8] [8]
VA_PMU
C355 SRCLKEN FCHR_ENB
D9 B7 D8 B8
A10 A11
[2] CHD_DM [2] CHD_DP 1 0 3 T H
L302
4 3 3 C
VCAMA P3 VCN33 M6 AVDD33_RTC C3
AUD_MOSI AUD_CLK AUD_MISO
A2 M1
A8
R360
VPA_SW
VCN28 N3 VTCXO L4
PMU_TESTMODE
DVDD18_DIG_PMIC
ifbatteryNT Cis 10kohm, R334=16.9K, R335=27K K 0 2
VPROC_FB [1] GND_VPROC_FB
VPA A14 VPA B14 VPA_FB D12
N13
N2
Referto MT6323 design 40mils
BATSNS ISENSE BATON VCDT VDRV
CONTROLSIGNAL
1K
AUXADC_REF [3,11]
40mils
P13 P12 K3 A12 M13
R316 [10] PWRKEY [2] WATCHDOG_B SYSRST_B [2]
Between ICand IO port 4 3 3 R
1
VPROC_FB B12 GND_VPROC_FB C12
VSYS F u 0 . 1
VIO18_PMU[1,2,3,4,5,6,8,9,11] M M 7 8 . 0 0 - 3 P P T T
AVDD28_ABB AVDD28_AUXADC GND_ABB
E2
BATSNS ISENSE BAT_ON VCDT VDRV
Place on the path ISENSE [3]
1K
0 6 3 F C N
J2 D3 H2
[5] ACCDET
VF: 4.85V~ 5.36V
R317
BATTCON-BA2C04311-R
AU_VIN2_P AU_VIN2_N
connector) AUXADC_REF
5 6
BAC3290401
AU_VIN1_P AU_VIN1_N
D2 D1
[3] BATSNS [3] ISENSE [3] BAT_ON [3] VCDT [3] VDRV
ortest point orIO 40mils TP-1.0MM TP305 TP-1.0MM TP306
1 1
AU_VIN0_P AUDIO AU_VIN0_N
G3 G4
AU_VIN2_P AU_VIN2_N
CHR_LDO [3]
1
1
J301
E4 F4
[5] AU_VIN1_P [5] AU_VIN1_N
AU_HSP [5] AU_HSN[5]
AU_HPL H4 AU_HPR J4
CHARGER
Add ZenarDio de
BATTERY
[5] AU_VIN0_P [5] AU_VIN0_N
AU_SPKP AU_SPKN
AU_HSP H1 AU_HSN G1
CHR_LDO [3]
40mils
TP-1.0MM TP-1.0MM TP303 TP302 TP-0.8MM TP304
AU_MICBIAS0 AU_MICBIAS1
3.3K
40mils
O D L _ R H C ] 3 [
F2 G2
MICBIAS1
2 4 2 F C u 0 . 1
VCDT r ating: ating: 1.268 V
R324 39K
40mils
V R D V ] 3 [
GND_SPK
VA_PMU
VA_PMU
9 2 3 C
F u 1
Phone OVPspec.
3 0 3 U
L2
2 . 2 uF
MICBIAS0
1. Close to Battery Connector. (Rsense (R328) U303's E, -> U303's C-> R328 -> VBAT) 3. Star connection from R328 to BAT Connector cap rating depends on
VBAT_SPK
C 3 13
VBUS
SPK_P K1 SPK_N L1
P1
RTC
RTC_32K1V8 D5 RTC_32K2V8 C4 XIN A3 XOUT A4
SIMLS2_SCLK SIMLS2_SIO SIMLS2_SRST
GND_ISINK GND_VSYS GND_VPA GND_VPROC GND_VPROC GND_VPROC
0 2 3 C F n 0 0 1
dedicate VSS ball, must return to cap then to main GND: 1. GND_VREF(N14) => C320 HT305
RTC
RTC32K_CK [2] 32K_IN 32K_OUT
B10 G11 E13 E11 F11 F10
6 3 3 R
GND_LDO K6 GND_LDO K8 GND_LDO F5 GND_LDO F6 GND_LDO F7 F8 F9 G5 G6
0
RT C32K: X301+C324+C319=> mount, R333=> NC 32K-less: X301+C324=> remove, C319+R333=> 0R
Close to chip R333
0
DCXO_32K DCXO_32K [11]
O O O O O O O O O O O O O O GND_LDO D D D D D D D D D D D D D D GND_LDO L L L L L L L L L L L L L L _ _ _ _ _ _ _ _ _ _ _ _ _ _ D D D D D D D D D D D D D D GND_LDO N N N N N N N N N N N N N N GND_LDO G G G G G G G G G G G G G G 6 0 9 8 7 6 5 9 8 7 7 J 8 J 9 J 0 J 1 H H H H H G G G 1 J H
VIBR_PMU
Referto MT6323 desig n notice forBuck GND layout rule F u 1
1 1 3 C
VRTC
MOT L304
[3]
VIBR_PMU 68nH
K 1
2 L305
F N
4 1 3 C
F N
5 1 3 C
1 68nH
2 0 3 J
Referto GPS co-clock layout rule 5 2 3 C
Vibra
2 1 3 R
F u 7 4
6 F 2 u 3 2 C 2
==> for longer RTCtime sustain after battery remove, please refer to RTCdesign notice
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R401
0 DVDD18_EMI
VIO18_PMU
VDD1 :Core 1 DVDD18_EMI U401
EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 ED0 ED1 ED2 ED3 ED4 ED5 ED6 ED7 ED8 ED9 ED10 ED11 ED12 ED13 ED14 ED15 ED16 ED17 ED18 ED19 ED20 ED21 ED22 ED23 ED24 ED25 ED26 ED27 ED28 ED29 ED30 ED31 R402 240 1 1 GND
R403
2 2
240
GND
Y2 Y3 W2 W3 V3 L3 K3 J3 J2 H2
CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9
W12 V11 V13 U11 U13 T11 T13 R12 N12 M13 M11 L13 L11 K11 K13 J12 AB12 AB11 AB10 AA13 AA12 AA10 Y13 Y11 H11 H13 G10 G12 G13 F10 F11 F12
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
Power
G2 ZQ0 G3 ZQ1 F13 G11 H10 J8 J13 K8 K9 L10 L12 M8 N13 P9 R13 T8 U10 U12 V8 V9 W8 W13 Y10 AA11
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
F2 G4 G8 H3 H5 L4 M3 M4 N4 N8 P4 P12 R3 R4 R8 T4 Y4 Y5 AA2 AA4 AA8
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSSQ VSSQ VSSQ VSSQ VSSQ
H4 J4 K4 P2 U4 V4 W4
VSSCA VSSCA VSSCA VSSCA VSSCA VSSCA VSSCA
A3 A8 A12 B2 B7 B11 C3 C5 C8 C10 C12 C13 D7
VSSM VSSM VSSM VSSM
A2 A13 B1 B14 D2 D3 D4 D5 D6
VSF VSF VSF VSF VSF VSF VSF VSF VSF
VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM
A7 RFU
VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1
F3 F4 F9 G5 AA3 AA5 AB3 AB4 AB9
VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2
F5 F8 J5 K5 L2 L5 M5 N5 P5 P8 P11 R5 T5 U5 V5 W5 AB5 AB8
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
G9 H8 H12 J11 K10 K12 L8 L9 M10 M12 N11 R11 T10 T12 U8 U9 V10 V12 W11 Y8 Y12 AA9
2
F u 2 . 2
1 0 4 C 1
F n 0 0 1
2 0 4 C
GND GND
DVDD12_EMI
VDD2 :Core 2
2 3 0 4 C
F 4 u 0 2 . 4 2 C
F 6 n 0 0 0 4 1 C
5 0 F 4 u C 7 . 4
F 8 n 0 0 0 4 1 C
F 7 n 0 0 0 4 1 C
GND
GND
G ND
G ND
GND
eMMC
LP-DDR3
2. VCCQ :IO Voltage 1.7v~1.95v (low voltage range)
R404
B3 B12 B13 C4 D8 A4 B6 B9 C7 C11 A11
F u 7 . 4
GND
GND
0 VIO18_PMU
B4 A5 A10 C9 B5 C6 B10 A9
EMMC_DAT7 EMMC_DAT6 EMMC_DAT5 EMMC_DAT4 EMMC_DAT3 EMMC_DAT2 EMMC_DAT1 EMMC_DAT0
CS0# CS1#
[2] [2] [2] [2] [2] [2] [2] [2]
U3 T3
ECS0_B [2] ECS1_B [2]
CKE0 T2 CKE1 R2
ECKE [2,4] ECKE [2,4]
CLK P3 CLK# N3
EDCLK [2] EDCLK_B [2]
T9 R9 M9 N9 Y9 W9 H9 J9
EDQS0 [2] EDQS0_B [2] EDQS1 [2] EDQS1_B [2] EDQS2 [2] EDQS2_B [2] EDQS3 [2] EDQS3_B [2]
R10 DM0 N10 DM1 DM2 W10 DM3 J10
F u 1 1 1 4 C
F n 0 0 1 2 1 4
GND C
2 3 1 4 C
F 4 u 1 2 . 4 2 C
F n 0 0 1
1
GND
GND
EDQM0 [2] EDQM1 EDQM2 [2] EDQM3 [2]
VREFCA M2 VREFDQ P13 AB14 AB13 AB2 AB1 AA14 AA1 A14 A1
0
F u 2 2 . 0
R405
EMMC_CLK [2] EMMC_RST [2] EMMC_CM D [2]
DAT7 DAT6 DAT5 DAT4 DAT3 DAT2 DAT1 DAT0
DNU DNU DNU DNU DNU DNU DNU DNU
VEMC_3V3_PMU 2
0 1 9 4 0 C 4 C 1
CLKM B8 RST C2 CMD A6
DQS0 DQS0# DQS1 DQS1# DQS2 DQS2# DQS3 DQS3#
GND
1. VCC :Core Voltage 2.7v ~ 3.6v
K2 VDDCA VDDCA N2 VDDCA U2 VDDCA V2 VCC VCC VCC VCC VCC VCCQ VCCQ VCCQ VCCQ VCCQ VCCI
F n 0 0 1
1
EVREF [2]
F u 7 . 4 5 1 4 C
GND
F n 0 0 1 6 1 4 C
GND
ODT P10
L P E M R + D 3B A 8T 1Q C 9H U
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Receiver Ear Earphone phone Audio c los e to I C
s ame powe r domain c los e to I C
close to connector
R501
[3] AU_HSP
1 0 5 C
F P 0 0 1
2 0 5 C
F P 3 3
3 0 5 C
0
R506
[2] EINT11_HP
Reserve bead+C footprint forFM
REC501
R502
(1) CTIA:L-R-G-M
VIO18_PMU F P 3 3
AUDIO-REC-MRFD1206A011A18
[3] AU_HSN
470K
R505
close to connector
performance tuning
1 2
0 [5] HP_MP3L-OUT V 5 S N 9 D 1 0 S 5 E - S S V V T T D S E
1
BEAD501 1800ohm BEAD502 1800ohm
3
[5] HP_MP3R-OUT
C504 22uF
F N
F N
6 0 5 C
7 0 5 C
[ 5] HP_MIC
R503 100
C505 22uF
R504
0 1 5 C
F u 1 . 0
BEAD503
47K TP-0.8MM TP1
1800ohm
BEAD504
1800ohm
BEAD505
1800ohm
HP_MIC-1 HP_MP3L L-1 -1
FM_ANT-1
1
1
1
1
1
AUDIO-EAR-PH12-6B05F35D [5] HP_MP3R-1 [5] HP_MP3L-1 EAR_DET
[5]
[5]
1 1 0 5 R V
C
TP-0.8MM TP5
[5]
3 4 5 2 6 1
C542
[5] FM_ANT-1
9 0 5
8 0 5 C
[5 ]
TP-0.8MM TP-0.8MM TP-0.8MM TP2 TP3 TP4
EAR_DET [5] HP_MP3R 3 R -1 [5]
F P 3 3
F P 3 3
100
2
[5] HP_MIC-1
4.7PF J501
2
R507 470 2 0 5 S V T
3 0 5 S V T
R508 470 m h o 0 2 2
4 0 5 S V T F N 1 1 1 5 C
F N 1 1 4 5 C
Handset Microphone
R509
0
R510
0
FM_ANT [13]
6 0 5 D A E B
FM_RX_N_6572 [13]
MICBIAS0
Single via to GND plane 1 2 5 R
K 1 Close to
Close to
MIC
BB K 5 . 1
2 2 5 R
C522 [3] AU_VIN0_P 100nF
C524
C523
4.7uF
F P 0 0 1 / C N
[3] AU_VIN0_N 100nF 3 2 5 R
K 5 . 1
4 2 5 R
K 1
F P 3 3 / C N
F P 3 3 / C
5 2 5 C
6 2 5 C
[6] AU_VIN0_P-1
7 2 5 C
[6] AU_VIN0_N-1
N
Earphone MICPHONE
Analog Switch VBAT
U502
3 COM1 R514
5 NC1
1K [5] HP_MP3L-OUT
V+
IN1 4
R515
7 NC2
AU_HPL [3,5,10]
NO2 10 IN2 8 7 1 5 R
K 0 0 1
8 1 5 R F p 0 8 6
0 7 4
0 2 5 C
9 1 5 R
1 2 5 C
0
F p 0
100nF
1K
F P 0 0 1
7 to 8 6 close codec 4
close to codec
C515 4 1 5 C
GPIO_0 [2] GPIO_0 [2]
C513
C517
4.7uF via
m h o 0 6
Close to EarJack 33PF
1.5K
C516 33PF HP_MIC [5]
[3] AU_VIN1_P 100nF 3 1 5 R
K 1
togetherthen single via to main GND
IN=0, COMConnected to NC; IN=1, COMConnected to NO;
C533 4.7uF
3 A
D2
1 3 5 C
R525
3K
R526
3K
33nF
C1
F u 2 . 2
D1
2 3 5 C
B2
B1
A1 A2 A4
[2] GPIO5_AUDIO_PA_EN
7 2 5 R
K 0 0 1
220PF 2
C530 1
C1P
D D V
3 B
C534 100nF
D D V
C1N C2P
U501
4.7uF
PVDD
C535
VOP
VON
INP
Close to SPK
D3
C2N C2N
B4
BEAD507220ohm
D4
SPK_P [6]
BEAD508 SPK_N [6]
220ohm
INN SHDN
D D D N N N G G G 2 3 4 C C C
to GND plane GND
R512
[3] ACCDET
F u 2 . 2
C529
[3,10] R520
should tie togetherand single
K 1
AU_VIN1_N1
[3] AU_VIN1_N
AU_HPR
GND of C(4.7uF) and headset
Cl os e t oMI C
C512
1
D N G
1 0 5 B F
[3,5,10] AU_HPL
Cl os e t o BB
C519 0.1uF
6
NO1 2
SWITCH-ANALOG-SGM5223YWQ10/TR
C528 33nF
1 1 5 R
9 C OM2
1K
VBAT
MICBIAS1 0 0 3
1uF
GND
[5] HP_MP3R-OUT
K-Class Aud io PA
6 1 5 R
C518
together then single via to main GND
AUDIO-AMP-AW8736
F n 1
F n 1
6 3 5 C
7 3 5 C
8 3 5 C
F P 3 3 / C 9 3 N 5 C
F P 3 3 / C N
F P 0 0 1 / C N
0 4 5 C
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05_AUDIO
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CTP
Backlight LED Driver TP-0.8MM TP-0.8MM TP7 TP6
TP-0.8MM TP-0.8MM TP8 TP9
ĬÈÏ3*3· â×°
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