SAP-1 Simple as Possible Computer Schematic Diagram

Cp Ep Lm CE Li Ei La Ea Su Eu Lb Lo

T1 T2 T3 T4 T5 T6

OP0

OP1

OP2

OP3

OP4

OP5

OP6

OP7

VCC

U24:A 1

VCC

3

CLR

? ? ? ? ? ? ? ? ? ? ? ?

SW5

W7 W6 W5 W4 W3 W2 W1 W0

? ? ? ? ? ?

2

ADR3 ADR2 ADR1 ADR0

START

Clear/Start D7 D6 D5 D4 D3 D2 D1 D0

U24:B CLEAR

4 6

? ? ? ? ? ? ? ?

CLR

5

VCC

D7 D6 D5 D4 D3 D2 D1 D0

ADR3 ADR2 ADR1 ADR0

7400

U24:C VCC 8 7 6 5 4 3 2 1

SW3

8

ON

10 OPCode / Data Switches

OFF

Address Switch

SW4

SW6

WEram Write Memory

LOW

Single Step

U24:D

9 10 11 12 13 14 15 16

4 3 2 1

ON

OFF

5 6 7 8

SW1

9

VCC

HIGH

12 11 13

VCC Note: The RAM has inverting outputs so this switch has also been inverted to enter the correct data. UP = Logic 0 input = Logic 1 Output from RAM DOWN = Logic 1 input = Logic 0 output from RAM (Observe W-Bus indicators for correct value)

SW2

1 2 13

12

U26:A 1

VCC

U26:D

3

SW8

VCC

U25:A HLT 7400

2

Ep ENmar

SW7

ENpc

U27:A

U27:B

13 11

Manual

1

2

3

4

Manual/Auto

Program/Run

U27:C

U26:B

CE

Auto

ENram Note: This extra switch was added to isolate the output of the Program Counter from the W-bus when entering data, otherwise a logic contention will occur.

Program/Run

CLK

12

U25:B

4 6

VCC

3 4 5

HLT

5

5

6

CLK

6

Note: The 555 timer circuit has been substituted with a virtual clock source to speed up the simulation.

U25:B(C) INIT=LOW START=0 COUNT=-1 CLOCK=1

W7 W6 W5 W4 W3 W2 W1 W0

Cp 74LS107 1

J

CLK

K

6

Q

K

3

74LS107

Q

J

9

CLK

11

2

Q

K

1

5

Q

8

J

12

9

CLK

4

6

Q

13

4

8

10

R

J

13

Q

74LS107

Q

12

CLK 2

5

R

Q

U2:B

CLK

11

K

10

74LS107 3

U2:A

R

U1:B

R

U1:A

U3:D

74LS173 Accumulator

D0 D1 D2 D3 3 4 5 6

3 4 5 6

Q0 Q1 Q2 Q3

D0 D1 D2 D3

U10

CLK OE1 OE2 E1 E2 MR

14 13 12 11

7 1 2 9 10 15 74LS173 Accumulator

Q0 Q1 Q2 Q3

ENpc

U11

CLK OE1 OE2 E1 E2 MR

14 13 12 11

11

74LS126

CLK La

7 1 2 9 10 15

CLK La

13

8

10

6

4

3

1

U3:C

12

U3:B

9

5

CLK Ea

11 12 13 14

3

2

3

5

6

2

Q3 Q2 Q1 Q0

4

74LS173 Memory Address Register

4

U4

D3 D2 D1 D0

15 10 9 2 1 7 MR E2 E1 OE2 OE1 CLK

1

Ea

1

Lm

5

10

10

6 5 4 3

6

ADR0 ADR1 ADR2 ADR3

8

9

9

13

13

8

ENmar

4B 4A 3B 3A 2B 2A 1B 1A

74LS126 Accumulator Output

1Y 4

7

6 2 15 11

U16

C0

A0 A1 A2 A3

C0

B0 B1 B2 B3

5 3 14 12

7

6 2 15 11 B0 B1 B2 B3

5 3 14 12 A0 A1 A2 A3

Carry

U17

C4

12

74LS126

10

13 11

8

4 6

1 3

13

9

5

2

12

9 8

3

10

Eu

6 5 4 3

Q3 Q2 Q1 Q0

74LS173 Instruction Register (Address)

4 6

1

11

U9

U18:D

74LS126

I7 I6 I5 I4

6 5 4 3

5

2

11 12 13 14

U19:D

D3 D2 D1 D0

MR E2 E1 OE2 OE1 CLK

74LS173 Instruction Register (OPCode)

9

4 1 13 10

S0 S1 S2 S3

C4

Carry

15 10 9 2 1 7

11 12 13 14

U8

74LS283 Full Adder (MSB)

9

S0 S1 S2 S3 4 1 13 10 CLK Ei Li

11

8

6

3

11

8

6

3

11 9 7 5

11 9 7 5 CLK Li CLR

Q3 Q2 Q1 Q0

13 74LS86

74LS283 Full Adder (LSB)

15 10 9 2 1 7

12

U14:D

74LS86

Su

MR E2 E1 OE2 OE1 CLK

10

9

5

1

U15:D

Q4 Q3 Q2 Q1

74LS89 16 X 4-bit RAM

4

Su

13

12

10

9

5

4

1

U7

WE ME A3 A2 A1 A0 D4 D3 D2 D1

74LS89 16 X 4-bit RAM

Q4 Q3 Q2 Q1

WE ME A3 A2 A1 A0 D4 D3 D2 D1

U6

2

Su

3 2 13 14 15 1 12 10 6 4

ENram WEram

2

3Y

2Y 7

9

U12:D

74LS126 Accumulator Output

D3 D2 D1 D0

3 2 13 14 15 1 12 10 6 4

ENram WEram

12

13 14 10 11 6 5 3 2 12

D7 D6 D5 D4

11

12

U13:D

U5 74LS157 2-1 Multiplexer

4Y

E A/B

15 1

11

D3 D2 D1 D0

74LS173 B Register (MSB)

3 4 5 6

3 4 5 6

Q0 Q1 Q2 Q3

74LS173 B Register (LSB)

Q0 Q1 Q2 Q3

U20

CLK OE1 OE2 E1 E2 MR

D0 D1 D2 D3

7 1 2 9 10 15

7 1 2 9 10 15

14 13 12 11

CLK Lb

U21

CLK OE1 OE2 E1 E2 MR

D0 D1 D2 D3

14 13 12 11

CLK Lb

7 1 2 9 10 15

D0 D1 D2 D3

CLK OE1 OE2 E1 E2 MR

U23

U22

CLK OE1 OE2 E1 E2 MR

14 13 12 11

7 1 2 9 10 15

CLK Lo CLR

74LS173 Output Register

3 4 5 6

3 4 5 6

Q0 Q1 Q2 Q3

74LS173 Output Register

Q0 Q1 Q2 Q3

D0 D1 D2 D3

14 13 12 11

CLK Lo CLR

OP0 OP1 OP2 OP3

I4

Ring Counter

U31:A 2

1 CLK

U37:B

U38:A

74LS107

74LS107

74LS107

2

Q

6

Q

3

Q

2

Q

5

Q

J

12

CLK

11

K

1

J

9

CLK

4

K

8

J

CLK 6

4

K

Q

K

8

3

Q

74LS107 1

J

9 2

Q

Q

9

CLK 6

4

K

8

J

12

CLK

11

5

Q

11

K

10

13

10

5 10

6

Q

12

CLK

U31:C

5

R

1

J

R

Q

U38:B

R

U37:A

74LS107

R

3

3

U36:B

74LS107

13

4

U36:A

R

U31:B

R

CLR

U31:D 12

13 T6 T5 T4 T3 T2

13

T1

U35:E

1 2

U32:A

Control Matrix

12

Instruction Decoder

U35:D

U35:A 6

1

2

4 5

LDA ADD SUB

U35:B

U39:D 1 2

U33:A

U40:D

U41:D

10

9

5

4

2

1

13

12

10

9

5

4

2

1

13

12

10

9

5

4

2

1

13

12

10

9

5

4

2

1

13

12

1

10

4

12 13

9

3

5

8

OUT

4

U32:B

2

9 10

U42:D

U43:C

U35:C 6

5

8

9

6

U33:B

8

6

3

11

8

6

3

11

8

6

3

11

8

6

3

11

U44:B

U45:A

U45:B

5

4

2

1

3 4 5

1 2 13

12 13

U44:A

U46:A

U46:B

U47:C

U47:F

Li

Ei

U48:B

La

Ea

U48:A 2

12

10

8

4 CE

6

2 Lm

6

U47:E U47:D

Cp Ep

3

3 1

13

6

9

11

12

U47:B

Su

4

U47:A

5

3

1

6

HLT

8

U34:A 6

4 5

9 10

4 5

8

12 13

1 2

8

U35:F 1 2

9 10

6

4 5 3

I5

13

I6

11

I7

Note: These pull-up resistors are necessary because the outputs of the 74LS89 (substitute for the 74LS189) are open collector.

OP4 OP5 OP6 OP7

VCC

10

2

CLR

U3:A

Eu

Lb

Lo