Samsung Plasma Training Manual

May 10, 2017 | Author: edsel72 | Category: N/A
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 `                   2-1 Drive Description on SMPS 2-2 Operation Explanation of Driving Circuit 2-3 Logic-Main Board 2-4 Scaler Board

`           [PDP Mod ule Pic ture ] Y buffer "Upper"

SMPS X- MAIN

Y- MAIN

Lo g ic - Main

Y buffer "Lo wer"

E- buffer

F- buffer

COF x 7

G- buffer

Ö         `  [ ¢ ¢¢     ¢ ! ‰ It is the supplier to provide voltage and current to work the drive voltage and panel in each board.

[.V "# $ ‰ It makes the drive wave form by switching FETs to Timing Controlle coming from logic-board and supplies X electrode of panel with the drive wave form via connector.

[.v "# $ ‰ It makes the drive wave form by switching FETs to Timing Controller coming from the logic-board and provides Y electrode of panel with the drive wave form via Scan Driver IC on Y buffer board in order.

[ %"

"# $

‰ It process image signal and performs buffering of the logic-main board (to create XY drive signal and output) and the address driver output signal. Then it supplies the output signal to the address driver IC(COF Module).

Ö           [. %" &$''%! ‰ It delivers the data signal and control signal to the COF.

[.v&$ &' ! ‰ It is the board to impress the scan waveform on the Y board and consist of 2 boards (upper board and lower board). 8 Y-buffers are fixed at the scan driver (STV7617 of STC corp. ‰ 64 or 65 Output).

[. #  r ‰ It has functions to remove noise(low frequency) coming from AC LINE and prevent surge. It gives serious effects on the safety regulations (EMC, EMI) according to AC filter.

[.   ! ‰ It impress the Va pulse to the address electrode in the address section and forms the address discharge by electric potential difference with scanning pulse to be dismissed by the Y electrode. It is made in the form of COF and one COF consists of 4 Data Drive IC (STV7610A ‰ 6 Output), otherwise single scan is made of 7 COF.

 ¢$&&$   r  



   r 

   

  

r

 ( ¢  A1

A2

A3

A4

A5

A6

A7

ú Y1 X Y2 X

q

ú

Y4 8 0 X

Re fe r e n c e - A1 ,A2 , , , : Add r e s s Ele c tr od e - Y1 ,Y2 , , , : S c an & S us ta in Ele c tr od e - X : Com m o n & S us ta in Ele c tr od e

$¢¢ $"#

"    '    

¢&¢"# $"#

       ¢  

` ¢&"  " % $¢¢ ¢!

·  

˜  °  

°         °    °   °  

 



˜  ° 

˜  °   

  °  

 °  

°  

  °   °  

°    

$  ¢$&&$ ¢!

scan line

SF1 1 2 .. ...

SF2

SF3

SF4

SF5

SF6

SF7

SF8 sub-field address

1T 2T 4T 8T 16T

32T

64T

128T

sustain

480

1TV field (time) Reset Period

D X Y1 Y2 Yn

Address Period

Sustain Period

`  ¢  )  

scan line

SF1 1 2 .. ...

SF2

SF3

SF4

SF5

SF6

SF7

SF8 sub-field address

1T 2T 4T 8T 16T

32T

64T

480

1TV field (time)

128T

sustain

        [Whole Bloc k Diagra m] Y- Ma in B'd

X- Ma in B'd

Dis p la y

Lo g ic B'd

Da ta DRAM

Drive r

PDP Panel

Ro w Drive r

852 X 4 80 Pixe ls

Timing Inp ut Da ta

Da ta Co ntro lle r

Drive r Timing

Pro c e s s o r

Co ntro lle r

S can Timing

853 X 3 X 480 Ce lls

X- Puls e Ge ne ra to r

Y- Puls e Ge ne ra to r Co lumn Drive r

Clo c k : Clo c k : 27MHz

Clo c k :

20MHz

60MHz

40MHz

Po we r B'd

Po we r S up p ly

LVDS Ana lo g B'd

Dig ita l B'd

Mic o m

Ima g e Enha nc e r

De inte rla c e r

Aud io Pro c e s s o r

Ima g e S c a le rr

Vid e o De c o d e r

Vid e o S /W

AD Co nve rte rr

TMDS Re c e ive rr

Co mb Filte r

Tune r

AC Po we r S o urc e 220V

`  ¢  )   [ K      ]

CN805 (10 P)

CN805 (10 P)

S MPS CN806) CN812 (5P) CN802 CN803 (10 P) (11 P)

Y- Ma in

LA03 (31 P) CN201

CN201

CN401

CN806)

EF1

CN111 CN601

Digital

CN802

CN804 (9P)

CN801 (10 P)

CN804 (9P)

X- Ma in

CN803 (10 P)

Log ic

CN101

CN402

CN403

FE1 FG1

GF1

CN101 CN102 CN103

CN801

CN101

AC Inle t

Ana log

"# #"%&$"# [ S c a le r Dgita l Ī Log ic (CN601) ]

[ S c a le r : Ana log Ī Dgita l ] CN101(Co ntro l)

CN102(Vid e o /S ync )

CN103(Vid e o /S ync )

NO

PIN Name

NO

PIN Name

1

GND

16 Tx CLK Out+ / Rx CLK In+

2

GND

17

GND

NO

PIN Name

NO

PIN Name

NO

PIN Name

1

GND

1

ANAL_YCOMB

1

ANAL_YCOMB

3

Tx Out0- / Rx In0-

18

GND

2

S CL1

2

GND

2

GND

4

Tx Out0+ / Rx In0+

19

Tx Out0- / Rx In0-

3

S DA1

3

ANAL_CCOMB

3

ANAL_CCOMB

5

GND

20

Tx Out0- / Rx In0-

4

GND

4

GND

4

GND

6

GND

21

GND

5

S AFT

5

ANAL_Y2

5

ANAL_Y2

7

Tx Out1- / Rx In1-

22

GND

6

GND

6

GND

6

GND

8

Tx Out1+ / Rx In1+

23

GND

9

GND

24

GND

7

MUTE

7

ANAL_PB2

7

ANAL_PB2

10

GND

25

RES ET_MN

8

GND

8

GND

8

GND

11

Tx Out2- / Rx In2-

26

GND

9

MAFT

9

ANAL_PR2

9

ANAL_PR2

12

Tx Out2+ / Rx In2+

27

IIC S CL2

10

GND

10

GND

10

GND

13

GND

28

GND

11

ANAL_CVBS

11

ANAL_H

11

ANAL_H

14

GND

29

IIC S DA2

12

GND

12

ANAL_V

12

ANAL_V

15 Tx CLK Out- / Rx CLK In- 30

GND

31

GND

"# #"%&$"# [ S MPS Ī X,Y- Ma in / Buffe r ]

[ S MPS Ī Ana log / Digital / Log ic ] CN801(An a lo g Tu)

CN802(Dig ita l Tu)

NO

Po we r

NO

Po we r

NO

Po we r

NO

Po we r

NO

Po we r

NO

Po we r

1

GND

1

THEM_D

1

D3 3V

1

D5V

1

D5V

1

Va

2

A33V

2

S TD_5V

2

D3 3V

2

VG

2

VG

2

Va

3

GND

3

GND

3

GND

3

GND

3

GND

3

NC

4

GND

4

PS _ON

4

GND

4

GND

4

Vs c a n

4

GND

5

AMP12V

5

NC

5

D5V

5

VE

5

GND

5

GND

6

AMP12V

6

GND

6

GND

6

GND

6

Vs e t

7

GND

7

GND

7

IC2

7

GND

7

GND

8

D12V

8

D3 3V

8

IC2

8

VS

8

GND

9

GND

9

D3 3V

9

PS _ON

9

VS

9

VS

10

D6V

10

GND

10

GND

10

VS

11

D6V

[ FAN B+:For VMB] CN807/ 811(FAN) NO

Po we r

1

12V

2

GND

5

Fa n_D

CN803(Lo g ic )

CN804(X- Ma in)

CN805(Y- Ma in)

CN806/ 812(Buffe r)

`

*    ¢ ¢ [ S MPS Blo c k Dia g ra m] HOT AC input

Vs (+ 8 5V)

COLD

3 8 5Vd c b u s

DC/DC Converter

Vs et (+ 9 5V)

DC/DC Con ve r te r

Ve (+ 11 0 V)

90 Vú2 6 4V EMI

Bo o s t PFC

Vs _S witc hing

S tag e

S tag e

FILT ER

Retur n

NOIS E FILTER

PWM c o ntrol S tag e

DC/DC Con ve r te r

Va_S witc hing

Vs c an (+ 78 V)

Va(+ 7 9 V)

S tag e

Retur n

Aux ilia ry PWM c o ntrol

Vcc

S tag e

S tag e VT (+ 3 3V 0 03 A) 1 2V(+ 12 V 0 7A) S tand_By

5V

A1 2 V(+ 1 2V) V_dig ital V_analo g

PS - ON/Relay S ignal

Cho ppe r REG

D5 V (+ 5V)) Retur n

S witc hing S tag e MAG- AMP

D3 3 V (+ 3 3 V)

Reg

Vg (+ 15 V)

Vs Log ic _ON Ac tive_High

1 2 V Amp(+ 12 v) A6 V(+ 6V) PWM c o ntrol

COLD

HOT

S tag e

D6 V(+ 6V)

COLD

     ¢ ¢ 1. Overview SMPS used in PDP 42" developed into the compact-sized with high efficiency. The asymmetrical half bridge and the flyback converter are applied into all output. To comply with the harmonic restrictions, it takes the power factor improvementcircuit, which converts AC into the high DC and uses as the input of another converter controller.

2. Input controller SMPS works in whole section of AC 0~264V. It is possible to start in the AC 0 and can restart with new input voltage, even in interruption of electric power. STD_5V comes out when AC is impressed

3. Output Controller Given SMPS have 15 output voltages. The following shows the specification of output voltage and output current in case of their successive drive.

     ¢ ¢ Name

Vo ltag e

Curre n t(Max ) Us ing in P DP Driving

VS

+ 75V ~ 1 00V

4 5A

S us tain Vo ltag e

VA

+ 65V ~ 8 0V

0 6A

Addres s Vo ltag e

Name

Vo ltag e

Curre n t(Max ) Us ing in P DP Driving

A12V

+ 1 2V

0 3A

D6V

+ 6V

0 1A

A6V

+ 6V

0 1A

D5V

+ 5V

1 0A

+ 3 3V

4 5A

VS CAN

+ 65V ~ 1 00V

0 1A

VS ET

+ 80V ~ 1 00V

0 1A

D3 3V

VE

+ 100V ~ 120V

0 1A

12VAMP + 1 2V

1 7A

VG

+ 15V

1 5A

VT

+ 3 3V

0 003A

D12V

+ 12V

0 1A

S T D_5V

+ 5V

0 6A

Driving Vo ltag e o f F e t

IC Driving Vo ltag e o f Lo g ic

Amp Vo ltag e o f Audio

S tandby fo r Re mo te Co ntro l

3-1. Overvoltage protection It has circuit to maintain normal voltage, additionally with circuit for sensing overvoltage, so it means any overvoltage does not give impacts on other output controller. SMPS prevents overvoltage in the latch mode. VS(85V) works protection function more than 100V, over 4V for VA(75V), over 8.2V for D6V, over 4.7V for D3.3V

     ¢ ¢ 3-2. Short circuit and overvoltage protection It forms definition that in the short circuit of output controller the output impedance is lower than 300mohm. If the VS output have a short circuit in case of given SMPS, SMPS stops its working. Even in the case of short circuit between main output and STD_5V, SMPS does not break down. When the short circuit is removed, it restarts.

4. Detail Description  AC-DC Converter It converts AC into DC by using the power factor improvementcircuit. This converter was designated to control the high frequency noise, with the function to improve the power factor. This part becomes input controller of another constant-voltage.

[ P F C Drive F ET (S P W4 7 N6 0) Dra in P u ls e ]

[ P F C Drive F ET (S P W4 7 N6 0) Ga te P u ls e ]

     ¢ ¢ A Auxiliary Power It is the part to supply power of mycom for remote control. When the power is on, it will work, which means that MICOM is on standby. This output part is stand_by voltage. When the power-on signal from remote control impress, it works main power panel of SMPS via stand_by voltage.

´ Configuration of VS output Major part of PDF SMPS outputs 85V 5A. It takes asymmetrical half bridge converter and connects 2 converters with 85V output in parallel, which increases efficiency than one 85V converter, on the other hand, decreases its size.

[ Dr i vi ng FET(2SK2372) Dr ai n Pul s e&Cur r ent wave

]

[ Driving FET (2 S K2 3 72 ) Ga te P uls e ]

     ¢ ¢ - PWM Part It uses PWM part of ML4824, but there are some points to take cautions. As this part is synchronized with the PFC part, PWM wave in the current mode drive is induced via the current sensor resistance or current transformer, and shows the current flowing in the output controller.

â DC-DC Converter ‰ Input of VSCAN, VSET and VE belongs to the VS part

[ VS ET Puls e ]

[ VE Puls e ]

[ Vs c an Puls e ]

     ¢ ¢ ù Output (VA,Multi Outputs) Pulse

[ Va Ma in P uls e ]

[ Multi Outputs Ma in P uls e ]

   

 ¢ ¢ Po we r ON Che c k c o rd c o nne c tio n OK

NG

Chec k the IC2,D2 8

S TB_5V

OK

Chec k the IC1,Q1 ,Q2

PFC

OK

OK

PFC

NG

Chec k the IC35

NG PFC

Chec k the IC7

   

 ¢ ¢

NG

VS

Che c k the Q6 ,Q8

OK

Vs c an VE,Vs e t

Che c k the IC16 , IC17 , IC18

OK

Che c k the Othe r boa rd ( Ima ge Board or Drive r Board ) or Ca ble

2-2. Operation Explanation of Driving Circuit ` Overview of Driver Circuit 1) Definition of Driver Circuit The driver circuit division drives the panel with the proper wave form (high voltage pulse) to develop image on the outside terminal division (X electrode group, Y electrode group, Address electrode). High voltage switching pulse is made by MOSFET combination.

2) Working Principle of Driver Circuit To develop image on the PDP, the voltage should be impressed into the X, Y and ADDRESS electrodes (which are component of each pictorial element) under the proper conditions. The driver wave form which is currently applied to is ADS (Address & Display Separate‰ Driving method to work by dividing address and constant-current section ) Based on this method, the discharge to be done in the pictorial element of PDP can be divided into 3 types as follows.

' A  +  (    *      (   *     (   ( (  * ! ‰ It is the discharge produced by difference between the positive electric potential of address electrode (normally, Va impressed voltage of 70~75V +Positive Wall charge) and negative electric potential of Y electrode (GND level impression+ Negative Wall charge).

     *   '    + "        (   *       *  (     " (,      (! ‰ It is the Self Sustaining Discharge made by combining the electric potential of coherent pulse, normally 160-170Volt, which alternates the X electrode with Y electrode in the sustain section, with the wall voltage according to the pictorial element condition changed by if the former discharge exists or not. That is to say, it works according to

(     (   (  ,       

   !       

If the wall voltage formerly exists in the pictorial element(i.e., the pictorial element is on), the discharge makes forms again because the voltage higher than one of the discharging starting time is impressed by combination of the wall voltage and of the next impressed constant-current. While if the wall voltage does not exist in the pictorial element (i.e., the pictorial element is off), the discharge does not form because the voltage could not reach to the level of the discharging starting time, only with constant-current.

     *   '   +  *  (       * '    (   (    (         !         -   (      * (    *  (        * (     *     (     $( .* (     

‰ The purpose of intialization (Erasing) discharge is to make wall voltage within the the whole of Pixels. In other words, the erasing discharge must make difference between wall voltages uniform depending on whether or not the sustain discharge exists in the previous state. Namely it must remove the wall voltage formed by the sustain discharge and supply ions or elements by causing discharge for removing the wall voltage. In the other words, To remove the wall voltage, limit the time when polarity of the wall voltage is reversely charged by causing discharge or prevent polarity form being reversely charged by supplying appropriate quantity of ions or elements through forming weak discharge Ölow voltage of erasing]. There are two types of the weak discharge Ölow voltage]as known so far. 1) Log Waveform adopted by the F-company 2) Weak erasing discharge by the Ramp Waveform largely adopted by Matsushita company, etc. Outside applied voltage is adjusted depending on difference of wall voltage within Pixel, since discharge is formed when the sumof the existing wall voltage remained and the voltage on a rising waveform exceed the driving beginning voltage, by slowly applying the rising slope of the erased waveform for these two methods. In addition, weak discharge is formed since the strength of applied voltage is small.

     *   3) Essential factors for driving board operation - Supplied from power board and the optimum value may somewhat differ from the below cases.

' Vs

‰ 85V

- Sustain

' Vset ‰ 60V ~ 70V

- Y Rising Ramp

' Ve

- Ve bias

‰ 110V

' Vscan ‰ 70V ~ 80V - Scan bias ' Vdd ‰ 3.3V

- Logic signal buffer IC

' Vcc ‰ 15V

- FET Gate drive IC

' Logic Signal ‰ Supplied from logic board ‰ Gate signal of each FET

* .* ( ¢   ( Y ris ing

Y s us tain

Ra mp

P uls e Y falling Ra mp

Y s c an P uls e X s us tain P uls e

Addre s s P uls e

A1, 2 X Y1, 2

Addr es s (=Dat a) El ect r ode

Vs

85V

Ve

110V

Common & Sus t ai n El ect r ode

Vs et

95V

Va

79V

Scan & Sus t ai n El ect r ode

Vs can

85V

      ' Y Rising Ramp Pulse Outside voltage of about 3 0V~400V is applied to the Y electrode in the Y Rising Ramp zone, and weak discharge begins if respective gap voltage equals to the discharge beginning voltage. Negative Wall charges accumulate on the Y electrode and the Positive Wall charges on the X electrode in the whole while weak discharge is maintained.

' Y Falling Ramp Pulse Most of Negative Wall charges accumulated on the Y electrode by the X bias of about 200V are used to remove Positive Wall charges in the Y Falling Ramp zone, and most of Positive charges accumulated on the (0V) Rising Ramp zone toward the address electrode are maintained, having distribution of wall charges beneficial for the subsequent address discharge.

      ' Y Scan Pulse Y scan pulse is called as injection pulse, and selects the Y electrode one by one (Line-at-a-time). In this case, Vscan is called as Scan bias. For the electrode line with the Vscan voltage applied, voltage of about 70 Volt (Vscan) is applied, and voltage of 0 Volt(GN0) is applied. However, since Negative Wall charges accumulate on the Y electrode by the application of Ramp pulse and Positive Wall charges accumulate on the address electrode, voltage of more than the discharge beginning voltage is applied to the cell where address pulse(70V~75V) is allotted and thus address discharge occurs. Address time of the PDP is very long since both scan pulse and data pulse must be applied in line at a time.

' 1st Sustain Pulse The Sustain Pulse always begins from the Y electrode, it is because Positive Wall charges are formed on the Y electrode if address discharge occurs. The wall charges formed by the address discharge are less than those for the sustain discharge, and thus the strength of the initial discharge is weak. Sustain discharge usually become stable after 5~6 times of discharge depending on structure of electrode and environment. Therefore, the initial long sustain pulse is intended to form the initial discharge stable and form the wall charges much as possible as.

     *   1. Y buffer - To check whether there is failure of the Y Main, firstly check normal operation of the Y buffer. - After separating both the Y Main and the Y buffer connector, - Check forward voltage drop of 0.4V ~ 0.5V by diode check between OUTL and OUTH. - In addition, resistance between both ends is also more than several kȍ.

OUT L

OUT H

OUTL OUTH

OUTL

OUTH

     *   2. Y Main - After connecting both the Y Main and the Y buffer, check that output of one of OUT1~8 of the Y buffer is done as follows in application of power OUT1

OUT2

OUT3 OUT4 OUT6

OUT5

Ę You mus t check 1EA of Scan pul s e i s out put

     *   3. X Main - Check output of the TPOUT on the X board is done as follows in application of power

TPOUT

2-3. Operation Explanation of Logic Board [ Lo g ic Blo c k Dia g ra m] Vs St art Si gnal

I mage Si gnal

LA03 IIC (SCL, SDA)

X2000

CN803 Vs s t art U2004 27MHz LVDS SW2001 I mage Si gnal 8 bi t pe r DATA R G B 1 bi t pe r H, V SYNC

FPGA

Y CONTROL Y CONTROL CN201 28BV256K U2001

FRONT_XY U2005

60MHz 64M

28 636MHz X2002 OSC

SDRAM U2014

CY2305 U2003

EP20K400EBC652- 1

IIC VCC(3 3V) GND

Logi c Power 3 3V, 5V

64M CY2305 U2002

SDRAM U2013

X CONTROL X CONTROL

EPC2 U2011

EPC2 U2007

EPC2 U2006

RESET SPS10- MEM ASI C MEMORY CONTROLLER U2000

8 bi t per DATA R G B 1 bi t per H, V SYNC 1 bi t per DATA_EN, TSC, POL, SEN, SDA, SCLK _nRESET

CLK_XY(20MHz), SV_SYNC nRESET

CN101

Ci r cui t

40MHz X2001

I I C(SCL, SDA) CN2002 CN401

e-buff er

ADRV101~106 ADRV201~206 ADRV301~306 CLK, BLK, POL, STB

ADRV401~406 CLK, BLK, POL, STB

CN402

f-buff er

ADRV501~506 ADRV601~606 ADRV701~706 CLK, BLK, POL, STB

CN403

g-buff er

   #(  (

    



A





LOGIC BOARD ù

M O D E L

OP T ION S /W

REMARKS

S T AT US â

´

ON

Ex te rnal : 2,4 On

OFF

Inte rnal : 3 On

4 2" S D 1 2 3 4



 I t em



No 

LVDS connect or

Expl anat i on Connect or for recei vi ng RGB, H, V, DATAEN, DCLK encoded i n t he LVDS from i mage board

A

LED for operat i on check

LED t o s how t hat Sync, cl ock i s nor mal l y i nput i nt o t he l ogi c board

´ â

I 2C connect or 256K

Connect or connect i ng t he Key Scan Board t hat checks and adj us t s 256K dat a Eeprom t o s ave ʇ t abl e, APC t abl e, dri vi ng wavef orm t i mi ng and ot her opt i on, et c

ù

Y connect or

Connect or t o out put cont r ol s i gnal of t he Y dri vi ng board

X connect or

Connect or t o out put cont r ol s i gnal of t he X dri vi ng board



CN401(E- addres s buf fer connect or)

Connect or t o out put addres s dat a, cont r ol s i gnal t o t he E-buf fer board

 

CN402(F- addres s buf fer connect or) CN403(G- addres s buf fer] connect or)

Cnnec t or t o out put addres s dat a, cont r ol s i gnal t o t he F-buf fer board Connect or t o out put addres s dat a, cont r ol s i gnal t o t he G-buf fer board



Power connect or

Connect or t o recei ve power 95V] t o t he l ogi c board

 

Power fus e OPTI ON S/ W

Fus e at t ac hed t o power [5V] t o t he l ogi c board I nner / Out er cut -off S/ W

     Logic board is composed of a logic main board that generates and outputs the address driver output signal and the XY driving signal by processing image signal, and a buffer board that buffers the address driver output signal and delivers it to the address driver IC (COF Module).

Logi c Board

Funct i on - Pr oces s es I mage s i gnal (W/L, er r or di s per s i on, APC)

Logi c Mai n

- Out put s i mage s i gnal as addr es s dr i ver cont r ol s i gnal , dat a s i gnal buf fer boar d - Out put s t he XY dr i vi ng boar d cont r ol s i gnal

E Buf fer boar d

Buf fer Boar d

F Buf fer boadr

G Buf fer boar d

- Del i ver s dat a s i gnal and cont r ol s i gnal t o t he r i ght / r i ght COF - Del i ver s dat a s i gnal and cont r ol s i gnal t o t he mi ddl e/ l ower COF - Del i ver s dat a s i gnal and cont r ol s i gnal t o t he Ri ght / Lower COF

Remar ks

/

 

¢"(  !   DIGIT AL BOARD I C & SI GNAL BLOCK DI AGRAM

ANALOG Si gnal

CRYSTAL

CLOCK Si gnal

DI GI TAL Si gnal

TO LOGI C

FROM SMPS

DS90C385 Z86129 M 2 7 V 1 6 0

K4S643232E SNI

VPC3230

FLI 2200

CVBS

K4S643232E 20 25M K4S641632E

Y/ C

K4S643232E

K4S643232E

M27V160 ASI 500

K4S643232E

14 3181M

Y/ Pb/ Pr/ H/ V

SDA6000

AD9883 FROM CONTROL PCB

6M

VPC3230

BA7657

20 25M

Si I 161A 74HC4052

DVI L/ R

S- VHS Y/ C R/ G/ B/ H/ V

RS- 232

DVI

DVI SOUND

D- SUB

D- SUB L/ R

D- SUB Sound

S- VI DEO

DVI , D- SUB L/ R S- VHS L/ R

S- VI DEO/ VI DEO Sound

 

¢"(  !   ANALOG BOARD I C & SI GNAL BLOCK DI AGRAM CN8 01

CRYSTAL

ANALOG SI GNAL

DI GI TAL SI GNAL

CLOCK SI GNAL

FROM SMPS

18 432M

Y/ C CN1 01

UPD64083

20M

SUB WOOPER CVBS

CVBS

DVI , D- SUB L/ R

MSP3451

L/ R S- VHS L/ R

Y/ Pb/ Pr/ H/ V CN1 02

CXA2151 4M

S- CVBS TEA6425

M- CVBS

Y/ Pb/ Pr TA1101

BA7657

TUNER 2

TUNER 1

CN1 03 VI DEO- CVBS

VODEO

Y/ Pb/ Pr 1

COMPONENT1

Y/ Pb/ Pr 2

COMPONENT1 SOUND

COMPONENT2

COMPONENT2 SOUND

SOUND OUTPUT

RF I NPUT

Sub-woof er Out put

      1. UPD 64083 (COMB FILTER) I TEM

TV/ Vi deo/ S- Vi de o/ Component 1, 2(SD)

Component 1, 2(HD)

PC

DVI

VAPGAI N

4

4

4

4

VAPI NV

16

16

16

16

YPFP

3

3

3

3

YPFG

9

9

9

9

2. VPC 3230(M) ‰ Main VCD I TEM

TV/ Vi deo/ S- Vi de o/ Component 1, 2(SD)

Component 1, 2(HD)

PC

DVI

CONTRAST

43

43

43

43

BRI GHTNESS

47

47

47

47

PEAKI NG

5

5

5

5

CORI NG

0

0

0

0

LUMA DELAY

255

255

255

255

HPLL SPEED

1

1

1

1

YUV CONTRAST

29

29

29

29

YUV BRI GHTNESS

68

68

68

68

YUV SATCB

42

42

42

42

YUV SATCR

42

42

42

42

YUV TI NT

3

3

3

3

SATURATI ON

2000

2000

2000

2000

TI NT

32

32

32

32

      3. VPC 3230(S) ‰ SUB VCD I TEM

TV/ Vi deo/ S-Vi deo/ Component 1, 2(SD)

Component 1, 2(HD)

PC

DVI

PI P CONTRAST

43

43

43

43

PI P BRI GHTNESS

47

47

47

47

YUV CONTRAST

29

29

29

29

YUV BRI GHTNESS

68

68

68

68

LUMA DELAY

255

255

255

255

H POSI TI ON

0

0

0

0

V POSI TI ON

0

0

0

0

4. FLI 2200 (De-Interlacer) I TEM

TV/ Vi deo/ S-Vi deo/ Component 1, 2(SD)

Component 1, 2(HD)

PC

DVI

Y CLAMP

64

64

64

64

C CLAMP

512

512

512

512

Y DELAY

4

4

4

4

C DELAY

11

11

11

11

MOTI ON DETECT

48

48

48

48

      0 ¢"011 ƒ ¢ $ "# 2 ¢! I TEM

TV/ Vi deo/ S- Vi de o/ Component 1, 2(SD)

Component 1, 2(HD)

R CONTRAST

32

G CONTRAST B CONTRAST

32

R BRI GHTNESS

0

G BRI GHTNESS B BRI GHTNESS

0

TEXT ALPHA

1

TEXT THRESHOLD FI LTER ML

7

FI LTER MR

0

FI LTER FR FI LTER MC

16

FI LTER UC

0

FI LTER LC FI LTER YPASS

0

R GAMMA

32

G GAMMA B GAMMA

32

H POSI TI ON

0

V POSI TI ON H SI ZE

0

V SI ZE

0

OVERSCAN B OVERSCAN G

63

OVERSCAN R

63

32

0

0

0

0

32

0

63

PC

DVI

      3 ¢"011 È ¢ $ "! I TEM

TV/ Vi deo/ S-Vi deo/ Component 1, 2(SD)

Component 1, 2(HD)

PI P R CONT

32

PI P G CONT

32

PI P B CONT

32

PI P R BRI GHT

0

PI P G BRI GHT

0

PI P B BRI GHT

0

PI P FI LTER LC

0

PI P FI LTER ML

0

PI P FI LTER MR

0

PI P FI LTER UC

0

PC

DVI

) V`0`4  ## &V! I TEM

TV/ Vi deo/ S- Vi de o/ Component 1, 2(SD)

Component 1, 2(HD)

PC

DVI

GAI N-SEL CR GAI N CB GAI N Y GAI N

1 7 7 7

1 7 7 7

1 7 7 7

1 7 7 7

      5 #"   ! I TEM

TV/ Vi deo/ S- Vi de o/ Component 1, 2(SD)

Component 1, 2(HD)

BRI GHT OFFSET

0

CONTRA OFFSET

0

NR SCALE MAX

52

NR SCALE MI N

18

DE GAI N COR

3

DE GAI N CLI P

60

CE UPPER

240

CE CUTOFF

64

CE GAI N

48

WTE Y THRE

230

R CTL

2

SYNC MODE

1

PATT SEL

0

RED CONPENSA

616

BLUE CONPENSA

616

WTE GAI N

58

RAST VSI ZE

1023

RAST HSI ZE

895

SHARP OFFSET

0

PC

DVI

      6  6))7   *! I TEM

TV/ Vi deo/ S- Vi de o/ Component 1, 2(SD)

Component 1, 2(HD)

PC

DVI

R GAI N G GAI N

142 142

142 142

142 142

142 142

B GAI N R, CR OFFSET

142 60

142 60

142 54

142 60

G, Y OFFSET B, CB OFFSET Aut o Col or

48 64

48 64

54 54

48 64

`1   *! I TEM

TV/ Vi deo/ S- Vi de o/ Component 1, 2(SD)

Component 1, 2(HD)

PC

DVI

R DRI VE G DRI VE

140 130

140 130

140 130

140 130

B DRI VE R CUTOFF

120 0

120 0

120 0

120 0

G CUTOFF

0

0

0

0

B CUTOFF GAMMA GTS SET ERD MODE

0

0

0

0

1 0 2

RANDOM NOI SE

0

DI FF FI LTER APC APC SET APC VALUE

1 1 0 127

ACTI VE VPOS ACTI VE HPOS VSYNC POS

12 19 3

HSYNC POS VSYNC WIDTH HSYNC WIDTH

32 2 12

      ``  %¢" +   %"2¢ $ I TEM

TV/ Vi deo/ S- Vi de o/ Component 1, 2(SD)

Component 1, 2(HD)

LOG PATTERN

0

LOG HI GH LEVEL

255

LOG LOWLEVEL

0

ASI COLORBAR

0

PC

DVI

`   I TEM

TV/ Vi deo/ S- Vi de o/ Component 1, 2(SD)

Component 1, 2(HD)

PC

DVI

Remar k

PI X SHI FT

0

0 : OFF

1 : ON

SHI FT TEST

0

0 : mi nut e

1 : s econd

PI X NUMBER

2

Number of s hi ft ed Li nes hori zont al l y

SHI FT LI NE

1

Number of s hi ft ed Li nes vert i cal l y

SHI FT TI ME COUNTRY

4 0

Ti me fi xed at SHI FT TEST

TEMP PROTECT

0

SNI DEMO

0

0 : OFF

SNI THROUGH

0

0 : NOT THROUGH

VI DEO MUTE

10

I RC AFN

0

0 : for cus t omer

LANGUAGE

0

0 : Engl i s h

CUSTOMER

0

0 : CE

TUNER

0

0: 1 TUNER

0 : domes t i c

1 : USA 2 : Japan

1: ON 1 : THROUGH

Uni t : 100ms ec 1 : for mi l i t ar y

1 : Fr ench 1 : VMB 1: 2 TUNER

2 : Spani s h

¢ .* (  8  8!   " ¢ + )    " ¢ + )

ANALOG BOARD I C103(TEA6425D) PI N6(VI DEO-CVBS)

ANALOG BOARD CN102 PI N10(3D_C_OUT)

ANALOG BOARD CN102 PI N12(3D_Y_OUT)

DI GI TAL BOARD I C101(VPC3230D- C5) PI N57(VPC_VSYNC)

¢ .* (  8  8!   " ¢ + )   

DI GI TAL BOARD I C101(VPC3230D-C5) PI N56(VPC_HSYNC)

DI GI TAL BOARD I C104(FLI 2200) PI N91(FLI _VSYNC)

i   

DI GI TAL BOARD I C101(VPC3230D-C5) PI N28(VPC_CLK)

DI GI TAL BOARD I C104(FLI 2200) PI N92(FLI _HSYNC)

¢ .* (  8  8!   " ¢ + )   

DI GI TAL BOARD I C104(FLI 2200) PI N90(FLI _DE)

DI GI TAL BOARD I C104(FLI 2200) PI N117(FLI _CLK)

DI GI TAL BOARD RW507(ASI 500 OUTPUT) PI N2(MN_I N_V)

DI GI TAL BOARD RW507(ASI 500 OUTPUT) PI N1(MN_I N_H)

¢ .* (  8  8!   " ¢ + )   

DI GI TAL BOARD RW507(ASI 500 OUTPUT) PI N4(MN_I N_CLK)

DI GI TAL BOARD I C601(SNI OUTPUT) PI N9(OUT_VSYNC)

DI GI TAL BOARD I C601(SNI OUTPUT) PI N10(OUT_HSYNC)

DI GI TAL BOARD I C601(SNI OUTPUT) PI N8(OUT_DE)

¢ .* (  8  8!   " ¢ + )   

DI GI TAL BOARD I C601(SNI OUTPUT) PI N12(OUT_CLK)

ANALOG BOARD I C101(CXA2151 OUTPUT) PI N26(COMP_PB)

ANALOG BOARD I C101(CXA2151 OUTPUT) PI N27(COMP_Y)

ANALOG BOARD I C101(CXA2151 OUTPUT) PI N25(COMP_PR)

¢ .* (  8  8!   " ¢ + )   

ANALOG BOARD I C101(CXA2151 OUTPUT) PI N23(COMP_V)

ANALOG BOARD I C101(CXA2151 OUTPUT) PI N22(COMP_H)

DI GI TAL BOARD I C705(AD9883 OUTPUT) PI N64(ASI _SUB_V)

DI GI TAL BOARD I C705(AD9883 OUTPUT) PI N66(ASI _SUB_H)

¢ .* (  8  8!   " ¢ + )   

DI GI TAL BOARD I C705(AD9883 OUTPUT) PI N65(ASI _SUB_SOG)

DI GI TAL BOARD I C705(AD9883 OUTPUT) PI N67(ASI _SUB_CLK)

DI GI TAL BOARD I C702(SI I 169CT OUTPUT) PI N47(DVI _VSYNC)

DI GI TAL BOARD I C702(SI I 169CT OUTPUT) PI N48(DVI _HSYNC)

¢ .* (  8  8!   " ¢ + )   

DI GI TAL BOARD I C702(SI I 169CT OUTPUT) PI N46(DVI _DE)

DI GI TAL BOARD I C702(SI I 169CT OUTPUT) PI N44(DVI _CLK)

  ¢  

 ¢ Tur n on t he s et

Connect

Pr ot ect i on or LED Nor mal

Remove al l Connect or s

LED pr obl ems

NO

OK

OK

X- Mai n

Connect

OK

Y- Mai n

Connect Addres s

OK

Che ck t he pr ot ect i on

Change

NO

NO

SMPS

or vol t age s

Change X- Mai n

NO

Change Y- Mai n

ot her Boards

Buf fer

f r om SMPS(except AV) and

Che ck

NO

Change Addres s Buf fer

OK

Che ck PS_ON( 0V: SMPS CN802 pi n4) &

OK

NO LED Che ck s t and_by 5V(SMPS CN802 pi n2) Remove

Che ck Vol t age s NO

on t he SMPS (Vs , Va, Ve, Vs et

Connect or s f r om

NO

X, Y-Mai n, Addr es s vol t age s on SMPS agai n

OK

Remove al l Connect or s

Al mos t No

NO

on t he SMPS? OK

NO Vol t age s

Yes

Change Di gi t al

NO Onl y Vs or Va cannot be meas ur e d Che ck VS_ON(3V)

SMPS

Che ck t he damaged

OK

f r om SMPS and Che ck t he vol t age s on AV Boards

Change

compone nt s on

Key-Pad

Vol t age s

Buf fer s and Che ck t he

)

Che ck t he

NO

CN803(SMPS pi n2)

Change SMPS

Change Logi c

Change t he damaged Board

X, Y-Mai n & Addres s Board

NO Damaged Compone nt s Che ck t he Fus es on X, Y-Mai n Boards (F4003, F5003)

Change t he NO

damaged Board

OK

I can s ee s ome Vi deo

Change

ex) TV, Vi de o or et c I nput s our ce

Anal og

Che ck whe t her

Change Y- Mai n

al ways No Vi deo

Change X- Mai n NO

NO

about al l AV i nput s

Change NO, can' t s ee any Vi deo

Di gi t al

Che ck t he NO

LVDS cabl e

Change NO

Logi c

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