RS-232 FPGA based transmitter and receiver using VHDL code

RS-232 TRANSMITTER AND RECEIVER USING FPGA WITH VHDL CODE

Internal Guide by:Prof. Hardik .H .Patel Assistance professor, Department of EC, SRPEC, Unjha.

External Guide by:Mr. Elesh Patel

By:Ankita Patel(090780111007) Kinjal Prajapati(100783111004) Vidhi Patel(090780111001) 8th Semester, B.E (EC), SRPEC, Dabhi – Unjha

CONTENTS           

AIM MOTIVATION OVERVIEW OF PROJECT COMPONENT SPECIFICATION STATE DIAGRAM SIMULATION /RESULTS WORK PLAN CONCLUSION FUTURE WORK REFERENCES

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AIM  Aim of this project is to transfer data from PC to FPGA and FPGA to PC using serial communication. For this Serial communication we are using RS-232 for interfacing of PC and FPGA and Using Code of data transfer with VHDL language we Transfer data between FPGA and PC.  Hyper terminal is used for transferring data and for giving input for receiver section and showing output on hyper terminal for transmitting section.

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MOTIVATION  Many more Data acquisition system are available in the market Based on DSP ,microcontroller and FPGA etc…But the Faster response, low Power Consumption, less time consuming of FPGA we are going though FPGA. • Reason for Choosing FPGA based System:  Faster Response.  Low Power Consumption.  Less Time Consuming.  Data Security.  Accuracy. 8/14/2013

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OVERVIEW OF PROJECT

Fig:1 general block diagram of our project

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ALTERA MODEL[1]

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BLOCK DIAGRAM OF RECEIVER

RX

RECIVER RECEIVR DATA DATA BLOCK BLOCK

RST

8 BIT

DATA R (7 DOWN T0 0)

CLK

Fig:2 BLOCK DIAGRAM OF RECEIVER 8/14/2013

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BLOCK DIAGRAM OF TRANSMITTER

TX 8 BIT DATA_TX (7 DOWN T0 0)

TRANSMITTER DATA BLOCK

RST

CLK

Fig:3 BLOCK DIAGRAM OF TRANSMITTER 8/14/2013

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HYPER TERMINAL  This is a built in interface in windows which sends and receives data through the serial port.it has the option of sending through port COM1 and COM2 and also has flexible baud rate.

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Fig:4 snap of hiper terminal 8/14/2013

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COMPONENTS     

Altera kit(FPGA) RS-232 Power Supply Cyclone QUARTUS II software PC

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SPECIFICATION OF ALTERA KIT  5volt external supply.  9600 baud rate.  27 MHZ/25 MHZ frequency.

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DECIDING THE CLOCK AND BAUDRATE  In FPGA clock in not standard. That is ,in FPGA clock is use by 10MHZ,27MHZ,50MHZ etc..  Baud rate that we are using is 9600.  Also there is miss match between clock and baudrate so calculate clock by: Frequency/baud rate= new clock genereted that is used in FPGA

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DECIDING THE CLOCK AND BAUDRATE  Here, 27MHZ/9600=2812 cycle  so,there is a 1406 clock cycle for upper cycle and similarly 1406 clock cycle for lower cycle.  In this way clock and baud rate is decided

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8/14/2013 RS-232 TX/RX USING FPGA WITH VHDL CODE

STATE DIAGRAM

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STATE DIGRAM OF RECEIVER Fig:5 state diagram

1

RST

1

Data_r(7)