Quartus II Training 2

 

Quartus II Basic Training

Corporation   Copyright © 2005 Altera Corporation 

 

Programmable Logic Families  

Structured ASIC ®  HardCopy  II, HardCopy Stratix High & Medium Density FPGAs  FPGAs  

 

Low-Cost FPGAs  FPGAs   Cyclone II & Cyclone FPGAs with Clock Data Recovery 



MAX II, MAX 7000 & MAX 3000

Embedded Processor Solutions  Solutions  



Stratix II GX

CPLDs   CPLDs 



Stratix II, Stratix, APEX™ II, APEX 20K, & FLEX 10K® 

Nios II

Configuration Devices 

Serial (EPCS) & Enhanced (EPC)

Copyright © 2005 Altera Corporation  Corporation   2

 

MAX 7000A & MAX 3000A Family Overview Parameter    A    2    3    0    3    M    P    E

MAX 3000A

   E    A    4    6    0    7    M    P    E

   E    A    8    2    1    7    M    P    E

   E    A    6    5    2    7    M    P    E

600 1,250

2,500

5,000

10,000

64

128

256

512

36

68

100

164

212

7.5

4.5

4.5

5.0

5.5

7.5

127

116

227

222

192

172

116

3.3

5.2

5.6

2.9

2.8

3.3

3.9

5.6

3.4

4.8

4.7

3.0

3.1

3.4

3.5

4.7

   A    2    1    5    3    M    P    E

   E    A    2    3    0    7    M    P    E

   A    4    6    0    3    M    P    E

   A    8    2    1    3    M    P    E

   A    6    5    2    3    M    P    E

Useable Gates

600 1,250

2,500

5,000

10,000

Macrocells

32

64

128

256

512

32

Maximum User I/O Pins

34

66

96

158

208

tPD (ns)

4.5

4.5

5.0

7.5

f CNT (MHz)

227

222

192

tSU (ns)

2.9

2.8

tCO1 (ns)

3.0

3.1

Copyright © 2005 Altera Corporation  Corporation   3

MAX 7000A    E    A    2    1    5    7    M    P    E

 

Complete Voltage Portfolio 5.0 V

3.3 V

2.5 V

MAX 7000S

MAX 7000AE

MAX 7000B

 Performance Leader  Feature Leader Range of  Wide Package Offerings  Industrial-Grade Offerings

 High Performance  Feature Leader  Wide Range of

 High Performance  Feature Leader  Wide Range of

Package Offerings

Package Offerings

MAX 3000A

 Price Leader

 Feature & Package Subset of MAX 7000AE

Copyright © 2005 Altera Corporation  Corporation   4

4  

MAX Device Block Diagram

Copyright © 2005 Altera Corporation  Corporation  

5  

MAX Macrocell

Global Global Clear Clock

7000 has two Global Clock Clock  

Parallel Logic Expanders (from other MCs)

Programmable Register Register Bypass

ProductTerm Select Matrix

PRn D Q

VCC

ENA CLRn

Clear Select

Shared Logic Expanders

36 Programmable  Programmable 36 Interconnect Signals

16 16 Expander  Expander Product Terms

Copyright © 2005 Altera Corporation  Corporation  

Clock/ Enable to PIA Select

to I/O Control Block

6  

MAX II: The Lowest-Cost CPLD Ever  New

Logic Architecture



1/2 the Cost



1/10 the Power Consumption



2X the Performance



4X the Density

 Non-Volatile,

Instant-On

 Supports

3.3-, 2.5- & 1.8-V Supply Voltages

Break through Technology T echnology to Expand the Mar k et

Copyright © 2005 Altera Corporation  Corporation  

7  

Flexible Supply Voltage  On-Chip

Voltage Regulator

 Accepts

3.3-, 2.5- & 3.3-,

1.8-V Supply Inputs  Internally Converted to 1.8-V Core Voltage Conv enience of 3.3 V with Convenience the Po Power wer Perfor Perf or m ance of 1.8 V Copyright © 2005 Altera Corporation  Corporation  

8  

MAX II Device Family

Device

Typical Logic Elements Macro(LEs) cells

User I/O Pins

Speed Grades

Fastest tpd1 (ns) 

User Flash Memory (bits)

EPM240

240

192

80

3, 4, 5

4.7

8,192

EPM570

570

440

160

3, 4, 5

5.5

8,192

EPM1270

1,270

980

212

3, 4, 5

6.3

8,192

EPM2210

2,210

1,700

272

3, 4, 5

7.1

8,192

Copyright © 2005 Altera Corporation  Corporation  

9  

MAX II Packaging & User I/O Pins Device

100-Pin TQFP1  144-Pin TQFP 256-Pin FBGA2  324-Pin FBGA 0.5-mm Pitch 0.5-mm Pitch 1.0-mm Pitch 1.0-mm Pitch 16 x 16 mm 22 x 22 mm 17 x 17 mm 19 x 19 mm

EPM240

80

EPM570

76

EPM1270 EPM2210 Denotes Vertical Migration Notes: 1. TQFP: thin quad flat pack 2. FineLine BGA® package (1.0-mm pitch)

Copyright © 2005 Altera Corporation  Corporation  

116

160

116

212 204

272

10  

New Small Packages T100 0.5mm TQFP 16x16mm

New Packages

Partial M100 0.5mm MBGA 6x6mm

F256 1.0mm FBGA 17x17mm

Partial M256 0.5mm MBGA 11x11mm

 Packages

minimize PCB area and optimize ease-of-use 

Partial arrays allow for 2 layer PCB break out Copyright © 2005 Altera Corporation  Corporation  

11  

MAX II Architecture Logic Elements (LEs) Staggered I/O Pads

Configuration Flash Memory

JTAG & Control Circuitry User Flash Memory

Copyright © 2005 Altera Corporation  Corporation  

12  

MAX II Logic Element (LE) sload

sclear

aload

Register Chain

addnsub

Reg data1 data2 data3

4-Input LUT

cin data4

clock ena aclr

Row, Column & Direct Link Routing Local Routing LUT Chain Register Chain

Copyright © 2005 Altera Corporation  Corporation  

13  

User Flash Memory  Feature 

 

Flash Memory Storage Bank 8,192 Bits Per Device

Industry First!

Interface to SPI, I2C, Parallel, or Proprietary Buses

 Applications 



Store Revision & Serial Number Data Store Boot-Up & Configuration Configuratio n Data

Copyright © 2005 Altera Corporation  Corporation  

User Flash Memory Block

14  

MAX & MAX II Comparison Parameter Process Technology echnolo gy Logic Architecture Density Range

MAX

MAX II

0.3-um EEPROM

0.18-um Flash

Product Term

Look-Up Table (LUT)

32 to 512 Macrocells

128 to 2210 Macrocells (240 to 2,210 LEs)

Routing Architecture Architecture On-Chip Flash Memory

Global None

Row & Column 8 Kbits

212

272

5.0 V, 3.3 V, 2.5 V 

3.3 V/2.5 V, 1.8 V

5.0 V, 3.3 V, 2.5 V, 1.8 V

3.3 V, 2.5 V, 1.8 V, 1.5 V

Global Clock Networks

2 per Device

4 per Device

Output Enables (OEs)

6 to 10 per Device

1 per I/O Pin

None

1 per I/O Pin

Maximum User I/O Pins Supply Voltage I/O Voltages olta ges

Schmitt Triggers Copyright © 2005 Altera Corporation  Corporation  

15  

What is Nios II?   Altera’s

Second Generation Generation Soft-Core Soft-Core 32 Bit RISC Microprocessor

Developed By Altera - Nios II Plus Internally All Peripherals Written In HDL



Harvard Architecture - Can Be Targeted For All Altera FPGAs



Royalty-Free - Synthesis Using Quartus II Integrated Synthesis



Nios II CPU Debug

  e    h   c   a    C

On-Chip ROM On-Chip RAM

FPGA Copyright © 2005 Altera Corporation  Corporation  

  c    i   r    b   a    F    h   c    t    i   w    S   n   o    l   a   v    A

UART GPIO Timer SPI SDRAM Controller

16  

Nios II Processor Architecture Classic

Pipelined RISC Machine



32 General Purpose Registers



3 Instruction Formats



32-Bit Instructions

 

32-Bit Data Path Flat Register File



Separate Instruction and Data Cache (configurable sizes)



Tightly-Coupled Tight ly-Coupled Memory Options

 

Branch Prediction 32 Prioritized Interrupts



On-Chip Hardware (Multiply, (Multiply, Shift, Rotate)



Custom Instructions



JTAG-Based JT AG-Based Hardware Debug Unit

Copyright © 2005 Altera Corporation  Corporation  

17  

Problem: Reduce Cost, Complexity & Power Flash

I/O CPU

SDRAM

I/O I/O

I/O

I/O

I/O

FPGA CPU

DSP

DSP

Solution: Replace External Devices with Programmable Logic

Copyright © 2005 Altera Corporation  Corporation  

18  

Problem: Cost, Complexity & System OnReduce A Programmable Chip (SOPC) Power

Flash

FPGA SDRAM

CP U is a Criti Critical cal Con trol Function Solution: Replace Exter nal Devices Required with wit for h Program Systemma -Level -Lev ble bl el e Logi Logic Integ crati ration on Copyright © 2005 Altera Corporation  Corporation  

19  

Licensing  Licensing   Nios II Delivered As Encrypted Megacore  Licensed Via Feature Line In Existing Quartus II License File  

Consistent With General Altera Megacore Delivery Mechanism Enables Detection Of Nios II In Customer Designs (Talkback)

 No  

Nios II Feature Line (OpenCore Plus Mode)

System Runs If Tethered To Host PC System Times Out If Disconnected from PC After ~ 1 hr

 Nios 



Subscription and New Dev Kit Customers Obtain Licenses From www.altera.com www.altera.com   Nios II CPU RTL Remains Encrypted

 Nios  

II Feature Line (Active Subscriber)

II Source License

 Available Upon Request On Case-By-Case Basis Included With Purchase Of Nios II ASIC License

Copyright © 2005 Altera Corporation  Corporation  

20  

Quartus II Basic Training Quartus II Development System Feature Overview Corporation   Copyright © 2005 Altera Corporation 

 

Software & Development Tools 

Quartus  All Stratix, II Cyclone & Hardcopy Devices Devices  







 APEX II, APEX 20K/E/C, 20K/E/C, Excalibur, & Mercury Devices FLEX 10K/A/E, ACEX 1K, FLEX 6000 Devices MAX II, II, MAX 7000S/AE/B, 7000S/AE/B, MAX 30 3000A 00A Devices

Quartus II Web Edition  

Free Version Not All Features & Devices Included 



MAX+PLUS® II 

Copyright © 2005 Altera Corporation  Corporation  

See www.altera.com www.altera.com for  for Feature Comparison

 All FLEX, ACEX, & MAX MAX Devices

22  

Quartus II Development System  Fully-Integrated

Design Tool



Multiple Design Entry Methods



Logic Synthesis

Place & Route  Simulation 



Timing & Power Analysis



Device Programming

Copyright © 2005 Altera Corporation  Corporation  

 

Typical PLD Design Flow Design Entry/RTL Coding - Behavioral or Structural Description of Design

Design Specification

RTL Simulation - Functional Simulation (Modelsim®, Quartus II) - Verify Logic Model & Data Flow (No Timing Delays)

LE M4K

M512

I/O

Synthesis - Translate Design into Device Specific Primitives - Optimization to Meet Required Area & Performance Constraints - Precision Synthesis, Synplify/Synplify Pro, Design Compiler FPGA, Quartus II

Place & Route - Map Primitives to Specific Locations inside Target Technology with Reference to Area & Performance Constraints - Specify Routing Resources to Be Used Copyright © 2005 Altera Corporation  Corporation  

24  

Typical PLD Design Flow t clk

Timing Analysis Specifications Were Met - Verify Performance - Static Timing Analysis

Gate Level Simulation - Timing Simulation - Verify Design Will Work in Target Technology

PC Board Simulation & Test - Simulate Board Design - Program & T Test est Device on Board - Use SignalTap II for Debugging Copyright © 2005 Altera Corporation  Corporation  

25  

Design Entry Methods  Quartus II  Text Editor

TopLevel File

Top-level design files can be schematic, HDL or 3rdParty Netlist File

 AHDL

VHDL  Verilog

 

Schematic Editor File  Block Diagram  

Graphic Design File

HEX  MIF

 3rd-Party  

Block File

.bsf

Symbol File

.tdf

Text File

.vhd

Text File

.v

Text File

.edf

.v, vlg,

.edif

.vhd, .vhdl, vqm

Text File

Text File

Memory Editor 



.bdf .gdf

Generated within Quartus II

EDA Tools

EDIF HDL VQM

 Mixing

& Matching Design Files Allowed

Copyright © 2005 Altera Corporation  Corporation  

Imported from 3rd-Party EDA tools

26  

Quartus II Basic Quartus II Quick Training Start LAB1 Corporation   Copyright © 2005 Altera Corporation 

 

Objectives  Create

Wizard

 Name

a project using the New Project

the project

 Add

design files

 Pick

a device

Copyright © 2005 Altera Corporation  Corporation  

28  

Step 1 (Setup Project for QII5_1) Under File, Select New Project Wizard….  A new window appears. If an Introduction screen appears, click Next.

Copyright © 2005 Altera Corporation  Corporation  

29  

Step 2 (Setup Project for QII5_1) Page 1 of the wizard should be completed with the following

 

working directory for this project   \Dsp_7_segment\ name of project 

Dsp_7_segment

top-level design entity 

Dsp_7_segment

Copy “state_machine.v” and past in  Dsp_7_segment  C l i c k N e x t to advance to the P r o j e c t W i z ar ar d : A d d F i l e es s [ p a g e 2 o f 5 ] .  

Copyright © 2005 Altera Corporation  Corporation   30  

Step 3 (Setup Project for QII5_1) Using the browse button, select state_machine.v  Add to the project. Click Next.

Copyright © 2005 Altera Corporation  Corporation   31  

Step 4 (Setup Project for QII5_1) On page 3, select Stratix as the Family. Also, in the Filters section, set Package to FBFA, Pin count to 780, and Speed grade to 5. Select the EP1S25F780C5 device from the Available devices: window. Click Next.

Copyright © 2005 Altera Corporation  Corporation   32  

Step 5 (Setup Project for QII5_1) On page 4 , you can specify any third party EDA tools you may be using along with with Quartus II. Since these exer exercises cises will be done entirely within Quartus II, click Next.

Copyright © 2005 Altera Corporation  Corporation   33  

Step 6 (Setup Project for QII5_1) The summary screen appears as shown. Click Finish. The project is now created.

Copyright © 2005 Altera Corporation  Corporation   34  

Quartus II Basic Training Quartus II Quick Start LAB2

Copyright © 2005 Altera Corporation  Corporation    

Objectives  Create

a counter using the MegaWizard Plug-in Manager

 Build

a design using the schematic editor

 Analyze

and an d elaborate elaborate the design design to check check for errors

Copyright © 2005 Altera Corporation  Corporation   36  

Step 1 Create schematic file  Select File New and select Block Diagram/Schematic File. Click OK. Select File Save As and save the file as  \Dsp_7_segment\  \Dsp_7_segment\ Dsp_7_segme Dsp_7_segment.bdf  nt.bdf  

Copyright © 2005 Altera Corporation  Corporation   37  

Step 2 Build an 23 bits counter using the MegaWizard Plug-in Manager   1.Choose Tools

t hat appears, MegaWizard Plug-In Manager . In the window that

select Create a new custom megafunction variation variation.. Click on Next Next.. 2.On page 2a of the MegaWizard expand the arithmetic  folder and select LPM_COUNTER. 3.Choose Verilog HDL output For the name of the output file, type timer_1s. Click on Next 

Copyright © 2005 Altera Corporation  Corporation   38  

Step 3 1.

Set the output bus to 27 bits. For the remaining settings in this window window,,

2. 3.

use the defaults that appear .. Select next .Turn on “Modulus , with a count modulus of  “and key in 79999999 Select finish

Copyright © 2005 Altera Corporation  Corporation   39  

Step 4 In the Graphic Editor , double-click in the screen so that the Symbol Window appears. Inside the symbol w window, indow, click on to expand the symbols defined in the Project folder. Double-click on timer_1s. Click the left mouse button to put down the symbol inside the schematic file.. The symbol for “ timer_1s timer_1s” now appears in the schematic. 

Copyright © 2005 Altera Corporation  Corporation   40  

Step 5 1. 2.

3. 4.

From the File menu, open the file state_machine.v  From the File menu, go the Create/Update menu option and select Create Symbol Files for Current File. Click Y  Yes es to save changes to Dsp_7_segment.bdf . II is finished creating the symbol, click OK OK.. Close the Once Quartus II is state_machine.v file In the Graphic Editor , double-click in the screen so that the t he Symbol Window appears again. Double-click on state_machine in the Project folder. Click OK... The symbol for state_machine  now appears in the schematic. 

Copyright © 2005 Altera Corporation  Corporation   41  

Step 6 Add Pins to the Design Input 

Output 

sys_clk

7_out[6..0]

reset

Dig1 

For each of the pins listed in left Table , you must insert a pin and change its name

1.

To pla place ce pi pins ns in the the s sch chem emat atic ic file, file, go to Edit Insert Symbol OR  double-click in any empty location of the Graphic Editor .

2.

Browse to libraries primitives pin folder. Double-click on input  or output Hint: To insert insert multiple pins select Repeat Insert Mod e  .  To rename tth he pins double-click on the pin name after it has been inserted. Type ype the the n nam ame e in the the Pin Pin nam name( e(s) s) ffie ield ld and and Cl Clic ick k OK

3. 4. . 

Copyright © 2005 Altera Corporation  Corporation   42  

Step 7 Connect the Pins and Blocks in the Schematic 1.

In the lef leftt hand hand too tooll bar clic click k on

but button ton to dra draw w a wir wire e and

but button ton to dra draw w a bus bus..

 Another way to draw wires and busses is to place the cursor next to the port of any symbol. When you do this, the w wire ire or bus tool will auto automatically matically appear. appear.

2.

Conn Connec ectt al alll of the the pins pins and and blo block cks s as as sho show wn in the the figure below

Copyright © 2005 Altera Corporation  Corporation   43  

Step 8 Save and check the schematic 1. 2.

3.

Click on the Save button in the toolbar to save the schematic. From From the the Proj Project ect menu, menu, sele select ct Add Add/Re /Remov move e Fi Files les in Pro Projec ject. t. Click on the browse button to make sure the Dsp_7_segment.bdf , timer_1s and state_machine are added to the project. From the Processing menu, select Start  Start Analysis & Elaboration.

 Analysis and elaboration checks that all the design files are present and connections have been made correctly correctly.. 4. Click O K  when analysis and elaboration is completed  

Copyright © 2005 Altera Corporation  Corporation   44  

Quartus II Basic Training Quartus II Quick Start LAB3

Copyright © 2005 Altera Corporation  Corporation    

Objectives  Pin

assignment compilation Build a design  Perform full compilation  using the schematic editor  How

to Download programming file

Copyright © 2005 Altera Corporation  Corporation   46  

Step 1 1. 2. 3.

Choose Assignments  Assignment editor. editor. From the View menu, select Show All All Know Pin Names. Please click Pin in Category

Copyright © 2005 Altera Corporation  Corporation   47  

Step 2 1. 2. 3. 4. 5. 6. 7.

Pls in insta stall ll DSP DSP Deve Develo lopm pmen entt Kit Kit Str Strat atix ix edtio edtion n CD Open Open ds_stra ds_stratix tix_ds _dsp_b p_bd.p d.pdf df from C:\ C:\meg megaco acore\ re\str strati atix_d x_dsp_ sp_kitkit-v1.1 v1.1.0\ .0\Doc Doc Check Check clk clk , push pushbot botton ton and seve seven n segme segment nt d disp isplay lay p pin in loca locatio tion n from from ds_stratix_dsp_bd.pdf Key Key your your pi pin n numb number er in lo loca cati tion on Click on the Save button in the toolbar From Assignments, select Device. Click Devic Device e & Pin options. Click Unused pins  pins  .Select As input tri-stated from tri-stated from Reserv Reserve e all unused pins From the Processing menu, select Start Compilation

Copyright © 2005 Altera Corporation  Corporation   48  

Step 3 1. 2. 3. 4.

From the Tools menu, select programmer Click on Add File. Select Dsp_7_segment.sof. Check Hardware Setup. Select your download cable on cable on Currently selected hardware(ByteBlas hardware(ByteBlasterII) terII) Select JTAG from Mode

Copyright © 2005 Altera Corporation  Corporation   49  

Step 4 1. 2. 3.

Turn on Program/configure. Or see figure below Click Start See 7-segment status

Copyright © 2005 Altera Corporation  Corporation   50  

SignalTap II Agenda  SignalTap II Overview & Features  Using SignalTap II Interface  Advanced

Triggering  Triggering 

Copyright © 2005 Altera Corporation  Corporation   51  

SignalTap II ELA  Captures

the Logic State of FPGA Internal Signals Using a Defined Clock Signal  Gives Designers Ability to Monitor Buried Signals 

Connects to Quartus II through FPGA JTAG Pins  Captures Real-Time Data 

 Is  

Up to 200 Mhz

Available for Free Installed with Full Subscription or Web Edition Installed with Stand-Alone Programmer

Copyright © 2005 Altera Corporation  Corporation   52  

SignalTap II Device Support  Stratix

& Stratix II  Stratix GX  Cyclone

& Cyclone II

 Excalibur  Mercury  APEX  APEX

II 20K/E/C

Copyright © 2005 Altera Corporation  Corporation   53  

How Does It Work? 1. Conf Confiigu gure re EL ELA 2. Do Down wnlo load ad EL ELA A in into to FPGA along with Design 3. ELA ELA Sa Samp mple les s Inte Intern rnal al Signals 4. Quart rtu us II II Communicates with ELA through JT JTAG AG

Copyright © 2005 Altera Corporation  Corporation   54  

Stratix/Cyclone Sample Resource Usage Number of Channels

Logic Elements Trigger Level 1

Trigger Level 2

Trigger Level 3

8

316

371

426

32

566

773

981

256

2900

4528

6156

Number of Channels

M4Ks Based on Sample Depth 256

512

2K

8K

32K

8 32