QUICK REFRESHER GUIDE For
Computer Science & Information Technology
By
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Quick Refresher Guide
Contents
CONTENTS Topic #1.Mathemathics 1.1Linear Algebra 1.2Probability and Distribution 1.3Numerical Methods 1.4Calculus
#2.Discrete Mathematics and Graph Theory 2.1Mathematical Logic 2.2Combinatorics 2.3Sets and Relations 2.4Graph Theory
#3.Data Structures and Algorithms 3.1Data Structure and Algorithm Analysis 3.2Elements of Discrete Mathematics for Data Structure 3.3Abstract Data Type (ADT) 3.4Stacks 3.5Queue 3.6Trees 3.7 Height Balanced Trees (AVL Trees, B and B+) 3.8Hashing 3.9Graph Algorithms 3.10Sorting Algorithms
#4.
Operating System 4.1Introduction to Operating System 4.2Process Management 4.3Threads 4.4CPU Scheduling 4.5Deadlocks 4.6Memory Management & Virtual Memory 4.7File System 4.8I/O Systems 4.9Protection and Security
#5.Data Base Management Systems 5.1ER Diagrams 5.2Functional Dependencies & Normalization 5.3Relational Algebra & Relational Calculus
Page No. 1 – 30 1–8 9 – 14 15 – 19 20 – 30
31 – 70 31 – 36 37 – 42 43 – 56 57 – 70
71 – 105 71 – 75 76 – 77 78 79 80 81 - 85 86 – 94 95 – 97 98 – 100 101 – 105
106 – 157 106 – 108 109 – 123 124 – 125 126 – 128 129 – 133 134 – 144 145 – 149 150 – 153 154 – 157
158 – 193 158 – 163 164 – 170 171 – 174
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5.4SQL 5.5Transactions and Concurrency Control 5.6File Structures (Sequential files, indexing B & B+ trees)
#6.Theory of Computation 6.1Introudction 6.2Finite Automata 6.3Regular Expression 6.4Context free grammar 6.5Turing Machines
#7.Computer Organization 7.1Introduction of Computer Organization 7.2Memory Hierarchy 7.3Pipelining 7.4Instruction Types 7.5Addressing Modes 7.6I/O Data Transfer
#8.Digital Logic 8.1Number Systems & Code Conversions 8.2Boolean Algebra &Karnaugh Maps 8.3Logic Gates 8.4Combinational Digital Circuits 8.5Semiconductor Memory
#9. Compiler Design 9.1 Introduction 9.2Syntax Analysis 9.3Syntax Directed Translation 9.4Run Time Environment 9.5Intermediate Code Generation 9.6Code Optimization 9.7Code Generation
#10. Computer Networks 10.1 Introduction to Computer Networks 10.2Multiple Access Protocols 10.3The Data Link Layer 10.4Routing & Congestion Control 10.5TCP/IP, UDP and Stocks, IP(V4) 10.6Application Layer 10.7Network Security
Contents
175 - 180 181 – 188 189 – 193
194 – 238 194 195 – 198 199 – 208 209 – 218 219 – 238
239 – 278 239 – 244 245 –252 253 – 258 259 – 263 264 – 266 267 – 278
279 – 292 279 – 280 281 – 282 283 – 286 287 – 291 292
293 – 349 293 – 300 301 – 325 326 – 334 335 – 336 337 – 342 343 – 344 345 – 349
350 – 381 350 – 357 358 – 360 361 – 365 366 – 369 370 – 376 377 – 378 379 – 381
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#11. Software Engineering and Web Technology 11.1Introduction 11.2Process Models and Software Estimation 11.3 Validation and Verification 11.4 HTML 11.5 XML & DTDs
# Reference Book
Contents
382 – 417 382 – 389 390 – 401 402 – 407 408 – 413 414 – 417
418 – 419
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Mathematics
Part - 1: Mathematics 1.1 Linear Algebra 1.1.1
Matrix Definition: A system of “m n” numbers arranged along m rows and n columns. Conventionally, single capital letter is used to denote a matrix. Thus,
A=[
a a
a a
a a
a a a
a
a a a a
]
ith row, jth column
1.1.1.1 Types of Matrices 1.1.1.2 Row and Column Matrices Row Matrix [ 2, 7, 8, 9]
Column Matrix
[
]
single row ( or row vector) single column (or column vector)
1.1.1.3 Square Matrix -
Same number of rows and columns. Order of Square matrix no. of rows or columns Principle Diagonal (or Main diagonal or Leading diagonal): The diagonal of a square matrix (from the top left to the bottom right) is called as principal diagonal. Trace of the Matrix: The sum of the diagonal elements of a square matrix. tr (λ A) = λ tr(A) [ λ is scalar] tr ( A+B) = tr (A) + tr (B) tr (AB) = tr (BA)
1.1.1.4 Rectangular Matrix Number of rows
Number of columns
1.1.1.5 Diagonal Matrix A Square matrix in which all the elements except those in leading diagonal are zero. e.g.[
]
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1.1.1.6 Unit Matrix (or Identity Matrix) A Diagonal matrix in which all the leading diagonal elements are ‘ ’. e.g. =
[
]
1.1.1.7 Null Matrix (or Zero Matrix) A matrix is said to be Null Matrix if all the elements are zero. e.g.[
]
1.1.1.8 Symmetric and Skew Symmetric Matrices: Symmetric, when a = +a for all i and j. In other words Skew symmetric, when a = - a In other words = -A
=A
Note: All the diagonal elements of skew symmetric matrix must be zero. Symmetric Skew symmetric a h g h g [h b ] [h ] g c g
Symmetric Matrix
=A
Skew Symmetric Matrix
=-A
1.1.1.9 Triangular Matrix A matrix is said to be “upper triangular” i all the elements below its principal diagonal are zeros. A matrix is said to be “lower triangular” i all the elements above its principal diagonal are zeros. a a h g [ ] [ g b ] b h c c Upper Triangular Matrix Lower Triangular Matrix 1.1.1.10
Orthogonal Matrix: If A.A = , then matrix A is said to be Orthogonal matrix.
1.1.1.11
Singular Matrix: If |A| = 0, then A is called a singular matrix.
1.1.1.12
̅ ) = transpose of a conjugate of matrix A Unitary Matrix: If we define, A = (A Then the matrix is unitary if A . A =
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1.1.1.13
Mathematics
Hermitian Matrix: It is a square matrix with complex entries which is equal to its own conjugate transpose.
A = A or a = a̅̅̅ 1.1.1.14
Note: In Hermitian matrix, diagonal elements
always real
1.1.1.15 Skew Hermitian matrix: It is a square matrix with complex entries which is equal to the negative of conjugate transpose. A = A ora =
a̅̅̅
Note: In Skew-Hermitianmatrix , diagonal elements 1.1.1.16
either zero or Pure Imaginary
Idempotent Matrix If A = A, then the matrix A is called idempotent matrix.
1.1.1.17
Multiplication of Matrix by a Scalar:
Every element of the matrix gets multiplied by that scalar. Multiplication of Matrices: Two matrices can be multiplied only when number of columns of the first matrix is equal to the number of rows of the second matrix. Multiplication of (m n) [ ] and(n p) matrices results in matrix o (m p)dimension [ ] =[ ] . 1.1.1.18
Determinant:
An n order determinant is an expression associated with n
n square matrix.
If A = [a ] , Element a with ith row, jth column. For n = 2 ,
a D = det A = |a
a a |=a a
-a a
Determinant o “order n”
D = |A| = det A = ||
a a
a
a
a
a
a a
| |
a
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1.1.1.19
Mathematics
Minors & Co-Factors:
The minor of an element in a determinant is the determinant obtained by deleting the row and the column which intersect that element. Co actor is the minor with “proper sign”. The sign is given by (-1) (where the element th th belongs to i row, j column).
1.1.1.20 Properties of Determinants: 1. A determinant remains unaltered by changing its rows into columns and columns into rows. 2. If two parallel lines of a determinant are inter-changed, the determinant retains its numerical values but changes its sign. (In a general manner, a row or a column is referred as line). 3. Determinant vanishes if two parallel lines are identical. 4. If each element of a line be multiplied by the same factor, the whole determinant is multiplied by that factor. [Note the difference with matrix]. 5. If each element of a line consists of the m terms, then determinant can be expressed as sum of the m determinants. 6. If each element of a line be added equi-multiple of the corresponding elements of one or more parallel lines, determinant is unaffected. e.g.by the operation, + p +q , determinant is unaffected. 7. Determinant of an upper triangular/ lower triangular/diagonal/scalar matrix is equal to the product of the leading diagonal elements of the matrix. 8. If A & B are square matrix of the same order, then |AB|=|BA|=|A||B|. 9. If A is non singular matrix, then |A |=| | (as a result of previous). 10. 11. 12. 13.
Determinant of a skew symmetric matrix (i.e. A =-A) of odd order is zero. If A is a unitary matrix or orthogonal matrix (i.e. A = A ) then |A|= ±1. If A is a square matrix of order n, then |k A| = |A|. | | = 1 ( is the identity matrix of order n).
1.1.1.21 Inverse of a Matrix A = | |
|A| must be non-zero (i.e. A must be non-singular). Inverse of a matrix, if exists, is always unique. a b d If it is a 2x2 matrix [ ] , its inverse will be [ c d c
b ] a
Important Points: 1. A = A = A, (Here A is square matrix of the same order as that of ) 2. 0 A = A 0 = 0, (Here 0 is null matrix) 3. AB = , then it is not necessarily that A or B is null matrix. Also it doesn’t mean BA = . 4. If the product of two non-zero square matrices A & B is a zero matrix, then A & B are singular matrices. 5. If A is non-singular matrix and A.B=0, then B is null matrix. 6. AB BA (in general) Commutative property does not hold 7. A(BC) = (AB)C Associative property holds 8. A(B+C) = AB AC Distributive property holds 9. AC = AD , doesn’t imply C = D [even when A ]. 10. If A, C, D be matrix, and if rank (A)= n & AC=AD, then C=D. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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11. 12. 13. 14. 15. 16. 17. 18. 19. 20.
Mathematics
(A+B)T = A + B (AB)T = B . A (AB)-1 = B . A AA =A A= (kA)T = k.A (k is scalar, A is vector) (kA)-1 = . A (k is scalar , A is vector) (A ) = (A ) ̅̅̅̅) = (A ̅ ) (Conjugate of a transpose of matrix= Transpose of conjugate of matrix) (A If a non-singular matrix A is symmetric, then A is also symmetric. If A is a orthogonal matrix , then A and A are also orthogonal.
21. If A is a square matrix of order n then (i) |adj A|=|A| (ii) |adj (adj A)|=|A|( ) (iii) adj (adj A) =|A|
A
1.1.1.22 Elementary Transformation of a Matrix: 1. Interchange of any 2 lines 2. Multiplication of a line by a constant (e.g. k ) 3. Addition of constant multiplication of any line to the another line (e. g.
+p
)
Note: Elementary trans ormations don’t change the ran o the matrix. However it changes the Eigen value of the matrix. 1.1.1.23
Rank of Matrix
If we select any r rows and r columns from any matrix A,deleting all other rows and columns, then the determinant formed by these r r elements is called minor of A of order r. Definition: A matrix is said to be of rank r when, i) It has at least one non-zero minor of order r. ii) Every minor of order higher than r vanishes. Other definition: The rank is also defined as maximum number of linearly independent row vectors. Special case: Rank of Square matrix Rank = Number of non-zero row in upper triangular matrix using elementary transformation. Note: 1. 2. 3. 4.
r(A.B) min { r(A), r (B)} r(A+B) r(A) + r (B) r(A-B) r(A) - r (B) The rank of a diagonal matrix is simply the number of non-zero elements in principal diagonal. 5. A system of homogeneous equations such that the number of unknown variable exceeds the number of equations, necessarily has non-zero solutions. 6. If A is a non-singular matrix, then all the row/column vectors are independent. 7. If A is a singular matrix, then vectors of A are linearly dependent. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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8. r(A)=0 iff (if and only if) A is a null matrix. 9. If two matrices A and B have the same size and the same rank then A, B are equivalent matrices. 10. Every non-singular matrix is row matrix and it is equivalent to identity matrix. 1.1.1.24
Solution of linear System of Equations:
For the following system of equations A X = B a
a a
x x
a a
Where, A =
, [
a
a
a
]
=
, [x ]
B = [
]
A= Coefficient Matrix, C = (A, B) = Augmented Matrix r = rank (A), r = rank (C), n = Number of unknown variables (x , x , - - - x ) Consistency of a System of Equations: For Non-Homogenous Equations (A X = B) i) If r r , the equations are inconsistent i.e. there is no solution. ii) If r = r = n, the equations are consistent and there is a unique solution. iii) If r = r < n, the equations are consistent and there are infinite number of solutions. For Homogenous Equations (A X = 0) i) If r = n, the equations have only a trivial zero solution ( i.e. x = x = - - -x = 0). ii) If r < n, then (n-r) linearly independent solution (i.e. infinite non-trivial solutions). Note: Consistent means:
one or more solution (i.e. unique or infinite solution)
Inconsistent means:
No solution
Cramer’s ule Let the following two equations be there a x +a x = b ---------------------------------------(i) a x +a x = b ---------------------------------------(ii) a D = |b
a b |
b D =| b
a | a
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a D =| a
Mathematics
b | b
Solution using Cramer’s rule: x =
and x =
In the above method, it is assumed that 1. No of equations = No of unknowns 2. D 0 In general, for Non-Homogenous Equations D 0 single solution (non trivial) D = 0 infinite solution For Homogenous Equations D 0 trivial solutions ( x = x =………………………x = 0) D = 0 non- trivial solution (or infinite solution) Eigen Values & Eigen Vectors 1.1.1.25
Characteristic Equation and Eigen Values:
Characteristic equation: | A λ |= 0, The roots of this equation are called the characteristic roots /latent roots / Eigen values of the matrix A. Eigen vectors: [
]X=0
For each Eigen value λ, solving for X gives the corresponding Eigen vector. Note: For a given Eigen value, there can be different Eigen vectors, but for same Eigen vector, there can’t be di erent Eigen values. Properties of Eigen values 1. The sum of the Eigen values of a matrix is equal to the sum of its principal diagonal. 2. The product of the Eigen values of a matrix is equal to its determinant. 3. The largest Eigen values of a matrix is always greater than or equal to any of the diagonal elements of the matrix. 4. If λ is an Eigen value of orthogonal matrix, then 1/ λ is also its Eigen value. 5. If A is real, then its Eigen value is real or complex conjugate pair. 6. Matrix A and its transpose A has same characteristic root (Eigen values). 7. The Eigen values of triangular matrix are just the diagonal elements of the matrix. 8. Zero is the Eigen value of the matrix if and only if the matrix is singular. 9. Eigen values o a unitary matrix or orthogonal matrix has absolute value ‘ ’. 10. Eigen values of Hermitian or symmetric matrix are purely real. 11. Eigen values of skew Hermitian or skew symmetric matrix is zero or pure imaginary. | | 12. is an Eigen value of adj A (because adj A = |A|. A ). 13. If λ is an Eigen value of the matrix then , i) Eigen value of A is 1/λ THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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ii) iii) iv) v)
Eigen value of A is Eigen value of kA are Eigen value of A Eigen value of (A
Mathematics
λ λ (k is scalar) are λ + k )2 are ( )
Properties of Eigen Vectors 1) Eigen vector X of matrix A is not unique. Let is Eigen vector, then C is also Eigen vector (C = scalar constant). 2) If λ , λ , λ . . . . . λ are distinct, then , . . . . . are linearly independent . 3) If two or more Eigen values are equal, it may or may not be possible to get linearly independent Eigen vectors corresponding to equal roots. 4) Two Eigen vectors are called orthogonal vectors if T∙ = 0. ( , are column vector) (Note: For a single vector to be orthogonal , A = A or, A. A = A. A = ) 5) Eigen vectors of a symmetric matrix corresponding to different Eigen values are orthogonal. Cayley Hamilton Theorem: Every square matrix satisfies its own characteristic equation. 1.1.1.26
Vector:
Any quantity having n components is called a vector of order n. Linear Dependence of Vectors If one vector can be written as linear combination of others, the vector is linearly dependent. Linearly Independent Vectors If no vectors can be written as a linear combination of others, then they are linearly independent. Suppose the vectors are x x x x
Its linear combination is λ x + λ x + λ x + λ x = 0 Ifλ , λ , λ , λ are not “all zero” they are linearly dependent. If all λ are zero they are linearly independent.
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1.2 Probability and Distribution 1.2.1
Probability
Event: Outcome of an experiment is called event. Mutually Exclusive Events (Disjoint Events): Two events are called mutually exclusive, if the occurrence o one excludes the occurrence o others i.e. both can’t occur simultaneously. A
B =φ, P(A
B) =0
Equally Likely Events: If one of the events cannot happen in preference to other, then such events are said to be equally likely. Odds in Favour of an Event = Where m n
no. o ways avourable to A
no. o ways not avourable to A
Odds Against the Event = Probability: P(A)= =
. .
P(A)+ P(A’)= Important points: P(A B) Probability of happening of “at least one” event o A & B P(A B) ) Probability of happening of “both” events o A & B If the events are certain to happen, then the probability is unity. If the events are impossible to happen, then the probability is zero. Addition Law ofProbability: a. For every events A, B and C not mutually exclusive P(A B C)= P(A)+ P(B)+ P(C)- P(A B)- P(B C)- P(C A)+ P(A B C) b. For the event A, B and C which are mutually exclusive P(A B C)= P(A)+ P(B)+ P(C) Independent Events: Two events are said to be independent, if the occurrence of one does not affect the occurrence of the other. If P(A B)= P(A) P(B)
Independent events A & B
Conditional Probability: If A and B are dependent events, then P( ) denotes the probability of occurrence of B when A has already occurred. This is known as conditional probability. P(B/A)=
(
) ( )
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For independent events A & B
Mathematics
P(B/A) = P(B)
Theorem of Combined Probability: If the probability of an event A happening as a result of trial is P(A). Probability of an event B happening as a result of trial after A has happened is P(B/A) then the probability of both the events A and B happening is P(A B)= P(A). P(B/A), = P(B). P(A/B),
[ P(A) 0]
[ P(B) 0]
This is also known as Multiplication Theorem. For independent events A&B P(B/A) = P(B), P(A/B )= P(A) Hence P(A B) = P(A) P(B) Important Points: If P 1. 2. 3. 4.
&P are probabilities of two independent events then P (1-P ) probability o irst event happens and second ails (i.e only irst happens) (1-P )(1-P ) probability o both event ails 1-(1-P )(1-P ) probability o at least one event occur PP probability o both event occurs
Baye’s theorem: An event A corresponds to a number of exhaustive events B ,B ,..,B . If P(B ) and P(A/B ) are given then, P( )=
( (
). ( ) ). ( )
This is also known as theorem of Inverse Probability. Random variable: Real variable associated with the outcome of a random experiment is called a random variable. 1.2.2
Distribution
Probability Density Function (PDF) or Probability Mass Function: The set of values Xi with their probabilities P constitute a probability distribution or probability density function of the variable X. If f(x) is the PDF, then f(x ) = P( = x ) , PDF has the following properties: Probability density function is always positive i.e. f(x) (x)dx = (Continuous) ∫ (x ) = (Discrete)
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Discrete Cumulative Distribution Function (CDF) or Distribution Function The Cumulative Distribution Function F(x) of the discrete variable x is defined by, (x) = (x)= P(X x) =
P(x )=
(x )
Continuous Cumulative Distribution function (CDF) or Distribution Function: If (x) = P(X x) =∫ (x)dx, then F(x) is defined as the cumulative distribution function or simply the distribution function of the continuous variable. CDF has the following properties: ( ) (x) =f(x) 0 i) = (x) 0 ii) 1 iii) If x x then (x ) (x ) , i.e. CDF is monotone (non-decreasing function) )=0 iv) ( ( ) =1 v) (a) vi) P(a x b) =∫ (x)dx =∫ (x)dx - ∫ (x)dx = (b) Expectation [E(x)]: 1. E(X) = x (x ) (Discrete case) 2. E(X) =∫ x (x )dx (Continuous case) Properties of Expectation 1. E(constant) = constant 2. E(CX) = C . E(X) [C is constant] 3. E(AX+BY) = A E(X)+B E(Y) [A& B are constants] 4. E(XY)= E(X) E(Y/X)= E(Y) E(X/Y) E(XY) E(X) E(Y) in general But E(XY) = E(X) E(Y) , if X & Y are independent Variance (Var(X)) Var(X) =E[(x
) ]
Var(X)= (x x
) (xx ) (Discrete case)
Var(X)=∫ (xx Var(X) =E(
) f(x)dx (Continuous case)
)-[E(x)]
Properties of Variance 1. Var(constant) = 0 2. Var(Cx)= C Var(x) -Variance is non-linear [here C is constant] THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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3. Var(Cx D)=C Var(x) -Variance is translational invariant [C & D are constants] 4. Var(x-k) = Var(x) [k is constant] 5. Var(ax+by) =a Var(x) +b Var(y) 2ab cov(x,y) (if not independent) [A & B are constants] = a Var(x) +b Var(y) (if independent) Covariance Cov (x,y)=E(xy)-E(x) E(y) If independent
covariance=0,
E(xy) = E(x) . E(y)
(if covariance = 0, then the events are not necessarily independent) Properties of Covariance 1. Cov(x,y) = Cov(y,x) (i.e. symmetric) 2. Cov(x,x) = Var(x) 3. |Cov(x,y)| Standard Distribution Function (Discrete r.v. case): 1. Binomial Distribution : P(r) = C p Mean = np, Variance = npq, S.D. =√np 2. Poisson Distribution: Probability of k success is P (k) = no. o success trials ,n no. o trials , P success case probability mean o the distribution For Poisson distribution: Mean = , variance = , and =np Standard Distribution Function (Continuous r.v. case): 1. Normal Distribution (Gaussian Distribution): f(x) =
√
e
(
)
Where and are the mean and standard deviation respectively P( 0
+ C (n + r, r) = C (n +r + 1, r) + C (m, n) C (n, n) = C (m + n, n) for integers
Column Summation: 13. 14. 15. 16.
C (r, r) + C (r + 1, r) + + C (n, r) = C (n + 1, r + 1), for any positive integer n > r 2.1 C2 + 3.2 C2 + + n (n – 1) Cn = 2n - 1 n (n - 1) 12 C1 + 22 C2 + + n2Cn = 2n – 2 n (n + 1) 3 3 1 C1 + 2 C2 + + n3Cn = 2n – 3 n2 (n + 3)
Recurrence Relations Definition: A recurrence relation is a formula that relates for any integer n>1, the n-th term of sequence an to one or more of the terms a0, a1 an-1. Examples of recurrence relations: If Sn denotes the sum of the first n positive integers, then 1. Sn=n+Sn-1. Similarly if d is a real number, then the nth term of an arithmetic progression with common difference satisfies the relation 2. an=an-1+d. Likewise if Pn denotes the nth term of a geometric progression with common ratio r, then 3. Pn = rPn-1. We list other examples as: Fibonacci relation: The relation F = F conditionF = 0 and = F = 1
+F
is called the Fibonacci relation with the initial
The numbers generated by the Fibonacci relation with the initial condition are called Fibonacci numbers. 0, 1, 1, 2, , , , 1 ,
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DMGT
Linear Recurrence Relation A relation of the form c (n)a + c (n)a c (n), c (n)
+
c (n)a
= f(n), when n,
∈
,n >
c (n)&f(n) are function of n is linear recurrence relation.
ifc (n) are constants, then Linear Recurrence Relation with constant coefficient Homogeneous f(n) = 0 Non-homogeneous f(n) ≠ 0 Degree: the number of previous terms of sequence used to define an Ex: 1. f = f 2. 3. 4. 5.
a a a a
+ f
=a =a =a = a
(degree z linear)
(degree 5 linear) + a ( non-linear) + 2a ( linear homogeneous degree 2 ) + 11a + a (linear homogeneous degree 3)
Solution Of Recurrence Relations Homogenous linear recurrence relations with coefficients: In general, to solve the equation y
+a y
+a y
+
+a y = 0
Where a’s are constants: i) ii) iii)
Write the equation in the symbolic form (E + a E Write down the auxillary equation i.eE + a E + write the solution as follows:
Roots for A.E 1.
,
,
2.
,
,
3.
,
4. i
+ +a )y =0 +a = 0 and solve it for E
Solution i.e.C.F ,
(real and distinct roots) ,
,
c ( ) +c ( ) +c ( ) +
(2 real and e ual roots) (c + c n)( ) + c ( ) +
( real and e ual roots)
+i , (a pair of imaginary roots)
(c + c n + c n )( ) + r (c cos n + c sin n ) where r= √(
+
) and = tan (
)
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Non Homogeneous Linear Recurrence Relations With Constant Coefficients. Rules for Finding The Particular Solution: Consider the equation y
+a y
+
+ a y = f(n)
Which in symbolic form is Where ∅(E) =E + a E
+ +a .
Then the particular integral is given by P.I =[1/∅(E)]f(n) Case (i): when f(n)=a P.l =[1/∅ (E) ]a , Put E=a. = [1/∅(a) ]a ,provided ∅(a) ≠ 0 If ∅(a) =0, then for equation (i) (E-a)y = a , (ii) (E
I = (1/E-a ) a = na
a) y = a ,
(iii) ((E
I=(
a) y = a ,
a =
)
I=(
)
a =
(
) (
a )(
)
a
and so on. Case(ii): When f(n)=np P.I. =
( )
np =
(
)
nP.
(1) Expand [ (1 + )]-1 in ascending powers of by the Binomial theorem, as far as the term in P. (2) Express np in the factorial form and operate on it with each term of the expansion. Case(iii): When f(n) = an F(n), F(n) being a polynomial of finite degree in n. P.I. =
( )
an F(n)=an.
(
)
F(n)
Now F(n) being a polynomial in n, proceed as in case ii.
Divide And Conquer Relations Relations of the form a = c a
+ f(n) where c and d are constants.
Usually these relations can be solved by substituting a power of d for n.
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2.3: Sets and Relations Set: Set is a unordered collection of well defined objects (called the elements of the set). A, B, C,
denotes the set
a, b, c,
denotes the elements
∈
is an element of the set “A” is not an element of the set “A”
Set builder notations:A={
( )
( )property that element of A should have ex: 0 =
∈
is odd}
0 = 1, , , 7, Sub Set: Let A and B be any two sets. If every element of A is an element of B, then A is called a subset of B Symbolically this relation is denoted by A⊆ B Note: For any set A, A⊆A and ∅ ⊆ A i e , for any set A,∅ and A are called trivial sub sets Some examples of set are N = the set of natural numbers or positive integers: 1, 2, 3, . . . Z = the set of all integers: . . . , 2, 1, 0, 1, 2, . . . Q = the set of rational numbers R = the set of real numbers C = the set of complex numbers Observe that N ⊆ ⊆ ⊆R ⊆C. Proper Sub Set: If A⊆ B and A ≠ B, then A is called a proper sub set of A This relationship is denoted by A⊂B Equal Sets: Two sets A and B are equal [A = B] iff A⊆ B and B⊆ A Sets are equal if they have same elements ∀ ( ) Equivalent set: of two sets A and B are equivalent iff
=
denoted by A ~ B
Empty Set: A set with no elements is called the empty set and it is denoted by ∅ Or { } [ { ≠ ] Universal Set: The set of all objects under consideration or discussion, and is denoted by U. Singleton: A set with only one element is called singleton. Ex { Set Difference:
or {0 , {1
A B=
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Set Union:
A∪B=
Set Intersection:
A
Set Complement:
Ac =
[A∪
DMGT
=(
)∪(
)∪(
)]
B= A
Disjoint Sets: Two sets A and B are said to be disjoint sets if A
B=∅
Symmetric Difference (Boolean Sum): A
B = (A – B) ∪ (B – A) = (A ∪ B) – (A
B)
A⊕B= Venn diagram: It is a pictorial representation of sets in which sets are represented by enclosed areas in the plane. The universal set U is represented by the interior of a rectangle, and the other sets are represented by disks lying within the rectangle.
U B
A
(d)
∪
(e)
(f) A
B
Cardinality of a Set: The number of elements in a set is called the cardinality of that set. It is denoted by |A|. ∪
=
+ ∪
∪ ∪
= ∪
+ =
=
+
+
iff A & B are disjoint sets +
+
+
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Equivalent set: Two sets A and B are equivalent iff
=
DMGT
denoted by A ~ B
Ex: A = { 1, 2 } P(A) = {{ } ,{1}, {2},{1,2}} Power Set: Let A be any set. Then the set of all subsets of A is called the power set of A. It is denoted by p (A) Note: If a set A contains n elements, then its power set P(A) contains 2n elements. The set operations satisfy the following laws:
Table 3.1 Laws of the algebra of sets Idempotent Laws:
(1a)
Associative Laws:
(2a)( ∪ ) ∪
Commutative Laws: (3a) Distributive Laws:
Identity Laws Involution Laws: Complement Laws: DeMorgan’s Laws:
∪
∪
=
=
=
∪( ∪ )
∪
(4a) ∪( ( ∪ )
)=( ∪ )
(1b)
=
(2b) (
)
(3b)
=
=
( ∪ )=(
(4b) ( )
(5a)
∪∅=
(5b)
=
(6a)
∪
(6b)
∅=∅
(7) (
) =
(8a)
∪
(9a)
=
=
=∅
(
(8b)
)
)∪
=∅
(9b) ∅ =
(10a) ( ∪ ) =
(10b) (
) =
∪
Each of the above laws has the corresponding dual. Cartesian product: Cartesian product of two sets A and B, written as A × B and is defined as = ( , )
∈
= ( , , ) Ex: {1, 2}
∈ ∈
,
∈ , ∈
{a, b} = {(1, a), (1, b), (2, a), (2, b)}
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Note: 1. 2. 3. 4. 5. 6. 7.
In general, ≠ If = then either = or ( If = , = and = then ( ∪ )=( )∪( ) ( )=( ) ( ) ( )=( ) ( ) ( ) ( )=( ) ( )
∅) =
and
=
Relation: A (binary) relation R from A to B is a sub set of A × B. [If A= B, we say R is a relation on A (R ⊆ A
)].
Domain and Range: Let R be a relation from A to B. Then, Domain of R = {x x ∈ A and (x, y) ∈ R for some y ∈ B}. Range of R = {y y ∈ B and (x, y) ∈ R for some x ∈ A}. Clearly, dom R ⊆ A and ran R ⊆ B. Moreover, domain of R is the set of first co-ordinates in R and its range is set of all second co- ordinates in R. We some times write, (x, y) ∈ R as x R y which reads 'x relates y'. Inverse Relation: Let R be a relation from a set A to B. The inverse of R, denoted by R -1 is the relation from B to A which consists of those ordered pairs, which when reversed belongs to R i.e. R-1 = { (b, a)| (a, b) ∈ R} Equivalence Relation: Let R be relation on A. R is said to be an equivalence relation if the following conditions are satisfied. 1) 2) 3)
xRx ∀ x ∈ A ( R is reflexive) If x Ry then y Rx (R is symmetric) If x R y and y R z then xRz( R is transitive)
Reflexive Relation:- A relation R on a set A is said to be reflexive if ( , ) ∈
∀
∈
Symmetric Relation :-A relation R on a set A is called symmetric if ( , ) ∈ , then ( , )) ∈ ∀ , ∈ , i.e. ∀ ∀ (( , ) ∈ ( , )∈ ) Transitive Relation :-A relation R on a set a is transitive if whenever ( , ) ∈ then ( , )∈ ∀ , , ∈ ( , ) ∈ ( , ) ∈ ) ∀ ∀ ∀ (( , ) ∈ ( ) Note: there are 2 different reflexive relation possible on a set of n element.
and ( , ) ∈
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Anti-Symmetric Relation: A relation R on a set A is anti symmetric relation if aRb and bRa a = b ; i.e. ∀
∀
(( , ) ∈
i.e. whenever a R b and b R a then a = b ( , )∈
)
a=b
Note: 1) The properties of being symmetric and being anti symmetric are not negatives of each other. 2) For the sets A and B, A × B is called universal relation from A to B and ∅ is called the empty relation from A to B. 3) A relation can be symmetric an antisymmetric both or cannot have both Irreflexive relation: A relation R on a set A is irreflexive if (x , x)
R for all x ∈ A.
Note: Any relation which is not reflexive is not necessarily irreflexive and vice versa . Asymmetric relation: ∀ x, y if (x ,y) ∈ R then (y ,x) R Diagonal Relation: Let A be any set. The diagonal relation consists of all ordered pairs (a,b) such that a = b ie = (a, a) I a ∈ A} Composition of Relations: 9.
Let A, B and C be sets, and let R be a relation from A to B and let S be a relation from B tC. That is, R isa subset of A× B and S is a subset of B × C. Then R and S give rise to a relation from A to C denoted by R◦S and defined by: a(R◦S)c if for some b ∈B we have aRband bSc.
10.
Equivalently, R ◦S = {(a, c) | there exists b ∈B for which (a, b) ∈R and (b, c) ∈S}.
Partial Ordering Relation:a relation R on a set is called a partial order if R is reflexive, antisymmetric and transitive. Poset:A set S together with a partial order R is called a partially ordered set or poset. Complementary Relation: R is a relation from A to B then Rc = {(a, b) ∈ (A
) ( , )
}
Note: i) A relation R* is the transitive ( symmetric, reflexive) closure of R , if R* is the smallest relation containing R which is transitive ( symmetric, reflexive). ii) R ∪ R-1 is the symmetric closure of R and R∪ A is the reflexive closure of R. Partition: A partition of S is a sub division of S into non overlapping, non empty sub sets such that A1∪ A2∪ and Ai
∪An = S Aj∅ if i≠ j
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Equivalence Classes: Given any set A and an equivalence relation R on A, the equivalence class [x] of each element x of A is defined by [x] = { y∈ A | x R y } Note: i) We can have [x] = [y] even if ≠ y, provided
Ry
ii) Given any set A and any equivalence relation R on A, S = { [x] | x ∈ A } is a partition of A. Comparability: Two elements a and b in a posetA are said to be comparable under the relation m > degree of every vertex in V2 NOTE: This condition is a sufficient condition and not necessary for the existence of a complete matching. The maximal number of vertices in set V1 that can be mapped in to V2 is equal to number of vertices in V1 – δ (G) Edge Covering In a graph G, a set of edges is said to cover G if every vertex in G is incident on atleast one edge in G. A set of edges that covers a graph G is said to be an edge covering (a covering sub graph or simply a covering) of G. D e A
e
e
C e B
e e e e is a covering e e is a Minimal covering Minimal Edge Covering: A covering from which no edge can be removed without destroying its ability to cover the graph. A covering exists for a graph iff the graph has no isolated vertex. A covering of an 'n' vertex graph has atleast⌈ 2⌉edges. Every covering contains a minimal covering. No minimal covering can contain a circuit. A graph, in general, has many coverings, and then may be of different sizes (i.e consisting of different number of edges). The number of edges in a minimal covering of smallest size is called the edge covering number of the graph denoted by THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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A covering g of a graph is minimal if g contains no paths of length three or more. If a covering g contains no path of length three or more, all its components must be star graphs. (From a star graph no edge can be removed). An Edge covering of n- vertex graph has at least [ ⁄2] edges A sub-set S of V is called an edge independent set of G if no two vertices of S are adjacent in G. An independent set ‘S' is minimum if G has no independent set S1 such that S' ⊂ S The number of vertices in a maximum edge independent set is called the edge independence number of G, denoted by D
+
= A
C
B
Edge Independent set = = , Independent No = 2 Vertex Covering: A vertex covering of a graph G = (V, E) is a subset K of V such that every edge of G is incident with a vertex in K. A covering K is called a minimum vertex covering if G has no covering K1 with |K1| = n; taking the log on both side 2h+1 >= n + 1 => h +1 >= log(n + 1) Which implies h is of O(logn). On the other hand if the resulting tree is having one node per level then h is of O(n). Binary Tree with Full Nodes (a full node has exactly two children) Theorem: A binary tree (in which each node has exactly two children except leaf nodes) with n internal nodes will have n + 1 leaf nodes and therefore total nodes would be 2n + 1.
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Tree Traversals Traversal is used to visit each node in the tree exactly once. A full traversal as a binary tree gives a linear ordering of the data in the tree. Inorder Traversal 1. Traverse the left sub tree of the root node R in inorder 2. Visit the root node R 3. Traverse the right subtree of the root node R in inorder for n nodes inorder takes O(n). Postorder Traversal 1. Traverse the left subtree of the root R in post order. 2. Traverse the right sub tree of the root R in post order 3. Visit the root node R. Running time is O(n) which can be derived as discussed for inorder running time. Binary Tree Construction Using Postorder A unique binary tree cannot be constructed using a postorder sequence as there can be many tree exists for the given sequence. Preorder Traversal 1. Visit the root node R 2. Traverse the left subtree of R in preorder 3. Traverse the right subtree of R in preorder Running time is O(n) which can be derived as discussed for inorder running time. Binary Tree Construction Using Preorder A unique binary tree cannot be constructed using a preorder sequence as there can be many tree exists for the given sequence. Levelorder Traversal This traverses the tree nodes in level by level order. Binary Tree Construction Using Levelorder A unique binary tree cannot be constructed using a level order sequence as there can be many tree existing for the given sequence.
The generalized form of level order traversal is BFS.
The nodes can be visited in any order of a level however nodes from deeper level cannot be visited unless nodes from higher levels are visited.
Queue data structure can be used to implement level order traversal efficiently.
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Binary Tree Construction Using inorder and postorder Inorder must be needed along with postorder for building a unique binary tree. The idea is very simple which is described as follows: Tree* createTree(intinorder[], intpostorder[]) { 1. newNode = Pick up the last key of the post order sequence and create a node of it; 2. newNode->left = create left subtree recursively using the values preceding root key in inorder. 3. newNode->right = create right subtree recursively using the values following root key in inorder. 4. return newNode; } Running Time analysis We need to consider the running time consumed on each node as usual. In worst case finding index of root key into inorder array takes L unit where L is the length of inorder array. Therefore, the following equation will best describe the running time; T(n) = (n-1) + (n-2) + (n-3) + …+ 1 = O( 2). The algorithm shows up worst case behaviour when postorder and inorder sequences are same. Binary Tree Construction Using inorder and preorder Inorder must be needed along with preorder for building a unique binary tree. The idea is very similar to above one which is described as follows: Tree* createTree(intinorder[], int preorder[]) { 1. newNode = Pick up the first key of the pre order sequence and create a node of it; 2. newNode->left = create left subtree recursively using the values preceding root key in inorder. 3. newNode->right = create right subtree recursively using the values following root key in inorder. 4. return newNode; } Running Time analysis The running time is O(n2). This can be derived in the same way as discussed in using post and in order section.
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Binary Search Trees BST is a binary tree in which each node satisfies search property. The each node key value must be greater than all values in its left subtree and must be less than all values in its right subtree. Basic BST Operations Insert I sert per ti
i sert v ue if it d es ’t re dy exist.
Algorithm The new value is either inserted into left subtree or right subtree of the root node. Thus by comparing root and new value we identify the correct subtree to be chosen. And the same steps are applied to each subtree until a null subtree is found. Running Time Analysis The running time can be measured in terms of height of the tree which can vary from logn to n. Thus in worst case it would be n. However if the insertion is done into a perfect balanced tree then it would be logn. Delete This operation deletes a node from a given BST. Algorithm M i y 3 c ses sh u d be c
sidered. Let’s s y X is the de eti
de the ;
Case1: if (Node X is Null) Then traverse the tree until reaches the X parent node and make the parent pointer that is pointing to X, pointing to Null now. And free up the node X. (Running time --->O(n)) Case2: if (Node X has exactly one child subtree) Then traverse the tree until it reach the X parent node and make the parent pointer, that is p i ti t X, p i ti t X’s chi d subtree w. A d free up the de X. (Running time --->O(n)) Case3: if (Node X has exactly two children subtree(left and right)) This is somewhat complicated case as compare to other two. This will require immediate predecessor or successor in inorder sequence of the deleting node to be copied in place of it. The greatest key in left subtree is the required immediate predecessor and can be found as follows: Tree *maxNode = findMax(X->left);
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OR The least key in right subtree is the required immediate successor and can be found as follows: Tree *minNode = findMin(X->right); Then copy minNode->val/maxNode->val into X->val; Thereafter call either case1 or case2 as minNode/maxNode will have either one child or none. (Running time --->O(n)) Running Time Analysis Only one of the cases (case1, case2 or case3) is executed for one deletion. Therefore running time is max (case1 RT, case2 RT, case3 RT) which is O(n). If the tree were a perfect balanced tree then it would be logn. The Other Operations The running time of the following operations is O(n) in worst case since a single path from root to leaf level is being traversed by all these operations.
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3.7
DSA
Height Balanced Trees (AVL Trees, B and B+)
Tree structures support various basic dynamic set operations including Search, Predecessor, Successor, Minimum, Maximum, Insert, and Delete in time proportional to the height of the tree. To ensure that the height of the tree is as small as possible and therefore provide the best running time, a balanced tree structure like an AVL tree, or B-tree, or B+ tree must be used. AVL Trees AVL tree is a self-balancing binary search tree with height-balanced condition. That means for every node the height of left subtree and right subtree can differ by at most 1. The following tree a bad binary tree. Requiring balance at root is not enough. Minimum Number of Nodes in AVL Tree of Height h Let (h) be the umber f des i the sm est AVL tree f hei ht h. Si ce it’s AVL tree the definitely the height of its subtrees will be either (h-1 and h-2) or (h -1 and h -1). Now to have smallest AVL tree for the given height, its two subtree must also be smallest possible AVL tree. And that is possible only if subtrees are of height h-1 and h-2(if it was of h -1 height then it will have at least one extra node than the subtree of height h-2 has.). Then clearly the following recurrence can represent the smallest AVL tree. n(h) = n(h-1) + n(h-2) + 1 Maximum Number of Nodes in AVL Tree of Height h The largest AVL tree will have 2h+1 – 1 node. The derivation follows as discussed before in binary tree section. Height Analysis Since it is a balanced tree the height order is O(logn). Insertion After insertion it might be possible that only nodes that are on the path from the insertion point to the root might have their balance altered because only those nodes have their subtree altered. In that case we need to follow the path up to the root and update the balancing information; we may find a node whose new balance violates the AVL condition. At this moment using the rotations we can restore the AVL condition for this node and that rebalancing itself would be sufficient for the entire tree too, that means we will not need rebalancing on the further nodes on path to root. A violation might occur in the four cases
An insertion into the left subtree of the left child of node X(where X violates the AVL condition).
An insertion into the right subtree of the right child of node X THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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An insertion into the right subtree of the left child of node X
An insertion into the left subtree of the right child of node X
DSA
1st two cases are symmetric and called as outside insertion that mean left-left or right-right and can be fixed by the simple single rotation. Last two are also symmetric and called as inside insertion that mean left-right or right-left and can be fixed by double rotation (two single rotations). Single Rotation The following rotation is called a right rotation. Here tree on the left side becomes imbalance because the insertion of a new node in x subtree causes k2 to violates AVL condition. This will fall into left-left case. NOTE:
After the rotation, k2 and k1 not only satisfy AVL condition but also have subtree that are exactly the same height. Furthermore, the new height of the entire subtree is exactly the same as the height of the original one prior to the insertion that caused the X(Z) to grow up hence will not require any more rebalancing of the further nodes on the path to root. Double rotation is also retained the same height of the entire affected subtree what was there prior to insertion. Therefore the height of the entire tree is unchanged in these cases.
The main idea of rotation is to level the height of both left and right subtrees of the imbalance subtree by transferring the nodes from the deeper subtree to another subtree. After rotation deeper subtree height will get restored to the original one and another subtree height is increased by one. Thereby level the required heights. Double Rotation This rotation is required when inside insertion happens. As mentioned above that this can be implemented with left and right single rotation appropriately. Right-Left Double Rotation This case occurs when insertion happens into the left subtree of the right child of node X. A right-left rotation requires a single right rotation followed by a single left rotation on the appropriate keys.
Step1: single right rotation on right child of X, where X node violates the property.
Step2: single left rotation on node X
Left-Right Double Rotation This case occurs when insertion happens into the right subtree of the left child of node X.
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A left-right rotation requires a single left rotation followed by a single right rotation on the appropriate keys.
Step1: single left rotation on left child of X, where X node violates the property.
Step2: single right rotation on node X
B - Tree
In computer science, a B-tree is a tree data structure that keeps data sorted and allows searches, insertions, deletions, and sequential access in logarithmic amortized time.
The B-tree is a generalization of a binary search tree in that more than two paths diverge from a single node.
Unlike self-balancing binary search trees, the B-tree is optimized for systems that read and write large blocks of data in secondary storage such as a magnetic disk. Since disk accesses are expensive (time consuming) operations, a b-tree tries to minimize the number of disk accesses. It is most commonly used in databases and filesystems.
Overview
In B-trees, internal (non-leaf) nodes can have a variable number of child nodes within some pre-defined range. When data is inserted or removed from a node, its number of child nodes changes. In order to maintain the pre-defined range, internal nodes may be joined or split. Because a range of child nodes is permitted, B-trees do not need re-balancing as frequently as other self-balancing search trees, but may waste some space, since nodes are not entirely full. The lower and upper bounds on the number of child nodes are typically fixed for a particular implementation. For example, in a 2-3 B-tree (often simply referred to as a 2-3 tree), each internal node may have only 2 or 3 child nodes.
A B-tree is kept balanced by requiring that all leaf nodes are at the same depth. This depth will increase slowly as elements are added to the tree, but an increase in the overall depth is infrequent.
Advantages B-trees have substantial advantages over alternative implementations when node access times far exceed access times within nodes. This usually occurs when the nodes are in secondary storage such as disk drives. By maximizing the number of child nodes within each internal node, the height of the tree decreases and the number of expensive node accesses is reduced. In addition, rebalancing the tree occurs less often. NOTE: By maximizing the number of child nodes within each internal node, the height of the tree decreases and the number of expensive node accesses is reduced. Definition The terminology used for B-trees is inconsistent in the literature. Unfortunately, the literature on B-trees is not uniform in its use of terms relating to B-Trees.
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A B-tree of order m is a tree which satisfies the following properties: 1. Every node has at most 2m children. 2. Every node (except root and leaves) has at least m children. 3. The root has at least two children if it is not a leaf node. 4. All leaves appear in the same level, and carry information. 5. A non-leaf node with k children contains k–1 keys. 6. Leaf nodes contains at least m-1 and at most 2m-1 keys. Each internal node's elements act as separation values which divide its subtrees. For example, if an internal node has three child nodes (or subtrees) then it must have two separation values or elements a1 and a2. All values in the leftmost subtree will be less than a1 , all values in the middle subtree will be between a1 and a2, and all values in the rightmost subtree will be greater than a2. Maximum Nodes In a B-Tree of Height h. As we discussed in binary tree chapter, we will follow the same instructions here too for getting the maximum number of nodes. We will get this only if each internal node has maximum number of children. Thus B-Tree of degree m will have maximum nodes at each level as follows: 1st level 2nd level 3rd level … Last level
(2m)0 (2m)1 (2m)2 (2m)h
Thus Nmax = (2m)0 + (2m)1 + (2m)2 …+(2m)h = ((2m)h+1 - 1 )/ (2m – 1) From this we will get maximum records also which is Nmax * (2m -1). Minimum Nodes In a B-Tree of Height h. This is somewhat interesting and important also. We will get this only if each internal node has minimum number of children. Thus B-Tree of degree m will have minimum nodes at each level as follows: 1st level (1) nd 2 level 2(m)0Remember root is allowed to 2 children minimally rd 3 level 2(m)1 th 4 level 2(m)2 … Last level 2(m)h -1 Thus Nmin = 1 + 2 *(mh – 1) / (m – 1)
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From this we will get minimum records also which is 1 + (Nmin – 1)* (m -1). Notice that not all node in Nminwill have m – 1 keys. The root node will have one key. NOTE: The best case height of a B-Tree is: O(log2mN) The worst case height of a B-Tree is: O(logmN) where m is the B-Tree degree. Maximizing B-Tree Degree A bad degree choice will lead to worst case height of B-Tree and hence its operations will become expensive. It is always good to choose a good degree to minimize the height this will not only utilizes the disk spaces but also reduces the access cost since height gets reduced in this case. The following derivation will let you enable for choosing the best degree.
Fig 4.12 As the diagram shows that each B-Tree node contains fields for child pointers, data pointers and keys. Let disk block size is = B bytes, and degree is = d (child pointers per node) And index pointer to data and child are of = b bytes, And key length is of = k bytes. Then a value of d would be best choice if it maximizes value of the left side of below equation such that result is closest to right side (B). (d – 1) * b + d * b + (d – 1)*k = B ----------- 1 Insertion All insertions start at a leaf node. To insert a new element Search the tree to find the leaf node where the new element should be added. Insert the new element into that node with the following steps:
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1. If the node contains fewer than the maximum legal number of elements, then there is room for the new element. Insert the new element in the node, keeping the node's elements ordered. 2. Otherwise, the node it is full, so evenly split it into two nodes.
A single median is chosen from among the leaf's elements and the new element.
Values less than the median are put in the new left node and values greater than the median are put in the new right node, with the median acting as a separation value.
Insert the separation value in the node's parent, which may cause it to be split, and so on. If the node has no parent (i.e., the node was the root), create a new root above this node (increasing the height of the tree).
If the splitting goes all the way up to the root, it creates a new root with a single separator value and two children, which is why the lower bound on the size of internal nodes does not apply to the root. Deletion The logic to delete a record is to locate and delete the item, then restructure the tree to regain its invariants There are two special cases to consider when deleting an element:
The element in an internal node may be a separator for its child nodes.
Deleting an element may put its node under the minimum number of elements and children.
Each of these cases will be dealt with in order. Deletion from a leaf node Search for the value to delete. If the value is in a leaf node, it can simply be deleted from the node, perhaps leaving the node with too few elements; so some additional changes to the tree will be required. Deletion from an internal node Each element in an internal node acts as a separation value for two subtrees, and when such an element is deleted, two cases arise. In the first case, both of the two child nodes to the left and right of the deleted element have the minimum number of elements, namely L. They can then be joined into a single node with 2Lelements, a number which does not exceed allowed maximum number of elements per node. In the second case, one of the two child nodes contains more than the minimum number of elements. Then a new separator for those subtrees must be found. Note that the largest element in the left subtree is still less than the separator. Likewise, the smallest element in the right subtree is the smallest element which is still greater than the separator. Both of those elements are in leaf nodes, and either can be the new separator for the two subtrees. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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If the value is in an internal node, choose a new separator (either the largest element in the left subtree or the smallest element in the right subtree), remove it from the leaf node it is in, and replace the element to be deleted with the new separator.
This has deleted an element from a leaf node, and so is now equivalent to the previous case.
Rebalancing after deletion If deleting an element from a leaf node has brought it under the minimum size, some elements must be redistributed to bring all nodes up to the minimum. In some cases the rearrangement will move the deficiency to the parent, and the redistribution must be applied iteratively up the tree, perhaps even to the root. Since the minimum element count doesn't apply to the root, making the root be the only deficient node is not a problem. The algorithm to rebalance the tree is as follows: If the right sibling has more than the minimum number of elements. Add the separator to the end of the deficient node. Replace the separator in the parent with the first element of the right sibling. Append the first child of the right sibling as the last child of the deficient node otherwise, if the left sibling has more than the minimum number of elements. Add the separator to the start of the deficient node. Replace the separator in the parent with the last element of the left sibling. Insert the last child of the left sibling as the first child of the deficient node, if both immediate siblings have only the minimum number of elements. Create a new node with all the elements from the deficient node, all the elements from one of its siblings, and the separator in the parent between the two combined sibling nodes. Remove the separator from the parent, and replace the two children it separated withthe combined node. If that brings the number of elements in the parent under the minimum, repeat these steps with that deficient node, unless it is the root, since the root may be deficient. The only other case to account for is when the root has no elements and one child. In this case it is sufficient to replace it with its only child. B+ Tree A B+ tree is a type of tree, which represents sorted data in a way that allows for efficient insertion, retrieval, and removal of records, each of which is identified by a key. It is a dynamic, multilevel index, with maximum and minimum bounds on the number of keys in each index segment (usually called a "block" or "node"). NOTE: In a B+ tree, in contrast to a B-tree, all records are stored at the leaf level of the tree; only keys are stored in interior nodes.
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Fig 4.17. B+ Tree NOTE:
The primary value of a B+ tree is in storing data for efficient retrieval in a blockoriented storage context. This is primarily because unlike binary search trees, B+ trees have very high fanout (typically on the order of 100 or more), which reduces the number of I/O operations required to find an element in the tree.
Notice that duplicates keys exist in B+ Trees.
B+ Trees are designed for having the range query running faster. The nodes in leaf level are connected in linked list fashion and that makes it possible.
Maximizing B+ Tree Degree The following derivation will let you enable for choosing the best degree.
Fig 4.18 As the diagram shows that each B+ tree internal node contains fields for child pointers, and keys. Let disk block size is = B bytes, and degree is = d (child pointers per node) And index pointer to child is of = b bytes, And key length is of = k bytes. Then a value of d would be best choice if it maximizes value of the left side of below equation such that result is closest to right side (B). d * b + (d – 1)*k = B ----------- 1 THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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Insertion in B+ Tree 1. do a search to determine what bucket the new record should go in 2. if the bucket is not full, add the record. 3. Otherwise, split the bucket. 4. allocate new leaf and move half the bucket's elements to the new bucket 5. Insert the new leaf's smallest key and address into the parent. 6. if the parent is full, split it also 7. now add the middle key to the parent node 8. repeat until a parent is found that need not split 9. if the root splits, create a new root which has one key and two pointers.
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3. 8 HASHING Hashtables
A memory-efficient alternative for sparse arrays.
The set of posible keys (here: {0,1,2,...,K-1,K}) is called the universe.
If the universe U is much larger than the number of keys actually stored (here: N), then a hashtable might be better than a standard array.
In our problem we have |U| = 109 and N N void store (int key, int value) { hashtable[h(key)] = value; }
voidget_value (int key) { returnhashtable[h(key)]; } int h (int key) { return h % M; }
Instead of using key as the index, we use h(key).
h is a function that maps the universe U of possible keys to the indices of the hashtable.
h : U -> {0,1,2,...,M-2,M-1}
Usual hash functions:
o
h(k) = k mod "a prime not too close to a power of 2"
o
h(k) = floor(m*(k*c mod 1)) with 0 ANY (SELECT credits FROM student WHERE major='mis'); THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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ALL: The ALL key word specifies that the search condition is true if the companion is true for every value, that the sub query returns. Grouping
Partition the set of tuples in a relation into group based on certain criteria and compute aggregate functions for each group All tuples that agree on a set of attributes (i.e., have the same value or each of these attributes) called grouping attributes are put into a group.
Example: Determine that maximum of the GATE CS marks obtained by students in each city for all cities. SELECT City, MAX(Marks) As Max marks FROM Gate Marks WHERE Branch
‘CS’
GROUP BY City; Result: City
Max Marks
Hyderabad
87
Chennai
84
Mysore
90
Bangalore
82
Join operation Join operation takes two relations and return another relation as a result. Join Types 1. Inner Join (default) (r inner join r on < >) use of just ‘join’ is equivalent to inner join Example: loan INNER JOIN borrower ON loan. loan Number = borrower loan Number. 2. Left Outer Join (r left outer join r on < >) Example : loan LEFT OUTER JOIN borrower on loan. loan Number = borrower loan Number 3. Right Outer Join (r right outer join r on < >) Example : loan RIGHT OUTER JOIN borrower ON loan.loanNumber = borrower loan Number. The right outer join is symmetric to the left outer join. Tuples from the right hand-side relation that do not match any tuples in the left hand-side relation are padded with nulls and are added to the result of the right outer join.
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4. Full Outer Join (r full outer join r on < >) It is a combination of the left & right outer join types. Natural Join: The condition ‘natural’ can be used with any of the join types of specify natural join. (r natural < > r on < > [using < , >]) Natural join by default considers all common attributes A subset of common attributes can be specified in an optional using phrase Views Views provide virtual relations which contain data spread across different tables. Views are mainly used for Simplified query formulations Data hiding Logical data independence Creating view CREATEVIEW V AS Create view V with structure defined by outcome of the query expression Tables involved in the view definition are called BASE tables. Operations in views: Querying is allowed Update operations are usually restricted because 1. Updates on a view may modify many base tables 2. There may not be unique way of updating the base tables to reflect the update on view 3. View may contain some aggregate values 4. Ambiguity where primary key of a base table is not included in view definition Update on views defined on joining of more than one table are not allowed Updates on views defined with ‘group by’ cause and aggregated functions is not permitted as a tuple in view will not have a corresponding tuple in base relation. Update on views which do not include primary key of base table are also not permitted. Updates to view are allowed only if: Defined on single base table Not defined using group by’ clause and aggregate functions Include primary key of base table
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Part 5.5: Transactions and Concurrency Control
Transactions A transaction T is a logical unit of database processing that includes one or more database access operations
Embedded within application program Specified interactively (e.g., via SQL)
ACID properties Atomicity: Either all operations of the transaction are reflected properly in the database, or none. This property is maintained by transaction management component of DBMS. Consistency: Execution of a transaction in isolation (that is, with no other transaction executing concurrently) preserves the consistency of the database. This is typically the responsibility of the application programmer who codes the transactions. Isolation: When multiple transactions execute concurrently, it should be the case that, for every pair of transactions Ti and Tj, it appears to Ti that either Tj finished execution before Ti started or Tj started execution after Ti finished. Thus, each transaction is unaware of other transactions executing concurrently with it. The user view of a transaction system requires the isolation property and the property that concurrent schedules take the system from one consistent state to another. It is enforced by concurrenty control component of database Durability: After a transaction completes successfully, the changes it has made to the database persist, even if there are system failures. It is enforced by recovery management component of the DBMS. Transaction States (fig. 5.5.1)
BEGIN_TRANSACTION: marks start of transaction. READ or WRITE: two possible operations on the data. END_TRANSACTION: marks the end of the read or write operations; start checking whether everything went according to plan. COMIT_TRANSACTION: signals successful end of transaction; changes can be “committed” to DB. ROLLBACK (or ABORT): signals unsuccessful end of transaction; changes applied to DB must be undone.
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BEGIN TRANSACTION
Active END TRANSACTION COMMIT Partially committed READ WRITE
Committed
ABORT ABORT Failed
Terminated
Fig. 5.5.1
Schedule When transactions are executing concurrently in an interleaved fashion, then the order of execution of operations from the various transactions is known as Schedule. Types of schedules: Serial, Non serial, Recoverable and Non recoverable schedules Serial schedule:A schedule where the operations of each transaction are executed consecutively without any interleaved operations from other transactions. Nonserial schedule: A schedule where the operations from a set of concurrent transactions are interleaved. Recoverable Schedule: A schedule which recovers from aborts by itself Non-recoverable Schedule: A schedule which is not recoverable Serializability A schedule'S' of 'n' transactions is Serializable if it is equivalent to some serial schedule of the same 'n' transactions, i.e If interleaved schedule produces the same result as that of the serial schedule, then the interleaved schedule is said to be serializable. For two schedules to be equivalent, the operations applied to each data item affected by the schedules should be applied to that item in both schedules in the same order. There are two types of equivalences they are conflict equivalence and view equivalence and they lead to (a) Conflict Serializability (b) View Serializability. Conflict Serializabilty
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Can reorder the non-conflicting operations to improve efficiency Non-conflicting operations: Reads and writes from same transaction Reads from different transactions Reads and writes from different transactions on different data items Conflicting operations: Reads and writes from different transactions on same data item
View Serializability Consider two schedules S and S1, they are said to be view equivalent if the following conditions are met. 1. For each data item Q if transaction Ti reads the initial value of Q in schedule S, then transaction Timust in schedules S1 must also read the initial value of Q. 2. For each data item Q, if transaction Ti executes read Q in schedule S and that value was produced by Tj (if any), then transaction Ti must in schedule S1, also read the value of Q that was produced by transaction Tj. 3. For each data item Q, the transaction (if any) that performs the final write (Q) operation in schedule S must perform the final write (Q) operation is schedule S1. Conditions 1 and 2, ensure that each transaction reads the same values in both schedules and therefore performs the same computation. Condition 3 ensures that both schedules result in the same final system state. The concept of view equivalence leads to the concept of view serilizability. Concurrency control Protocols Two-phase-locking protocol
Basic 2PL: Transaction is said to follow the two-phase-locking protocol if all locking operations precede the first unlock operation Two phases Expanding or growing: New locks on items can be acquired but none can be released. Shrinking: Existing locks can be released but no new locks can be acquired.
Conservative 2PL (static) 2PL: Lock all items needed BEFORE execution begins by predeclaring its read and write set If any of the items in read or write set is already locked (by other transactions), transaction waits (does not acquire any locks) Deadlock free but not very realistic
Strict 2PL: Transaction does not release its write locks until AFTER it aborts/commits Not deadlock free but guarantees recoverable schedules Most popular variation of 2PL
Rigorous 2PL: No lock is released until after abort/commit Transaction is in its expanding phase until it ends
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Gurantees Strict schedules (strict schedule: Transaction can neither read/write X until last transaction that wrote X has committed/aborted)
Graph based protocols The simplest graph based protocol is tree locking protocol which is used to employ exclusive locks and when the database is in the form of a tree of data items. In the tree locking protocol, each transaction Ti can lock a data item at most once and must observe the following rules. a. b. c. d. e.
All locks are exclusive locks. The first lock by Ti can be any data item including the root node. Ti can lock a data item Q only if Ti currently locks the parent of Q Data items may be unlocked at any time. Ti cannot subsequently lock a data item that has been locked and unlocked by Ti.
A schedule with a set of transactions, that uses the tree locking protocol can be shown to be serializable. The transactions need not be two phase. Advantage of tree locking control: a. Compared to the two phase locking protocol, unlocking of the data item is earlier. So it leads to the shorter waiting times and increase in concurrency. Disadvantages of tree locking control: a. A transaction may have to lock data items that it does not access, because to access descendants we have to lock its parent also. So the number of locks and associated locking overhead is high. b. A risk of deadlock: One problem that is not solved by two-phase locking is the potential for deadlocks, where several transactions are forced by the scheduler to wait forever for a lock held by another transaction Timestamp based protocols The use of locks, combined with the two phase locking protocol, guarantees serializability of schedules. The order of transactions in the equivalent serial schedule is based on the order in which executing transactions lock the items they require. If a transaction needs an item that is already locked, it may be forced to wait until the item is released. A different approach that guarantees serializability involves using transaction timestamps to order transaction execution for an equivalent serial schedule. Time Stamps A Timestamp is a unique identifier created by the DBMS to identify a transaction. Timestamp values are assigned in the order in which the transactions are submitted to the system. So a timestamp is considered as the transaction start time with each transaction Ti in the system, a unique timestamp is assigned and it is denoted by TS(Ti). When a new transaction Tj enters the system, then TS(Ti) < TS(Tj), this is known as timestamp ordering scheme. To implement this scheme, each data item (Q) is associated with two timestamp values. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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1. "W-timestamp(Q)"denotes the largest timestamp of any transaction that executed write(Q) successfully. 2. "R-timestamp(Q)"denotes the largest timestamp of any transaction that executed read(Q) successfully. These timestamps are updated whenever a new read (Q) or write (Q) instruction is executed. Timestamp ordering protocol The timestamp ordering protocol ensures that any conflicting read and write operations are executed in timestamp order. This protocol operation is as follows. a. Suppose transaction Ti issues read(Q) a) If TS(Ti) < W- timestamp(Q) then Ti needs to read a value of Q that was already overwritten. Hence, the read operation is rejected and Ti is rolled back. b) If TS(Ti) > W-timestamp(Q), then the read operation is executed and R-timestamp(Q) is set to the maximum of R-timestamp(Q) and TS(Ti). b. Transaction issue a write(X) a) If TS(Ti) < read-timestamp(X), this means that a younger transaction is already using the current value of the item and it would be an error to update it now. This occurs when a transaction is late in doing a write and younger transaction has already read the old value. b) If TS(Ti) < write-timestamp(X). This means transaction T asks to write any item(X) whose value has already been written by a younger transaction, i.e., T is attempting to write an absolute value of data item X. So T should be rolled hack and restarted using a later timestamp c) Otherwise, the write operation can proceed we set write-timestamp (X)-TS(Ti) This scheme is called basic timestamp ordering and guarantees that transaction are conflict serializable and the results are equivalent to a serial schedule. Advantages of timestamp ordering protocol 1. Conflicting operations are processed in timestamp order and therefore it ensures conflict serializability. 2. Since timestamps do not use locks, deadlocks cannot occur. Disadvantages of timestamp ordering protocol: 1. Starvation may occur if a transaction is continually aborted and restarted. 2. It does not ensure recoverable schedules. Thomas's write rule: A modification to the basic timestamp ordering protocol is that it relaxes conflict serializability and provides greater concurrency by rejecting absolute write operation. The extension is known as Thomas's write rule. Suppose transaction Ti issues read(Q): no change , same as Time stamp ordering protocol.
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If transaction issue a write(X): a) If TS(T) < read-timestamp(X), this means that a younger transaction is already using the current value of the item and it would be an error to update it now. This occurs when a transaction is late in doing a write and younger transaction has already read the old value. b) If TS(Ti) < write-timestamp(X). This means that a young transaction has already updated the value of the item and the value that the older transaction is writing must be based on an absolute value of the item. In this case the write operation can safely be ignored. This is sometimes known as the ignore absolute write rule and allows greater concurrency. Problems of Dirty Data There is a problem that the commit bit is designed to help with the dirty read problem. A transaction T reads , and was written by another transaction . The time stamp of is less than that of T, and the read by T occurs write by in real time, so the events are physically realizable. However it is possible that after T reads , the transaction will abort. The value of read by T becomes invalid. In this case it is better to delay T; read of until commits or aborts. (See Fig. below) writes
start
T reads
T start
aborts
Multiple Granularity:
Allow data items to be of various sizes and define a hierarchy of data granularities, where the small granularities are nested within larger ones. Can be represented graphically as a tree. When a transaction locks a node in the tree explicitly, it implicitly locks all nodes descendants in the same lock mode. Granularity of locking (level in tree where locking is done): Fine granularity (lower in tree): High concurrency high locking overhead Coarse Granularity (higher in tree): Low locking overhead, low concurrenty. Example of granularity hierarchy:
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DB
Fa
r
r
r
A1
A2
Fb
Fc
r
r
r
r
The highest level in the example hierarchy is the entire database. The levels below are of type area, file and record in that order. Intention Lock Modes: In addition to shred and exclusive lock modes, there are three additional lock modes with multiple granularity. Intention shared (IS) indicates explicit locking at a lower level of the tree but only with shared locks Intention exclusive (IX) indicates explicit locking at a lower level with exclusive or shared locks. Shared and intention exclusive (SIX)The subtree rooted by that node is locked explicitly in shared mode and explicit locking is being done at a lower level with exclusive mode locks. Compatibility matrix with intention lock modes IS IX S SIX X IS IX S SIX X
Multi version Schemes In multi version database systems, each write operation on data item say Q creates a new version of Q. When a read (Q) operation is issued, the system selects one of the versions of Q to read. The concurrency control scheme must ensure that the selection of the version to be read is done in a manner that ensures serializability. There are two multi version schemes 1. Multi version Timestamp ordering. 2. Multi version Two-phase locking. Multi version timestamp ordering In this technique, several versions Q1Q2 ......Qkof each data item Q are kept by the system. For each version the value of the version Qk and the following two timestamps are kept. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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1. W-timestamp(Qk) is the timestamp of the transaction that created version Qk. 2. R-timestamp(Qk) is the largest timestamp of any transaction that successfully read version Qk. The scheme operates as follows: When transaction Ti issues a read(Q) or write(Q) operation. Let Qk denote the version of Q whose write timestamp is the largest write timestamp less than or equal to TS(Ti). 1. It transaction Ti issues a read(Q), then the value returned is the content of version Qk 2. It transaction Ti issues a write(Q), and if TS(Ti) < R-timestamp(Qk), then transaction Ti is rolled back. Otherwise if TS(Ti) = W-timestamp(Qk) the contents of Qk are overwritten, otherwise a new version of Q is created. Advantages 1. The read request never fails and is never made to wait. Disadvantages 1. It requires more storage to maintain multiple versions of the data item. 2. Reading of a data item also requires the update of the R-timestamp field, resulting in two potential disk accesses. 3. Conflicts between transactions are resolved through roll backs, rather than through waits. This may be expensive. Multi version Two Phase Locking The multi version two phase locking protocol attempts to combine the advantage of multi version concurrency control with the advantages of two phase locking. In the standard locking scheme, once a transactions obtain a write lock on an item, no other transactions can access that item. So here it allows other transactions T1 to read an item X while a single transaction T holds a write lock on X. This is accomplished by allowing two versions of each item of X. When an update transaction reads an item it gets shared lock on the item and reads the latest version of that item. When an update transactions wants to write an item, it first gets an exclusive lock on the item and then creates a new version of the data item. The write is performed on the new versions the timestamp of the new version is initially set to a value . Advantages 1. Reads can proceed concurrently with a write operation but it is not permitted in standard two phase locking. 2. It avoids cascading aborts, since transactions are only allowed to read the version that was written by a committed transaction. Disadvantages 1. It requires more storage to maintain multiple versions of the data item. 2. Dead locks may occur.
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Part 5.6: File Structures (Sequential files, indexing, B and B+ trees)
Dynamic Multilevel Indexes Using B – Trees and
-Trees
B-trees and B+ trees are special cases of the well – known tree data structure. We introduce very briefly the terminology used in discussing tree data structures. A tree is formed of nodes. Each node in the tree, except for a special node called the root, has one parent node and several – zero or more – child nodes. The root node has no parent. A node that does not have any child nodes is called a leaf node; a nonleaf node is called an internal node. The level of a node is always one more than the level of its parent, with the level of the root node being zero. A sub tree of a node consists of that node and all its descendant node – its child nodes, the child nodes of its child nodes, and so on. A precise recursive definition of a sub tree is that it consists of a node n and the sub trees of all the child nodes of n. In this figure the root node is A, and its child nodes are B, C, and D. Nodes E, J, C, G, H, and K are leaf nodes. Usually, we display a tree with the root node at the top, as shown in Figure 5.6.1. One way to implement a tree is to have an many pointers in each node as there are child nodes
SUBTREE FOR NODE B
nodes at level 1
D
B
E
root node (level 0)
A
C
F
G G
J
H
I
nodes at level 2
K
nodes at level 3
(nodes E,J,C,G,H and K are leaf nodes of the tree) Figure 5.6.1 A tree data structure that shows an unbalanced tree. of that node. In some cases, a parent pointer is also stored in each node. In addition to pointers, a node usually contains some kind of stored information. When a multilevel index is implemented as a tree structure, this information includes the values of the file’s indexing field that are used to guide the search for a particular record. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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Search Trees and B-Trees Search Trees. A search tree is slightly different from a multilevel index. A search tree of order p is a tree such that each node contains at most p – 1 search values of p pointers in the order , where q ≤ p; each P is a pointer to a child node (or a null pointer); and each K is a search value from some ordered set of values. All search values are assumed to be unique. Figure 5.6.2 illustrates a node in a search tree. Two constraints must hold at all times on the search tree: 1. Within each node, K < K < P
K
where q ≤ p. Each P is a tree pointer – a pointer to another node in the B-tree. Each Pr is a data pointer – a pointer to the record whose search key field value is equal to K (or to the data file block containing the record). 2. Within each node, K < K < < K . 3. For all search key field values X in the subtree pointed at by P (the ithsubtree, see Figure 6.4a), we have: K < < K for 1 < < ; X < K for i = 1; and K < for i = q. 4. Each node has at most p tree pointers. 5. Each node, except the root and leaf nodes, has at least ⌈(p 2)⌉ tree pointers. The root node has at least two tree pointers unless it is the only node in the tree. 6. A node with q tree pointers, q ≤ p, has q – 1 search key field values (and hence has q – 1 data pointers). 7. All leaf nodes are at the same level. Leaf node have the same structure as internal nodes except that all of their tree pointers P are null. A B-tree starts with a single root node (which is also a leaf node) at level 0 (zero). Once the root node is full with p – 1 search key values and we attempt to insert another entry in the tree, the root node splits into two nodes at level 1. Only the middle value is kept in the root node, and the rest of the values are split evenly between the other two nodes. When a nonroot node is full and a new entry is inserted into it, that node is split into two nodes at the same level, and the middle entry is moved to the parent node along with two pointers to the new split nodes. If the parent node is full, it is also split. Splitting can propagate all the way to the root node, creating a new level if the root is split. .
(a) tree pointer
data pointer
X X<
tree pointer
. tree data pointer pointer
X
<
tree data pointer pointer
data pointer
X <
<
(b)
Tree node pointer 5 0
8 0
0 Data pointer Null node pointer
1 0
3 0
6 0
7 0
9 0
1 2
0
Figure 5.6.3 B-tree structures. (a) A node in a B-tree with q – 1 search values. (b) A B-tree of order p = 3. The values were inserted in the order 8, 5, 1, 7, 3, 12, 9, 6. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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If deletion of a value causes a node to be less that half full, it is combined with its neighboring nodes, and this can also propagate all the way to the root. Hence, deletion can reduce the number of tree levels. It has been shown by analysis and simulation that, after numerous random insertions and deletions on a B-tree, the nodes are approximately 69 percent full when the number of values in the tree stabilizes. This is also true of B+-trees. If this happens, node splitting and combining will occur only rarely, so insertion and deletion become quite efficient. If the number of values grows, the tree will expand without a problem – although splitting of nodes may occur, so some insertions will take more time. B-trees are sometimes used as primary file organizations. In this case, whole records are stored within the B-tree nodes rather than just the entries. This works well for files with a relatively small number of records, and a small record size. Otherwise, the fan-out and the number of levels become too great to permit efficient access. In summary, B-trees provide a multilevel access structure that is a balanced tree structure in which each node is at least half full. Each node in a B-tree of order p can have at most p – 1 search values. -Trees Most implementations of a dynamic multilevel index use a variation of the B-tree data structure called a -tree. In a B-tree, every value of the search field appears once at some level in the tree, along with a data pointer. In a B -tree, data pointers are stored only at the leaf nodes of the tree; hence, the structure of leaf nodes differs from the structure of internal nodes. The leaf nodes have an entry for every value of the search field, along with a data pointer to the record (or to the block that contains this record) if the search field is a key field. For a nonkey search field, the pointer points to a block containing pointers to the data file records, creating an extra level of indirection. The leaf nodes of the B -tree are usually linked together to provide ordered access on the search field to the records. These leaf nodes are similar to the first (base) level of an index. Internal nodes of the B -tree correspond to the other levels of a multilevel index. Some search field values from the leaf nodes are repeated in the internal nodes of the B - tree to guide the search. The structure of the internal nodes of a B -tree of order p (Figure 5.6.4a) is as follows: 1. Each internal nodes is of the form Where q ≤ p and each P is a tree pointer. 2. Within each internal node, K < K < < K . 3. For all search field values X in the subtree pointed at by P , we have K < ≤ K for 1 < i < q; X ≤ K for i = 1; and K < for i = q (see Figure 5.6.4a). 4. Each internal node has at most p tree pointers. 5. Each internal node, except the root, has at least ⌈(p 2)⌉ tree pointers. The root node has at least two tree pointers if it is an internal node. 6. An internal node with q pointers, q ≤ p, has q – 1 search field values. The structure of the leaf nodes of a B -tree of order p (Figure 5.6.4b) is as follows: 1. Each leaf node is of the form , < K , Pr >,
,< K
, Pr
>, P
>
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(a)
…
…
tree pointer X
X
<
X≤
….
data pointer
data pointer
Figure 5.6.4 The nodes of a Leaf node of a
2. 3. 4. 5.
tree pointer
tree pointer
(b)
DBMS
X
<
<
pointer to next leaf node in tree
…. data pointer
data pointer
-tree. (a) Internal node of a -tree with q – 1 search values. (b) -tree with q – 1 search values and q – 1 data pointers.
where q ≤ p, each Pr is a data pointer, and P points to the next leaf node of the B tree. Within each leaf node, K < K < < K ; q ≤ p. Each Pr is a data pointer that points to the record whose search field value is K or to a file block containing the record (or to a block of record pointers that point to records whose search field value is K if the search field is not a key). Each leaf node has at least ⌈(p 2)⌉ values. All leaf nodes are at the same level.
The pointers in internal nodes are tree pointers to blocks that are tree nodes, whereas the pointers in leaf nodes are data pointers to the data file records or blocks––except for the P pointer, which is a tree pointer to the next leaf node. By starting at the leftmost leaf node, it is possible to traverse leaf nodes as a linked list, using the P pointers. This provides ordered access to the data records on the indexing field. A P pointer can also be included. For a B -tree on a nonkey field, an extra level of indirection is needed so the Pr pointers are block pointers to blocks that contain a set of record pointers to the actual records in the data file. Because entries in the internal nodes of a B -tree include search values and tree pointers without any data pointers, more entries can be packed into an internal node of a B -tree then for a similar B -tree. Thus, for the same block (node) size, the order p will be larger for the B -tree than for the B-tree. This can lead to fewer B -tree levels, improving search time. Because the structures for internal and for leaf nodes of a B -tree are different, the order p can be different. We will use p to denote the order for internal nodes and p to denote the order for leaf nodes, which we define as being the maximum number of data pointers in a leaf node. As with the B-tree, we may need additional information––to implement the insertion and deletion algorithms––in each node. This information can include the type of node (internal or leaf), the number of current entries q in the node, and pointers to the parent and sibling nodes. Hence, before we do the above calculations for p and p , we should reduce the block size by the amount of space needed for all such information. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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Part – 6: Theory of Computation 6.1: Introduction/ Preliminaries (string, alphabet, set, relation, equivalence of relation etc.) PRELIMINARIES: 1. String:A string is a finite sequence of symbols put together. Note: The length of empty string denoted by , is the string consisting of zero symbols. Thus I I = 0. 2. Alphabet:An alphabet is a finite set of symbols. It is denoted by 3. Formal language: A formal language is a set of strings of symbols from some 1 alphabet. Note: 1. The empty set, ∅, is a formal language. The cardinality (size) of this language is zero. 2. The set consisting of empty string, { } is a formal language. The cardinality (size) of this language is one. 4. Set: A set is a collection of objects (members of the set) without repetition. i. Finite Set: A set which contains finite number of elements is said to be finite set. ii. Countably Infinite Set:Sets that can be placed in one-to-one correspondence with the integers are said to be countably infinite or countable or denumerable. iii. Uncountable set: Sets that can't be placed in one-to-one correspondence with the integers are said to be uncountable sets. 5. Relations: A(binary) relation is a set of ordered tuple. The first component of each tuple is chosen from a set and the second component of each pair is chosen from a (possibly different) set.
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6.2: Finite Automata Introduction: A finite automaton involves states and transitions among states in response to inputs. A Deterministic finite automaton is represented by a Quintuple (5-tuple): (Q, ,δ,q0,F) where Q : Finite set of states : Finite set of input symbols called the alphabet. δ : Q X ⇨ Q (δ is a transition function from Q X to Q) q0 : A start state, one of the states in Q F : A set of final states, such that F ⊆ Q.
Acceptance by an Automata : A string “X” is said to be accepted by a finite automaton M = (Q, , δ, q 0, F) if δ (q0, x) = P for some p in F. The language accepted by M, designated L (M), is the set {x | δ(q0,x) is in F}. A language is a regular set (or just regular) if it is the set accepted by some automaton. There are two preferred notations for describing Automata 1. Transition diagram 2. Transition table 1. Give DFA for accepting the set of all strings containing ‘111’ as substring. Transition diagram : 0/1
0 Start
1 q0
1 q2
q1 11
11 11
0 11 111 111 Transition Table: 1
q0 q1 q2 *q3
0
1
q0 q0 q0 1q3 1
q1 q2 q3 q3
111 111 1
111 0 111 1
111 111 1
1 q3 11 11 111 111 1
111 111 1
111 111 Extending transition function from single symbol to string: For the behavior of a finite automaton 1
on string, we must extend the transition function ‘δ’ to apply to a state and a string rather than a state and a symbol. We define a function δ̂ from Q X *⇨Q.
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1. δ̂ (q, ) = q, and 2. for all strings “w” and input symbols ‘a’, δ̂ (q, wa) = δ( δ̂ (q,w),a) In any DFA, for a given input string and state the transition path will always be unique.
Non-Deterministic Finite Automata: A nondeterministic finite state machine or nondeterministic finite automaton (NFA) is a finite state machine where for each pair of state and input symbol there may be several possible next states. An NFA is represented by a 5-tuple(Q, , δ, q0, F) where 1. Q is a finite set of states, 2. is a finite set of input symbols 3. δ : Q x ⇨ 2Q (‘δ’ is a transition function from Q x to power set of Q) 4. q0 , a member of Q, is the start state and 5. F, a subset of Q, is the set of final states. ⟶Non-deterministic finite automata can also be represented by transition diagram and transition table. Extending transition function from single symbol to string: The function ‘δ’ can be extended to function δ̂ mapping Q X * to 2Q and reflecting sequences of input as follows: 1. δ̂ (q, ) = {q} 2. Suppose ‘w’ is of the form w = xa, where a is the final symbol of w and x is the rest of w. Alsosuppose hatδ̂ (q, x)= {P1, P2 ……Pk}. Let ⋃ δ (pI, a) = { r1, r2, …… rm} Then δ̂ (q, w) ={r1, r2, ……. , rm}. Less formally, we compute δ̂ (q, w) by first computing δ̂ (q, x) and by then following any transition from any of these states that is labeled as ‘a’. Acceptance by NFA: An NFA accepts a string ‘w’ if it is possible to make any sequence of choices of next state, while reading the characters of w, and go form start state to any accepting state. if M = (Q, , δ, q0, F} is an NFA, then L(A) = {w / δ(q0, w) ∩ F ≠ ∅}. That is, L(A) is the set of strings w in * such that δ̂ (q0, w) containing at least one accepting state. 1. Construct an NFA for the set of all strings over the alphabet {0,1} containing 111 as substring. Transition diagram: 0/1 0/1 1
1
1
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Construction of DFA from NFA(Sub Set Construction): Let N = (QN, , δN q0, FN) be a NFA. We have to construct D = (QD, , δD{q0}, FD) such that L(D) = L(N) QD is the set of subsets of QN, i.e..power set of QN has ‘n’ states, then QD will have 2n states. Often not all these states are accessible from the start state of QD. Inaccessible states can be “thrown away”. So effectively the number of states of D may be much smaller then 2n. FD is the set of subsets S of QN such that S ∩ FN ≠ ∅. That is , FD is all sets of Ns states that include set S ⊆ QN and for each input symbol a in , δD(S,a) = ∪ δN (P,a) That is , to compute δD(S,a) We look at all states p in S, see what states N goes to from p on input ‘a’, and take the union of all those sets. NFA With -Transitions (Epsilon Transitions): An NFA is allowed to make a transition spontaneously, without receiving an input symbol. These NFA’s can be converted to DFA’s accepting the same language. We may represent an NFA exactly as we do an NFA with one exception Q δ: Q X U { } → 2 Closure: closure (q) is the set of all vertices p such that there is a path from q to p on alone. 1 ϵ
0
ϵ
ϵ q0 In this diagram
2
q1
q2
-closure of q0 = {q0, q1, q2} -closure of q1 = {q1, q2} -closure of q2 = {q2}
Extended transitions and language for -NFA’s: 1. δ̂(q, ) = -closure(q). That is, if the label of the path is , then we can follow only -labeled arcs extending from state q, 2. Suppose ‘w’ is of the form xa, where a is the last symbol of w. Note a is a member of ; It cannot be , which is not in . We compute δ̂(q,w)as follows: (A) Let {p1,p2,……..pk} be δ̂(q,x)). That is, the p’s are all and only the states that we can reach from q following a path labeled x. This path may end with one or more transitions labeled , and may have -transitions as well. (B) Let ∪ δ(pi,a) be the set {r1,r2…….rm}. That is, follow all transitions labeled ‘a’ from states i=1 we can reach from q along paths labeled x, The rj’s are some of the states we can reach from q along paths labeled w. The additional states we can reach are found from the r j’s followed by ϵ-labeled arcs in step(C), below. M
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(C) Then δ̂(q,w) = ∪ ϵ-closure (rj). This additional closure step includes all the paths from j = 1. q labeled w, by considering the possibility that there are additional ϵ-labeled arcs that we can follow after making a transition on the final ‘real’ symbol a. Eliminating -Transitions (Construction of DFA from -NFA); Let E=(Q , , δ , q , F )be the given -NFA then the equivalent DFA D=(Q , δ , q , F )is defined as follows 1. q = closure (q ) 2. Q is the set of all subsets of Q more precisely ,we shall find that the only accessible states of D ate the -colsed subset of Q , that is those sets S≤Q such that S= -closure (S). 3. F is those sets of states that contain atleast one accepting state of E i.e., F ={S/S is in Q and S∩F ≠ ∅} 4. δ is computed ,for all a in and sets S in Q by (A) Let S={P , p … … , p } (B) Compute ∪δ(p , a) ; Let this set be {r , r … . . , r } m (C) Then δ (S, a) -closure (r ) ∪
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6.3: Regular Expression This algebraic notation describes exactly the same languages as finite automata: the regular languages. The regular expression operators are union, concatenation (or “dot”), and closure (or “star”). A set of languages A ⊆ * is said to be a regular if A = L(M), for some finite automation M. where L(M) is the language accepted by M. Definitions: Union of two languages: L and M denoted by L U M is the set of strings that are either in L or M or both. For Example L = {0, 1} and M = {00, 11, 111} then L U M = {0, 1, 00, 11, 111} Concatenation of two languages: L and M denoted by LM is the set of strings that can be formed by taking any string of L and concatenating it with any string in M. Closure (Kleen closure or star) of a Language: It is denoted as L* and represents the set of those strings that can be formed by taking any number of strings from L, possibly with repetitions and concatenating all of them. That mean L* is the infinite union Ui>= 0 Li, where L0 = {ϵ}, L1 = L and Li for i > 1 is LLL…L (the concatenation of I copies of L) Regular Expression: Let
be a given alphabet. Then 1. ϕ, ϵ, and a ϵ are all regular expressions. These are called primitive regular expressions. 2. If r1 and r2 are regular expressions, so are r1+ r2, r1.r2, r1*, and (r1). 3. A string is a regular expression if and only if it can be derived from the primitive regular expressions by a finite number of applications of the rules in (2).
Languages Associated with Regular Expressions: Regular expressions can be used to describe some simple languages. If r is a regular expression, we will let L(r) denote the language associated with r. The language is defined as follows Definition: The language L(r) denoted by any regular expression r is defined by the following rules. 1. ∅ is a regular expression denoting the empty set(L(∅) = {}). 2. is a regular expression denoting the set L( ) = { }. 3. For every a , ‘a’ is a regular expression denoting the set {a}. If r1 and r2 are regular expressions, then 4. L(r1 + r2) = L(r1) ∪ L(r2) 5. L(r1 . r2) = L(r1) L(r2) 6. L(r1*) = (L(r1))*
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Precedence of Regular Expression Operators: 1. Closure has higher precedence than concatenation. 2. Concatenation has higher precedence than union. Equivalence of Regular Expressions: Two regular expressions are said to be equivalent if they denote the same language Algebraic Laws For Regular Expressions: Let r1, r2 and r3 be three regular expressions 1. Commutative law for union: The commutative law for union, say that we may take the union of two languages in either order. r1 + r2 = r2 + r1 2. Associative law for union: The associative law for union says that we may take the union of three languages either by taking the union of the first two initially, or taking the union of the last two initially. (r1 + r2)+r3 = r1+(r2 + r3) 3. Associative law for concatenation: (r1r2)r3 = r1(r2r3) 4. Distributive Laws For Concatenation: → Concatenation is left distributive over union i.e., r1(r2 + r3) = r1r2 + r1r3 → Concatenation is right distributive over union i.e., (r1 + r2)r3 = r1r3 + r2r3 5.
Identities For Union And Concatenation: → ∅ is the identity for union operator i.e. r1 + ∅ = ∅ + r1 = r1 → is the identity for concatenation operator i.e. r1 = r1 = r1 6. Annihilators For Union And Concatenation: An annihilators for an operator is a value such that when the operator is applies to the annihilator and some other value, the result is the annihilator. ∅ is the annihilator for concatenation. i.e., ∅r1 = r1∅ = ∅ There is no annihilator for union operator. 7. Idempotent Law For Union: This law states that if we take the union of two identical expressions, we can replace them by one copy of the expression. i.e. r1 + r1 = r1 8. Laws Involving Closure Let ‘r’ be a regular expression, then 1. (r*)* = r* 2. ∅* = THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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3. * = 4. r+ = r.r* = r*.r i.e r+ = rr* = r*r 5. r* = r+ + 6. r? = + r (Unary postfix operator? means zero or one instance) Converting Regular Expression To Automata ( -NFA): Basis: Automata for , ∅ and a are (a), (b) and (c) respectively start
a
start
start q0
q0
qf
q0
(a) r = (b) r = ∅ Induction: Automata for r + s, rs and r* are (p), (q) and (s) respectively. q1
(c) r = a
f1
M1
Є star t
qf
Є f0
q0 Є
Є q2
f2
M2 (p) r+s
start
Є q1
M1
f1
q2
M2
f2
(q)rs
Є Є
start q0
Є q1
M1
f1
ff0 0
Є (s)r*
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Finite Automata with Output: Moore Machine: A Moore machine is a six-tuple (Q, , Δ, δ, λ, q0) Where Q: finite set of states : finite set of input symbols Δ: finite set of output alphabet δ: Q x → Q (transition function from Q x to Q λ: Q → Δ (λ is a function from Q to Δ) q0: start state In Moore machine output is associated with states Melay Machine: A Melay machine is sixtuple (Q, , Δ, δ, λ, q0) Q: finite set of states : finite set of input alphabet Δ: finite set of output alphabet δ: Q x → Q λ: Q x → Δ (i.e λ(q,a) gives the output associated with the transition from state q on input a) q0: starting state In Melay machine output is associated with each transition. Example: M = {{q0, p0, p1}, {0,1}, {y,n}, δ, λ, q0} 0/y p0 0/n 0/n 1/n q0 p1 1/n
1/y
Fig: Melay machine for (0+1)*(00 + 11) Equivalence of Moore and Melay machines: Melay machine equivalent to Moore machine: If M1 = (Q, , Δ, δ, λ, q0) is a Moore machine then there is a Melay machine M2 equivalent to M1. Construction of Moore machine: Let M = (Q, , Δ, δ, λ, q0) be the given Melay machine and M’ = (Q’, , Δ, δ’, λ’, [q0, b0]), Where B0 is an arbitrarily selected member of Δ THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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The states of Moore machine are [q0,y], [q0,n], [p0,y],[p0,n] [p1,y] and [p1,n]. As ‘q0’ is the start stae of Melay machine choose either [q0,n]. The start stae of Moore machine is [q0,n]
Regular Grammars Definition of a Grammar: A phrase-structure grammar (or simply a grammar) is ( V,T,P,S), where i. V is a finite nonempty set, whose elements are called variables. ii. T is a finite nonempty set, whose elements are called terminals. iii. V ∩ T = ϕ, iv. S is a special variable (i.e an element of V) called the start symbol, and v. P is a finite set whose elements are α → β, where α and β are strings on V ∪ T. α has at least one symbol from V. Elements of P are called productions or production rules or rewriting rules. Right-Linear Grammar: A grammar G = (V,T,S,P) is said to be right-linear if all productions are of the form A → xB A → x. Where A,B V and x T*. Left-Linear Grammar: A grammar G = (V,T,P,S) is said to be left-linear grammar if all productions are of the form A → Bx or A → x. Either right-linear or left-linear grammar is a Regular grammar. Example: The grammar G1 = ({s}, {a,b}, S, P1), with P1 given as S → abS/a is right-linear grammar. The grammar G2 = ({S, S1, S2}, {a,b}, S, P2} with productions. S → S1ab, S1 → S1ab|S2, S2 → a, is left-linear grammar. Both G1 and G2 are regular grammars. A language L is regular if and only if there exists a left-linear grammar G such that L = L(G). A language L is regular if and only if there exists a right-linear grammar G such that L = L(G). Construction of -NFA from right-linear grammar: Let G = (V,T,P,S) be a right-linear grammar. We construct an NFA with -moves, M = (Q,T,δ,[S],[ ]} that simulates deviation in ‘G’ Q consists of the symbols [α] such that α is S or a (not necessarily proper) suffix of some righthand side of a production in P. We define δ by: 1. If A is a variable, then δ([A], ) = { [α] | A → α is a production} 2. If a is in T and α in T* ∪ T*V, then δ([aα],a) = {[α]}
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Construction of ϵ-NFA from a left-linear grammar: If ‘G’ is a left-linear grammar we will reverse all the right hand sides of the productions then we will get right-linear grammar from which we will construct ϵ-NFA. To get ϵ-NFA of given leftlinear we will exchange initial, final states and reverse the direction of all the edges. Construction of right-linear and left-linear grammars from a given Finite Automata: Right linear grammar: Let M = (Q, , δ, q0, F) be the given finite automata. First suppose that q0 is not a final state. Then L = L(G) for a right-linear grammar G = (Q, , P, q0), where P consists of production p → aq whenever δ(p,a) = q and also p → a whenever δ(p, a) is a final state. Now let q0 be final state, so ϵ is in L. So introduce a new start symbol S with productions S → q0 | ϵ. Right linear grammar A → 0A| B, B → aB|bB|a|b A → B can be written as A → B (since B = B) The resulting grammar is A → 0A|B, B → aB|bB|a|b As A → B is a unit production we can eliminate it by substituting and the resulting grammar is A → 0A | aB|bB|a|b, B → aB|bB|a|b Now substitute 10 for a and 11 for b A → 0A | 10B|11B|10|11, B → 10B|11B|10|11 Left linear grammar: This can be obtained by reversing all the right hand sides of the production in the right – linear grammars and the production set contains the following productions. A → A0 | B01|B11|01|11, B → B01|B11|01|11 Overview of Finite Automata and Regular Expressions: 1. Regular sets DFA 2. NFA DFA 3. NFA – ε – Moves NFA 4. Regular Regular grammar 5. Regular grammar Right linear grammar 6. Regular grammar Left linear grammar 7. Regular set Unique minimal finite automata 8. Right linear NFA 9. Left linear NFA 10. Moore machine melay machine
Properties Of Regular Languages: Closure Properties of Regular Languages: 1. Regular languages are closed under union, concatenation and Kleene closure. 2. Regular languages are closed under complementation. That is, L is a regular language and L ⊆ *, then * - L is a regular languages. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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3. Regular languages are closed under intersection. That is if L1 and L2 are regular languages then L1 ∩ L2 and L1 ∪ L2 are also regular languages. 4. Regular languages are closed under difference. That is if L and M are regular languages, then so is L – M. 5. Regular languages are closed under string reversal. → The reversal of a string a1 a2 ……an is the string written backwards, that is an an-1 ….a1 we use WR for the reversal of a string w. The reversal of a language L, written LR, is the language consisting of the reversals of all its strings. Given a language L that is L (M) for some deterministic finite automata, we may construct an automata for LR by 1. Reverse all the arcs in the transition diagram for M 2. Make that start state of A be the only accepting states for new automata 3. Create a new start P0 with transitions on to all the accepting states of M. The result is an automata that simulates M “in reverse” and therefore accepts a string w if and only if A accepts wR. 6. Regular languages are closed under substitution. → Let R ⊆ * be a regular set and for each ‘a’ in , let Ra⊆ Δ* be a regular set Let f: → Δ* be the substitution defined by f (a) = Ra. Select regular expression denoting R and each Ra. Replace each occurrence of the symbol ‘a’ in the regular expression for R by the regular expression for Ra. Example: Let f (0) = a and f(1) = b* That is , f(0) is the language {a} and f(1) is the language of all strings of b’s then f(010) is the regular set ab*a. If L is the language 0*(0+1)1*, then f(L) is a*(a + b*) (b*)* =a*b*. 7. Regular languages are closed under homomorphism and inverse homomorphism. ⟶homomorphism: A homomorphism h is a substitution such that h(a) contains a string for each a. We generally take h (a) to be the string itself, rather than the set containing that string. Suppose and ∆ are alphabet, then a function h: ⟶∆* is called a homomorphism The domain of the function h is extended to strings in an obvious fashion: if W=a1a2 ….. an then h(w) = h(a1)h(a2) h(a3) …….h(an). If ‘L’ is a language on , then its homomorphic image is defined as h (L) = {h(w):w L}. 8. Inverse Homomorphism: The inverse homomorphic image of a language L is h-1(L) ={x / h (x) is in L} for string w,h-1(w) = {x / h (x) = w} 1. Regular languages are closed under quotient with arbitrary sets. Definition: The quotient of languages L1 and L2 written L1/L2 is {x | there exist y in L2 such that xy is in L1} 2. Regular languages are closed under INIT operation Definition: Let ‘L’ be a language. Then INIT(L) ={x/ for some y, xy is in L} THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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3. Regular languages are closed under Kleen closure. i.e if ‘L’ is a regular set then L* is also a regular set. Decision Algorithms for Regular languages: The set of sentences accepted by a finite automata M with n states is: 1. Non empty if and only if the finite automaton accepts a sentence of length less than ‘n’. 2. Infinite if and only if the finite automaton accepts some sentences of length l, where n ≤ l < 2n. Note: To test whether a DFA accepts the empty set, take its transition diagram and delete all states that are not reachable on any input from the start state. If one or more final states remain, the language is non empty. Then without changing the language accepted, we may delete “all states that are not final and from which one cannot reach a final state”. The DFA accepts an infinite language if and only if the resulting transition diagram has a cycle. The same method works for NFA’s also. Equivalence of Regular languages: There is an algorithm to determine if two finite automata are equivalent (i.e., if they accept the same language). ̅̅̅ ∩ L2) is accepted by →Let M1 and M2 be FA accepting L1 and L2 respectively. (L1∩ ̅̅̅ L ) ∪ (L some finite automaton M3. It is easy to see that M3 accepts a word if and only if L1 ≠ L2. Hence we can find whether L1 = L2 or not. Right invariant relation: A relation R such that xRy implies xzRyz is said to be right invariant (with respect to concatenation) Myhill-Nerode Theorem: The following three statements are equivalent. 1. The set L ⊆ * is accepted by some finite automaton. 2. L is the union of some of the equivalence classes of a right invariant equivalence relation of finite index. 3. Let equivalence relation RL be defined by :xRLy if and only if for all z in *, xz is in L exactly when yz is in L. Then RL is of finite index. Pumping Lemma for Regular languages: Pigeon Hole Principle: If we put ‘n’ objects into ‘m’ boxes (pigeon holes), and if n>m, then atleast one box must have more than one item in it. Pumping Lemma for Regular languages: Pumping Lemma uses pigeon hole principle to show that certain languages are not regular. This theorem state that all regular languages have a special property. There are three forms of Pumping Lemma.
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1. Standard Form of Pumping Lemma: Let ‘L’ be an infinite regular language. Then there exists some positive integer ‘n’ such that any z L with |z| ≥ n can be decomposed as z = uvw with |uv| ≤ n, and |v| ≥ 1, such that z = uvw, is also in L for all i = 0,1,2……. To paraphrase this, every sufficiently long string L can be broken into three parts in such a way that an arbitrary number of repetitions of the middle part yields another string in L. We say that middle string is “pumped”, hence the term Pumping Lemma for this result. 2. Strong Form of Pumping Lemma: If L is an infinite regular then there exists a ‘n’, such that the following holds for every sufficiently long z L and every one of its decompositions z = z1z2z3, with z1,z2 *, |z2| ≥ n. The middle string z2 can be written as z2 = uvw with |uv| ≤ n, |v| ≥ 1, such that z1uvwz3 L for all i = 0,1,2…….. 3. Weak Form of Pumping Lemma: Suppose L is an infinite regular language, there are integers p and q, with q>0, so that for every n ≥ 0, L contains a string of length p + nq. In other words, the set of integers, Lengths (L) = { |z| |z L} contains the “arithmetic progression” of all integers p + nq (where n ≥ 0). L (an infinite language)
Regular Language no
Yes Satisfies Weak form no Yes Satisfies Standard form
no
L is not regular
Yes no Satisfies Strong form
Yes We cannot say anything regularity of L If a language satisfies Pumping Lemma it may or may not be regular. But a language which doesn’t satisfy Pumping Lemma is not regular.
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Examples: Of pumping lemma 1. L = {0 | n prime} is not regular. 2. L = {a b | i > } is not regular. 3. L = {a b | n ≥ 0} is not regular 4. L = {ω ω ω ε } is not regular 5. L = {a b | n ≠ 1} is not regular 6. 7. 8. 9.
L = {a | n ≥ 1} is not regular. L = {0 | n ≥ 1} is not regular L = {∝ ω ∝ | ∝, ω in (0 + 1) } is not regular L = {∝ ∝ ω | ∝, ω in (0 + 1) } is not regular
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6.4: Context free grammar CFG is a 4 – tuple G = (V, T, P,S) where V and T are disjoint finite sets, S is an element of V, and P is a finite set of formulas of the form A → ∝ where A V and ∝ (VUT)*. Context free language: Let G= (V, T, P, S) be a CFG. The language generated by G is L(G) = {x is a CFL if there is CFG G so that L = L(G).
T*/S*→ x}. A language L
Leftmost And Rightmost Derivations and Ambiguity If at each step in a derivation a production is applied to the leftmost variable, then the derivation is said to be leftmost. If at each step in a derivation a production is applied to the rightmost variable, then the derivation is said to be rightmost. Derivations Tree: Let G (V,T,P,S) be a CFG. A tree is a derivation (or parse) tree for G if: Every vertex has a label, which is a symbol of V ∪ T ∪ { } The label of the root is S. If a vertex is interior and has label A, then A must be in V. If Vertex n has label A and vertices n1, n2..nk are the sons of vertex n, in order from the left, with labels X1,X2….Xk, respectively, the A → X1,X2.Xk must be a production in P. If vertex n has label , then n is a leaf and is the only son of its father. If w is L (G) for a CFG G, then w has at least two leftmost derivations or at least two rightmost derivations or at least two derivation trees then that grammar is said to be ambiguous.
Simplication of Context – Free Grammars If L is a nonempty CFL then it can be generated by a CFG with the following properties. Each variable and Each terminal of G appears in the derivation of some word in L There are no productions of the form A→B where A and B are variables. Furthermore if is not in L, there need be no productions of the A→ . In fact, if is not in L, we can require that every production of G be of one of the forms A→BC and A→ a, where A, B and Care arbitrary variables and is an arbitrary terminal Alternatively, we could make every production of G be of the from A→ a∝ where ∝is a string of variables (possibly empty). Elimination of useless symbols Let G ≈ (V,T,P,S) be a grammar A symbol X is useful if there is a derivation → ∝XB→ w for some ∝, β and w, where w is in T , otherwise X is useless. There are two aspects to usefulness. First some terminal string must be derivable from X and second, X must occur in some string derivable from S. These two conditions are not however; sufficient to guarantee that X is useful since X may occur only in sentential forms that contain a variable from which on terminal string can be derived. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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(A→ B means Band be derived from A after zero or more number of intermediate steps) Lemmal 1: Given a CFG =(V,T,P,S) with L(G) ≠∅, we can effectively find an equivalent CFGG =(V ,T,p ,S) ,such that for each A in V there is some w in T for which s w. Lemmal 2: Given a CFGG=(V, T, P, S) with : (G) ≠ ∅, we can effectively find an equivalent CFG G = (V , T , P ,S) such that for each X in V ∪ T there exists ∝ andβ in (V ∪ T )* for which S∝ Xβ Procedure for Eliminating Useless Symbols: Let G(V,T,P,S) be given CFG then by Applying Lemmal. G =(V , T,P ,S) can be find as follows, Calculation of V begin OLDV:=∅; NEWV:={A/A→w for some win T }; while OLDV≠NEWV do begin OLDV:=NEWV; NEWV:=OLWV: ∪{A/A→∝o for some ∝ in (T∪OLDV) } End ; P is the set of all productions whose symbols are in V ∪T. Now by applying lemma2 on G we can fine G as follows Place Sin V lf A is placed inV and A→∝ /∝ …./∝ , then add all variables of ∝ ,∝ …..∝ to set V and all terminals of ∝ ,∝ ….∝ toT p is the set of productions of P containing only symbols ofV ∪T Notes: Every Non empty CFL is generated by CFG with no useless symbols
Eliminating ϵ- productions : Productions of the form A →ϵare called -Productions Surely if ϵ is in L(G) we cannot eliminate all ϵproduction from G, but isϵ is not in L(G) it turns out that we can The method is to determine for each variable A whether A ϵ lf so we call A mullable we may replace each production B→X X …X by all productions formed by striking out some subset of those x ‘s that are nullable but we don ‘t include B → even if allX ‘s are nullable. →lf L = L(G) for some CFG G = (V,T,P,S) than L {ϵ} is L(G) for a C F GG with no useless symbols or ϵ- productions. Algorithm for finding nullable symbols of a CFG If A→ϵis a production, then A is nullable. Then if B→∝is a production and all symbols of ∝ have been found nullable, then B nullableWe repeat this process until no more nullable symbols can be found. The set of production P is constructed as follows. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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If A→X X .. ....X is in P, then add all productions A→∝ ∝ …..∝ isP then add all productions 1 If X is not nullable, then ∝ =X ; 2 If X is nullable, then ∝ is either X or ϵ; 3 not all ∝ s are ϵ lf G is CFG we can find an equivalent CFGG without nullable productions except S→ϵ when in L(G) lf S→ϵ is in the production set then ‘S’ dose appear on the right side of and other production Elimination of Unit Productions: Productions of the form A→B are called unit productions i.e., productions whose right hand side consists of single variable Procedure for eliminating unit productions: For every pair of different non terminals A and B, if a CFG with no ϵ- productions has unit production A→B of if there is a chain of unit productions leading from A to B, such as A=X =X =……. =B Where X , X are some non terminals, we then introduce new productions according the following rule lf the non –unit productions from B are B→∝ /∝ /∝ …. Create the productions A→∝ /∝ /∝ …. we do the same for all such pairs of A’s and B’s simultaneously We can then eliminate all unit productions. Note : Every CFL without is defined by a grammar with no useless symbols, -productions, or unit productions
Normal Forms Chomsky Normal Form Any CFL without έ is generated by a grammar in which all productions are of the form A BC or Aa. Here A,B and C are variables and ‘a’ is a terminal. Example: Consider the grammar ({S,A,B}, {a,b}, P,S} that has the productions SbA | aB A bAA | aS | a B aBB | bS | b And find an equivalent grammar in CNF. Solution: The only productions already in proper form are Aa and Bb. There are no unit productions, so we may begin by replacing terminals on the right by variables, except in the case of productions Aa and Bb. SbA is replaced by SCbA and Cb b Similarly AaS is replaced by ACaS and Caa AbAA is replaced by ACbAA SaB is replaced by SCaB BbS is replaced by BCbS, BaBB is replaced by BCaBB In the next stage THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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ACbAA is replaced by ACbD1 and D1AA BCaBB is replaced by BCaD2 and D2BB The complete lists of productions are SCbA|CaB ACaS|CbD1|a BCbS|CaD2|b D1AA D2BB Caa Cbb
Greibach Normal Form Every context-free language L without έ can be generated by a grammar for which every production is of the form Aaά, where A is a variable, a is a terminal and ά is a (possibly empty) string of variables. Lemma 3: Define an A-production to be a production with variable A on the left Let G = (V, T, P, S) be a CFG. Let Aά1 Bά2 be a production in P and Bβ1|β2|…..|βr be the set of all B-productions. Let G1 = (V, T, P1, S) be obtained from G by deleting the production Aά1Bά2 from P and adding the productions Aά1β1ά2|ά1β2ά2|ά1β3ά2|……..|ά1βrά2.Then L(G) = L(G1). Lemma 4: Let G = (V,T,P,S) be a CFG. Let AAά1|Aά2|. . . . |Aάr be the set of A-productions for which A is the leftmost symbol of the right-hand side. Let Aβ1|β2|. . . . |βs. Let Aβ1|β2|. . . . |βs be the remaining A-productions. Let G1 = (Y ∪ {B}, T, P1, S) be the CFG formed by adding the variable B to V and replacing all the A-productions by the productions. 1) Aβi 2) Bαi AβiB 1≤ i ≤ S BαiB 1≤ i ≤ r Then L (G1) = L (G). By applying Lemma1 and Lemma2 we can construct GNF form -free CFL. Inherently ambiguous context free language: A context free language for which we cannot an unambiguous grammar is inherently ambiguous CFL. Ex:- L = {an bncm dm|n≥ 1, m ≥ 1} ∪ {anbmemdn|n≥ 1, m ≥ 1}. An operator grammar is a CFG with no - productions such that no consecutive symbols on the right side of productions are variables. Every CFL without has an operator grammar If all productions of a CFG are of the form AωB or Aω, then L (G) is a regular set where ω is a terminal string.
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Pushdown Automata Just as the regular sets have an equivalent automaton the finite automaton, the context free grammars has their machine counterpart - the pushdown automation. The deterministic version of PDA accepts only a subset of all CFL’s where as non-deterministic version allows all CFL’s. The PDA will have an input tape, a finite control, and a stack.
Q0 Z0 Where Qo is initial state and Zo is bottom stack symbol. The language accepted by a PDA can be defined in two ways. 1. The first is the language accepted to be the set of all inputs for which some sequences of moves causes the pushdown automaton to empty stack. Definition of PDA: A PDA M is a system (Q, ,F,δ,q0,Z0,F), where 1. Q is a finite set of states; 2. Ε is an alphabet called the input alphabet; 3. F is an alphabet called the stack alphabet; 4. Q0 in Q is the initial state; 5. Z0 in F is a particular stack symbol called the star symbol; 6. F ε Q is the set of final states; 7. δis a mapping from Q*( ∪ { }) x F to finite subsets of Q x F*. Instantaneous Descriptions: To formally describe the configuration of a PDA at a given instant we define an instantaneous description (ID), we define an ID to be trible (q, w, r), where q is a state, w is a string of input symbols, and ‘γ’ a string of stack symbols. If M = (Q,E,F,δ,qo,Z0,F) is a PDA, we say (q, aw, zά) (p, w, βά) if δ(q, a, z) contains (p, β) note that a may be ε or an input symbol. We use */M for the reflexive and transitive closure of /M. That is l */ I for each ID I, and I */M j and J*/M k imply I */M K. we write 1 I K if ID i can become k after exactly I moves the subscript is dropped from |M i|M and *|M whenever the particular PDA M is understood. We can define L(M) the language accepted by a PDA M = (Q, , , δ, q0 z0, ) find state to be, {w/(q0 w, z0) * (p, , γ) for some p in F and γ in F*}. We define N(M), the language accepted y empty stack (or null stack) to be {w/( q0 w, z0) * (p , ) for some in Q}. When acceptance is by empty stack, the set of final states is irrelevant, and in this case, we usually let the set of final states be the empty set. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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Deterministic Pda’s A PDA M = (Q, δ q0 z0, F), is deterministic if: For each q in Q and Z in , whenever δ (q, z) is nonempty, then δ (q, a z ) is empty for all a in : 2. For non q in q Z in and a in ∪{ } does δ (q, a, z) contain more than one element Note: for finite automata, the deterministic and non- deterministic models were equivalent respect to the languages accepted. The same is not true for PDA’s DPDA’s accepts only a subset languages accepted NPDAs. That is NPDA is more powerful tan DPDA. If L is a CFL, then there exists a PDA, m that accepts L. 1.
Construction of CFGfrom A PDAwith Empty Stack If M = (Q, , , δ, q0, z0, ϕ) is a PDA with empty stack then there exist an equivalent CFG (V, ,P,S ). If Q is {q0,q1} then V consists of S, [q0,z0, q0], [q0,z0, q1], , [q0, A, q0], , [q0, A, q1], , [q1,z0, q0], , [q1,z0, q1] , [q1,A, q0], , [q1, A, q1]. Production set P is Rule 1: S → , [q0,z0, q],for each q is Q. Rule 2: Each move erasing a pushdown symbol given by (q1, ϵ) ϵ δ ( q, a, A) induces the production ,[q, A, q1] →a. Rule 3: Each move not erasing a push down symbol given by , [q1,B1B2.....Bm) ) ϵ δ (q, a, A) induces many production of the form ) [q, A qm+1] → a [q1, B1,q2], [q2,B2,q3]. . . . [qm, Bm,qm+1] Where each of the sates q, q1, q2…..qm+1 can be any one of the states in Q, each a in ⋃ { }.
Deterministric Pushdown Automata A PDA P = (Q , , ,δ, q0,z0,F) to be deterministic, if and only if the following condition, are met: 1. δ (q,a,x) has at most one member for any q in Q , a in , or a = , and x in . 2. If δ (q,a,x) is nonempty, for some a in , then δ (q, ,x) must be empty. {wcwR | w is in (0+1)*} can be recognized by a deterministic PDA. The strategy of the DPDA is to store 0’s and 1’s on its stack, until it sees the center mark c. It then goes to another state, in which it matches input symbols against stack symbols and pops the stack if they match. If it ever finds a non match, its input cannot be of the form wcw R. If it succeeds in popping its stack down to the initial symbol, which marks the bottom of the stack then it accepts its input. Important Points 1. A language L is accepted by some DPDA with empty stack if any only if L has the prefix property (A language L has the prefix property if there are no two different strings x and y in L such that x is a proper prefix of y) and L is accepted by some DPDA by final state. 2. The languages accepted by DPDA’s by final state properly include the regular languages, but are properly include the regular languages, but are properly included in the CFLS. 3. The two modes of acceptance by final state and empty stack are not the same for DPDA’s Rather, the languages accepted by empty stack are exactly those of the languages accepted by final state that have the prefix property. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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4. All the regular language are accepted (by final state) by DPDA’s and there are non regular languages accepted by DPDA’s. The DPDA languages are context free languages, and in fact are languages that have unambiguous CFG’s. The DPDA languages lie strictly between the regular languages and the context free languages. 5. Deterministic CFLs are closed under complements, inverse homomorphism, 6. Intersection with regular sets and regular difference (DCFL – regular). 7. Deterministic EFLS are closed under union, concatenation, kleene closer, homomorphism and intersection.
Properties of Context Free Languages Closure properties of context free languages. Context free languages are closed under union. i.e., union of two CFL’s is again a CFL. Context free languages are closed under concatenation (Product) i.e., when we concatenate two CFL’s we will get another CFL. Context free languages are closed under Kleene closure i.e., is a CFL then L* is also CFL. Context – free languages are closed under substitution. Let L be a CFL L ⊆ *, and for each a in let La be a CFL. Let L be L (G) and for each a in let La be L (Ga). Assume that the variables of G and the Ga’s are disjoint. Construct a grammar G1as follows The variables of G1 are all the variables of G Ga’s The terminals of G1 are the terminals of the Ga’s The stat symbol of G1 is the start symbol of G. The productions of G1 are all the productions of the Ga’s together with those productions formed by taking a production A → α of G and substituting Sa the start symbol of Ga for each instance of a in appearing in α. CFL’s are closed under homomorphism: A type of substitution that is of special interest is the homomorphism. A homomorphism h is a substitution such that h (a) contains a single string for each a. we generally take h(a) to be the string itself, rather than the set containing that string. As CFL’s are closed under substitution, we can say that CFL’s are closed under homomorphism. The context free languages are closed under inverse homomorphism. If ha is a homomorphism, and L is any language, then h-1 (L) is the set of strings w such that h(w) is in L. The PDA to accept the inverse homomorphism of what a given PDA accepts.
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Input a
h
Theory of Computation
h(a) P DA state
Accept / Reject
The key idea in this diagram is that after input a is read, h (a) is placed in a “buffer”. The symbols of h(a) are used one at a time and fed to the PDA being simulated. Only when the buffer is empty does the constructed PDA read another of its input symbols and apply the homomorphism to it. If L is a CFL and R is a regular language, then L ∪ R is a CFL: A PDA and a FA can run in parallel to create a new PDA as shown below.
FA state
AND
Accept/Reject
PDA state
stack
If L is a CFL’s and R is a regular language then L - R is a context – free language If L is a CFL’s and R is a regular language then Intersection between these two is a context – free language If ‘L’ is a CFL then LR (Reversal of L) is a CFL. Let L = L (G) for some CFG G = (V,T,P,S). Construct. GR = (V,T.PR,S), where PR is the “reverse” of each production in P. That is, if A → α is a production of G, then A→αR is a production of GR An easy induction on the lengths of derivations of sentential forms of G, and vice versa.
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CFL’s are closed under INIT operation. INIT (L) = {w | for some x, wx is in L}. ‘L1’ and ‘L2’ are two CFL’S then L1 ∩L2 may or may not CFL . That is CFL’s are not closed under intersection. May CFG All regular languages are context- free. The intersection of two regular languages is regular therefore, if L1and L2 are regular and context – free, then L1 ∩L2 is both regular and context free. May not CFG Let L1 = {anbnam| where n, m = ,1,2,3……., but n is not necessarily the same as m} Let L2 = {anbmam| where n, m = ,1,2,3……., but n is not necessarily the same as m} Both the languages are context – free, but their intersection is the language L3 = L1 ∩ L2 {anbnan for n = 1,2,3……} Which is not a CFL (we will prove it later). Therefore, the intersection of two context – free languages can be non – context- free The Complement of a context-free language may or not be context-free.
Decision Algorithms for CFL’s: 1. Given a CF G G = (V,T,P,S) there exists an algorithm for deciding whether or not L(G) is empty, finite or infinite. Assume the given language does not contain . Find the reduced grammar (i.e., eliminate useless productions, - productions and unit productions) of the given grammar. 1. If the reduced grammar vanishes then the given language is empty. 2. Draw a graph with the productions of the reduced grammar. If the graph contains cycle the given grammar generates infinite language, otherwise it generates finite language.
Non-Context-Free Languages Important points: 1. Let G be a CFG in CNF. Let us call the productions of the form Non-terminal → Nonterminal Nonterminal; Live and the productions of the form Nonterminal → terminal; Dead. 2. If G is a CFG in CNF that has p live productions and q dead productions, and if w is a word generated by G that has more than 2p letters in it, then somewhere in every derivation tree for w there is some non-terminal being used twice where the second z is descended from the first z. 3. In a given derivation of a word in a given CFG, a non-terminal is said to be self-embedded if it occurs as a tree descendent of itself.
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The Pumping Lemma for CFLs Pumping Lemma for CFL’s is used to show that certain languages are non context free. There are three forms of pumping lemma. Standard form of pumping lemma:- Let “L” be any infinite CFL. Then there is a constant such that i) |vx| ≥ 1, ii) |vwx| ≤ n, and iii) for all i ≥ 0, uv’wx’y is in L. Strong form of pumping lemma (Ogden’s Lemma): Let L be an infinite CFL. Then there is a constant n such that if z is any word in L, and we mark any n or more positions of z “distinguished”, then we can write Z = uvwxy such that v and x together have atleast one distinguished position, vwx has atmost n distinguished positions, and for all i ≥ 0, uv’wx’y is in L. Weak form of pumping Lemma: Let L be on infinite CFL. When we pump the length of strings are |uvwxy| = |uwy| + |vx| |uv2wx2y| = |uwy| + 2|vx| ………………………… |uv’wx’y| = |uwy| + i|vx| when we pump the lengths are in Arithmetic progression
Membership Algorithm For Context – Free Grammars Assume that we have a grammar G = (V, T, S, P) in Chomsky normal form and a string w = a 1 a2 …an We define sub strings wij = ai……aj and subsets of V Vij = { A V : A
Wij}
Clearly w ϵ L (G) if and only if s ϵ V1n. To compute Vij observe that A ϵ Vii can be computed for all 1 ≤ i≤ n by inspection of w and the productions of the grammar. To continue, notice that for j >i, A derives wij if and only if there is a production A → BC, with B
wik and C
W(k + 1)j for
some k with i ≤ k < j. In other words, Vij* = ∪ {A : A → BC, with B ϵVik, C ϵ V(k + 1)j}. kϵ { i,i + 1 , ….j – 1} All the Vij ‘s can be easily computed if we follow the following sequence. Compute V11, V22, …….Vnn Compute V12, V23, …….Vn -1, n Compute V13, V24, …….Vn – 2, n And so on.
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6.5: Turing Machines A tuning machine is an automaton whose temperature storage is a tape. This tape is divided into cells, each of which is capable of holding one symbol. Associated with the tape is a read-write read that can be travel right or left on the tape and that can be read and write a single symbol on each move A diagram giving an intuitive visualization of turning is … … .
… … .
an
B
… … ….
Finite Control Definition: A Turing machine M is defined by M = (Q,ε, δ q B, F) where Q is the inite set of internal states is the finite set of allowable tape symbols B a symbol of is the blank εis a subset if not including B is the set of input symbols, δis the next move function a napping from Q x to Q x x {L,R} (δ may however undefined for some arugements) Q0 in Q is the start state, F Q is the head of final states We denote instantaneous description (ID) of the Turing machine M by α qα Here q the current state of M is in Q, α α is the string in we assume that Q and are disjoint to avoid confusion Finally the tape head is assumed to be scanning the left most symbol of α or if α = ,the head is scanning a blank We define a move of M as follows Let x1,x2,x3……xi ….qx….xn be an ID suppose δ(q, x) = (P, , L) where if i-l=1=n then x is taken to be B if i=1 then there is no next ID as the tape head is not allowed to fall off the left end of the tape if i>1 then we write x1,x2…….xi-1qx1….xn However if any suffix is completely blank that suffix is deleted in (1) Note that in the case i-1=n the string x1…..xn is empty and the right side of (2) is longer than the left side if two ID’s are related by M say that the second results from another by some finite number of moves including zero moves they are related by the symbol M The language accepted by M denoted L (M) is the set of those words in that cause M to enter a final state when placed justified at the left on the tape of M with M is state q0 and the tape head of M at the left most cell .Given a TM recognizing a language L we assume without loss of generality that the TM halts i.e., has no next move whenever the input is a accepted However for words not accepted it is possible that the TM will never halt.
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Modification of Turing Machines 1.
Two – Way infinite TM: L is recognized by a turing machine with a two-way infinite tape if and only if it is recognized by a TM with one-way infinite tape
……. .
a
a2
………… ……….
a1
B
…… ….
…… …
Finite control 2. Multitape – TM: If L is a language, accepted by a multi tape turing machine it is accepted by a single-tape machine Finite control
……… ……… ……… ………
…… …… …… …… …… ……
……… ……… ……… Fig: Multitape TM 3. Non – deterministic TM:If L is accepted by a non – deterministic turing machine M1,then L is accepted by some deterministic turing machine M2. 4. Multi Dimensional TM:In K-dimensional TM the tape consists of K- dimensional array cells infinite in all 2K direction for some fixed K. If L is accepted by a K-dimensional turing machine M1, then L is accepted by some Single tape turing machine M2. 5. Multi Head Turing Machine: A K- head TM has some fixed numer K of heads The heads are numbered I through K and a move of TM depends on the state and on the symbol scannd by each head In one move the haeds may move independently left right or remain stationery If L is accepted by some K-head by some K-head TM M1, it is accepted by a one head TM M2,
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…………… …
…………… … Finite control
Fig: K – head TM 6. MULTI TRACK TURING MACHINE: we can imagine that the rope of the TM is divied into k tracks, for any finite k.
k-tracks
Finite control 7. TURING MACHINE WITH STAY OPTION: In these TMs the read-writehead can stay atthe current position upon reading an input symbol (possibly changing) without moving left to right. 8. OFF-LINE TURING MACHINE: An off-line TM is a multitape TM whose input tape isread-only. Usually we surround the input by end makers’ c on the left and s on the right. The turing machine is not allowed to move the input tape head off the region between c and s it should be obvious that the off-line TM is just a special case of the Multiple TM. An off-line TM can simulate any TM M by using one more tape than M. The first thing the off-line TM does is copy its own input onto the extra tape and it then simulates M as if extra tape were M’s input. All these Modifications does not add any language accepting power and all these are equivalent to the Basic model. POST MACHINE: A post machine denoted PM, is a collection of five things: 1. The alphabet of input letters plus the special symbol 2. A linear storage location (a place where a string of symbols is kept) called the STORE or QUEUE which initially contains the input string. We allow for the possibility that characters not in can be used in the STORE, characters from an alphabets called the store alphabet. 3. Read states, for example which remove the left most character from the STORE and branches accordingly? The only branching in the machine takes place at the Read states. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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There may be a branch for every character in from the READ have the same label.
Theory of Computation
or PMs are deterministic so on two edges
#
a
read
b
4. ADD states
ADD
a
ADD
b
ADD
#
Which concatenate a character onto the right end of the string in the STORE. This is different Form PDA pushes state .No branching can take place at an ADD state.It is possible to have an ADD state for every letter in and 5.
A start state (unutterable) and some halt states called Accept and REJECT
start
ACCEPT
REJECT
We could also define a Non deterministic post machine NPM. This would allow for more than one edge with the same label to come from a READ state. In their strength NPM-PM. Two - Stack Machine: A two-push down stack machine a 2PDA is like a PDA except that it has two push down STACKS,STACKS1,STACKS2.When we wish to push a character x into a stack, we have to specify which stack either PUSH1 x or PUSH2 x . When we POP a STACK for the purpose of branching we must specify which STACK either POP1 or POP2 (Read a character from read-only input tape) the functions of start, Read, Accept and Reject are same as in the post machine.
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Counter-Machines: A counter machine may be thought of in one or two ways: 1. The counter machine has the same structure as the multistack machine but in place of each stack is a counter .Counters hold any nonnegative integer but we can only distinguish between zero and nonzero counters. That is the move of the counter machine depends on its state input symbol and which if any of the counter are zero . In one or more the counter machine can a. Change state b. Add or subtract 1 form any of its counters, independently. However a counter is not allowed to become negative, so it cannot subtract from a counter that is currently 0 2. A counter machine may also be regarded as a restricted multistack machine. The restrictions are as follows. a. There are only two stack symbols. Which we shall refer to as z (the bottom of stack marker), and X. c. Zo is initially on each state d. We may replace Z0 only by a string of the form XZ0 for some i ≥ 0. e. We may replace X only by X’ for some i ≥ 0That is Z0appears only on the bottom of each stack and all other stack symbols if any are X. The two definitions clearly define machines of equivalent power 1. Every recursively enumerable language is accepted by a three counter machine( we can simulate two stacks by 3-counters only) 2. Every recursively enumerable language is accepted by a two-counter machine(we can simulate two stacks by 2-counters only) 3. Every recursively enumerable language is accepted by a 3-pebble machine (3-pebble machine are sufficient to simulate two counters).
….
….
….
….
….
….
…… .
3-PEBBLES
Storage in the State: We can use the finite control not only to represent a position in the ‘program’ of the turing machine but to hold a finite amount of data. The technique requires no extension to the TM model we merely think of the state as a tuple.
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State
q A
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B
C
Storage
……… … The transition function of above TM is as follows: 1. δ([q , B], a = ([q , a], a, R) For a=0 or a=1initially is the control state , and the data in state is B. The symbol scanned is copied into second component of the state and M moves right entering control state as it does so. 2. δ([q , a], a = ([q , a], a, R) wherea is the “complement” of a that is 0 if a=1 and 1 if a=0 in state M skips over each symbol 0 or 1 that is different from the one it has stored in its state, and continues moving right 3. δ([q , a], B = ([q , B], B, R)for a=0 or a=1 if M reaches the first blank it enters the accepting state [ , ]. Notice that M has no definition for δ([q , a], a) for a=0 or a=1 Thus if M encounters a second occurrence of the symbol stored initially in its finite control it halts without having entered the accepting state,
Multiple Tracks: Another useful “ trick” is to think of the tape of TM as composed of several tracks each track can hold one symbol and tape alphabet of the TH consists of tuples, eith one component for each track. Like the technique of storage in the finite control, using multiple tracks does not extend what the TM cando. A common use of the multiple track is to treat one track as holding the data and a second track as holding a mark. We can check of each symbol as we use it or we keep track of a small number of positions within the data marking those positions. Finite control
X
Track 1 Track 2 Track 3
Y X
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Universal Turing Machine: An universal TM Mo is an automation that given as input the description of any M. and a string w. can simulate the computation of M on we to occur construct such an Mo. We first choose a standard way of description turing machines we maywithout of generality, assume that. Q = {q ,q q } With q the initial state q the single final state and ={a. , a , … … … … . . a } Where a represents the blank. We then select an encoding in which q is represented 1 q is represented by 11 and so on. Similarly a is encoded as 1 a as 11 etc. the symbol ‘O’ is used as a separator between the 1’ s wit the initial and final stare and the blank defied by this conversion any turingmachine can be descried withδ only. The transition function is encoded according to this scheme, with the arguments and result in some prescribed sequence For example δ(q , a ) = (q a , L)might apper as ……………… 10110110111010………………… It follows from this that any Turing machine has finite encoding as a string on {0,1} +, and that any encoding of M, we can decode it uniquely. Some strings will not represent any Turing machine (e.g) the string 00011), but we can easily spot these, spot these, so they are of no concern. A universal TM M , then has an input alphabet that includes {0, 1} and the structure of a multitape machine as shown below . Control Unit of
Description of M
Internal states of M
Tape contents of M For any input M and W tape will keep an encoded definition of M, tape 2 will contain the tape contents of M and tape 3 the internal state of M Mu looks first at the contents of tape 2 and 3 to determine the configuration of M. it then consults tape1 to see what M would do in this configuration. Finally tapes 2 and tapes 3 will be modified to reflect the result of the move This implementation clearly can be done using some programming languages. There, we expect that it can also be done by a standard Turing machine Context sensitive grammar: A grammar G=(V,T,P,S) is said to be context-sensitive if all production are of the form α → β Where α, β ε (VUT)+and |α|≤ |β| THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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This definition shows clearly one aspects of this type of grammar. It is non contracting in the sense that the length of successive sentential forms can never decrease. Context sensitive language: A language is said to be context sensitive if there exists a context sensitive grammar G, such that L = L (G) or L=L(G) U {ε} Context sensitive grammar does not contain productions of the form αε so, that a contextsensitive grammar can never generate a language containing the empty strong By including the empty string in the definition of a context-sensitive language, we can claim that the family of context-free language is a subset of the family of context sensitive language
Linear Bounded Automata A linear bounded automata (LBA) is a non deterministicTuring machine satisfying the following two conditions. 1. Its input alphabet includes two special symbols C and $, the left and right end markers, respectively 2. The LBA has no moves left from C or right from $, nor it may print another symbol over C or $. The linear bounded automaton is simply a Turing machine which, instead of having potentially infinite tape on which to compute, is restricted to the portion of the tape containing the input & plus the two tape squares holding the end markers . Restricting the Turing machine to an amount of tape that, on each input is bounded by some linear function of the length of the input would result in the identical computational ability as restricting the turing machine to the portion of the tape containing the input- hence the name “linear bounded automation” An LBA will be denoted M = (Q. , ,δ, q , C, $, F ), where (Q. , ,δ, q , C, $, F ). Were Q. , ,δ, q , and F are as for a Nodeterministic TM; C and $ are symbols in the left and right end markers L (M) , the language accepted by M, is {w|w is in ( - {C, $ })* and q c w $
∝ qβ for some q in F}
M 1. If L is a CSL, then L is accepted y some LBA. 2. IF L = (M) for LBAM = ((Q. , ,δ, q , C, $, F ) then L – { } is a CSL 3. Every CSL is recursive but converse is not true. A string is accepted a LBA if there is a possible sequence of moves q C w$ C ∝ q ∝ $ For some q F, ∝ , ∝ *.The language accepted by the LBA is the set of all such accepted strings. Hierarchy of formal languages (Chomsky Hierarchy ) 1. Unrestricted grammars (or Type 0 of grammars ): A grammar G = (V, T, P, S) is called unrestricted if all the production are of the form ∝β + Where ∝ is in (VUT) and β is in (VUT)* Any language generated by an unrestricted grammar is recursively enumerable.
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2. Content sensitive grammars (or type 1 grammars ): A grammar G = (V, T, P, S ) is said to be context sensitive if all productions are of the form ∝β Where ∝ B, (VUT) + and |∝| ≤|β| (Except for S and start symbol S does not appear on the right hand side of any production) 3. Context free grammars (Tupe2 grammars): A grammar G = (V,T,PS) is said to be context – free if all production in P the form A∝, Where A V and ∝ (VUT)* 4. Regular grammar: A right linear grammar consists of production of the form AxB, Ax where A,B ε V and x T*. A left linear grammar consists of productions of the form AB x Ax where A,B ε V and x ε T*. Type 0 Type 1
Type 2
TYPE3 OR REGULAR GRAMMAR
OR CONTEXT FREE GRAMMAR OR CONTEXT SENSITIVE GRAMMAR
OR UNRESTRICTED GRAMMAR
TYPE3 TYPE2 TYPE1 TYPE 0
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UNDESIDABILITY: Recursive language: A language L over the alphabet Σ is called recursively enumerable if there is a TM T that access every word in L Recursive enumerable language: A language L over the alphabet Σ is called recursively enumerable if there is a TM T that accepts Every word in L the either rejects or loops for every word in the language L , the complement L. Non recursively enumerable language : For any nonempty Σ there exists languages there exist language that are not recursively enumerable Suppose we have a list of (0+1)* in canonical order(if = {0,1}, The canonical order is 0,1,00,01,10,11,000,000…}Where W is the ith word, and M is the TM whose code is the integer j written in binary, imagine an infinite table that tells for all I and j whether W is in L(M ) J
i
1
2
3
4
…………..
1
0
1
1
0
……………
2
1
1
0
0
…………..
3
0
0
1
0
…………..
4
0
1
0
1 Diagonal
We construct language L by using the diagonal entries of the table to determine membership inL To guarantee that no TM accepts L .We insist that W is in L if and only if if the (i.i) entry is 0. that is , if M doesnot accept W Suppose that some TM MJ accepted L . Then we are faced with the following contradiction if W .is in L then (j.j) entry is 0, implying that w is tin L(M ) and contradiction if L = L(M ) or the other hand if W is not in L the (j, j) entry is 1, implying that W is I l(M ) , which again contradicts L = L(M ) , as W is either in or not in Ld we conclude that our assumption L = L(M ) is false. Thus no TM in the list accepts L . The universal language: Define L , the “universal language “ to be { / M accepts w} we call L “ universal since the question of whether any particular string W in ( 0+1)* is accepted by any particular TM.. M THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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is equivalent to the question of whether is in Lu. Where M’ is the one tape TM with tape alphabet {0,1,B} equivalent to M. Lu is recursively enumerable but not recursive Ld is recursively enumerable but not recursive Relationship between recursive, recursively enumerable and non enumerable languages
Non recursive enumerable
Recursively enumerable
Recursive
But not recursive enumerable
Reductions
If there is a reduction from p1 to
then:
a) If p1 is un decidable then so is b) If p1 is non-RE, then so is
yes
yes N0 o
no
P1
P2
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Turing machines that accept empty language: (L∅ ) L = { all encoded TM’s whose language is empty } or { M/L(M)=ø} (L ∅ ) L ={ all encoded TM’s whose language is not empty} or {M/L(M)≠ø} i.eL is the language of all codes for TM’s that accept at least one input string . L is recursively enumerable. We have only to exhibit a TM that accepts L Accept
guessed W U
M
Accept
Accept
M for
Fig: construction of NTM to accept The operation of M is as follows 1. M takes as input a TMcode M 2. Using it’s non determine capability. M guess an input W that M might accept 3. M tests whether Mi accepts W for this part M can simulate the universal TM U that accepts Lu 4. If Mi accepts wi, then W accepts it’s own input , which isM in this manner, If M1accepts even one string M will guess that string and accept Mi. however, if L(M )=ø then no guess w leads to acceptance by M . So M does not accept M thus L(M)=L . L is non recursively enumerable Let A be a hypothetical algorthim accepting L . There is an algorithm B that given Constructs a TM M that accepts ø if M does not accept W and accepts (0+1)* if M accepts w. the plan of the construction ofM is as shown below W
accept
accept
M X
M’
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M ignores it’s own input x and instead simulates M on input W, accepting note that M is not B. Rather B is like a compiler that takes as “ source program” and produces M’ as “ object program “ the construction of B is simple, it takes and isolates W say W = a a …….. a is of length n, B creates n+3 states q , q ,-----------q +3. With moves δ(q X) = (q ,$, R) for any X (print maker), δ(q ,X)=(q +1, a , R) for any X and 2≤ 1 ≤ n+1 (print w) δ(q ,X) = (q ,B,R) for X≠B (erase tape) δ(q ,B) = (q ,B,L) δ(q ,X) = δ(q ,,B,L) for X ≠$ (find maker) having produced the code for these moves B then adds n+3 to the indices of the states of M and includes the move δ(q , $) = δ(q , $,R) /* state up M*/ and all the moves of M it is generating TM Now suppose algorithm A accepting L shown below.
exists. Then we construct an algorithm C for L
as
yes yes (M,w)
A
B
No No
Fig: algorithm constructed for
assuming that algorithm A for
exists.
As L is RE it doesn’t have algorithm . thusL is not recursive. If L were recursive, L would also. Thus L is R.E but not recursive, If L were R.E then L and L would be recursive . ThenL is not recursively enumerable .
Yes start w
M
yes
X
Fig: TM
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As in the previous example, we have described the output of A. we leave the construction of A to the reader. ̅̅̅ as shown below Given A and M we could construct a Tm acceptingL
yes yes
A
Which behaves as follows. On input the TM uses A to produce M , uses M to determine if the set accepted by M is recursive, and accepts if and only if L(M ) is recursive iff L(M ) = ∅, which mean M does not accept w. thus the above hypothetical TM accepts off is in L Now let us turn to L . Suppose we have TM M accepting L and an algorithm B, to be ̅̅̅ B takes as input and produces as output a TM constructed by the reader, to accept L M such that L(M ) = if M accepts w, L if M does not accept w.
M
yes
yes
yes
X
yes
B
Thus M accepts a recursive language iff M accepts w. M which B must produce, is shown in fig (a) and TM to accept ̅̅̅ L given B and M is shown in fig (b) The TM of fig (b) accepts iffL(M ) is not recursive or equivalently, if and only if M does ̅̅̅ since we have already shown that not accept w. i.e., the TM accepts iff is in L
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no such Tm exists , the assumption that M exists is false. We conclude that L is not recursively enumerable. Rice theorem for recursive index sets: We can’t decide if he set accepted by a turingmachine is empty, recursive, finite, infinite regular, context free or has an even number of strings, or satisfies many or satisfies many other predicates. We can decide only trivial predicates,“ does a TM accepts a R.E which are either true for all Turing machines or false for all TM’s. Rice’s theorem: any nontrivial property of the r.e languages is undecidable. Rice’s theorem for recursively enumerable index sets The condition under which a set L is R.E is for more complicated. We shall show that L is R.E iff satisfies the following three conditions. 1. If L is in and L L , for some R.EL then L is in 2. If L is an infinite language in , then there is a finite subset of L in 3. The set of finite languages in is enumerable, in the sense that there is a Tm that generates the (possibly) infinite string code1# code2#........., where code1 is a code for the ith finite language in (in any order). The code for finite languages { w , w , … w } is just w ,w ,…w . IMP Points: Point 1: If does not have the containment property then, L is not R.E Point2: If has an infinite language L such that no finite subset of L is in , than L is not R.E Point3: If L is R.E, then the of binary codes for the finite sets in L is enumerable L isR.Eiff 1. If L in and L L for some R.E, L then L , is in . 2. If L is an infinite set in then there is some finite subset L of L that is in . 3. The set of finite languages in is enumerable The following properties of R.E sets are not R.E (A) L = ∅ (B) L = * (C) L is recursive (D) L is not recursive (E) L is a singleton (has exactly one member) (F) L is a regular set (G) L – Lu = ∅ Proof: in each case condition 1 is violated, except for (B) where 2 is violated and (G), where 3 is violated. The following properties of R.E sets are R.E (A) L ≠ ∅ (B) L contains at least 10 members. (C) W is in L for some fixed word w. (D) L ∩ Lu ≠ ∅
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Post correspondence problem: It is a valuable tool in establishing other problems to undecidable. An instance of post correspondence problem (PCP) consist of two lists, A = w , . . w and B = x , … x of strings over some alphabet . This instance of PCP has a solution if there is any sequence of integers i , i , … i with m ≥1, such that w w ….w = x x …x The sequence i , i , … i is a solution to this instance of PCP . In the following table D means decidable,U means undecidable, T means Trivially decidable and ? means open question( answer is not known).
Question
Regular Sets D
DCFL's
CFL's
CSL's
D
D
D
D
D
2. is L=∅? (Emptiness problem)
D
D
D
U
U
U
3.is L = *? (completeness problem)
D
D
D
U
U
U
4. is L1 = L2? (equality problem)
D
?
U
U
U
U
5.is L1⊑ L2 ? (subset problem)
D
U
U
U
U
U
6. is L1 ∩ L2 = ∅?
D
U
U
U
U
U
7.i s L - R, where R is a given regular set
D
D
U
U
U
U
8.is L regular?
T
U
U
U
U
U
9.i s the intersection of two languages, a language of the same type?
T
U
U
T
T
T
1. is w in L? (membership problem)
Recursive Sets r.e Sets
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10. is the complement of a language also a language of the same type
T
T
u
?
T
U
11.is L finite or infinite?
D
D
D
U
U
U
DCFL's
CFL's
Closure properties of formal languages Regular Sets
CSL's
Recursive Sets ✓
R.E Sets
1. Union
✓
X
✓
✓
2. Concatenation
✓
X
✓
✓
✓
✓
3. Kleene closure
✓
X
✓
X
X
✓
4. Intersection
✓
X
X
✓
✓
✓
5. complementation.
✓
✓
X
?
✓
X
6. Homomorphism
✓
X
✓
X
X
✓
7. Inverse Homomorphism
✓
✓
✓
✓
✓
✓
8. Substitution
✓
X
✓
✓
X
✓
9. Reversal
✓
X
✓
✓
✓
✓
10. Intersection with regular sets
✓
✓
✓
✓
✓
✓
11. Quotient regular sets
✓
✓
✓
X
X
✓
with
✓
The Classes P &NP P consists of all those languages or problems accepted by some deterministic Turing Machine that runs in some polynomial amount of time, as a function of its input length NP is the class of languages or problems that are accepted by non deterministic TM's with a polynominal bound on the time taken along any sequence of nondeterministic choices. The P » NP question : it is un known whether or not P and NP are really the same classes of languages, although we suspect strongly that there are languages in NP that are not in P.
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Polynominal-Time Reductions: If we can transform instances of one problem in deterministic polynominal time into instances of a second problem that has the same answer -yes or no - then we say the first problem is polynomial time reducible to the second. NP Complete problems; A language is NP-Complete if it is in NP, and there is a Polynominaltime reduction from each language in NP to the language in question. We believe strongly that none of the NP-complete problems are in P, and the fact that no one has ever found a polynominal time algorithm for .any of the thousands of known NP-complete problems is mutually re-enforcing evidence that none are in P. If P| is NP~complete, and there is a. poly nominal-time reduction of P1 to P2then P2 is NPcomplete. If some NP-complete problem is in P then P = NP. NP~ Hardproblem: If there is a language L such that every language L1 in NP can be polynominally reducible to L and we cannot prove that L is in NP then L is said to be NP-hard problem. (Note;If we can prove that L is in NP and every NP problem can be poly nominally reducible to L then L is said to be NP-complete problem) Some of the NP - Complete problems: 1. (cook's Theorem) Boolean satisfiability problem simply SA T is NP-complete. 2. CSAT,3SAT Problems are NP-Complete. 3. Traveling sales man problem (TSP) is NP-complete. 4. Hamilton circuit and directed Hamilton circuit problems are NP-complete. 5. Vertex cover problem: which asks us to find the smallest set of nodes that cover all the edges, in the sense that at least one end of every edge is in the selected set., is NP-complete. 6. Independent set problem :Given a graph, find a maximal independent set. This problem is NP-complete. 7. Chromatic Number Problem is NP-complete. 8. The partition problem: Given a list of integers i1 , i2, …..ik, does there exist a subset whose sum is exactly ½ (i1 , i2, …..ik). Note that this problem appears to be in P until we remember that the length of an instance is not i1 , i2, …..ik, but sum of the length of the i1’s written in binary or some other fixed base. 9. A K-Clique in a graph G is a set of k nodes of G such that there is an edge between every two nodes in the clique. CLIQUE isNP-Complete. 10. The coloring problem: Given a graph G and an integer k, is G "K- colorable", that is can we assign one of k-colors to each node of G in such a way that no edge has both of its ends colored with the same color. The coloring problem is NP-Complete. 11. The subgraph - isomorphism problem :given graphs G1 and G2does G1 contain a copy of G2as a subgraph ? That is, we can find a subset of the nodes of G1 that, together with the edges among them in G1, forms an exact copy of G2when we choose the correspondence between nodes of G2and nodes of the subgraph of G1 properly? The subgraph - isomorphism problem is NP-complete. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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12. The edge cove problem : Given a graph G and an integer k, does G have an "edge cover" of k edges, that is, a set of k edges such that node of G is an end of at least one edge is the edge cover. The edge cover problem is NP-complete. 13. The linear integer programming problem is NP-complete. 14. The dominating set problem .-.Given a graph G and an integer k, does there exist a subset S of k nodes of G such that each node is either in S or adjacent a node of S? This problem is NP complete. 15. The half-clique problem :Given a graph G with an even number of vertices, does there exist a clique of G consisting of exactly half the nodes of G? The half-clique problem is NP-complete. 16. The unit-execution time scheduling problem is NP - complete. 17. Exact cover problem: Given a set S and a set of subsets S1,S2, ....Sn of S, is there a set of subsets T ⊆ {S1, S2,...Sn} such that each element x of S is inexactly one member of T? Exact cover problem is NP-Complete. 18. The knapsack problem is NP-Complete. 19. Given graphG and an integer k, does G have a spanning tree with at most k leaf vertices. 20. Given graph G and an integer d, does G have a spanning tree with no node of degree greater than d ?. (The degree of a node n in the spanning tree is the number of edges of the tree that have n as an end).This problem is NP-Complete. 21. Do two FA's with the same input alphabet recognize different languages isNP-Complete. 22. Do two R.E E1on E2over the operators (+,.,*) represent "different languages is NP- Complete. 23. Do two regular grammars G1and G2generate different languages is NP-Complete. 24. Does a given CFG generates a given string x is NP-Complete. 25. Satisfiability, CNF-satisfiability problems are NP- complete. Some of the NP-Hard Problems: 1. Halting problem is to determine for an arbitrary deterministic algorithm A and an input I whether algorithm A with input I ever terminates. It is well known that this problem is undecidable. Hence, there exist no algorithm (of any complexity) to solve this problem. So, it clearly can't be in NP. Two problem L1 and L2 are said to be polynomially equivalent if and only if L1 is polynomilally reducible to L2 and viceversa. Only a decision problem can be NP - complete. However, an optimization problem may be NP-hard. Further more if L1 is a decision problem and L2 an optimization, it is quite possible that L1 and L2 (Li is polynomially reducible to L2). Knapsack decision → Optimization Clique decision → Optimization Yet optimization problems can't be NP-complete where as decision problems can. There also exist NP - Hard decision problems that are not NP-complete. → To show that a problem L2 is NP-hard, it is adequate to show L1 and L2, where L1 is some problem already known to be NP-hard. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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Intractable Problems: *The problems solvable in polynomial time on a deterministic TM are tractable. * The problems which require more than polynomial time on a deterministic TM are intractable. The Class of languages Co-NP P is closed under complementation but its is not known whether NP is closed under complementation .A suspected relationship between Co-NP and other classes of languages is shown below NP-Complete Problems
NP P Co-NP
Complements of NPComplete Problems * If P = NP then P, NP and Co-NP all are same. *NP = Co-NP if and only if there is some NP-Complete problem whose complement is in NP.
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Part – 7: Computer Organization 7.1: Introduction to Computer Organization
Computer architecture deals with the structure and behavior of the computer system. It includes the information formats, the instruction set and the hardware units that implement the instructions alongwith the techniques for addressing memory. Computer organization deals with the way the various hardware components operate and the way they are connected together to form the computer system. It also deals with the units of the computer that receive information from external sources and send computed results to external destinations. Computer design is concerned with the hardware design of the computer. This aspect of computer hardware is sometimes referred to as computer implementation. Basic blocks of a Computer System Input Unit: It is a medium of communication between the user and the computer. With the help of input unit, it is possible to give programs and data to the computer. Examples: Keyboard, floppy disk drive, hard disk drive, mouse, Magnetic Ink Character Recognition (MICR), Optical Character Recognition (OCR), paper tape reader, Magnetic tape reader, Scanner etc. Output Unit: It is a medium of communication between the computer and the user. With the help of output unit only it is possible to take results from the computer. Example: Printers, Video Display Unit (VDU), Floppy disk drive, Hard disk drive, Magnetic tape drive, punched cards, paper tape, plotter, digitizer etc. Memory: The memory unit is responsible for storing the user programs and data as well as system programs. The digital computer memory unit consists of two types of memories: Read Only Memory (ROM) and Read Write Memory (R/WM) or Random Access Memory (RAM). ALU: All arithmetic and logical operations are performed within this unit.
Control unit: It is used to generate necessary timing and control signals to activate different blocks in the computer to perform the given task. Central Processing Unite (CPU): The ALU and Control Unit together are called CPU. It is the heart of any digital computer. Byte Ordering or Endianness When computers try to read or store multiple bytes. Where does the biggest byte appear? THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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Big endian machine: Stores data big-end (MSB) first. When looking at multiple bytes, the first byte (lowest address) is the biggest.
Little endian machine: Stores data little-end (LSB) first. When looking at multiple bytes, the first byte is smallest.
Memory Unit ROM:ROM is used to store permanent programs or system programs. It does not have write capability. Types: PROM, EPROM, EEPROM RAM: It is also called user memory because the user programs or application programs are stored in this memory. The CPU is able to write or read information into or from this type of memory. Types: static, dynamic, scratch pad etc.
ALU (Arithmetic Logic Unit) The data processing part of CPU is responsible for executing arithmetic and logical instructions on various operand types including fixed point and floating point numbers. 1. Combinational ALU’s: The simple ALU’s combine the functions of 2’s complement adder-subtracter with those of a circuit that generates word based logic functions of the form f(x, y). 2. Sequential ALU’s: Both multiplication and division can be implemented by combinational logic. It is generally impractical to merge these operations with addition and subtraction into a single, combinational ALU. The combinational multipliers and dividers are costly in terms of hardware. They are also much slower than addition and subtraction. Circuits, a consequence of their many logic levels. The bus lines carry data, address and control signals.Since, this bus can be used only for single transfer at a time multiplebuses are introduced so as to achieve more concurrency in operations by allowing two or more transfers to be carried out at the same time. Hereby, increasing performance but at an increased cost. The internal organization of a digital system is defined by the sequence of primitiveoperations; it performs on the data stored in its registers. In a special purpose digital system, the sequence of micro-operation is fixed by the hardware and the system performs the same specific task over and over again. The data for the digital computer can be represented most frequently in two different ways a) Fixed point representation, and b) Floating point representation While storing the signed binary numbers in the internal registers of a digital computer, most significant bit position is always reserved for sign bit and the remaining bits are used for the magnitude representation.
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When the binary number is positive, the sign bit is represented by ‘0’. When the binary number is negative, the sign bit is represented by ‘1’. The representation of the decimal point (or binary point) in a register is complicated by the fact that it is characterized by a position between two flip- flops in the register. There are two ways of specifying the position of the decimal point in a register. 1. Fixed Point
2. Floating Point
The fixed point method assumes that the decimal point (or binary point) is always fixed in one position. The two positions most widely used are (1) a decimal point in the extreme left of the register to make the stored number a fraction, and (2) a decimal point in the extreme right of the register to make the stored number an integer. Negative number can be represented in one of three possible ways Signed- magnitude representation Signed -1’s complement representation Signed -2’s complement representation The 2’s complement of a given binary number can be formed by leaving all least significant zeros and the first non-zero digit unchanged, and then replacing 1’s by 0’s and 0’s by 1’s in all other higher significant digits. Subtraction using 2’s complement represent the negative number in signed 2’s complement form. Add the two numbers, including their sign bit and discard any carry out of the most significant bit. Since negative number are represented in 2’s complement form, negative results also obtained in signed 2’s complement form. 2’s complement form is usually chosen over 1’s complement to avoid the occurrence of a negative zero. The 1’s complement of 1’s complement of a given number is same number. The general form of floating point number is Smr .Where S= sign bit, M= Mantissa, r = base, e = exponent. The Mantissa can be a fixed point fraction or fixed point integer Normalization: Getting non-zero digit in the most significant bit or digit position of the mantissa is called Normalization. It is possible to store more number of significant digits as a result accuracy can be improved, if the floating point number is normalized. A zero can not be normalized because it does not contain a non- zero digit. The hexadecimal code is widely used in digital systems because it is very convenient to enter binary data in a digital system using hexcode. There are mainly two types of numbering systems: a) Non positional number systems
b) Positional number systems
Roman numeral system is an example of a Non positional number system. The most widely used number system is Positional number system: Positional number system has a ‘radix’ or ‘base’. A number with radix ‘r’ is represented as an an-1 an-2……………………………a0. a a ………………….a and can be interpreted as anr +a r +a r + an-3 r +……………..+ a0r +a 0r a r +……..+a r For example a number system has a radix 10. A number in this system is represented as a 10 +an-1 10 +an-2 10 + …………..a010 + a 10 + a 10 + ….+a 10 THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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This number system is known as Decimal number system. A Decimal number system of counting having ten different digits or symbols namely 0…………..9. This number system said to have a base of ten as it has ten different digits. The commonly used number systems with their symbols and bases. Number system Binary Octal Decimal Hexadecimal
Radix 2
Essential Digits 0, 1
8
0, 1, 2, 3, 4, 5, 6, 7
10
0, 1, 2, 3, 4, 5, 6, 7, 8, 9
16
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F
Binary Number System: All digital computers and systems are based on binary number system.Binary means two. Thebinary number system uses only two digits, i.e. 0 and 1. Hence the radix is 2. Binary number are strings of 0’s and 1’s. The electronic devices are most reliable when designed for two-state (binary) operation. All input and output voltages are either low or high. Where low voltage represents binary 0, and high voltage represents binary 1. Binary to Decimal Conversion: We can summarise the binary –to – decimal conversion by the following procedure: Write the binary number. The binary number write2 , 2 ,2 2 2 ……………..working from right to left. Add the decimal weights to obtain the decimal equivalent. Decimal to Binary conversion: To convert decimal numbers to binary number is the ‘double dabble’ method. In this method, divide the decimal number by 2 Write down the remainder after each division. The remainders, take in reverse order (down to up) to form the binary number. Octal Numbers: The number system with base (or radix) eight is known as ‘Octal number system’. The eight digits 0, 1,2,3,4,5,6 and 7 are used to represent numbers.
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Octal – to – Decimal Conversion: Octal to decimal is similar to binary to decimal conversion. In the Octal number system, each digit position corresponds to a power of 8. To convert from octal to decimal, multiply each octal digit by its weight and add the resulting products Decimal –to – Octal Conversion: Decimal to octal conversion is similar to decimal to binary conversion “Octal dabble” is the method used with octal numbers, while converting the decimalnumbers into octal numbers Instead of dividing by 2, divide by 8 writing down theremainders from down to up, after each division.
Data Representation In digital computer system, the information is represented by means of binary sequences, which are organized in words. A word is a unit of information of a fixed length.The binary information in digital computers is stored in memory or in processor registers. This binary information may be in the form of either data or control information. Types of Information:
Information o Instructions o Data Numerical Non – numerical Fixed – point Binary Decimal Floating point Binary Decimal
Fixed – Point Representation: The fixed point method assumes that the decimal or binary point is always fixed in one position. Thereare two ways of specifying the position of the decimal point or binary point in a register, i.e. by a ‘fixed’ position or by employing a ‘floating point’ representation. The two positions most widely used are i) A decimal point in the extreme left of the register to make the stored number as a fraction. ii) A decimal point in the extreme right of the register to make the stored number as an integer.
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Binary Fixed –Point Representation: A fixed point binary number is positive the sign is represented by’0’ and the magnitude by a positive binary number. When the number is negative the sign is represented by ‘1’. Decimal Fixed –Point Representation: The representation of the decimal number in registers is a function of the binary code usedto represent a decimal digit. A 4 bit decimal code required four flip- flops for each decimaldigit. requires 16 flip flops. This is the wastage of storage space since the number of bits needed to store a decimal number in a binary code is greater than the number of bits needed for its equivalent binary representation.
Floating –Point Representation: The floating point representation of a number consists of three parts. These are Mantissa(M), Exponent (E) and the Base (B) . These components together represent the number, as MX . The mantissa has a 0 in the left most position to denote a plus sign. The mantissa is considered to be a fixed point fraction. The exponent contains the decimal number +04 and the base is decimal number 10. MIPS(Million of Instruction Per Second) : MIPS is calculated by dividing the number of instruction executed in a running program by the time required to run the program and typically expressed in Million of Instruction Per Second(MIPS). CPI (Clock Per Instruction): The CPI of a given program on a given system is calculated by dividing the number of clock cycles required to execute the program by the number of instruction in running the program. IPC (Instruction Per Clock): IPC is calculated by dividing the number of instruction executed in running a program by the number of clock cycles required to execute the program, and is the reciprocal of CPI. IPC do not contain any information about a system’s clock rate and therefore less useful to measure the performance of a actual system. Speedup: Speedup is simply the ratio of the execution times before and after a change is made, so: Speedup = Amdahl’s Law: Amdahl’s law states that the performance improvement to be gained from using some faster mode of execution is limited by the function of the time the faster mode can be used. Overall speed up =
(
)
f: fraction of program that is enhanced s: speed up of the enhanced portion.
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7.2: Memory Hierarchy The objective of memory hierarchy is to provide the matching of the data transfer rate of faster processor to that of lowest level memory at a reasonable cost. Memory Unit: It is an essential unit in any digital computer since it is needed for storing the programs and data that are executed by the CPU. Main Memory: The memory unit that communicates directly with the CPU is called the mainmemory. Example; ROM AND RAM. Main memory is also called primary memory The principal technology used for the main memory is based on semiconductor integrated circuits. The static RAM consists essentially of internal flip-flops that store the binary information. The stored information remains valid as long as power is applied to the unit. The dynamic RAM stores the binary information in the form of electric charges that are applied to capacitors. The stored charge on the capacitors tends to discharge with time and the capacitors must be periodically recharged by refreshing the dynamic memory. Refreshing is done by cycling through the words every few milliseconds to restore the decaying charge. The dynamic RAM offers reduced power consumption and larger storage capacity in a single memory chip. The static RAM is easier to use, has shorter read and write cycles. Memory Hierarchy: Total memory capacity of a computer can be visualized as being a hierarchy of components. In memory hierarchy from top to down. 0. 1. 2. 3.
Size increases Access time increases Cost/bit decreases Decrease in frequency of access
Ci>Ci +1 (Cost per Bit) Si < Si + 1 (Size) Ti < Ti+ 1 (Access Time) The memory hierarchy system consists of all storage devices employed by a computer system from the slow but high –capacity auxiliary memory devices, to a relatively faster main memory, to an even smaller and very fast buffer memory accessible to the high speed processing logic. At the bottom of the hierarchy, the relatively slow magnetic tapes used to store removal files. The main memory occupies a central position in the memory hierarchy and can communicate directly with the CPU and with auxiliary devices through an I/O processor. The high speed small memory called cache memory occupies top position in the memory hierarchy. Cache Memory: A special very-high-speed memory called a cache is sometimes used to increase the speed of processing by making current programs data available to the CPU at a rapid rate. The cache memory is employed in computer systems to compensate for the speed difference between main memory access time and processor logic.
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Capacity: The capacity of a cache is simply the amount of data that can be stored in the cache, so a cache with a capacity of 32KB can store 32 Kilobytes of data. What is Cache? High speed memory module connected to the processor for it’s private use. Contains copies of recently referenced material. Copies between cache and memory in lines or blocks. By using cache memory the speed of operation will be increased and execution time will be reduced. Cache memory is also called high speed buffer memory
Processor
Cache
Main Memory
Fig.7.2.2 Example of Cache Memory
Line length: The line length of a cache is the cache’s block size. Associativity: The associativity of a cache determines how many locations within the cache may pertain to a given memory address. The speed of the main memory is very low in comparison with the speed of modern processors. An efficient solution is to use a fast cache memory which essentially makes the main memory appears to the processor to be faster than it really is. The effect of the cache mechanism is based on a property of computer programs called locality of reference. It manifests itself in two ways. i) temporal and ii) spatial. Temporal: Definition: Recently accessed items are likely to be accessed in future. The temporal aspect of the locality of reference suggests that whenever an information item (instruction or data) is first needed, this item should be brought into the cache, where it will hopefully remain until it is needed again. Spatial: Definition: Items whose addresses are near one another are tend to be referenced close together in time. The spatial aspect suggests that instead of fetching just one item from the main memory to the cache, it is useful to fetch several items that reside at adjacent addresses as well. We will use the term block to refer to a set of contiguous address locations of some size. Another term that is often used to refer to a cache block is cache line. The correspondence between the main memory blocks and those in the cache is specified by a mapping function. When the cache is full and a memory word (instruction or data) that is not in the cache is referenced, the cache control hardware must decide which block should be removed to create space for the new block that contains the referenced word. The collection of rules for making this decision constitutes the replacement algorithm. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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In a Read operation, the main memory is not involved. For a Write operation, the system can proceed in two ways. In the first technique, called the write-through protocol. The cache location and the main memory location are updated simultaneously. The second technique is to update only the cache location and to mark it as updated with an associated flag bit, often called the dirty or modified bit. The main memory location of the word is updated later, when the block containing this marked word is to be removed from the cache to make room for a new block. This technique is known as the write-back, or copy-back, protocol. When the addressed word in a Read operation is not in the cache, a read miss occurs. The block of words that contains the requested word is copied from the main memory into the cache. After the entire block is loaded into the cache, the particular word requested is forwarded to the processor. Alternatively, this word may be sent to the processor as soon as it is read from the main memory. The latter approach, which is called load-through or early restart reduces the processor’s waiting period. The performance of virtual memory or cache memory is measured with hit ratio. Hit ratio is defined as the number of hits divided by the total number of CPU references to the memory. (hits plus misses) Tavg = HC + (1 – H) M Where H = Hit ratio of cache memory C = time to access information in cache memory M = miss penalty + Main Memory access time + Cache Memory access time The average memory access time of a computer system can be improved considerably by use of a cache. Cache Coherence Problem:
Will have multiple copies of the “same” data in different caches Data in the caches is modified locally. Cache become inconsistent between caches, and between cache and main memory from which the cached data was copied
The transformation of data from main memory to cache memory is referred to as a mapping process. Multilevel Cache Hierarchy One of the fundamental issues is tradeoff between cache latency and hit rate. Larger caches have better hit rates but longer latency. To address this tradeoff, many computers use multiple levels of cache, with small fast caches backed up by larger slower caches. Multi-level caches generally operate by checking the smallest Level 1 (L1) cache first; if it hits, the processor proceeds at high speed. If the smaller cache misses, the next larger cache (L2) is checked, and so on, before external memory is checked. Multi-level caches introduce new design decisions. For instance, in some processors, all data in the L1 cache must also be somewhere in the L2 cache. These caches are called strictly inclusive. Other processors have exclusive caches — data is guaranteed to be in at most one of the L1 and L2 caches, never in both Address Mapping: a) Associative Mapping: The tag bits of an address received from the processor are compared to the tag bits of each block of the cache to see if the desired block is present. This is called to associative-mapping technique. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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An associative cache employs a tag, that is, a block address, as the key. At the start of a memory access, the incoming tag is compared simultaneously to all the tags stored in the cache’s tag memory. If a match (cache hit) occurs a match indicating signal triggers the cache to service the requested memory access. A no match signal identifies a cache miss, and the memory access requested is forwarded to the main memory for service. Main memory Block0 Tag
Block 0 Block 0
Tag
Block 1
Block i Block 127
Tag
Tag
Block Block 4095
Fig.7.2.3
Associative Mapped cache
b) Direct Mapping: An alternative, and simpler, address mapping technique for cache is known as Direct Mapping. Main memory Block 0 Block 1 Cache tag tag
tag
Block 127
Block 0
Block 128
Block 1
Block 129
Block 255 Block 256
Block 127
Tag
Block
Word
5
7
4
Main memory address Block 4095
Fig. 7.2.4 Direct Mapping Cache
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The direct- mapping technique is easy to implement, but it is not very flexible. The main drawback of direct mapping is that the cache’s hit ratio drops sharply if two or more frequently used blocks happen to map onto the same region in the cache. c) Set Associative Mapping: Here, combination of the direct and associative mapping techniques can be used. Blocks of the Cache are grouped into sets, and the mapping allows a block of the mainmemory to reside in any block of a specific set. At the same time, the hardware cost is reduced by decreasing by the size of the associative search. The tag field of the address must then be associatively compared to the tags of the two blocks of the set to check if the desired block is present. This two-way associative search is simple to implement. The number of blocks per set is a parameter that can be selected to suit the requirement of a particular computer. A cache that has k-blocks per set is referred to as a k-way setassociative cache. One more control bit, called the valid bit, must be provided for each block. This bit indicates whether the block contains valid data or not. Main memory
Block 0 Block 1 Set 0
Set 1
Cache Block 0 Block 1 Block 2
tag tag tag
Block 3
Set 63
Block 63 Block 64 Block 65 Block 127
tag tag
Block 126 Block 127
Block 128 Block 129
Block 4095 Tag 6
Set 6
Word 4 Fig. 7.2.5 Main memory address
The time required to find an item stored in memory can be reduced considerably if stored data can be identified for access by the content of the data itself rather than by an address. Match logic is used in the associative memory to identify data item.
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Page replacement policies The page replacement policy decides which frame entry information will be removed from the page table in case of conflict. 1. FIFO policy: This policy simply removes pages in the order they arrived in the main memory. Using this policy we simply remove a page based on the time of its arrival in the memory. 2. LRU policy: LRU expands to least recently used. This policy suggests that we remove a page whose last usage is farthest from current time. 3. NFU policy: NFU expands to not frequently used. This policy suggests using the criterion of the count of usage of page over the interval T. Let us briefly discuss the merits of choices that one is offered. FIFO is a very simple policy and it is relatively easy to implement. All it needs is the time of arrival. However, in following such a policy we may end up replacing a page frame that is referred often during the lifetime of a process LRU and NFU policies are certainly better in that regard but as is obvious we need to keep the information about the usage of the pages by the process. A more advanced technique of page replacement policy may look-up the likely future references to pages. Such a policy frame would require use of some form of predictive techniques. Virtual memory: The term virtual memory refers to the abstraction of separating LOGICAL memory--memory as seen by the process--from PHYSICAL memory--memory as seen by the processor. Because of this separation, the programmer needs to be aware of only the logical memory space while the operating system maintains two or more levels of physical memory space. The virtual memory abstraction is implemented by using secondary storage to augment the processor's main memory. Data is transferred from secondary to main storage as and when necessary and the data replaced is written back to the secondary storage according to a predetermined replacement algorithm. If the data swapped is designated a fixed size, this swapping is called paging, if variable sizes are permitted and the data is split along logical lines such as subroutines or matrices, it is called segmentation. TLB (Translation Look aside Buffer): The basic idea in the translation look-aside buffer access is quite simple. TLB is very effective in improving the performance of page frame access. This is a cache buffer to keep copies of some of the page frames in a cache buffer.. Note that a cache buffer is implemented in a technology which is faster than the main memory technology. So, a retrieval from the cache buffer is faster than that from the main memory. The hardware signal which looks up the page table is also used to look up (with address translation) to check if the cache buffer on a side has the desired page. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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This nature of look-up explains why this scheme is called Translation Look-aside Buffer (TLB) scheme. The basic TLB buffering scheme is shown in Figure. Suppose we wish to access page frame p. The following three possibilities may arise: 1. Cache presence: There is a copy of the page frame p. In this case it is procured from the lookaside buffer which is the cache. 2. Page table presence: The cache does not have a copy of the page frame p, but page table access results in a page hit. The page is accessed from the main memory. 3. Not in page table: This is a case when the copy of the page frame is neither in the cache buffer nor does it have an entry in the page table. Clearly, this is a case of page-fault. It is handled exactly as the page-fault is normally handled.
Offset CPU
offset
Main Memory
Page Table
TLB
The dotted lines shows the translation look aside buffer operation
Fig. 7.2.6 With 32-bit addresses and 1kB page, the VPN and PPN are 22 bits each. With 128 entries and 4 ways set associativity, there are 32 sets in the TLB; so 5 bits of the VPN are used to select a set. Therefore, we only have to store 17 bits of the VPN in order to determine if a hit has occurred, but we need all 22 bits of the PPN to determine the physical address of a virtual address. This gives a total of 41 bits per TLB entry. 41× 128 = 5,125 kB Memory mapping table is used to translate virtual address to physical address The virtual memory is divided into pages and the main memory is divided into blocks or frames. The size of the page must be equal to the size of the block or frames. Random access memory page table techniques or Associate memory page table techniques can be used to translate virtual address into main memory address. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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In Associative memory page table technique, the number of memory locations required to store memory mapping table is equal to the number of block available in the main memory. The wastage of memory is minimum in the case of associative memory page table technique. The most commonly used page replacement algorithms in virtual memory are (a) first-in-first-out and (b) the least recently used (LRU).
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7.3: Pipeline The speed of execution of programs is influenced by many factors. One way to improve performance is to use faster circuit technology to build the processor and the main memory. Another possibility, is to arrange the hardware in a manner so that more than one operation can be performed at the same time. Pipelining is particularly effective way of organizing concurrent activity in a computer system. Pipeline is commonly known as an assembly-line operation.
A pipeline can be visualized as a collection of processing segments through which binary information flows.
There are two area of computer design where the pipeline organization is applicable. 1. An Arithmetic Pipeline: It divides an arithmetic operation into sub-operations for execution in the pipeline segments. Pipeline arithmetic units are usually found in very fast speed computer. They are used to implement floating-point operations, multiplication of fixed-point number, and similar computations encountered in scientific problem. 2. An Instruction Pipeline: It operates on a stream of instructions by overlapping the fetch, decode and execute phases of the Instruction Cycle. Example of Instruction Pipeline
IF
ID
EX
OF
Totaltimewithpipe
T
WB
[ + (n 1)]T n
Where ‘n’ is the number of instructions ‘ ’ is the number of stages in pipe ‘T’ is the time for a stage which is maximum of all stages. [ +(
1)]
Cyclic Time of pipelined processors: Cycle Time Pipelined =
+ Pipeline Latch Latency
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Speed Up: The Speed Up of a pipeline processing over equivalent non pipeline processing is defined by the ratio of S=
(
)
Where ‘tn’ is the time taken to complete an instruction without pipeline. ‘tp’ is the time taken for a stage which is maximum of all stages.
Speed Up factor can also given by S= For ideal case, Pipeline stall cycles/instruction is zero. S = Pipeline depth= no. of stages Stall Cycles: Stall cycles are cycles which are used if one stage operation is delayed, then the previous stages for next instruction are waited for completion by using some empty cycles, these empty cycles are called as stall cycles.
a)
Sequential Execution: I1
F1
I3
I2
E1
F2
E2
F3
E3
…………
Interstate buffer B1 Instruction fetch unit
Execution unit
Fig. 7.3.1
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Hardware organization Time Clock cycle
1
2
F1
E1
3
4
Instruction I1
F2
I2
E2 F3
I3
E3
Fig. 7.3.2 Pipelined execution Consider how the idea of pipeline can be used in a computer. The processor executed a program by fetching and executing instructions. Execution of a program consists of a sequence of fetch and execute steps, as shown in figure7.3.1. Time Clock cycle
1
2
3
F1
D1
E1
F2
D2
4
5
6
7
Instruction I1 I2
F3
I3 I4
W1 E2
W2
D3
E3
W3
F4
D4
E4
W4
Fig. 7.3.3 Instruction execution divided into four steps Inter-stage buffers
D: Decode instruction and fetch operands
F : Fetch Instruction B1
E:Execute operation
B2
W : Write results B3
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The instruction fetched by the fetch unit is deposited in an intermediate storage buffer. This buffer is needed to enable the execution unit to execute the instruction while the fetch unit is fetching next instruction. The computer is controlled by a clock whose period is such that the fetch and execute steps of any instruction can each be completed in one clock cycle. An interchange storage buffer, B1, is needed to hold the information being passed from one stage to next. New information is loaded into this buffer at the end of each clock cycle. A pipelined processor may process each instruction in 4 steps: F
Fetch: Read the instruction from the memory.
D
Decode: decode the instruction and fetch the source operand.
E
Execute: perform the operation specified by the instruction.
W
Write: store the result in the destination location.
The sequence of events for this case is shown in Figure 7.3.3. Four instructions are in progress at any given time. This means that four distinct hardware units are needed, as shown in Figure 7.3.4. These units must be capable of performing their tasks simultaneously and without interfering with one another. Information is passed from one unit to the next through a storage buffer. As an instruction progresses through the pipeline all the information needed by the stages downstream must be passed along. For example, during clock cycle 4, the information in the buffers is as follows:
Buffer B1 holds instruction , which was fetched in cycle 3 and is being decoded by the instruction-decoding unit. Buffer B2 holds both the source operands for instruction and the specification of the operation to be performed. This is the information produced by the decoding hardware in cycle 3. The buffer also holds the information needed for the write step of instruction (step ). Even though it is not needed by stage E, this information must be passed on to stage W in the following clock cycle to enable that stage to perform the required Write operation. Buffer B3 holds the results produced by the execution unit and the destination information for instruction .
Pipeline Performance: In above figure, processor completes the processing of one instruction in each clock cycle, which means that the rate of instruction processing is four times as compared to sequential operation. For a variety of reasons, one of the pipeline stage may not be able to complete its processing task for a given instruction in the time allotted. Some operations, such as divide, may require more time to complete. Idle periods are called stalls. They are also referred to as bubbles in the pipeline. Once created as a result of a delay in one of the pipeline stages, a bubble moves down stream until it reaches the unit pipelined operations on the above situation, is said to have been stalled for two clock cycles. Any condition that cause the pipeline to stall is called a hazard.
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A data hazard is any condition in which either the source or the destination operands of an instruction are not available at the time expected in the pipeline. As a result some operations has to be delayed, and the pipeline stalls. The pipeline may also be stalled because of a delay in the availability of an instruction. For example, this may be a result of a miss in the cache, requiring the instruction to be fetched from the main memory. Such hazards are often called control hazards (or instruction hazards). A third type of hazards that may be encountered in pipelined operation is known as a structural hazard. This is the situation when two instructions require the use of a given hardware resource at the same time. The most common case in which this hazard may arise is in access to memory, or structure hazard occurs when the processor’s hardware is not capable of executing all instruction in the pipeline simultaneously. If instructions and data reside in the same cache unit, only one instruction can proceed and the other instruction is delayed. Many processors use separate instruction and data caches to avoid this delay. Data Hazards: A data hazard is a situation in which the pipeline is stalled hold because the data to be operated on are delayed for some reason. We must ensure that the results obtained when instructions are executed in a pipelined processor are identical to those obtained when the same instruction are executed sequentially. Pipeline Conflicts: In general, there are three major difficulties that cause the Instruction Pipeline to deviate from its normal operation. 1. Resource Conflicts caused by access to memory by two segments at the same time. Most of these conflicts can be resolved by using separate instruction on data memories. 2. Data Independency Conflicts arise when an instruction depends on the result of previous instruction, but this result is not yet available. 3. Branch Difficulties arise from branch and other instruction that change the value of PC. Data Hazards avoiding techniques: 1. Hardware Interlock or delayed load or bubble: The hardware interlock preserves the correct execution pattern of an instruction sequence. In general a hardware interlock detects the data hazard and stalls the pipeline until the hazard is cleared. 2. Operand Forwarding: The operand forwarding is a hardware technique to minimize the stalls in a pipelined execution of sequence of instructions. The key insight the forwarding is that the result of a previous instruction is directly fed to the next instruction through the pipelined registers without waiting to be written in WB stage to the register file. Branch Hazards avoiding techniques 1. Pipeline flushing : Simplest solution to the handle branches is to freeze or flush the pipeline, deleting any instruction after the branch until the target of the branch is known 2. Branch prediction: Continuing with the sequence of instructions as if branch were taken or not taken. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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3. Delayed Branching: A branch delay slot is introduced after the branch instruction and filled with the instruction will be executed irrespective of branch is taken or not. There are two types of Branch Prediction techniques. They are
(1) Static Branch Prediction
– done by compiler
(2) Dynamic Branch Prediction – done by processor H/w. Throughput of Pipeline Computer: Throughput = is cache miss penalty
is branch penalty.
Anti Dependence Write After Read (WAR) Hazard: Dependence resulting from reuse of a name. Data Dependence Read After Write (RAW) Hazard or True Dependence: True dependence resulting from use of a data value produced by an earlier statement. O/P Dependence Write After Write (WAW) Hazard: Dependence resulting by writing a value before a preceding write has completed.
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7.4: Instruction Types An instruction is a binary code, which specifies a basic operation (eg. add, subtract, and, or) for the computer. Types of Instructions Instruction varying accordingly in terms of word length, number and type of register between computers, are listed below: Load: Copy the contents of a specific location to the contents of a register. Add: Adds the contents of a specific location to the contents of a register. Subtract: Subtract the contents of a specific location to the contents of a register. Store: Copy the contents of a register into a specific memory location. Branch: Switch the CPU control to another instruction address other than the next in sequence. Register-register: Moves contents from one register to another. Shift: Moves bits in a memory location to the left or to the right for arithmetic purposes or for pattern manipulation. Input/output: Effects data transfer between a peripheral devices and memory. Logical Operator: (AND, OR, NOT, NAND, and so on)- combine the contents of a register and a specified memory location or register. The range of instructions available to any particular computer varies from system to system. Branch Instruction: Branch instruction cover a series of instruction that divert the program flow from one series of memory locations to a second non-contiguous series. This can be readily achieved by having an instruction that alters the contents of the Program Counter (PC) register. Branch instructions may be either conditional or non-conditional. In the former case some test is performed and if the out come of test is true then the contents of the PC are altered and hence the program flow jumps to the new point in memory. In non-conditional jump is always made. Branch instructions enable complex programs to be developed in which:
certain pieces of code are only executed if a condition is met (involved conditional branches) and loops are possible. Such that pieces of code can be executed over and over again.
Micro-operation: It is the elementary operation performed on the binary data stored in the internal registers of a digital computer during one clock period. The result of the operation THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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may replace the previous binary information of a register or may be transferred to another register. Macro-operation or operation: A set or micro operations is called a macro-operation. Instruction Code: It is a group of bits that tell the computer to perform a specific operation. It is divided into parts called fields, each having its own particular interpretation. The most basic part of an instruction code is its operation part. The basic instruction code format consists of two parts or two fields. Opcode
Address
OpCode: It is also called Operation Code field. It is a group of bits that define the operation performed by the instruction. The number of bits required for the operation part of an instruction code is a function of the total number of operations used. It must consist of at least n-bits for given 2n (or less) distinct operations. The address part of the instruction tells the control, where to find an operand in the memory. Operand: It is the data on which the given operation is to be performed. Stored Program Connect: It is the most important concept used in all the digital computers. In this concept the instructions are stored in one section of the memory and data is stored in another section of the memory. The CPU fetches one by one instructions from the memory and they will be decoded and executed. Computers that have a processor register usually assign to it name ‘’accumulator’’ and label it AC. In general, the length of Accumulator register or processor register must be equal to the length of each memory location. In general, the basic registers available in the digital computer are, Program Counter (PC), Memory Buffer Register (MBR),Memory Address Register (MAR), Operation Register (OPR), Accumulator register(AC), Mode bit flip- flop (1), Extension (E) flip-flop etc. PC: The Program Counter always holds the address of the next instruction to be fetched from the memory location. The length of the PC always depends on the addressing capacity of the CPU or the number of memory locations available in the memory. If the memory consist of 2n memory location then n bit PC is required. OPR: The operation register is used to hold the operation part of the instruction. The length of this register depends on the length of the operation part of the instruction. The length of MAR must be equal to the length of PC. The length of MBR is equal to the length of AC and length of each memory location. The use of mode flip-flop (l) is to hold mode bit. With the help of this mode bit the CPU can distinguish direct address instruction and indirect address instruction. The E flip-flop is an extension of the AC. It is used during shift operations. It receives the end –carry during addition, etc. The basic instruction code formats can be of three types: Immediate operand instructions, Direct address instructions, and Indirect address instructions. Immediate operand instructions: If the second field of an instruction code specifies an operand, the instruction is said to have an immediate operand. Op Code
Operand
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Direct address instructions: It is second field of an instruction code specifies the address of an operand, then it is called direct address instruction. Op Code
Address of operand
Indirect address instructions: If the second field of an instruction code designates an address of a memory word in which the address of the operand is found, is called the indirectaddressinstruction. Op Code
Address of address operand
Todistinguish direct and indirect address instructions a third field (one bit field) called Mode field is used in the instruction code format. I
Op Code Op Code
Address of operand
I = 0 Direct address instruction I = 1 Indirect address instruction
The most common fields found in the instruction code formats are: (a) mode bit field (b) Op Code field and (c) address field. The CPU requires zero memory references to complete the execution of the immediate types of instruction, once by instruction code is transferred from memory into CPU. The CPU requires one memory reference to complete the execution of the direct address type of instruction, once the instruction code is transferred from memory into the CPU. The CPU requires two memory references to complete the execution of the indirect address type of instruction, once the instruction code is transferred into the CPU. Depending on the way the CPU refers the memory, Input-Output and registers, the instructions of the basic computer can be of three types: Memory reference instructions, Registers reference instructions and Input-Output reference instructions. Memory reference instructions: The CPU is supposed to refer to the memory to get the operand for the completion of the execution of the instruction. Register reference instruction: The CPU is supposed to refer to the internal registers of the CPU to get the operand for the execution of the instruction. Input-Output reference instructions: The CPU is supposed to refer the input or output devices to complete the execution of the instruction. Most computers fall in three types of CPU organizations: Single AccumulatorOrganization, General Register Organization and Stack Organization. Based on the number of address fields available in the address part of the instruction, there are four different types of instructions. 1. Three address instructions 2. Two address instructions 3. One address instructions 4. Zero address instructions Three address instructions: The address field of the instruction code is divided into three sub fields. Example: ADD R 1, R2, R3 (R1) (R2) + (R3) The advantage of the three- address format is that it result in short program when evaluating arithmetic expression. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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Two address instructions: In this type of instruction the address field of the instruction code is divided into two sub fields. Example: ADD R1, R2 (R1) (R1) + (R2) The example of a computer which supports two address instructions is PDP -11 One Address Instructions: In this type of instructions, an implied accumulator (AC) register are used for all data manipulation. Example: LOAD A, AC M [A] ADD B, AC M [B] + AC The example of a computer which supports one – address instruction is PDP-8 Zero–address instructions: Some operational instructions do not require address field, such instructions are called zero address instructions. Example: computer which supports zero address instructions is Burroughs - 6700 Single accumulator organized computers uses one address instruction. General register organized computer uses two and three address instructions. Stack organized computer uses zero address instructions. Stack: It is a set of memory locations of the RAM which are used to store information in such a manner that the item stored last, is the first item retrieved. A very useful feature that is included in the CPU of many computers is a stack or Last In – First Out (LIFO) list. Stack Pointer (SP): It is a register, which always holds the address of the top of the stack. The length of the stack pointer register is equal to the length of PC register. PUSH and POP instructions are used to communicate with stack memory. FULL and EMPTY flip- flops are used to indicate status of the stack memory. The arithmetic expressions can be written in one of three ways 1. Infix notation 2.Prefix notation and 3.Postfix notation If the operator is placed between the operands then it is called infix notation. Ex: A+B The prefix notation is also called polish notation. In this notation the operator is placed before the operands. Ex: +AB The postfix notation is also called as reverse polish notation. In this notation the operator is placed after the operands. Ex: AB+ The reverse polish notation is suitable for stack organized computers. The expression A* B +C* D can be represented in reverse polish notation as AB*CD*+
RISC and CISC Architecture Complex Instruction Set Computer (CISC): A computer with large number of instructions is classified as a complex instruction set computer. Reduce Instruction Set Computer (RISC): A computer with fewer number of instructions is classified as a reduce instruction set computer. Example: • CISC –VAX, Intel X86, IBM 360/370, etc. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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• RISC – MIPS, DEC Alpha, SUN Sparc, IBM 801 RISC Vs CISC Characteristics of ISA (Instruction set architecture) CISC
RISC
Variable length instruction
Fixed length instruction
Variable format
Fixed field decoding
Memory Operands
Load/Store Architecture
Complex instruction
Simple Operations
Features CISC
RISC
Small chip size
Large chip size
Small code size
Large code size
less burden on software
Greater burden on software
Large number of instruction
Less number of instructions
Less register count
Large register count
Multiple clocks are required to complete a The instruction usually take a single clock instruction Difficult to take advantage of pipelining
More suitable for pipelining
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7.5: Addressing Modes The different ways in which the location of an operand is specified in an instruction are referred to as Addressing modes or the addressing mode specifies a rule for interpreting or modifying the address field of the instruction before the operand actually referenced.
General Adressing Modes: Name
Assembler Syntax
Addressing function
Implied
NIL
Implied
Immediate
# value
Operand =Value
Register
Ri
EA= Ri
Absolute ( Direct )
LOC
EA= LOC
Indirect
Ri
EA= [Ri]
Index
X (Ri)
EA = [Ri] +X
Base with index
(Ri, Rj)
EA= [Ri] + [Rj]
Base with index and offset
X (Ri,Rj)
EA= [Ri] + [Rj] + X
Relative
X (PC)
EA = [PC] + X
Auto increment
(Ri) +
EA = [Ri]; Increment Ri
Auto decrement
-(Ri)
Decrement Ri; EA = [Ri]
Fig7.5.1 Generic addressing modes Here, EA = Effective Address, Value = a signed number. Addressing Mode: The way in which the operand is specified in the address part of the instruction is called addressing mode. The addressing mode specifies a rule for interpreting or modifying the address field if the instruction before the operand is actually referenced. Computers use addressing mode techniques to give programming versatility to the user by providing such facilities such as a pointer, counters, indexing, program relocation and to reduce the number of bits in the address field of instruction. Different types of addressing modes used in computers are implied, immediate, Register, Register indirect, Auto increment or Auto decrement, direct address mode, Base register addressing mode, indirect address mode, relative addressing mode and indexed addressing mode.
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Effective Address: The effective address is defined to be the memory address obtained from the computation dictated by the given addressing mode. The effective address is the address of the operand in a computational type instruction. Implied mode: In this mode the operands are specified implicitly in the definition of the instruction. Zero – address instruction in a stack – organized computer are implied-mode instruction. EX: PUSH Immediate Mode: In this mode the operands are specified in the instruction itself. Register Mode: In this mode the operands are in register that reside within the CPU. Register Indirect Mode: In this mode the instruction specifies a register in the CPU whose contents give the address of operands in memory. Auto increment or Auto decrement: This is similar to the register indirect mode except that the register is incremented or decremented after (or before) its value is used to access memory. Direct Address Mode: In this mode the effective address is equal to the address part of the instruction. Indirect Address mode: In this mode the address field of the instruction gives the address where the effective address is stored in the memory. Relative Address Mode: In this mode the content of the program counter (PC) is added to the address part of the instruction in order to obtain the effective address. Relative addressing is often used with branch type instruction when the branch address is in the area surrounding the instruction word itself. Indexed Addressing Mode: In this mode the content of a index register is added to the address part of the instruction to obtain the effective address. The index register is a special CPU register that contains an index value. Base Register Addressing Mode: In this mode the content of a base register is added to the address part of the instruction to obtain the effective address. The addressing modes supported by one processor may differ from the addressing modes supported by the other processors. (A) Direct = 400 (B) Immediate = 301 (C) Relative = 302+400=702 (D) Register indirect = 200 (E) Indexed = 200+400 = 600 Computer cycle: Digital computers provide timing sequence of 8 to 16 repetitive timing signals. The time of one repetitive sequence is called a computer cycle. Types of computer cycles are Fetch cycle, Indirect cycle, Executive cycle and Interrupt cycle. Fetch cycle: When an instruction is read from memory the computer is said to be in an instruction fetch cycle. The first cycle of any instruction cycle must be always a fetch cycle. Indirect cycle: When the word read from the memory is an address of operand, the computer is said to be in an indirect cycle. Execute cycle: When the word read from memory is an operand, the computer is said to be in an execute cycle. The execute cycle can come after fetch cycle or indirect cycle. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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The indirect cycle must come after fetch cycle. The CPU will enter into interrupt cycle only after completion of execute cycle. The interrupts are generally used to transfer the program control from one place to another place. There are three types of interrupts that cause a break in the normal execution of the program. 1. External interrupts 2. Internal interrupts 3. Software interrupts External interrupts come from input-output devices, from a timing device, from a circuit monitoring the power supply, or from any other external source. Example: I/O device requesting transfer of data. Internal interrupts arise from illegal or erroneous use of an instruction or data. Internal interrupts are also called as traps. Example: attempt to divide by zero, stack overflow, invalid operation code etc. External and Internal interrupts are initiated from signals that occur in the hardware of the CPU. A software interrupt is initiated by executing an instruction. Internal interrupts are synchronous with the program while external interrupts are asynchronous. If the program returns. The internal interrupts will occur in the same place each time. The programmer to initiate an interrupt procedure at any desired point in the program can use software interrupts. The collection of all status bit conditions in the CPU is sometimes called a program status word or PSW. Program interrupt refers to the transfer of the program control from a currently running program to another service program as a result of an external or internal generated request.
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7.6: I/O Data Transfer Interfacing: Writing software instructions and designing hardware circuit to enable the central processing unit to communicate with peripheral devices is called interfacing, and the hardware circuit used is called interfacing circuit. Need for interface: 1. Most of the peripherals devices are electromechanical and electromagnetic devices and their manner of operation is different from the operation of the CPU and memory, which are electronic devices. 2. The data transfer rate of peripherals is much slower than the transfer rate in the central computer. 3. The operation of the peripheral must be synchronized with the operation of the CPU and memory unit. 4. Data format in peripherals differ from the data format in the central processor. The I/O processor is sometimes called a data channel controller. There are two ways to connect peripheral devices to CPU. (a) Memory mapped I/O and (b) Isolated I/O or I/O mapped I/O. Programmed I/O CPU has direct control over I/O Sending status Read/Write Commands Transferring data CPU waits for I/O module to complete operation Wastage CPU time
Details
CPU requests I/O operation. I/O module performs operation. I/O module sets status bits. CPU checks status bits periodically. I/O module does not interrupt CPU. CPU may wait or come back later.
Interrupt Driven I/O Overcome CPU waiting. No repeated CPU checking of device. I/O module interrupts when ready.
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I/O Mapping Memory mapped I/O. Devices and memory share an address space. I/O looks just like memory read/write. No special commands for I/O. Large selection of memory access commands available. Isolated I/O Separate address space. Need I/O or memory select lines. Special commands for I/O. Limited set. Basic Operation CPU issues read command. I/O module gets data from peripheral devices while CPU does other work. I/O module interrupts CPU. CPU requests data. I/O module transfers data. In memory mapped I/O techniques, the I/O devices are also treated as memory locations, under that assumption that they will be given addresses. Same control lines are used to activate memory locations as well as I/O devices. In I/O or Isolated I/O technique, the I/O devices are given separate addressed and separate control signals are used to activate memory locations and I/O devices. Data transfer between CPU and peripherals is handled in one of three possible modes: Data transfer under program controlled. Interrupt initiated data transfer. Direct memory Access (DMA) transfer. Program controlled operations are the result of I/O instruction written in the computer Each data item transfer is initiated by an instruction in the program. The disadvantage of program controlled data transfer is that, the processor stays in a program loop until the I/O unit indicates that it is ready. This is a time-consuming process since it keeps the processor busy needlessly. In interrupt initiated data transfer, when the peripheral is ready for data transfer, it generates an interrupt request to the processor. Then the processor stops momentarily the task it is doing, branches to a service routine to process the data transfer and then returns to the task it was performing. In Direct Memory Access (DMA) the interface transfers data into and out of memory unit through the memory bus generally to transfer bulk amount of data from memory to peripheral or from peripheral to CPU, DMA techniques is used. There are basically two formats of data transfer: parallel and serial. In parallel mode data bits (usually a byte) are transferred parallely over the communication lines referred to as buses. Thus all the bits of a byte are transferred simultaneously within the time frame allotted for the transmission. In serial data transfer, each data bit is sent sequentially over a single data line. In order to implement serial data transfer, the sender and receiver must divide the timeframe allotted for the transmission of a byte into subintervals during which each bit is sent and received. In serial transmission the information is transferred in the form of frames. The frame consists of three parts. Start bit, character code and stop bits. Start bit is always logic ‘0’ and stop bits are always at logic ‘1’ level. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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The data transfer in both the parallel and serial mode of operation can be either synchronous. In synchronous mode both source unit and destination unit work in synchronous mode with same control signal. In asynchronous mode the source unit and destination units have their own independent control signals. Asynchronous parallel data transfer can be of three types. (a) Strobe control (b) Two wire hand shaking method and (c) Three wire handshaking method. Asynchronous parallel transfer o Strobe control Source initiated Destination initiated o Two wire handshaking Source initiate Destination initiate o Three wire handshaking Asynchronous data transfer between two independent unit requires the control signals to be transmitted between the communication units to indicate the time at which data is being transmitted. One way of achieving this is by means of a strobe pulse supplied by one of the unit to indicate to the other unit when the transfer has to occur. Exchange of control signals between source and destination units during the data transfer operation is called as handshaking. The disadvantage of two-wire handshaking method is, it is not possible to connect more than one destination unit to a single source unit. Transmitter is used to interface serial I/O device to a parallel bus structure. In DMA transfer, the CPU initializes the DMA by sending a memory address and the number of words to be transferred. During DMA transfer, the CPU is idle and has no control of the memory buses. A DMA controller takes over the buses to manage the transfer directly between the I/O device and memory.
DBUS
Bus request BR
ABUS
Address bus bus Data bus
CPU
Bus grant
BG
RD
Read
WR
Write
High- impedance (disable) When BG is enabled
Fig 7.6.1 CPU bus signal for DMA transfer DMA is preferred data transfer for high speed peripheral devices such as magnetic disks. There are mainly three different modes of DMA operation. 1. Continuous DMA or burst mode of DMA 2. Cycle stealing and 3. Interleaved DMA THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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In burst mode a sequence of arbitrary length of data is transferred in a single continuous burst during which the DMA controller is the master of the system bus. In cycle stealing technique, the transfer is done by first checking if the memory unit is not used by the CPU and then the DMA steals one memory cycle to access a word in memory. Interleaved (multiplexed) DMA: In this Technique the processor and DMA access of memory can be interleaved on alternate half cycle of the clock. The DMA access the memory during first half of the cycle while CPU accesses during second half. Interrupt: It is the exceptional event, which causes the CPU to temporarily suspend the current program being executed. The control is subsequently transferred to some other programreferredto as interrupt service routine, which specifies the actions to be taken if the exceptional event occurs. Priority interrupt: It is an interrupt system that establishes a priority over the various sources to determine which condition is to be serviced first when two or more requests arrive simultaneously. Software or hardware can establish the priority of simultaneous interrupts. A polling procedure is used to identify the highest priority source by the software. In polling technique, there is one common branch address for all interrupts. The common service program begins at the branch address and polls the interrupt source in sequence. The disadvantages of the software method is that if there are many interrupts, the time required to poll them can exceed the time available to service the I/O device. The hardware priority function can be established either by a serial or a parallel connection of the interrupt links. The daisy-chain method of priority selection consists of all devices that request an interrupt from the processor. The device with the highest priority is placed in the first position, followed by lower priority device, up till the device with the lowest priority which is placed last in the chain.
VAD 1
VAD 2
VAD 3
Device 1 O I
Device 2 I O
Device 3 I O
Interrupt request Interrupt Acknowledge
To Next Device
I T C U I T AC
Fig 7.6.2 Daisy-Chain Priority Interrupt
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The parallel priority interrupt method uses a register whose bits are set separately by the interrupt request from each device priority is established according to the position of the bits in the register. Interrupts 1 Introduction An interrupt is signal either sent by an external device or internally by the software, indicating the need for attention or change in execution. Interrupts arising from an external events, is called asynchronous Interrupts arising from an internal even are generated by the software and generally called synchronous Following are the examples are both type of interrupts Externalities: Interrupts come typically from I/O devices which have completed a task, have run out of some resources or have run into some problems, such as an attempt to write to a write-disabled disk. Page faults: Running under virtual memory implies that many parts of a program will reside on disk. If references to those resident pages cannot be answered in reasonable time, a fault interrupt is issued which calls for a context switch to a task that can make use of the CPU while the missing pages are brought in from disk. Address translation errors: Address translation errors occur if events such as trying to write to read-only-memory or doing any operation in a space, that is not open to the running program. Illegal instructions fault: This type of faults includes undefined opcodes and instructions reserved for higher level of privilege. Arithmetic errors: This class includes divide-by-zero, word and half-word overflow. Direct Memory Access (DMA) 1. Overview Direct memory Access (DMA) is a operational transfer mode which allows data transfer within memory or between memory and I O device without processor’s intervention. A special DMA controller manages that data transfer. A DMA controller can be implemented as separated controller from the processor or integrated controller in the processor. In the following integrated DMA controller is considered. The DMA mechanism provides two unique methods for performing DMA transfer: Demand-mode transfer (synchronized to external hardware): Typically used for transfers between an external device and memory. In this mode, external hardware signals are provided to synchronize DMA transfers with external requesting devices. Block-Mode transfer (non-synchronized): Typically used to move block of data within memory. To perform a DMA operation the DMA controller uses microcode the core’s multi-process resources, the bus controller and internal hardware dedicated to the DMA controller. Loads and stores are executed in DMA microcode to perform each DMA transfer. Multi-process resources THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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are used to enable DMA operations to be executed concurrently with user’s program. The bus controller, directed by the DMA microcode, handles data transaction in external memory. External bus access is shared equally between the user and the DMA process. The bus controller executes bus requests by each process in alternating fashion. The DMA controller hardware synchronizes transfers with external devices or memory, provides the programmers interfaces to the DMA controller itself, and manages the priority for servicing DMA requests. 2. Data transfers Different DMA transfer modes are explained in the following paragraph. Multi-cycle Transfer Multi-cycle Transfer comprises of two or more bus requests: loads from source address are followed by stores to a destination address. To execute the transfer, DMA microcode issues the proper combination of bus requests. The processor effectively buffers the data for each transfer. When the DMA is configured for destination synchronization, the DMA controller buffers source data, waiting for the request from the destination requestor. The initial DMA request still requires the source data to be loaded before the request is acknowledged. 32bit memory Data source
Integrated DMA controller
32bit I/O device DREQ
Buffer load data
DACK
Data Destination
External system bus
Fig 7.6.3 Source data buffering for destination synchronized DMA’s Fly-By Single-Cycle Transfer Fly-by transfers are only executed with only a single load or store request. Source data is not buffered internally. Instead of this, the data is passed directly between sourced and destination via the external data bus. Fly-by transfers are common used for high-performance peripheral to memory transfers which can be described in the following example of a source-synchronized demand DMA mode. The source data is a peripheral device at a fixed address and the destination data is the system memory. Each data transfer is synchronized with source. The source requests a transfer by asserting the request pin *DRQ’s. As soon as the request is serviced, a store is issued to the destination memory while the requesting device is selected by the DMA acknowledged pin *DAC ’s. When selected the source data device must drive the data bus for the store instead of the processor. In this case, the processor must floats the data bus. If the destination is the requestor, i.e., destination synchronization, a load is issued to the source while the destination is selected with the acknowledge pin. The destination then reads the load data; the processor ignores the data from the load.
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32bit I/O device Data source
DREQ DACK
Integrated DMA controller
32bit memory Data Destination
Buffer load data
Source driven data
Computer Organization
One word step
External system bus
Processor floats bus during store operation
Fig 7.6.4 Source-synchronized fly-by DMA operation A Fly-by DMA in block mode is started by software and can be carried out in the same way like any block mode operation multi-cycle. Fly by DMA in block mode can be used to implement highperformance, memory-to-memory transfers where source and destination addresses are fixed at the block boundaries. In this case, the acknowledge pin must be used in conjunction with external hardware to unique address, the sources and destination for the transfer. With DMA, the processor is free to work on other tasks, except when initiating each DMA and responding to the interrupt at the end of each transfer. This takes 2500 cycles/transfer, or a total of 6,250,000 cycles spent handling DMAs each second. Since the processor operates at 200 MHz this means that 3.125 percent of each second or 3.125 percent of the processor’s time is spent handling DMAs, less than one-third of the overhead without DMA. 3. DMA Controller implementation Integrated DMA controller’s functions including data chaining data alignment and so on are implemented in microcode. Processor clock cycles are required to setup and execute a DMA operation. When considering whether to use the DMA controller, two questions generally arise: 1. When a DMA transfer is executing, how many internal processor clock cycles does the DMA operation consume? 2. When a DMA transfer is executing, how much of the total bus bandwidth is consumed by the DMA bus operation? A process switch from user process to DMA process occurs as a result of a DMA event. A DMA event is signaled when a DMA channel requires services or is in the process of setting up a channel. Signaling the DMA event is controlled by DMA logic. A DMA rarely uses the maximum available cycles for the DMA process. Actual cycle allocation between user process and DMA process depends on the type of DMA operation performed, DMA channel activity external bus loading and performance. 4. DMA Transfer Performances DMA transfer performance is characterized by two values: throughput and latency. Throughput measurement is needed as a measure of the DMA transfer bandwidth. Worst-case latency is required to determine if the DMA is fast enough in responding to transfer requests from DMA devices.
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Throughput describes how fast data is moved by a DMA operation. It is defined as the number of the controller clock cycles per DMA request. This value is denoted as The established measure of throughput, in units of byte/second, is derived by the following equation: Throughput (Bytes/Second) = (
f )
where:
: Number of controller clock cycles per DMA request Ng :Bytes per DMA request f : DMA Controller clock frequency In general, the DMA throughput for a particular system depends on the following factors: DMA transfer type. Memory system configuration and Bus activity generated by the user process. Latency is defined as the maximal time delay measured between the assertion of the request pin *DREQ and the assertion of the acknowledgement pin *DACK. The latency here is derived in number of the controller clock cycles, which is denoted as . The established measure of DMA latency, in units of seconds, is derived by the following equation: DMA latency (Second) =
f , where:
: Number of controller clock cycles, f : DMA Controller clock frequency Address bus
Data bus
Data bus buffer
Address bus buffer
Address register DMA Select
DS
Register Select
RS
Read
RD
Write
WR
Bus Request
BR
Word count register
Control Logic
Control register DMA request
Bus Grant
BG
Interrupt
Interrupt
DMA acknowledge to I/O Device
Fig 7.6.5 Block Diagram of DMA Controller
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The DMA latency in a system depends on the following factors: DMA transfer type and subsequently the worst-case throughput value calculated for that transfer; Number of channels enabled and the priority of the requesting channel; Status of the suspend DMA on interrupt bit in the DMA control register.
INPUT/OUTPUT: The devices that are connected to the periphery of the CPU are called peripheral devices. Example: input and output devices. Input devices: It is a medium of communication between user to the computer. Example: keyboard, Floppy disk drive, hard disk drive, Mouse, Magnetic tape drive, paper tape Deader, card reader, VDU etc., Output device: It is a medium of communication between computer to the user. Example: VDU printers, Floppy disk drive, punched cards, potters etc. On – line devices: Devices that are under the direct control of the processor are said to be connected on line. Off –line devices: When a device is offline then it is operated independently of the computer. All peripheral devices are electromechanical & electromagnetic devices. The I/O organization of a computer is a function of the size of the computer and the devices connected to it. Auxiliary Memory: The device that provide backup storage are called auxiliary or secondary memory. The secondary memory is not directly assessable to the CPU. Example: Hard disk, floppy disk, magnetic tape etc. The important characteristics of any device are its access mode, access time, transfer rate, capacity, and cost. Seek Time: It is the time required, to move the read/write head to the proper track. This depends on the initial position of the head relative to the track specified in the address. Rotational delay (latency time): This is the amount of time that elapses after the head is positioned over the correct track until the starting position of the addressed sector passes under the read/write head. On average, this is the time for half a rotation of the disk. Access Time: The sum of these two delays is called the disk access time.
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Disk Controller: Operation of a disk drive is controlled by disk controller, which also provides an interface between the disk drive and the bus that connects it to the rest of the computer System. The disk controller may be used to control more than one drive. The disk controller keeps track of such sector ad substitutes other sector instead. Main memory Address: The address of the first main memory location of the block of words involved in the transfer. Disk Address: The location of the sector containing the beginning of the desired block of words. Word Count: The number of words in the block to be transferred. Magnetic Hard Disks
Tracks
Sector
Read And Write Head
Fig 7.6.6 Magnetic Disk The disk system consists of three key parts. One part is the assembly of disk platters, which is usually referred to as the disk. The second part comprises the electromechanical mechanism that spins the disk and moves the read/write heads; it is called the disk drive. The third part is the electronic circuitry that controls the operation of the system which is called the disk controller. Each surface is divided into concentric tracks, and each track is divided into sectors. The set of corresponding tracks on all surfaces of a stack of disks forms a logical cylinder. The data on all tracks of a cylinder can be accessed without moving the read/write heads. The data are accessed by specifying the surface number, the track number, and the sector number. Floppy disks: Floppy disks are smaller, simpler, and cheaper disk units that consist of a flexible, removable, plastic diskette coated with magnetic material. One of the simplest schemes used in the first floppy disk for recording data is phase or Manchester encoding. Disks, encoded in this way are said to have single density. A more complicated variant of this scheme, called double density. The main feature of floppy disk is their low cost and shipping convenience.
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RAID Disk Arrays: RAID stands for, Redundant Array of Inexpensive Disks. Using multiple disks also makes it to improve the reliability of the overall system. Six different configurations were proposed. They are known as RAID levels even though there is no hierarchy involved. RAID 0 is the basic configuration intended to enhance performance. A single large file is stored in a several separate disk units by breaking the file up into a number of smaller pieces and storing these pieces on different disks. This is called data striping. RAID 1 is intended to provide better reliability by storing identical copies of data on two disks rather than just one. The two disks are said to be the mirrors of each other. RAID 2, RAID 3 and RAID 4 levels achieve increased reliability through various parity checking schemes without requiring a full duplication of disks. All of the parity information is kept on one disk. RAID 5 also makes use of parity based error recovery scheme. However, the parity information is distributed among all disks, rather than being stored on one disk. Indeed, the term RAID has been redefined by the industry to refer to “independent” disks. ATA/EIDE Disks: EIDE (Enhanced Integrated Drive Electronics) or as ATA (Advanced Technology Attachment). Many disk manufactures have a range of disks that have EIDE/ATA interfaces. In fact Intel’ s entium chip sets include on controller that allows EIDE ATA disks to be connected to the motherboard one of the main drawback is that separate controller is needed for each drive if two drives are to be used concurrently to improve performance. RAID Disks: RAID disks offer excellent performance and provide a large and reliable storage. They are used either in high-performance computers. Optical Disks & CD Technology: The optical technology that is used for CD systems is based on a laser light source. A laser beam is directed onto the surface of the spinning disk. Physical indentation in the surface are arranged along the tracks of the disk. They reflect the focused beam toward a photo detector, which detects the stored binary patterns. The laser emits a coherent light beam that is sharply focused on the surface of the disk. Coherent light consists of synchronized waves that have the same wavelength. If a coherentlight beam iscombined with another beam of the same kind, and the two beams are in phase, then the result will be a brighter beam. But, if the waves of the two beams are 180 degrees out of phase, they will cancel each other. Thus, if a photo detector is used to detect the beams, it will detect a bright spot in the first case and a dark spot in the second case. The bottom layer is polycarbonate plastic, which function as a clear glass base. The surface of this plastic is programmed to store data by indenting it with pit. The unindented parts are called lands. The laser source and the photo detector are positioned below the polycarbonate plastic. The emitted beam travels through this plastic reflects off the aluminum layer, and travels back toward the photo detector.
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CD-ROM: Science information is stored in binary form in CD’s they are suitable for use as a storage medium in computer system. The biggest problem is to ensure the integrity of stored data. Because pits are very small, it is difficult to implement all of pits perfectly. Stored data are organized on CD-ROM tracks in the form of blocks that are called sectors. Error handling Possible errors on a disk subsystem are: Programming error: For example the driver requests the controller to seek to a nonexistent sector. Most disk controllers check the parameter given to them and complain if they are invalid. Transient checksum error: That are caused by dust on the head. Most of the time they are eliminated by just repeating the operation few times. If error persists, the block has to be remarked as a bad block and avoided. Permanent checksum error: In this case, the disk blocks are assumed to be physically damaged. These errors are unrecoverable errors and these blocks are remarked as bad block and avoided. Seek error: For example, the arm was sent to cylinder 6, but it went to cylinder 7. Normally, it keeps track of the arm position internally. To perform a seek, it issues a series of pulses to the arm motor, one pulse per cylinder to move the arm to the destination cylinder. Then, the controller reads the actual cylinder number to check whether the seek operation is correct or not. If the seek error occurs, the controller moves the arm as far as it will go out, resets the internal current cylinder to 0 and tries it again. If it does not help, the drive must be repaired. Disk controller error: The controller refuses to accept command from the connected computer. It has to be replaced. Disk Structure: Disk drives are addressed as large 1-dimensional arrays of logical blocks, where the logical block is the smallest unit of transfer.
The 1-dimensional array of logical blocks is mapped into the sectors of the disk sequentially. Sector 0 is the first sector of the first track on the outermost cylinder. Mapping proceeds in order through that track, then the rest of the tracks in that cylinder, and then through the rest of the cylinders from outermost to innermost.
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Part – 8: Digital Logic 8.1: Number Systems & Code Conversions Characteristics of any number system are: 1. Base or radix is equal to the number of possible symbols in the system, 2. The largest value of digit is one (1) less than the radix Decimal to Binary Conversion: (a) Integer number: Divide the given decimal integer number repeatedly by 2 and collect the remainders. This must continue until the integer quotient becomes zero. (b) Fractional Number: Multiply by 2 to give an integer and a fraction. The new fraction is multiplied by 2 to give a new integer and a new fraction. This process is continued until the fraction becomes 0 or until the numbers of digits have sufficient accuracy. Note: To convert a decimal fraction to a number expressed in base r, a similar procedure is used. Multiplication is by r instead of 2 and the coefficients found from the integers any range in value from 0 to (r-1). The conversion of decimal number with both integer and fraction parts separately and then combining the answers together.
Don’t care values or unused states in BCD code are 1010, 1011, 1100, 1101, 1110, 1111. Don’t care values or unused state in excess – 3 codes are 0000, 0001, 0010, 1101, 1110, 1111. The binary equivalent of a given decimal number is not equivalent to its BCD value. Eg. Binary equivalent of 2510 is equal to 110012 while BCD equivalent is 00100101. In signed binary numbers,MSB is always sign bit and the remaining bits are used for magnitude. A7 A6 A5 A4 A3 A2 A1 A0
Sign Bit
Magnitude
For positive and negative binary number, the sign is respectively ‘0’ and ‘1’. Negative numbers can be represented in one of three possible ways. 1. Signed – magnitude representation. 2. Signed – 1’s complement representation. 3. Signed – 2’s complement representation.
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Example: Signed – magnitude
+9 0 0001001
Digital Logic
-9 (a) 1 000 1001 signed – magnitude (b) 1 111 0110 signed – 1’s complement (c) 1 111 0111 signed – 2’s complement
Subtraction using 2’s complement: Represent the negative numbers in signed 2’s complement form, add the two numbers, including their sign bit and discard any carry out of the most significant bit. Since negative numbers are represented in 2’s complement form, negative results also obtained in signed 2’s complement form. The range of binary integer number of n-bits using signed 1’s complement form is given by +(2 – 1) to –(2 – 1),which includes both types of zero’s i.e., +0 and -0. The range of integer binary numbers of n-bits length by using signed 2’s complement representation is given by + (2 – 1) to – 2n-1 which includes only one type of zero i.e. + 0. In weighted codes, each position of the number has specific weight. The decimal value of a weighted code number is the algebraic sum of the weights of those positions in which 1‘s appears. Most frequently used weighted codes are 8421, 2421 code, 5211 code and 84 2’1’ code.
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8.2: Boolean Algebra & Karnaugh Maps 1. Boolean properties: a) Properties of AND function 1. X . 0 = 0
2. 0 . X = 0
3. X . 1 = X
4 .1.X = X
b) Properties of OR function 5. X + 0 = X
6. 0 + X = X
7. X + 1 = 1
8. 1 + X = 1
c) Combining a variable with itself or its complement 9. X .X’ = 0
10. X . X = X
11. X + X = X
12. X + X’ = 1
13. (X’)’ = X d) e) f) g)
Commutative laws: Distributive laws: Associative laws: Absorption laws:
h) Demorgan’s laws:
14. 16. 18. 20.
x. y = y. x x(y +z) = x.y + x.z x(y.z) = (x. y) z x + xy= x
15. 17. 19. 21.
x+y=y+x x + y. z = ( x+y) (x + z) x + ( y + z) = (x + y) +z x(x + y) = x
22. x + x’y = x+ y
23. x(x’ + y) = xy
24. (x + y)’ = x’ .y’
25. (x . y)’ = x’ + y’
Duality principle: It states that every algebraic expression deducible from theorems of Boolean algebra remains valid if the operators and identify elements are interchanged. To get dual of an algebraic function, we simply exchange AND with OR and exchange 1 with 0. The dual of the exclusive – OR is equal to its complement. To find the complement of a function is take the dual of the function and complement each literal. Maxterm is the compliment of its corresponding minterm and vice versa. Sum of all the minterms of a given Boolean function is equal to 1. Product of all the maxterms of a given Boolean function is equal to 0 Boolean Algebraic Theorems Theorem No. Theorem ̅) = ( + B). ( + B 1. ̅ 2. B + C = ( + C)(̅ + B) ( + B)(̅ + C) = C + ̅ B 3. 4. B + ̅ C + BC = B + ̅ C ̅ ( + B)( + C)(B + C) = ( + B)(̅ + C) 5. ̅̅̅̅̅̅̅̅ ̅ + C̅ + 6. . B. C. = ̅ + B ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅. C̅ 7. + B + C + = ̅. B
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Karnaugh Maps (K – maps): A map is a diagram made up of squares. Each square represents either a minterm or a maxterms. The number of squares in the karnaugh map is given by 2 where n = number of variable. Gray code sequence is used in K – map so that any two adjacent cells will differ by only one bit. No. of cells Number of No. of variables No. of literals present containing 1’s variables eliminated in the resulting term grouped 4 2 0 2 1 1 2 1 0 2 8 3 0 4 2 1 2 1 2 3 1 0 3 16 4 0 8 3 1 4 2 2 4 2 1 3 1 0 4
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8.3: Logic Gates OR, AND, NOT are basic gates NAND and NOR gates are called Universal gates because, by using only NAND gates or by using only NOR gates we can realize any gate or any circuit. EXOR, EXNOR are arithmetic gates. There are two types of logic systems: 1) Positive level logic system (PLLS) : Out of the given two voltage levels, the more positive value is assumed as logic ‘1’ and the other as logic ‘0’. 2) Negative level logic system (NLLS):out of the given two voltage levels, the more negative value is assumed as logic ‘1’ and the other as logic ‘0’. NOT gate:Truth Table A Y 0
1
1
0
+VCC
Symbol A Y=̅
AND gate: Truth Table A B Y 0 0 0 0 1 0 1 0 0 1 1 1
VCC A B
Y = AB
A B
OR gate: A 0 0 1 1
B 0 1 0 1
Y 0 1 1 1
Y=̅
A
Y
A Y = A+B
B
A Y B
NAND gate: A 0 0 1 1
B 0 1 0 1
Y 1 1 1 0
A B
Y = ̅̅̅̅ B
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NOR gate: A 0 0 1 1
B 0 1 0 1
Y 1 0 0 0
A Y = ̅̅̅̅̅̅̅ +B
B
The circuit, which is working as AND gate with positive level logic system, will work as OR gate with negative level logic system and vice-versa. The circuit which is behaving as NAND gate with positive level logic system will behave as NOR gate with negative level logic system and vice – versa. Exclusive OR inputs”. A B 0 0 0 1 1 0 1 1
gate (X– OR): “The output of an X – OR gate is high for odd number of high A
Y 0 1 1 0
Y = A⊕B= B’ + ’B
B
Exclusive NOR gate (X–NOR): The output is high for odd number of low inputs”. (OR) “The output is high for even number of high inputs”. A B Y A 0 0 1 Y = A⨀B= B + ’B’ 0 1 0 B 1 0 0 1 1 1 Realization of Basic gates using NAND and NOR gates: NOT gate A
NAND Y=̅
A A 1
NOR Y = ( . )’ A = Y = ( .1)’ A 0 = ’
( + )’ = ’ Y = ( + 0)’ =
AND gate A A B
A Y =AB
B
Y =AB
Y =AB
B
OR gate: A A B
A Y =A+B B
Y = A+B B
Y = A+ B
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Realization of NAND gate using NOR gates: A
A Y = ( B)’
Y = ( B)’ B Realization of NOR gate using NAND gates: A
A Y = ( + B)’
B
B
Y = ( + B)’
Realization of X – OR gate using NAND and NOR gates: A Y = B’+ ’B
B A
Y = B’ + ’B B A `
Y = B’ +
B
B The minimum number of NAND gates required to realize X – OR gate is four. The minimum number of NOR gates required to realize X – OR gate is five. Equivalence Properties: 1. (X ⊕Y)’ = X’Y’ + XY = X 2. X 0 = X’ 3. X 1 = X 4. X X = 1 5. X X’= 0 6. X Y = Y X 7. (X Y)’ = X ⊕ Y
Y
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Alternate Logic Gate Symbols: A bubbled NAND gate is equivalent to OR gate A `
A Y=( B)
B `
=A+B
Y = A+B
B
A bubbled NOR gate is equivalent to AND gate A Y=(
B
A `
+ B ) =AB
B `
Y= B
A bubbled AND gate is equivalent to NOR gate A ` B `
A Y=
B = ( + B)
Y = ( + B)
B
A bubbled OR gate is equivalent to NAND gate A B
Y=
+ B =( B)
A ` B `
Y = ( B)
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8.4: Combinational Digital Circuits Digital circuits can be classified into two types: o Combinational digital circuits and o Sequential digital circuits. Combinational Digital Circuits: In these circuits “the outputs at any instant of time depends on the inputs present at that instant only.” For the design of Combinational digital circuits, basic gates (AND, OR, NOT) or universal gates (NAND, NOR) are used. Examples for combinational digital circuits are adder, decoder etc. Sequential Digital Circuits: The outputs at any instant of time not only depend on the present inputs but also on the previous inputs or outputs. For the design of these circuits in addition to gates we need one more element called flip-flop. Examples for sequential digital circuits are Registers, Shift register, Counters etc. Half Adder: A combinational circuit that performs the addition of two bits is called a halfadder. Sum = X ⊕ Y = XY’ + X’ Y
Carry = XY
Half Subtractor: It is a Combinational circuit that subtracts two bits and produces their difference. Diff. = X ⊕ Y = XY’ + X’Y Borrow = X’ Y Half adder can be converted into half subtractor with an additional inverter. Full Adder: It performs sum of three bits (two significant bits and a previous carry) and generates sum and carry. Sum=X⊕ ⊕Z Carry = XY + YZ + ZX Full adder can be implemented by using two half adders and an OR gate. X Y
H.A.
H.A.
Sum
Z
Carry
Full subtractor: It subtracts one bit from the other by taking pervious borrow into account and generates difference and borrow. Diff.=X⊕ ⊕Z Borrow = X’Y + YZ + ZX’
Full subtractor can be implemented by using two half- subtractors and an OR gate. X Y Z
H.S.
H.S.
Diff.
Borr.
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Multiplexers (MOX)
It selects binary information from one of many input lines and directs it to a single output line The selection of a particular input line is controlled by a set of selection lines There are 2 input lines where ‘n’ is the select lines i/p then n = log 2 : 1 MUX I 2:1 MUX
I
Y=S̅I + SI
Y
S 4 : 1 MUX I I I I
4:1 MUX
S1
S1 0 0 1 1
Y
S0 0 1 0 1
Y I I I I
S0
Y=S̅ S̅ I + S̅ S I + S S̅ I + S S I Decoder: Decoder is a combinational circuit that converts binary information from ‘n’ input lines to a maximum of 2 unique output lines. Truth table of active high output type of decoder.
X
Y
D
D
D
D
0
0
1
0
0
0
0
1
0
1
0
0
1
0
0
0
1
0
1
1
0
0
0
1
X 2
4
Y
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Encoder Encoder is a combinational circuit which has many inputs and many outputs It is used to convert other codes to binary such as octal to binary, hexadecimal to binary etc. Clocked S-R Flip-flop: It is called set reset flip-flop. No change Reset set Forbidden
0
0
0
1
0
1
0
1
1
1
*
Pr S Clk R
Q
Cr = S +R
PRESET S
Q
Clk
Q’
R CLEAR
S and R inputs are called synchronous inputs. Preset (pr) and Clear (Cr) inputs are called direct inputs or asynchronous inputs. The output of the flip-flop changes only during the clock pulse. In between clock pulses the output of the flip flop does not change. During normal operation of the flip flop, preset and clear inputs must be always high. The disadvantage of S-R flip-flop is S=1, R=1 output cannotbe determined. This can be eliminated in J-K flip-flop. S-R flip flop can be converted to J-K flip-flop by using the two equation S=J ’ and R= K .
J Q’
Pr
S
Q
J
Clk
Clk Q’
R Q K
Q
Cr
=J
K
Q’
+K
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Truth table
0
0
0
1
0
1
0
1
1
1
Race around problem is present in the J-K flip flop, when both J=K=1. Toggling the output more than one time during the clock pulse is called Race around Problem. The race around problem in J-K flip-flop can be eliminated by using edge triggered flip-flop or master slave J-K flip flop or by the clock signal whose pulse width is less than or equal to the propagation delay of flip-flop. Master-slave flip-flop is a cascading of two J-K flip-flops Positive or direct clock pulses are applied to master and these are inverted and applied to the slave flip-flop. D-Flip-Flop: It is also called a Delay flip-flop. By connecting an inverter in between J and K input terminals. D flip-flop is obtained. Truth table J
D 0
0
1
1
D
Q Clk
K
Q’
T Flip-flop: J K flip-flop can be converted into T- Flip-flop by connecting J and K input terminals to a common point. If T=1, then Q n+1 = . This unit changes state of the output with each clock pulse and hence it acts as a toggle switch. Truth table T 0 1
T
J
Q Clk
K
’
Ring Counter: Shift register can be used as ring counter when Q0 output terminal is connected to serial input terminal. An n-bit ring counter can have “n” different output states. It can count n-clock pulses. Twisted Ring counter: It is also called Johnson’s Ring counter. It is formed when output terminal is connected to the serial input terminal of the shift register. An n-bit twisted ring counter can have maximum of 2n different output states. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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Digital Logic
Counters: The counter is driven by a clock signal and can be used to count the number of clock cycles counter is nothing but a frequency divider circuit. Two types of counters are there: (i) Synchronous (ii) Asynchronous Synchronous counters are also called parallel counters. In this type clock pulses are applied simultaneously to all the flip – flops Asynchronous counters are also called ripple or serial counter. In this type of counters the output of one flip – flop is connected to the clock input of next flip – flop and soon.
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Digital Logic
8.5: Semiconductor Memory The capacity of a memory IC is represented by 2 xm, where ‘2 ’ represents number of memory locations available and ‘m’ represents number of bits stored in each memory location. Example:- 2 8 = 1024 8 To increase the bit capacity or length of each memory location, the memory ICs are connected in parallel and the corresponding memory location of each IC must be selected simultaneously. Eg. 1024 × 8 memory capacity can be obtained by using 4 ICs of memory capacity 1024×2. Types of Memories:
Memories
Semiconductor Memories
Magnetic Memories
Drum
Read/Write Memory (RAM or user memory)
Disk
Bubble
Core
Read Only Memory (ROM)
PROM Static RAM
Tape
EPROM
EEPROM
Dynamic RAM
Volatile Memory: The stores information is dependent on power supply i.e., the stored information will remain as long as power is applied. Eg. RAM Non- Volatile Memory: The stored information is independent of power supply i.e., the stored information will present even if the power fails. Eg: ROM, PROM, EPROM, EEPROM etc. Static RAM (SRAM): The binary information is stored in terms of voltage. SRAMs stores ones and zeros using conventional Flip-flops. Dynamic RAM (DRAM): The binary information is stored in terms of charge on the capacitor. The memory cells of DRAMs are basically charge storage capacitors with driver transistors. Because of the leakage property of the capacitor, DRAMs require periodic charge refreshing to maintain data storage. The package density is more in the case of DRAMs. But additional hardware is required for memory refresh operation. SRAMs consume more power when compared to DRAMs. SRAMS are faster than DRAMs.
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Part – 9: Complier Design 9.1 Introduction to Compilers Translator: A translator is a program that takes as input a program written in one language and produces as output a program in another language. Beside program translation, the translator performs another role, the error-detection. Any violation of the HLL specification would be detected and reported to the programmers. Important role of translator are: translating the HLL program input into an equivalent ML program and providing diagnostic messages wherever the programmer violates specification of the HLL. Type of Translators: - Interpreter, Compiler, Preprossessor, Etc Source program Preprocessor Source program Compiler Target assembly program Assembler Relocatable machine code Loader/link editor
library, relocatable object file
Absolute machine code Fig. 9.1.1.A language-processing system. In addition to a compiler, several other programs may be required to create an executable target program. Figure 9.1.1 shows a typical language processing process along with the compilation”. Interpreter: Unlike compiler, interpreter takes single instruction & executes. Advantage of Interpreter:
Certain language features supported by Interpreter rather than compiler. “Portability”
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COMPILERS
A compiler is a program that reads a program written in one language – the source language – and translates it into an equivalent program in another language – the target language As an important part of this translation process, the compiler reports to its user the presence of errors in the source program.
Source code
Applications:
Compiler
Machine code
Errors
Design of Interfaces Design of language migration tools Design of Re – engineering Tools
Two-Pass Assembly: The simplest form of assembler makes two passes over the input, where a pass consists of reading an input file once. In the first pass, all the identifiers that denote storage locations are found and stored in a symbol table. In the second pass, the assembler scans the input again. This time, it translates each operation code into the sequence of bits representing that operation in machine language, and it translates each identifier representing a location into the address given for that identifier in the symbol table. The output of the second pass is usually relocatable machine code, meaning that it can be loaded starting at any location L in memory; i.e., If L is added to all addresses in the code, then all references will be correct. Thus, the out- put of the assembler must distinguish those portions of instructions that refer to addresses that can be relocated. Loaders and Link-Editors:
A program called loader performs the two functions of loading and link-editing. The process of loading consists of taking relocatable machine code, altering the relocatable addresses and placing the altered instructions and data in memory at the proper locations. The link-editor makes a single program from several files of relocatable machine code.
The Phases of a Compiler A compiler includes the different phases, each of which transforms the source program from one representation to another. From figure 9.1.2 the compiler structure has following:
Lexical analysis Syntax Analysis Semantic analysis Intermediate code generation Code optimization Target code generation
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Source code
Front end
Intermediate Language
Back end
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Machine code
Errors
Front end is 0(n) or 0(n logn) Back end is NP-complete The six phases divided into 2 Groups 1. Front End: Depends on stream of tokens and parse tree ( also called analysis phase) 2. Back End: Dependent on Target, Independent of source code ( also called synthesis phase) The Compilation Model There are two parts to compilation: analysis and synthesis. High level program
Lexical Analyzer Stream of tokens Syntax Analyzer Parse tree Semantic Analyzer Annotates Parse tree Symbol Table Management
Intermediate code Generation
Error Handling Table
Intermediate form Code Optimization Optimized intermediate form Code Generatin
Assembly Program Fig. 9.1.2. Compiler structure
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Symbol-Table Management
A symbol table is a data structure containing a record for each identifier, with fields for the attributes of the identifier. Symbol table is a data Structure in a compiler used for managing information about variables & their attributes.
Error Detection and Reporting
The syntax and semantic analysis phases usually handle a large fraction of the errors detectable by the compiler. The lexical phase can detect errors where the characters remaining in the input do not form any token of the language. Errors where the token stream violates the structure rules (syntax) of the language are determined by the syntax analysis phase.
ANALYSIS PHASE OF THE SOURCE PROGRAM 1. Linear or Lexical analysis, in which stream of characters making up the source program is read from left-to-right and grouped into tokens that are sequences of characters having a collective meaning. 2. Hierarchical or Syntax analysis, in which characters or tokens are grouped hierarchically into nested collections with collective meaning. 3. Semantic analysis, in which certain checks are performed to ensure that the components of a program fit together meaningfully. Lexical Analysis:
The lexical analyzer is the first phase of a compiler. Its main task is to read the input characters and produce as output a sequence of tokens that the parser uses for syntax analysis. Sometimes, lexical analyzers are divided into a cascade of two phases, the first called “scanning” and the second "lexical analysis." The scanner is responsible for doing simple tasks, while the lexical analyzer does the more complex operations. Consider the expression t=t t where t,t t are floats Lexical analyzer will generate id
id
id
Syntax Analysis:
Hierarchical analysis is called parsing or syntax analysis. It involves grouping the tokens of the source program into grammatical phrases that are used by the compiler to synthesize output. The hierarchical structure of a program is usually expressed by recursive rules. For example, we might have the following rules as part of the definition of expressions: 1. Any identifier is an expression. 2. Any number is an expression. THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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3. If expression1 and expression2 are expression, then so are expression1 + expression 2 expression1 * expression 2 (expression1) Ex. Parser will generate
= id
+ ×
id
12
id Semantic Analysis:
The semantic analysis phase checks the source program for semantic errors and gathers type information for the subsequent code-generation phase. It uses the hierarchical structure determined by the syntax-analysis phase to identify the operators and operands of expressions and statements. An important component of semantic analysis is type checking. Ex. Now as t +1 &t are float. 12 is also converted to float
= id
+ ×
id id
Int to float 12
Intermediate Code Generation (or) ICG:
After syntax and semantic analysis compiler generate an explicit intermediate representation of the source program. This intermediate representation should have two important properties; easy to produce, and easy to translate into the target program. Ex. Intermediate code will be te = id . te id
id te
te
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Code Optimization: The code optimization phase attempts to improve the intermediate code, so that faster-running machine code will result. Some optimizations are trivial. Advantages of Code Optimization:Improves Efficiency Occupies less memory Executes fast
-
Ex. Optimized code will be te id
id id
. te
Code Generation: The final phase of the compiler is the generation of target code, consisting normally of relocatable machine code or assembly code. Memory locations are selected for each of the variables used by the program. Then, intermediate instructions are each translated into a sequence of machine instructions that perform the same task. A crucial aspect is the assignment of variables to registers. Machine code will look like MUL ADD MOV id Where
. contains id &
contains id .
Lexical Analysis
A token is a string of characters, categorized according to the rules as a symbol (e.g. IDENTIFIERS, KEYWORDS, OPERATORS, CONSTANTS, LITERAL STRINGS and PUNCTUATION SYMBOLS such as parenthesis, commas, and semicolons.).
The process of forming tokens from an input stream of characters is called tokenization and the lexer categorizes them according to a symbol type.
A lexeme is a sequence of characters in the source program that is matched by the pattern for a token. For example, the following statement
Int number ; The substring ‘nu ber’ is a lexe e for the token “identifier” or “ID” ‘int’ is a lexe e for the token “keyword” and ‘;’ is a lexe e for the token”;” THE GATE ACADEMY PVT.LTD. H.O.: #74, KeshavaKrupa (third Floor), 30th Cross, 10th Main, Jayanagar 4th Block, Bangalore-11 : 080-65700750,
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For example, in lexical analysis the characters in the assignment statement position : = initial + rate * 60, would be grouped into the following tokens: 1. 2. 3. 4. 5. 6. 7.
The identifier position. The assignment symbol : = The identifier initial. The plus sign. The identifier rate. The multiplication sign. The number 60.
The main purpose of a lexical analyzer in a compiler application is to translate the input stream into a form that is more manageable by the parser. However the tasks of a lexical analyzer can be divided into two phases. They are: Scanning & Lexical analysis. Lexical analyzer can also detect some lexical errors. a) Scanning: In the scanning phase it scans the input file and eliminates comments and white spaces in the form of blank, tab and new-line characters. So the parser will have not to consider it. The alternative is to incorporate white space into the syntax which is not nearly as easy to implement. This is why most compilers do such tasks at scanning phase. b) Lexical Analysis: At the second phase it matches pattern for each lexeme to generate token. In some compilers, the lexical analyzer is in charge of making a copy of the source program with the error message marked in it. It may also implements preprocessor functions if necessary. Issues in Lexical Analysis : There are several reasons for separating the analysis phase of compiling into lexical analysis and parsing. 1. Simpler design is perhaps the most important consideration. 2. Compiler efficiency is improved. A separate lexical analyzer allows us to construct a specialized and potentially more efficient processor for the task. 3. Compiler portability is enhanced. Input alphabet peculiarities and other device-specific anomalies can be restricted to the lexical analyzer. Tokens, Patterns, Lexemes (Important Point)
When talking about lexical analysis, we use the terms "token," "pattern," and "lexeme" with specific meanings. There is a set of strings in the input for which the same token is produced as output. This set of strings is described by a rule called a pattern associated with the token. A lexeme is a sequence of characters in the source program that is matched by the pattern for a token.
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TOKEN
SAMPLES LEXEMES
INFORMAL DESCRIPTION OF PATTERN
const
const
const
If
If
If
relation
, > =
< or < = or or > = or >
Id
pi, count, D2
letter followed by letters and digits
Num
3.1416, 0, 6.02E23
any numeric constant
literal
“core du
any characters between “and” exce t”
ed”
Fig. 9.1.2 Examples of tokens Lexical Errors: Few errors are discernible at the lexical level alone. But, suppose a situation does arise in which the lexical analyzer is unable to proceed because none of the patterns for tokens matches a prefix of the remaining input. Perhaps the simplest recovery strategy is “ anic ode” recovery. We delete successive characters from the remaining input until the lexical analyzer can find a well-formed token. This recovery technique may occasionally confuse the parser, but in an interactive computing environment it may be quite adequate. Other possible error-recovery actions are: 1. 2. 3. 4.
Deleting an extraneous character Inserting a missing character Replacing an incorrect character by a correct character Transposing two adjacent characters.
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9.2
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Syntax Analysis
The syntax of programming language constructs can be described by context-free grammars or BNF (Backus-Naur Form) notation. Grammars offer significant advantages to both language designers and compiler writers.
A grammar gives a precise, yet easy-to-understand syntactic specification of a programming language. From certain classes of grammars we can automatically construct an efficient parser that determines if a source program is syntactically well formed. A properly designed grammar imparts a structure to a programming language that is useful for the translation of source programs into correct object code and for the detection of errors. Tools are available for converting grammar-based descriptions of translations into working programs. Languages evolve over a period of time, acquiring new constructs and performing additional tasks. These new constructs can be added to a language more easily when there is an existing implementation based on a grammatical description of the language.
The Role of The Parser In our compiler model, the parser obtains a string of tokens from the lexical analyzer, as shown in Fig. 9.2.1 and verifies that the string can be generated by the grammar for the source language. token source progra m
lexical analyze r
Parser get next token
parse tree
rest of front end
intermediate representation
symbol table
Fig. 9.2.1 Position of parser in compiler model Syntax Error Handling: Planning the error handling right from the start can both simplify the structure of a compiler and improve its response to errors. Error-Recovery Strategies: panic mode, phrase level, error productions, global correction
Context-Free Grammars Grammars: It is a set of finite rules that may define infinite sentence. A context- free grammar (grammar for short) consists of terminals, non terminals, a start symbol, and productions.
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A context-free grammar G is a four-type (T,NT,S,P)
T is the set of terminals Non terminals are syntactic variables that denote sets of strings. The non terminals define sets of strings that help to define the language generated by the grammar. They also impose a hierarchical structure on the language that is useful for both syntax analysis and translation. In a grammar, one non terminal is distinguished as the start symbol, and the set of strings it denotes is the language defined by the grammar. The productions of a grammar specify the manner in which the terminals and non terminals can be combined to form strings. Each production consists of a non terminal, followed by an arrow (sometimes the symbol: = is used in place of the arrow), followed by a string of non terminals and terminals. i.e., Productions of the form NT (T+NT)*
Derivations: The central idea here is that a production is treated as a rewriting rule in which the non terminal on the left is replaced by the string on the right side of the production. We can take a single Non terminal and repeatedly apply productions in any order to obtain a sequence of replacements. We call such a sequence of replacements as derivation. Likewise, we use + to mean “derives in one or more steps. To ean “derives in zero or ore ste s”. "Given a grammar G with start symbol S, we can use the S
relation to define L (G); the
language generated by G. Strings in L (G) can contain only terminal symbols of G. We say a string of terminals w is in L (G) if and only if S
w. The string w is called a sentence of G. A language
that can be generated by a CFG is said to be a context-free language, If two grammars generate the same language, the grammars are said to be equivalent. If S
α where α
ay contain non ter inals then we say that α is a sentential form of G.
Note: A sentence is a sentential form with no non terminals. Parse Trees and Derivations: A parse tree may be viewed as a graphical representation for a derivation that filters out the choice regarding replacement order. The leaves of the parse tree are labeled by non terminals or terminals and, read from left to right; they constitute a sentential form, called the yield or frontier of the tree. Note : Let G = {V, T, P, S} is a grammar. The parse trees for G are trees with the following conditions: 1. Each interior node is labeled by a variable in V. 2. Each leaf is labeled by terminal or epsilon. However, if the leaf is labeled epsilon, then it must be the only child of its parent.
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Parsing means construct a parse tree. Using this parse tree we determine whether a string can be generated by a grammar. We can construct a parse tree in the following two ways: Top-Down parsing: When we construct a parse tree expanding the root, then expand all the non terminals until we get the leaves. Bottom-up parsing: When we construct a parse tree from bottom i.e., from leaf and get the root this parsing process is known as bottom-up parsing. A parse tree ignores variations in the order in which symbols in sentential forms are replaced. These variations in the order in which productions are applied can also be eliminated by considering only leftmost (or rightmost) derivations. It is not hard to see that every parse tree has associated with it a unique leftmost and/or a unique rightmost derivation. Grammar could be ambiguous or unambiguous. Ambiguous Grammars
Unambiguous Grammars
1. There exist more than one “LMD/ given string
MD ” for a
2. More than one parse tree for a given string
1. Unique “LMD/ MD” for a given string 2.
Unique parse tree for a given string
Ambiguity: A grammar that produces more than one parse tree for some sentence is said to be ambiguous. Eliminating Ambiguity Example : S S+S|S S|a Expression :a+a*a S S a
+ S a
S S+T|T T T*F|T
S S
S *
S
S
a
a
* S
S a
+ a
Two different parse trees
F a This grammar is equivalent to S S+S|S*S|a But it is unambiguous
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Importance of Left Recursion: Consider the example, one left-recursive: S –>Sx | x and one right-recursive: S –>xS | x There are the same number of states in the LR(1) parsers for the two grammars so there is no advantage in the runtime memory requirements for either table. Consider parsing the input xxx...x with a thousand x’s. In the left-recursive form, the parser shifts the first x, immediately reduces it to S, shifts another x, and then reduces Sx to S. It does this again and again for each subsequent x. The parse stack grows and shrinks, only getting three deep at its maximum. This left recursive will give infinite loop to LL (1) parser but LR parser will not get any problem. Hence elimination left recursive form is required for LL (1) parsers or Predictive parsers or Top-Down parsers. For the right-recursive grammar, the parser shifts the first x, and then shifts the second x, and so on. The arser doesn’t reduce until it gets to the $ at the end of the in ut. It then reduces the last x on top of the stack to S, then reduces the xS on the stack to S, again and again until the stack is empty. The stack had a thousand states on it by the time we got to the end of the input Although the LR parsing can handle either, the left-recursive grammar is handled more efficiently.
Elimination of Left Recursion:
A grammar is left recursive if it has a non terminal A such that there is a derivation A
Non-recursive predictive parser LL (1) methods cannot handle left-recursive grammars, so a transformation that eliminates left recursion is needed. We can eliminate immediate left recursion from them by the following technique. First, we group the A- productions as
Aα
A→Aα1|Aα2|………..|Aαm|β1|β2|……..|βn Where no β begins with an A. Then we re lace the A-productions by A →β1A’ | β2A’|………..|βnA’ A’→α1A’|α2A’|………..|αmA’|ϵ
Left recursion may appear either immediate or indirect left recursion in the grammar. If productions contain immediate left recursion then the above rule can be applied individually to the A-productions. If productions contain indirect left recursion then substitution procedure applied in the grammar. SAa|b AAc|Sd|∈ After removing left recursion for A, we will get SAa|b ASdA’ |A’ A’cA’ | ∈
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But still there left recursion. Consider ASdA’ substitution first SAa | b A Ac | Aad | bd | ∈ After removing left recursion, SAa | b AbdA’ | A’ AcA’ | adA’ | ∈
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S Aa, So it will be AAadA’. So we use
Left Factoring: Left factoring is a grammar transformation that is useful for producing a grammar suitable for predictive parsing. Left factoring is useful to avoid backtracking nature for parsers. The basic idea is that when it is not clear which of two alternative productions to use to expand a non terminal A, we may be able to rewrite the A-productions to defer the decision until we have seen enough of the input to make the right choice. For example, if we have the two productions st t → if ex r then st t else st t | if ex r then st t on seeing the input token if, we cannot immediately tell which production to choose to expand statement. In general if A →αβ1| αβ2 are two A-productions, and the input begins with a nonempty string derived fro A we do not know whether to ex and A to αβ1or to αβ2by seeing α. However, we ay defer the decision by ex anding A to αA'. Then after seeing the in ut derived fro we ex and A' to β1 or to β2. That is, left-factored, the original productions become A →α A’ A’→β1| β2 Example:Sabc | abd | ae | f Removing left factoring, SabS’ | ae | f S’c|d Once, again, repeat, the same procedure: SaS’’ | f S’ c | d S’’bS’ | e
Top-Down Parsing Recursive-Descent Parsing / Predictive Parsing:
Top-down parsing, called recursive descent, that may involve backtracking, that is, making repeated scans of the input.
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Transition Diagrams for Predictive Parsers: To construct the transition diagram of a predictive parser from a grammar, first eliminate left recursion from the grammar, and then left factor the grammar. Then for each non-terminal A do the following: 1. Create an initial and final (return) state. 2. For each production A→XR1 , XR2 . . . . XRn , create a path from the initial to the final slate, with edges labeled XR1 , XR2 . . . .XRn A predictive parsing program based on a transition diagram attempts to match terminal symbols against the input, and makes a potentially recursive procedure call whenever it has to follow an edge labeled by a non-terminal. A non-recursive implementation can be obtained by stacking the states The above approach works if the given transition diagram does not have non determinism. Non Recursive Predictive Parsing:
It is possible to build a non-recursive predictive parser by maintaining a stack explicitly, rather than implicitly via recursive calls. The key problem during predictive parsing is that of determining the production to be applied for a non-terminal. A table-driven predictive parser has an input buffer, a stack, a parsing table, and an output stream. a. The input buffer contains the string to be parsed, followed by $, a symbol used as a right end marker to indicate the end of the input string. The stack contains a sequence of grammar symbol with a $ on the bottom, indicating the bottom of the stack. Initially the stack contains the start symbol of the grammar on top of $. b. The parsing table is a two-dimensional array M [X, a], where X is a non-terminal, and a is a terminal or the symbol $. c. The key problem during predictive parsing is that of determining the production to be applied for a non-terminal. The non-recursive parse looks up the production to be applied in the parsing table The parser is controlled by a program that behaves as follows. The program considers X, the symbol on top of the stack, and a, the current input symbol. These two symbols determine the action of the parser. There are three possibilities. a. If X = a = $, the parser halts and announces successful completion of parsing. b. If X = a = $, the parser pops X off the stack and advances the input pointer to the next input symbol. c. If X is a non-terminal, the program consults entry M [X, a], a| of the parsing table M. This entry will be either an X-production of the grammar or an error entry.
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Complier Design
FIRST and FOLLOW
The construction of a predictive parser is aided by two functions associated with a grammar G. These functions, FIRST and FOLLOW, allow us to fill in the entries of a predictive parsing table for G, whenever possible. If a is any string of grammar symbols let FI ST (α ) be the set of ter inals that begin the strings derived from a. If ϵ , then e is also in FI ST(α). Define FOLLOW(A), for non-terminal A, to be the set of terminals a that can appear immediately to the right of A in some sentential form, that is, the set of terminals a such that there exists a derivation of the form S αAaβ for so e α and β Note that there ay at so e ti e during the derivation have been sy bols between A and α but if so they derived ϵ and disappeared. It A can be the rightmost symbol in some sentential form, then $ is in FOLLOW {A). To build FIRST (X) 1. 2. 3. 4.
If X is a terminal, FIRST (X) is {X} If X ϵ then ϵ ∈ FIRST (X) If X … . then put FIRST ( ) in FIRST (X) If X is a non-terminal and X …. then a ∈ FIRST (X) if a FIRST ( ) and ϵ ∈ FIRST ( ) for all ≤ j
