Qm_Xc6Slx16_Sdram Core Board: User Manual

QM_XC6S QM_XC6SL L X16_SDR X16_SDRA A M CORE BOARD B OARD USER USER MANUAL

Preface The QMTech® XC6SLX16 SDRAM core board uses Xilinx’s Xilinx’s Spartan  Spartan®-6 XC6SLX16-2FTG256C device to demonstrate industry leading connectivity features such as high logic-to-pin ratios, small form-factor packaging, MicroBlaze™ soft processor , 800Mb/s DDR3 support, and a diverse number of supported I/O protocols. Built on 45nm technology, the devices are ideally suited for advanced bridging applications found in automotive infotainment, consumer, and industrial automation.

QM_XC6SLX16_SDRAM Core Board

User Manual V01

Table of Contents 1.

INTRODUCTION ............................................................................... 3

1.1 1.2 2.

DOCUMENT SCOPE ....................................................................... 3 KIT OVERVIEW .............................................................................3

GETTING STARTED ........................................................................... 4

2.1 2.2

INSTALL DEVELOPMENT TOOLS ........................................................ 5 QM_XC6SLX16_SDRAM HARDWARE DESIGN................................ 6 2.2.1 QM_XC6SLX16_SDRAM Power Supply.........................6 2.2.2 QM_XC6SLX16_SDRAM SPI Boot ................................. 7  2.2.3 QM_XC6SLX16_SDRAM Memory.................................8 2.2.4 QM_XC6SLX16_SDRAM System Clock .........................8 2.2.5 QM_XC6SLX16 Extension IO ........................................9 2.2.1 QM_XC6SLX16_SDRAM 3.3V Power Supply .............. 10 2.2.2 QM_XC6SLX16_SDRAM JTAG Port............................. 10 2.2.3 QM_XC6SLX16_SDRAM User LED .............................. 10 2.2.4 QM_XC6SLX16_SDRAM User Key .............................. 11

3.

REFERENCE .................................................................................... 12

4.

REVISION ....................................................................................... 13

QM_XC6SLX16_SDRAM Core Board

User Manual V01

1.

Introduction

1.1

Document Scope This demo user manual introduces the QM_XC6SLX16_SDRAM core board and describes how to setup the core board running with application software Xilinx ISE 14.7. Users may employee the on board rich logic resource FPGA XC6SLX16-2FTG256C and large S DRAM memory MT48LC16M16 to implement various applications. The core board al so has 108 non-multiplexed FPGA IOs for extending customized modules, such as UART module, CMOS/CCD camera module, LCD/HDMI/VGA display module etc.

1.2

Kit Overview Below section lists the parameters of the QM_XC6SLX16_SDRAM core board:  On-Board FPGA: XC6SLX16-2FTG256C;  On-Board FPGA external crystal frequency: 50MHz;  XC6SLX16-2FTG256C has rich block RAM resource up to 576Kb ;  XC6SLX16-2FTG256C has 14,579 logic cells;  On-Board M25P80 SPI Flash，1M bytes for user configuration code;  On-Board 32MB Micron SDRAM，MT48LC16M16A2-75;  On-Board 3.3V power supply for FPGA by using MP2359 wide input range DC/DC;  XC6SLX16 development board has two 64p, 2.54mm pitch headers for extending user IOs. All IOs are precisely designed with length matching;  XC6SLX16 development board has 3 user switches;  XC6SLX16 development board has 4 user LEDs;  XC6SLX16 development board has JTAG interface, by using 6p, 2.54mm pitch header;  XC6SLX16 development board PCB size is: 6.7cm x 8.4cm;  Default power source for board is: 1A@5V DC, the DC header type: DC-050, 5.5mmx2.1mm;

Figure 1-1. QM_XC6SLX16_SDRAM Core Board Overview

QM_XC6SLX16_SDRAM Core Board

User Manual V01

2.

Gettin g Started The QM_XC6SLX16_SDRAM core board includes below item:

Figu re 2-1. QM_XC6SLX16_SDRAM Top View Below image shows the dimension of the QM_XC6SLX16_SDRAM core board: 6.7cm x 8.4cm. The unit in below is millimeter(mm).

Figure 2-2. QM_XC6SLX16_SDRAM Core Board Dimension

QM_XC6SLX16_SDRAM Core Board

User Manual V01

2.1

Install Developm ent Tools The QM_XC6SLX16_SDRAM core board tool chain consists of Xilinx ISE 14.7, Xilinx USB platform cable, XC6SLX16 core board and 5V DC power supply. Below image shows the Xilinx ISE14.7 development environment which could be downloaded from Xilinx office website:

Figu re 2-3. ISE 14.7 Below image shows the JTAG connection between Xilinx USB platform cable and XC6SLX16 core board:

TMS (Green) TDI (Purple) TDO (White) TCK (Yellow) GND (Black) VREF Red

5V DC

Figure 2-4. JTAG Conn ection and Power Supply

QM_XC6SLX16_SDRAM Core Board

User Manual V01

2.2

QM_XC6SLX16_SDRAM Hardware Design

2.2.1

QM_XC6SLX16_SDRAM Power Supp ly

The core board needs 5V DC input as power supply which could be directly injected from power header or the 64P female header U7/U8. Users may refer to the hardware schematic for the detailed design. The on board LED D4 indicates the 3.3V supply, it will be turned on when the 5V power supply is active. In default status, all the FPGA banks IO power level is 3.3V because bank power supply is 3.3V. However, BANK1 IO’s power level could be changed according to detailed custom requirement. There’re three 0 ohm resisters could be removed:R223/R224/R225, and instead the BANK1’s power supply could be injected fro m 64P female header U7. Detailed design refer to hardware schematic. Note: FPGA core supply 1.2V is regulated by On-Semi DC/DC chip NCP1529 which could output maximum 1A current. U2F GND_0 GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 VCCAUX_0 VCCAUX_1 VCCAUX_2 VCCAUX_3 VCCAUX_4 VCCAUX_5 VCCAUX_6 VCCAUX_7 VCCINT_0 VCCINT_1 VCCINT_2 VCCINT_3 VCCINT_4 VCCINT_5 VCCINT_6 VCCINT_7 VCCO_0_0 VCCO_0_1 VCCO_0_2 VCCO_0_3 VCCO_0_4 VCCO_1_0 VCCO_1_1 VCCO_1_2 VCCO_1_3 VCCO_1_4 VCCO_1_5 VCCO_2_0 VCCO_2_1 VCCO_2_2 VCCO_2_3 VCCO_3_0 VCCO_3_1 VCCO_3_2 VCCO_3_3 VCCO_3_4

 A1  A16 B11 B7 D13 D4 E9 G15 G2 G8 H12 H7 H9 J5 J8 K7 K9 L15 L2 M8 N13 P3 R10 R6 T1 T16 E5 F11 F8 G10 H6 J10 L6 L9 G7 G9 H10 H8 J7 J9 K10 K8 B13 B4 B9 D10 D7 D15 G13 J15 K13 N15 R13 N10 N7 R4 R8 D2 G4 J2 K4 N2

3V3

C53 4.7uF 10V C28 C29 C19 100NF 100NF 100NF C20 C22 100NF 100NF VCCO_1

C61 3V3

1V2

3V3

4.7uF 10V C63 100NF C62 1V2 100NF

C35 4.7uF 10V C36 100NF C37 100NF

VCCO_1

3V3

Spartan-6_XC6SLX16_FTG256

Figure 2-5. Power Supp ly fo r the FPGA

QM_XC6SLX16_SDRAM Core Board

User Manual V01

2.2.2

QM_XC6SLX16_SDRAM SPI Bo ot In default, QM_XC6SLX16 boots from external SPI Flash, detailed hardware design is shown in below figure. The SPI flash is using M25P80 manufactured by Micron, with 8Mbit memory storage. 3V3 3V3 U6 3V3

4.7K  

R15FPGA_CSO_B

FPGA_MISO R17 3V3

4.7K

0R

1

nCE

VDD

2

R18

HOLD

WP 4

C44   100NF

7 SO

3

R20

8

 

FPGA_CCLK

5

FPGA_MOSI

SCK

VSS

SI

4.7K

6

R16 1K 3V3

R24 1K

M25P80

Figure 2-6. SPI Flash The FPGA boot sequence setting M0:M1 is configured as 1:0 which indicates FPGA will boot from SPI Flash after power on. U2E IO_L1P_HSWAPEN_0 TCK TDI TMS TDO SUSPEND CMPCS_B_2 DONE_2 IO_L1P_CCLK_2 IO_L3P_D0_DIN_MISO_MISO1_2 IO_L3N_MOSI_CSI_B_MISO0_2 IO_L65N_CSO_B_2 IO_L65P_INIT_B_2 PROGRAM_B_2 IO_L1N_M0_CMPMISO_2 IO_L13P_M1_2

C4 C14 C12  A15 E14

R11

 

4.7K

TCK TDI TMS TDO

P14 L11 P13

FPGA_DONE

R11 P10 T10 T3

FPGA_CCLK FPGA_MISO FPGA_MOSI FPGA_CSO_B

R3

R19

 

4.7K

3V3

T2 PROG_BR22 T11 R23 N11

   

4.7K 4.7K

3V3 3V3

Spartan-6_XC6SLX16_FTG256

Figure 2-7. M0:M1 Hardware Settings The LED D2 will be turned on after the FPGA successfully loading configuration file from SPI Flash during power on stage. In this case, LED D2 could be used as FPGA loading status indicator. 3V3

R13 1K

FPGA_DONE         1

D2 Red         2

R25 1K

Figure 2-8. FPGA_DONE Status Indicato r

QM_XC6SLX16_SDRAM Core Board

User Manual V01

2.2.3

QM_XC6SLX16_SDRAM Memor y QM_XC6SLX16 has on board 16bit width data bus, 32MB memory size SDRAM MT48LC16M16 provided by Micron. Below image shows the detailed hardware design:  A0  A1  A2  A3  A4  A5  A6  A7  A8  A9  A10  A11

23 24 25 26 29 30 31 32 33 34 22 35

 A13  A14

20 21

 A12

36 40

SDCKE0

37

SDCLK0

38

DQML DQMH

15 39

CAS RAS

17 18

16 SDWE SD_NCS0 19

MN1  A0  A1  A2  A3  A4  A5  A6  A7  A8  A9  A10  A11

2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

 MT48LC 16M16 A2

BA0 BA1  A12 N.C

1 14 27 3 9 43 49

VDD VDD VDD VDDQ VDDQ VDDQ VDDQ

CKE CLK DQML DQMH

28 41 54 6 12 46 52

VSS VSS VSS VSSQ VSSQ VSSQ VSSQ

CAS RAS

WE CS

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 3V3

C3 C5 C7 C9 100NF 100NF 100NF 100NF C4 C6 C8 100NF 100NF 100NF

256Mbits

Figure 2-9. SDRAM 2.2.4

QM_XC6SLX16_SDRAM Syst em Cloc k FPGA chip XC6SLX16-2FTG256C has system clock frequency 50MHz which is directly provided by external crystal. The crystal is designed with high accuracy and stability with low temperature drift 10ppm/ °c. Below image shows the detailed hardware design: 3V3 R9

1

 

OE

4.7K

VDD

4 C42 100NF

50 MHz

2

VSS

 

OUT

3

SYS_CLK

Y1

SG-8002JC-50.0000M-PCB

Figure 2-10. 50MHz System Clock

QM_XC6SLX16_SDRAM Core Board

User Manual V01

2.2.1

QM_XC6SLX16_SDRAM 3.3V Power Supp ly The core board’s 3.3V power supply is using high efficiency DC/DC chip MP2359 provided by MPS Inc. The MP2359 supports wide voltage input range from 4.5V to 24V. In normal use case, 5V DC power supply is suggested to be applied on the board. Below image shows the MP2359 hardware design:

C67

 

10nF         2

VCCO_1

3V3

L6

3.3uH

R223 R224 R225

C69

0R 0R 0R

D5

C60 DNP

R128 100K

4.7uF

IN5819

U4 1

6 BST

SW

GND

VIN

2

REGULATED

        1

5VONLY

5V_IN

5

3

4 FB

4 3 2 1

R126 100K

EN

+

MP2359

C58 47uF

R129 33K

C68 100nF

R127 DNP

JP5 Power_Header_SMT

Figu re 2-12. MP2359 Hardwar e Design 2.2.2

QM_XC6SLX16_SDRAM JTAG Port The on board JTAG port uses 6P 2.54mm pitch header which could be easily connected to Xilinx USB platform cable. Below image shows the hardware design of the JTAG port: 3V3 J2 1 2 3 4 5 6

TCK TDO TDI TMS

JTAG

Figure 2-13. JTAG Port 2.2.3

QM_XC6SLX16_SDRAM User LED Below image shows two user LEDs and 3.3V power supply indicator: 3V3

R131 1K

3V3

R218 1K

3V3

R217 1K

1

2

BANK2_IO_T9

2

BANK2_IO_R9

D1 1 D3 1

2

D4

Figu re 2-14. LEDs

QM_XC6SLX16_SDRAM Core Board

User Manual V01

2.2.4

QM_XC6SLX16_SDRAM User Key Below image shows the PROGRAM_B key and two user keys: 3V3

PROG_B 2 SW1

R221 4.7K

R222 4.7K

BANK2_IO_T8

BANK2_IO_R7

2 SW2

1

3V3

2 SW3

1

1

Figure 2-15. Keys

QM_XC6SLX16_SDRAM Core Board

User Manual V01

3.

Reference [1] [2] [3] [4] [5] [6]

ug380-Configuration.pdf ug385-Package.pdf ug394-Power Managment.pdf M25P80.pdf LPC-Link-II_Rev_C.pdf QM_XC6SLX16.pdf

QM_XC6SLX16_SDRAM Core Board

User Manual V01

4.

Revision Doc. Rev.

Date

Commen ts

0.1

05/10/2017

Initial Version.

1.0

05/14/2017

V1.0 Formal Release.

QM_XC6SLX16_SDRAM Core Board

User Manual V01