Priority Encoder

EXPERIMENT NO.6 Aim To implement VHDL code for 4:2 and 8:3 priority encoder.

Tool required •

Mentor Graphics

•

FPGA advantage 8.1ps

•

Model sim 6.3a

Theory A priority encoder is a circuit or algorithm or algorithm that compresses multiple binary multiple binary inputs into a smaller  number of outputs. The output of a priority encoder is the binary representation of the ordinal number starting from zero of the most significant input bit. They are often used to control interrupt requests by acting on the highest priority request. If two or more inputs are given at the same time, the input having the highest priority will take  precedence  precedence.. An example of a single bit 4 to 2 encoder is encoder is shown, where highest-priority inputs are to the left and "x" indicates an irrelevant value - i.e. any input value there yields the same output since it is superseded by higher-priority input. Priority encoders can be easily connected in arrays to make larger encoders, such as one 16-to-4 encoder made from six 4-to-2 priority encoders - four 4-to-2 encoders having the signal source connected to their inputs, and the two remaining encoders take the output of the first four as input. The priority encoder is an improvement on a simple encoder circuit, in terms of handling all  possible  possible input configurations. configurations.

4:2 priority encoder A 4-bit priority encoder (also sometimes called a priority decoder). This circuit basically converts the 4-bit input into a binary representation. If the input n is active, all lower inputs (n-1 .. 0) are ignored:

Truth Table Input

Logic Equation A1 = D2 + D3 A0 = D1D2’ + D3 ANY = D1 + D2 + D3

Output

D3

D2

D1

D0

Q1

Q0

ANY

0

0

0

X

0

0

0

0

0

1

X

0

1

1

0

1

X

X

1

0

1

1

X

X

X

1

1

1

8:3 priority encoder

Truth Table Digital Inputs

Binary Output

D7

D6

D5

D4

D3

D2

D1

D0

Q2

Q1

Q0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

1

X

0

0

1

0

0

0

0

0

1

X

X

0

1

0

0

0

0

0

1

X

X

X

0

1

1

0

0

0

1

X

X

X

X

1

0

0

0

0

1

X

X

X

X

X

1

0

1

0

1

X

X

X

X

X

X

1

1

0

1

X

X

X

X

X

X

X

1

1

1

Logic Equation Q2 = D4 + D5 + D6 + D7 Q1 = D5’D4’D2 + D5’D4’D3 + D6 + D7 Q0 = D6’D4’D2’D1 + D6’D4’D3 + D6’D5 + D7

VHDL code for 4:2 Priority Encoder  LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY PENC4 IS PORT( D3,D2,D1,D0 : IN STD_LOGIC; A1,A0,ANY:OUT STD_LOGIC); END ENTITY PENC4; ARCHITECTURE PENC4_ARCH OF PENC4 IS BEGIN PROCESS(D3,D2,D1,D0) BEGIN IF(((D3='0' AND D2='0') AND D1='0') AND D0='0') THEN ANY