Pipeline

ECE4680 Computer Organization Organization and Arch itecture Designin De signin g a Pipeline Processor 

2002-4-3

ECE4680 Pipeline.1

 A Si ng le Cyc C ycle le Pr oc ess or  Branch

Instruction op

Jump

 

Instruction Fetch Unit

Zero Clk 

Rt RegDst

 

 

 

ALUop

Imm16 Imm16

1 Mux 0

 busW 32 Clk 

func Rs 5

ALUSrc

:

3

32 32-bit Registers

ALUctr 

3

 busA

Zero

32  busB 32

16

ALU Control

Rt 5

Rw Ra Rb

imm16 Instr

Main Control

Rd 

Rd 

RegWr  5

RegDst

E  x  t    e  n  d  32  e  r 

0 M

A L   U

0

32 32

 u x 1

MemtoReg

MemWr 

WrEn Adr  Data In 32 Clk 

M  u x 1

Data Memory

ALUSrc

ExtOp ECE4680 Pipeline.2

2002-4-3

Drawbacks Dra wbacks o f this Single Cycle Cycle Processor  !Long •

cycle time: Cycle time must be long enough for the load instructio n: -

PC’s Clock -to-Q +

-

Instructio n Memory Memory Access Time +

-

-

Register File Access Time +  AL U Delay (add res s c alc ulati ul ati on ) +

-

Data Memory Access Time +

-

Register File Setup Time Time +

-

Clock Skew

!Cycle

time is much longer than needed needed for all other instr uctions . Examples: •

R-type R-type instruc tions d o not require data memory memory access

•

Jump d oes not require ALU operation nor data memory access

2002-4-3

ECE4680 Pipeline.3

Overview of a Multiple Cycle Impl Impl ementation !The •

root of the single cycle processor’s pr oblems: The cycle cycle time has to be long enough for t he slowest instructi on

!Solution:

Break the instruction into smaller steps

•

Execute each each step (instead of the entire instr uction) in one cycle Cycle time: time it takes to execute the longest step

•

-

-

Keep all the steps to have similar length

This is the essence essence of the multiple cycle processor 

•

!The

advantage advantages s of the multiple c ycle processor:

•

Cycle time is much shorter 

•

Different instructions take different number of cycles to complete -

-

•

Load takes five cycles Jump o nly takes three cycles

 Allo  Al lo w s a f un ct io nal un it to be u sed mo re t han once on ce p er i ns tr uc ti on

ECE4680 Pipeline.4

Why will this hinder the pipeline?

2002-4-3

Multiple Cycle Processor  !MCP:

A functio nal unit to be used more than once per instruction

PCWr 

PCWrCond Zero IorD

MemWr 

IRWr 

RegDst

ALUSelA

RegWr 

32 32

0 M  u x

RAdr 

Ideal Memory

1

WrAdr  32 Din Dout

32 32

I   n  s   t   r   u  c   t    oi   n R  e   g

Rs 32

5

Rt 0 Rt M

5

Rb

 busA

Reg File Rw

 u x

Rd 

 busW busB 32

1

1 Mux  0

Imm 16