Pcb Dfm Dft Guidelines

  Released Manufactur ability/ Testability Guidelines TEP-005 - Design for Manufacturability/ Rev: 6 Date: 5/15/01

1

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Purpose The purpose of this procedure is to provide general guidelines for printed circuit board design with the intent to optimize for efficient, economical economical manufacturing, and testing testing techniques. techniques.

2

Scope This procedure applies to all employees and outside sources who design printed circuit boards for manufacturing at Inservco, Inc. Component Component pad design should conform to the following f ollowing standards (in order of precedence)and should b e collaborative between the customer and Inservco: Inservco’s “General D Design esign Recommendations” IPC-SM-782 standards Manufacturer standards 2.1 Attachments – Supplement 1 ,General SMT Land Patterns / Recommendations Recommendations Supplement 2, Guidelines, Guidelines, Designing for for BGA’s BGA’s ; CSP’s

3

Responsibility It is the responsibility of the Test and Manufacturing Engineering Department to maintain this procedure.

4

Mechanical Design Considerations 4. 0.

General :

4.0.1 Solder Solder mask mask clearance clearance around around board board features features (such (such as SMT SMT pads, pads, vias, vias, and plated plated through through holes) holes) should be .003 inches. 4.0.2 SMT passive passive compone component nt spacing spacing should should be at least least 0.8 0.8 mm mm (.030”) (.030”) from one one componen componentt to another. another. .050” preferred. 4.0.3

Via holes holes should should not not be located located under under the body body of of chip caps caps and resist resistors ors that that are 1206 or or smalle smaller. r.

4.0.4

Componen Component-tot-to-board board edge edge clearance clearance shou should ld be .197 .197 inches inches minim minimum. um. Inservco Inservco prefers prefers .250 .250 inches inches..

4.0.5

Componen Componentt orient orientation ation should should be clearly clearly indi indicated cated on the the PC substrate substrate..

4.0.6

Component pad design should conform to the standar ds as outlined in Supplement 1 – Land Pattern design.

4.0.7

Provide non-plated tooling holes as outlined in section 4.6.

4.0.8

Provision for three global fiducial targets for vision alignment should be accommodated. Dimensions should be .050 . 050 inch solid round pad with 0.100 inch solder mask clearance. clear ance.

4.0.9

For each fine pitch device, provide a local fiducial.

4.0.10 Retain consistent orientation on components when possible. _____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Commerce Drive, LaGrange, Ohio 44050 1 of 42

  Released Manufactur ability/ Testability Guidelines TEP-005 - Design for Manufacturability/ Rev: 6 Date: 5/15/01

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

4.0.11 Mount polarized devices in the same direction. 4.0.12 Allow reasonable component density and even distribution. 4.0.13 Select SMT devices in standard configurations. 4.0.14 Choose parts that will have multiple sources. 4.0.15 Design the circuit board to control excessive cost. 4.1

Design for Test [DFT] 4.1.1

General - When reviewing the assembly for testability, testability, verify the following following requirements. requirements.

4.1.1.2 One test probe contact node per net f or in-circuit test, minimum. minimum. 4.1.1.3 Test probe contact spacing of 2 mm (.080”) minimum. 4.1.1.4 Probe test test contact area of .9-1 mm (.035”- .040”) diameter. dia meter. 4.1.1.5 Assembly is testable from one side. 4.1.1.6 Probe body-to-component, body clearance of .8mm (.030”) minimum. 4.1.1.7 Do not rely on component, lead or land pattern for test, probe contact. The pressure of the spring-loaded spring-loaded probe pin can ca n add just enough pressure to a substandard substandard solder connection to mask a solder defect, when the pressure is released, the component lead is allowed to open and electrical continuity is broken. 4.1.1.8 Placement of Probe Targets for Bed-of-Nails Testing should be evenly distributed over the surface of the PCB (assembly). 4.1.1.9 The Printed Circuit Board should be designed such that there are test pads or vias (probe targets) available for probing all electrical nodes, including unused pins and no-connects, from one side of the board. SMT component component leads should not be used for probing. 4.1.2 Bottom Bottom side side probe probe targets targets should should be at least least 0.040” 0.040” diam diameter eter and should should have solder solder as the contact surface. 0.035” is the absolute minimum. Top side probe targets should be 0.045” diameter minimum. 4.1.3

Probe targets targets shoul should d be 0.100” 0.100” apart apart if if poss possible, ible, but at least 0.075” 0.075” apart.

0.050” unacceptable 0.100” preferred _____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Commerce Drive, LaGrange, Ohio 44050 2 of 42

  Released Manufactur ability/ Testability Guidelines TEP-005 - Design for Manufacturability/

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Rev: 6 Date: 5/15/01

4.1.4 tall).

Probe targets targets should should be located located at least least 0.200” 0.200” from from tall compon components ents (greater (greater than 0.250” 0.250”

4.1.5 Probe targe targets ts should should be located such such that that their their centerl centerlin inee is 0.060” away away from from the the edges edges of  other components (less than 0.250” tall). 4.1.6 4.3

Probe targets targets should should be be evenly evenly distribute distributed d over over the the PC board board surface. surface.

Thru-hole Pad/Via Design 4.3.1

The smallest recommended finished hole size is 0.013”.

4.3.2 4.3. 2 External pad size should be at least 0.018” greater than than the finished hole size. signal layer pad size should be at least 0.022” greater than the finished hole size.

Internal

4.3.3 Internal Internal power/g power/ground round clearance clearance pads pads should should be at least least 0.026” 0.026” great greater er than than the finished finished hole size. 4.3.4 Vias should should be isolat isolated ed from from compone component nt pads pads by at least least 0.025” 0.025” and and never located located within within a surface mount pad.

4.4

4.3.5

Vias should be filled with solder if possible to prevent vacuum leaks on bed-of-nails testers.

4.3.6

SMT passive component spacing should be at least 0.8 mm (.030”) from one component to another .050” preferred.

SMT Pad Design 4.4.1 In general, general, SMT SMT pads pads should should be 0.010” to to 0.020” 0.020” larger larger tha than n the contact contact area area of of the component’s component’s foot. Conformance to IPC-SM-782 is is highly highly recommended. recommended.

4.4.2 The width width of of a trace trace entering entering a surface surface moun mountt pad should should be no more more than 0.010” and and should enter enter the pad at the center. This provides a thermal thermal barrier for solderability. Wide traces trac es may be narrowed as shown below. Component Pads

0.010” 0.010”

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Commerce Drive, LaGrange, Ohio 44050 3 of 42

  Released Manufactur ability/ Testability Guidelines TEP-005 - Design for Manufacturability/ Rev: 6 Date: 5/15/01

4.4.3

Surface Surface mount mount pads should should never never be placed directly directly in contact with wit h other other pads. pads.

Acceptable

4.5

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Unacceptable

Design of Copper Traces

4.5.1 The minimum minimum recommended recommended line line width width and spacing spacing is 0.006” assuming ½ ounce ounce copper. Use a minimum of 0.010” for 1 ounce copper. 4.6

Tooling Holes

4.6.1 There There shoul should d be at least three three 0.125 0.125”” diame diameter ter non-plated tooling holes located as in the following diagram:

Preferred

4.6.2 4.6.2

Acceptable

Clear Clearan ance ce arou around nd too tooli ling ng hole holes: s: 0.125 diameter tooling hole

SMT free area = 0.125” annular radius

0.125” clearance from board edge to tooling hole.

 0.125 diameter diam eter tooling hole

Thru-hole technology free area = 0.375 radius from center of tooling hole to components, component leads, thru holes, or vias.

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Commerce Drive, LaGrange, Ohio 44050 4 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Rev: 6 Date: 5/15/01

4.6.3

Tolerance for Tooling Holes: Hole to Hole +/- 0.002” Hole to Pad +/- 0.002” Diameter +0.003” / -0.000”

4.7

Component Placement

4.7.1

SOTs and Chips

Chip Body

Solder Land

Chip Body

SOT Body

0.050” min

Solder Land

Solder Land 0.050” min

4.7.2

SOICs and Chips Chip Body

0.050” min

0.050” min Solder Land

Chip Body

Solder Land SOIC Comp. Body

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 5 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines Rev: 6 Date: 5/15/01

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

4.7.3 All components, thru-hole or surface mount, should be placed such that they are not in direct contact with another component’s body or leads. 4.7.4

Component Orientation for Wave Solder

Board Direction

Board Direction

Best Case

Both ends are soldered at once.

4.8

Worst Case

One end of the component enters the solder before the other.

4.7.5

Integrated circuits and polarized discretes should be oriented consistently throughout the assembly. For example, the positive end of all electrolytic capacitors should point in the same direction.

4.7.6

Component orientation should be clearly indicated on the PC substrate using silkscreen or polarization markings

Soldermask 4.8.1 Use Liquid Photo Imagable (LPI) soldermask for fine pitch designs.

4.8.2

Soldermask design for ICs 0.025” pitch and greater.

Clearance from pad to soldermask  must be at least 0.003” on all sides [pads,vias, and PTH] for Liquid Photo Imagable. At least 0.005” for Dryfilm.

Soldermask design for ICs less than 0.025” pitch.

Soldermask design for chip resistors, capacitors, etc.

4.8.3 All probe points such as test pads and vias must be free of soldermask to enable test probe contact with the board. _____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 6 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines Rev: 6 Date: 5/15/01

4.9

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Component Silkscreen

4.9.1 Component silkscreen must include at least a unique reference designator for each component to be installed on the board (top and bottom). 4.9.2 For polarized components, there must be an indication on the silkscreen ( on in copper ) of the correct orientation. 4.9.3

If space permits, include an outline of the component.

4.9.4 All test pads must be free of silkscreen markings to enable test probe contact with the pad. 4.10

General Mechanical Considerations

4.10.1 There should be a free area, no components or test pads, within 0.125” of the edge of the board. Component-to-board edge clearance should be .197 inches minimum. Inservco prefers .250 inches 4.10.2 Component lead protrusion on the solder side of the PC board should be 0.062” or less. 4.10.3 PC board thickness of less than 0.062” should be avoided.

5.0

Fiducial Marking

5.1

Fiducial Mark Design 5.1.1 The fiducial mark must be a solid filled circle, preferably 0.050 inch diameter. The circle may be as small as 0.040 inch or as large as 0.118 inch.

5.1.2 The size of the fiducial on the same printed circuit board must not vary by more than 0.001 inch diameter.

5.1.3

Clearance around a fiducial mark must be twice the radius of the fiducial mark. This area must be clear of any conductive material, markings, or coatings

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 7 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Rev: 6 Date: 5/15/01

Clearance radius = 0.050”

Fiducial radius = 0.025”

5.1.4 The fiducial mark should be made of bare or covered copper. The covering may be a clear anti-oxidation coating, nickel plating, or tin plating. Hot-air leveled solder may also be used for plating. The thickness of the coating should be from 0.0002 to 0.0004 inch. If solder is used, the thickness should never be greater than 0.001 inch.

5.2

Fiducial Mark Placement Global Fiducial - 3 preferred per board. 2 are acceptable if they are in opposite corners.

Local Fiducial required for large (84 pins or greater) , fine-pitch ICs (0.025 inch or less). 2 per IC.

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 8 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines Rev: 6 Date: 5/15/01

Panel Fiducial - 3 preferred. 2 are acceptable if they are in opposite corners.

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Image Fiducial - 3 preferred. 2 are acceptable if they are in opposite corners.

The clearance from a fiducial mark to the edge of the printed circuit board or panel must be no less than 0.187 inch.

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 9 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Rev: 6 Date: 5/15/01

6

Panelization and Break-away Design 6.1

Routed Panels Thoughtful placement of the perforations can make depanelization quick and easy.

Routed panels provide a smooth, precise edge on the finished piece. The break-away tabs can be designed such that no further processing is necessary to dress up the edge after depanelization.

Inconsistent orientation should be avoided.

0.093” routing is preferred.

Note positioning of tooling holes and fiducials.

Inconsistent orientation complicates automated assembly equipment programming and may hinder in-line inspection.

Break line

or good

better

The number of break-away tabs required is a function of the size of the panel, the weight of the parts being installed, and the stiffness required for the manufacturing process. It is good practice to discuss this with a manufacturing engineer.

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 10 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Rev: 6 Date: 5/15/01

Please refer to IPC-SM-782 for details on the design of break-away tabs and for more information on routed and scored panels.

6.2

Scored Panels

6.2.1 The previous illustration shows a routed board with perforations. In many cases it may be more cost effective to score the panels. The major stipulation for using a scored panel is that no components overhang the edge of any one of the individual assemblies.

A scored panel can be separated quickly with the proper equipment. The edges of the boards may need to be sanded if the customer requires a smooth edge. Inconsistent orientation should be avoided.

Note positioning of tooling holes and fiducials.

6.2.2

Score Design The depth of cut must be at least .012” on each side.

.004” radius

.012” to .027” after scoring

25

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 11 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Rev: 6 Date: 5/15/01

7

Electrical Considerations

7.1

Functional blocks should be partitioned such that they may be tested separately.

7.2 Control lines must be accessible for external and independent control by test equipment. (Preset, Clear, Reset, Enable, Chip Select, etc.) One way to accomplish this is to connect them through a resistor. For example, a control line that would normally be tied to VCC would be connected through a resistor as in the following example: VCC

Test Point D

PR

CLK

Test Point

CLR

CE

Test Point Not less than 47 ohms VCC

7.3 PALS and similar IC’s should have their equations written such than an input line may be used to tri-state the device for testing upstream devices. 7.4

Provisions should be made so that long timers/delays may be sped up for testing.

7.5 Clocks/oscillators must be designed such that they may be disabled or testing.

tri-stated for

7.6 There must be a testpad on the ground net for every three IC’s and one on the power net for every 5 IC’s. These ground and power test pads should be distributed evenly across the circuit board.

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 12 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Rev: 6 Date: 5/15/01

7.7 Closed loop systems should be designed such that they may be opened easily for troubleshooting. Instead of this…

…consider this. It provides the ability to open the loop for testing.

VCC

Test Control Line

8

Design Change Considerations

8.1 When making a design change it is desirable that any through-holes, testpads, or vias being used for probe points remain at the same locations. This will minimize changes to the test fixture. 8.2

All wires that are added to the board should be dressed on the top side of the circuit board.

8.3 Connected pins that are isolated and tied together with modification wiring should be connected also to an unused via for in-circuit test access.

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 13 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Rev: 6 Date: 5/15/01

SUPPLEMENT 1 – General SMT Land Patterns / Recommendations: The following suggestions SMT land pattern design on passive chip resistors and capacitors

. C

X

Y

G Z

The following table below refer for reflow pads. Component 0402 0603 0805 1206 1210 1812 2010 2512

Z (inches) .087 .100 .120 .160 .160 .234 .244 .294

G (inches) .016 .022 .024 .048 .048 .110 .110 .150

X (inches) .028 .040 .055 .070 .110 .130 .110 .126

Y (inches) .036 .038 .048 .050 .050 .060 .067 .072

C (inches) Ref. .052 .062 .072 .110 .110 .174 .177 .222

A land pattern that too large for chip will encourage an excess of solder build up. When wave soldering discrete components, it is possible to adapt an optional narrow pad geometry to limit the amount of solder volume at the component connection.

The following table below refer for wave solder pads  Component 0805 1206 1210 1812

Z (inches) .152 .198 .198 .270

G (inches) .024 .048 .048 .110

X (inches) .037 .047 .073 .087

Y (inches) .064 .075 .075 .080

C (inches) Ref. .088 .123 .123 .190

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 14 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Rev: 6 Date: 5/15/01

INDUCTORS C

X

Y

G Z

The following table below refer for reflow pads. Component Case A B C D

Z (inches)

G (inches)

X (inches)

Y (inches)

C (inches) Ref.

.187 .225 .400 .500

.043 .075 .100 .200

.050 .100 .100 .100

.062 .075 .150 .150

.125 .150 .250 .350

SOT-23 Geometry    .040” Square

  .080”

  .075”

  .040”

  .050”

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 15 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Rev: 6 Date: 5/15/01

SOT-89 Geometry    .087”

  .045°   .035”

  .087”

  .035”   .059”   .045°   .039”

.039”

.039”

  .020”   .020”

SOT-143 Geometry    .040” Square

  .080”

  .040”   .080”

  .040”   .040”

  .050”   .030”

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 16 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Rev: 6 Date: 5/15/01

Small outline IC

The SOP (EIAJ) of devices , generally wider body than the JEDEC SOIC packages, includes 8-lead through 42 lead package standard. The wider format, referred to as SO-L, SO-W or SO-X extends from 8 leads up to 36 leads. Carefully check manufacturer’s before beginning the design. The following suggestions SMT land pattern design on SOIC and SOIC-W.

SO-8, 14, 16 .060” - .090”

.050” typical

.020” - .025” typical

  .200”

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 17 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Rev: 6 Date: 5/15/01

JEDEC MS-012XX

Small out line package family. .150 inch body width. .1497” - .1574”

.050” typical

 .013” - .020”

.2284”- .244”

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 18 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Rev: 6 Date: 5/15/01

Land pattern recommended  

.225”

.050” typical

 .024”

  .150”

  .300”

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 19 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Rev: 6 Date: 5/15/01

MO-120 Plastic small outline with .350 inch body width .350” Nom.

.050” typical

.016” Mon.

.472” Mon.

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 20 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Rev: 6 Date: 5/15/01

Plastic small outline with .350 inch body width, .350” Nom.

.050” typical

 .024”

  .532”

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 21 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines Rev: 6 Date: 5/15/01

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

20-Pin TSSOP Plastic Thin Shrink Small Outline 4.4 mm wide 4.3mm - 4.5mm

  ..65mm

 .19 - .30mm

6.1mm - 6.7mm

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 22 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Rev: 6 Date: 5/15/01

Land pattern recommended   4.3mm

  .65mm

 .40mm

  7.72mm

20 Pin PLCC Component Dimensions 5.78 - 6.53 mm  .33 - .53mm

 9.78 - 10.03 mm

 1.27mm

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 23 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Rev: 6 Date: 5/15/01

20 Pin PLCC Land Pattern Dimensions  6.4mm  .60mm

10.8 mm

 1.27mm

Tsop48- 48 Lead Thin Small Outline, 12 X 20mm .50mm Pitch. Land pattern Dimensions. 18.3mm .3mm

 .50mm

 21.2mm

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 24 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Rev: 6 Date: 5/15/01

JEDEC MS-022- Quad Flat Packs (Square)

C .

A

.e1

B

Land Pattern Recommended

Dim. A B C e1

10 X 10 X 2 Body 13.8 10.00 .5 .80

14 X 14 Body 17.8 14.00 .50 1.00

Land Pattern Recommended (Dimensions in inches)

Dim. A B C Pitch

VQ44 VQ64 .543 .530 .401 .378 .20 .012 .0315 .0197

HQ160 1.258 1.110 .016 .0256

HQ208 1.258 1.110 .012 .0197

VQ100 .677 .535 .012 .0197

TQ144 .914 .772 .012 .0197

TQ176 1.071 .929 .012 .0197

HQ240 1.386 1.244 .012 .0197

HQ304 1.702 1.560 .012 .0197

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 25 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Rev: 6 Date: 5/15/01

JEDEC MO-150

Plastic Shrink Small Outline package (SSOP) 5.3 mm body width .65mm pitch. 5.3 mm/ .209 ”

.65 mm / .0255”

 .38 mm/ ” .015”

7.8 mm / .308”

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 26 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines Rev: 6 Date: 5/15/01

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Land pattern recommended  5.08mm / .200”

.65 mm / .0255”

 .40 mm/ ” .016”

9.09 mm/ .358”

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 27 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Rev: 6 Date: 5/15/01

MO-118 Plastic Shrink Small Outline package ; 48, 56 leads; body width 7.6 mm; .635 pitch. 7.6 mm / .299”

.635 mm / .025”

 .3mm/.012”

10.67 mm/ .420”

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 28 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Rev: 6 Date: 5/15/01

Land pattern recommended 7.2mm/ .284”

.635 mm / .025”

 .40 mm/ ” .016”

 11.94mm/ 470”

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 29 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines Rev: 6 Date: 5/15/01

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

Land pattern recommended:

.050” typical

.020” - .025” typical

  .375”

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SUPPLEMENT 2 – Designing for BGA’s

Designing boards for BGAs Most BGA packages use Solder mask Defined pads on the package side of the solder ball. PCB pad size is typically close to or identical to the package pad size. This provides for balanced stress during thermal cycling, which helps to maximize fatigue life.

1-Solder Mask Defined (SMD) Pad In the Solder Mask Defined (SMD) pad, the copper for the pad area is larger than the desired land size. The opening in the solder mask is made Smaller than the copper land, thus defining the mounting pad. A couple of points to consider with solder mask defined pad are: • There is an advantage in that overlap of solder mask onto copper enhances the copper adhesion to laminate surface. When using resin systems where adhesion is low, this is an important consideration. • One disadvantage of SMD pads is that the fatigue life has show to be lower the NSMD pads through long term reliability testing. Because this issue, the solder mask angle at the pad edge has been thinned on many new package designs to minimize the mask impingement on the solder ball.

2- Non-Solder Mask Defined (Non-SMD) Pad The Non-Solder mask (sometimes called metal or copper) defined pad, has a solder mask opening larger  than copper area. Pad size is controlled by the copper etch quality control. This is generally less accurate than the solder mask photo image control. Non-Solder Mask pad size varies more than with the SMD pad. However, because the edge of the copper do not need extent under solder mask, the pad can be either made larger, or provided more line routing space between pads. Pattern registration is also as accurate as the copper artwork, which is generally much more accurate than solder mask pattern. Vision registration on copper fiducials will give exact location of the site. With SMD pads, the mis-registration error of the solder mask will also shift the location of the entire site relative to vision fiducials.

3- BGA Package Considerations The following subsection addresses the BGA package layout and includes guidelines for pad size, vias and routing. It important to implement a keep-out zone around BGAs for rework purposes. The keep-out zone distance is determined by the type of rework equipment to be used.

4- Routing and pad size Many perimeter style BGA packages typically contain four or five rows of solder balls; as such, it is possible to route one or two traces between pads to route signals in a four layer board.

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• •

•

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

When routing one trace between pads, the manufacturers preferred line width and spacing technology become a limiting factor. When routing two traces between pads, 5 mil traces and 5mil spaces are required for 24 mil pad size. For a 20-mil pad size, 6 mil traces and 6-mil spacing can be used. Either pad size is acceptable, so the decision is primarily determined by the manufacturers preferred line width and spacing technology. When larger trace widths are desired, another alternative is to route 5/5 or 6/6 (mil space/mil trace) within the BGA pads, and then neck up to the larger trace widths once you have cleared the BGA component.

4- Plated Through Hole (PTH) Isolation Regardless of the technique used for the mounting pads shape or definition, isolation of the plated through hole (PTH) from the mounting pad is important. If the PTH is contained within the mounting pad, solder will wick down the PTH. The amount of solder that wicks depends on many factors, including PTH finish and coating variations. Because of this, the results are somewhat unpredictable. Some solder joints may be unaffected, while others will be starved joints with severely reduced cross section. This joint can have significantly lower fatigue life and result in early system failure. Because the quality of the solder joint guaranteed by control rather than inspection, designs/process that result random distributions are generally considered unacceptable, and the  PTH in pad is not suggested All vias located between the BGA ball pads must be covered with solder mask . The bottom side can also be covered.

5- PCB Quality and Co-planarity The assembly yields of mounting BGA components is influenced by PCB properties and process control procedures followed by manufacturer of PCB. PCB co-planarity requirements are directly related to the package size. Typical PCB manufacturing specifications allow up to 0.01mm (1%) of warpage. For 35mm component, this would equate to nearly 0.35mm of warpage in the area under the package footprint. It is obvious that no large body (>20mm) component, peripheral leaded or BGA, would consistently solder to a site with this amount of bow. Most responsible PCB vendors take precautions to be well below the 0.010mm specification that is recommended in the industry standard specifications.

6- Solder Paste Deposit Inspection. The quality of solder paste print is the single most important factor in producing high yield BGA assemblies. Defects defected after paste print require a strip and re-screen of the PCB. Any deviation can turn into a defect downstream requiring rework and repair. Thus the most economic area to intensify process controls when beginning BGA assembly is in the paste-screening step. Excessive volume of paste will have some negative effects on the self-centering properties of the BGA and could cause yield or reliability issues (shorts or bridges). However, adequate paste thickness is required to compensate for board warp, poor component co-planarity, and to achieve acceptable board reliability. Another factor in yield or reliability is the presence of adequate flux. Any situation, such as a plugged stencil hole, that causes flux or paste to be omitted or severely limited on a pad can lead to an open connection after reflow. Print mis-registration or excessive slumping that connects adjacent conductors (either pads or PTH) is also a source of concern, as a short may be final result. Therefore, it is _____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 32 of 42

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usually beneficial to perform a paste inspection step, especially during early manufacturing runs. Whether to use visual/microscope inspection, manual measurement, or invest in an automated system depends on the volume to be run and the overall manufacturing philosophy.

7- Solder Stencil The stencil thickness, as well as the etched pattern geometry, determines the precise volume of solder alloy deposit onto the device land pattern. Stencil alignment accuracy and consistent solder volume transfer is critical for uniform reflow-solder processing. Stencils are made of brass or stainless steel, with stainless steel being more durable. Hole designs are dependent on the solder ball size, squeegee type, board lay out and the paste used. There appears to be no single hole style that is used by everyone. There are companies that are using square, diamond, round and oval shaped holes.  Round holes are definitely the dominant design. Many companies are promoting a stencil with a rounded corner, square hole with 5 ° tapered opening has been shown to be a good hole design to use BGAs 20 mil or smaller solder balls. Thickness of stencils are usually in the 6 to 8 mil (.15 to .20mm) range. A squeegee durometer of 95 or harder should be used. The blade angle and speed must be fine-tuned to ensure even paste transfer. Ensuring proper stencil application is the most important factor with regards to reflow yields further on in the process. The paste materials tend to dry out when not properly environmentally controlled. It is also beneficial to use an opening at least as large as the mounting pad to give a wide placement window. A typical design might be a 0.028 opening in a .006 thick stencil, going over a .024 pad on the PCB with 30 mil solder balls. The printing of small amounts of paste onto solder mask surrounding the pad had not proven to be a problem in either yield or reliability.

8- Alignment The pick and place accuracy governs the package placement and rotational alignment. Slightly misaligned parts (less than 50% off the pad) typically automatically self-align during reflow> Self centering on the pads is greatly reduced for grossly misaligned packages (greater than 50% off the pads) and may develop electrical shorts, as a result of solder bridges, if they are subjected to reflow.

9- Outline for Machine Placement Variability of the body dimension specification is .10mm ( ∼4mils) worst case. The same data indicates that the ball location variability is .075mm ( ∼3mils) worst case. The impact on alignment during the placement process is: • If the package edge is used to determine the true center of the component, alignment of the balls is within .075mm of true position. • If only the package edge is used, alignment of the balls is within .10mm + .075mm (.175mm ∼6mils) of true position. Give that the allowable misalignment of the balls is 50% or less of the pad width, a manufacturable process can be achieved using only the package edge (outline) and alignment marks on the stencil for machine placement _____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 33 of 42

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10- Solder Reflow Except for semi-accurate placement of packages, there is no special requirements necessary when refolding BGA components. As with all SMT components, it is important that profiles be checked on all new board designs. In addition, if there are multiple PBGA on the board. Component temperatures may vary because of nearby surrounding components, location of the part on the board and areas of package densities. Temperatures may also be different at the edge of the package than in the center. When doing second pass wave solder of mixed technology components on the same board as BGAs insure that the solder wave profile is very tightly controlled.  A high temperature on the wave solder   process can warp the board and break the joints on the topside of the BGA component 

11- PBGA Example SMT Reflow Zone Preheat

Characteristic Description Initial heating of lead/component Peak temperature

Pre-Reflow

Dry-out and solder paste activation Soak time Time above 183°C Peak component body Temperature Cooling rate

Reflow

Cool Down

Window/Limits 1 - 3° C/Second 100 - 140° C 120 - 170° C 120 Seconds 45 - 120 Seconds 205 - 225°C 220°C Maximum 2 - 3°C/Second

12- SMT Process Many factor contribute to a high yielding BGA assembly process. A few of the key focus areas and their contributing factors are highlighted • Essentials for Assembly Quality Uniform viscosity and texture. Free from foreign material. Solder paste Solder Paste Quality should be used before the expiration date. Shipment and storage temperatures are maintained at the proper temperature. Paste is protected from drying out on the solder stencil. Clean, flat, well-plated solder ball land area. Good solder mask coverage. Mother Board Quality Tight tolerances are not usually required. The BGA can self center itself  Placement Accuracy as long as a major portion (less than 50%) of the solder ball is in contact with the fluxed solder paste land area on the board . Alignment marks (targets) on the PCB are helpful for placing parts. Know your components moisture sensitivity classification and adhere to Moisture Sensitivity Precaution IPC/JEDEC moisture control conditions or package delamination or cracking may occur. _____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 34 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines Rev: 6 Date: 5/15/01

INSERVCO, INC. P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050

13- Underfill The primary reason for underfill adhesive is to reduce the impact of mismatches in global thermal expansion characteristics between the silicon die and underlying substrate. In more traditional chip on board designs, these differences in coefficient of thermal expansion (CTE) are absorbed by the bond wires and the die-attach adhesive. In direct attach designs, like flip chip, the stress are concentrated on the solder balls. Because the ball-array solder joints represent the weakest points in the die-attach structure, they are inherently susceptible to failures during thermal expansion, which can result in functional failures of the assembly. The use underfill adhesive can greatly reduce the incidence of such failures by simultaneously adhering to the chip, solder balls and subtrate, thereby redistributing the thermal expansion tresses over the entire chip area. By underfill the area between the chip and subtrate, the direct stresses on the solder bump interconnects can be reduced significantly. Secondary benefits from using underfill include increased mechanical stiffness to protect against externally induced stress and strains such as flexing sharp impacts on the finished assembly. In addition, voidless underfill encapsulation can provide added protection against moisture or other contaminants and make assemblies easier to handle. Thus far, underfill dispensing technologies have involved to provide solid process capabilities for a variety of interconnect strategies, such as flip-chip and chip-scale packaging (CSP)

Designing boards for CSPs In most cases, CSPs use the same PCB design and assembly processes as BGA packages. 1- PCB design guidelines for .75mm µBGA, easy BGA and Stacked-CSP Feature .8mm Stacked CSP 1.0mm Easy BGA .75mm µBGA CSP Land pad size .30 (0.012) .30 (0.012) .30 (0.012) Solder mask opening .431 (0.018) .431 (0.018) .431 (0.018) Metal to mask clearance (min) .050 (.002) .050 (.002) .050 (.002) Max trace width .127 (.005) .127 (.005) .233 (.009) Typical spaces .160 (.00625) .187 (.0073) .233 (.009) Max Via capture pad .51 (.020) .51 (.020) .711 (.028) Max via drill size .25 (.010) .25 (.010) .457 (.018) Note: All dimensions in mm (Inches)

2- PCB design guidelines for .5mm pitch µBGA Feature Land pad size Solder mask opening Typical trace width

.5mm µBGA CSP .279 (.011) .356 (.014) .1016 (.004)

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Reduce trace width between land pads Typical micro via (Via-in-Pad) size Note: All dimensions in mm (inches)

.0737 (.0029) .1016 (.004)

3- Solder Stencil design for µBGA, easy BGA and Stacked-CSP Feature

.5mm µBGA CSP

Top of stencil .279 (.011) aperture Bottom of stencil .30 (.012) aperture Stencil Thickness .127 (.005) Note: All dimensions in mm (inches)

.75mm µBGA CSP

.8mm Stacked CSP

1.0mm Easy BGA

.33 (.013)

.33 (.013)

.33 (.013)

.356 (.014)

.356 (.014)

.356 (.014)

.127 (.005)

.127 (.005)

.127 (.005)

4- PBGA/HL-PBGA Example SMT reflow Zones Characteristic Description Preheat Initial heating of lead/component peak temperature

Pre-Reflow Reflow

Cool Down

Dry out and solder paste activation soak time Time above 183° C Peak component body Temperature Cooling rate

Windows/Limits 1-3° C/second 100-140° C 120 - 170° C 120 seconds 45 - 120 Seconds 205 - 225° C 220° C Maximum 2 - 3° C/Second

5- Essentials for Assembly quality Solder paste quality Uniform viscosity and texture. Free from foreign material. Solder paste should be used before the expiration date. Shipment and storage temperatures are maintained at the proper temperature. Paste is protected from frying out on the solder stencil. Motherboard quality Clean, flat, well-plated solder ball land area. Good solder mask coverage. Placement Accuracy Tight tolerances are not usually required. The BGA can self-center itself as long as a major portion (more than 50%) of the solder ball is contact with fluxed solder paste land area on the board. Alignment marks (targets) on the PCB are helpful for placing parts. Moisture Sensitivity Precautions Know your components moisture sensitivity classification and adhere to IPC/JEDEC moisture control conditions or package delamination or cracking may occur.

_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 36 of 42

  Released TEP-005 - Design for Manufacturability/ Testability Guidelines

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Rev: 6 Date: 5/15/01

6- Moisture Sensitivity Levels Level

1 2 2a 3 4 5 5a 6

Floor Life   Time

Floor Life   Conditions

Unlimited One Year Four Weeks 168 Hours 72 Hours 48 Hours 24 Hours Time On Label

≤30°C/85% RH ≤30°C/60% RH ≤30°C/60% RH ≤30°C/60% RH ≤30°C/60% RH ≤30°C/60% RH ≤30°C/60% RH ≤30°C/60% RH

SOAK REQUIREMENTS Standard Standard Accelerated   Time Conditions Equivalent  Time (Hours) 168 85°C/85% RH 168 85°C/60% RH 696 120 30°C/60% RH 192 40 30°C/60% RH 96 20 30°C/60% RH 72 15 30°C/60% RH 48 10 30°C/60% RH TOL 30°C/60% RH

Accelerated Equivalent  Conditions

60°C/60% RH 60°C/60% RH 60°C/60% RH 60°C/60% RH 60°C/60% RH

7- Reference Conditions for Drying Components That were Exposed to Conditions ≤60% RH Package Thickness Level Bake @ 125°C Bake @ 40°C ≤5% RH 2a 4 hours 5 days 3 7 hours 11 days 4 9 hours 13 days ≤1.4 mm 5 10 hours 14 days 5a 14 hours 19 days

≤2.0 mm

2a 3 4 5 5a

18 hours 24 hours 31 hours 37 hours 48 hours

21 days 33 days 43 days 52 days 68 days

≤4.0 mm

2a 3 4 5 5a

48 hours 48 hours 48 hours 48 hours 48 hours

67 days 67 days 68 days 68 days 68 days

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8- Default Baking Times Used Prior to Dry-Pack That were Exposed to Conditions ≤60% RH Package Thickness Level Bake @ 125°C Bake @ 150°C 2a 8 hours 4 hours 3 16 hours 8 hours 4 21 hours 10 hours ≤1.4 mm 5 24 hours 12 hours 5a 28 hours 14 hours 2a 23 hours 11 hours 3 43 hours 21 hours 4 48 hours 24 hours ≤2.0 mm 5 48 hours 24 hours 5a 48 hours 24 hours 2a 48 hours 24 hours 3 48 hours 24 hours 4 48 hours 24 hours ≤4.0 mm 5 48 hours 24 hours 5a 48 hours 24 hours • Bake out times start when all components reach the specified temperature • Oxidation risk Baking components may cause solder oxidation and/ or intermetallic growth, which excessive can result in solderability problems during board assembly. The temperature and time for baking components are therefore limited by solderability considerations. Unless otherwise indicated by supplier, one bake cycle is allowable on finished component. If more than one bake cycle is needed, the supplier should be consulted.

9- Classification Reflow Profiles

Average ramp-up rate (183 °C to peak Preheat temperature 125 ( ±25)°C Temperature maintained above 183 °C Time within 5°C of actual peak temperature Peak temperature range Ram-down rate Time 25°C to peak temperature

Convection or IR/Convection 3°C/second max. 120 second max. 60-150 Seconds 10-20 Seconds 220 +5/-0°C or 235 +5/-0°C 6°C/second max. 6 minutes max.

VPR 10°C/second max.

60 seconds 215 - 219°C or 235 +5/-0°C 10°C/ second max.

Designing boards for Ultra-Chip-Scale Package Introduction to Ultra-Chip-Scale Package (UCSP) The packaging technology in the Ultra-Chip-Scale Package (UCSP) enables integrated circuit to be attached to the printed-circuit board face-down, with the chip’s pads connecting to the PC board’s pads through individual balls of solder. This technology differs from other ball grid array, leaded and chip_____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 38 of 42

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scale packages because there are no bond wires or interstitial laminates. The principle advantage of the UCSP is that IC-to-PC board inductance is minimized. Secondary benefits are reduction in package size and manufacturing cycle time and enhanced thermal conduction characteristics.

.010” corner bump to die edge (Typ.)

.0197”/0.5mm

6 X 6 UCSP

Printed-Circuit Board Layout Two types of land patterns are used for surface-mount packages: 1- Solder-Mask Defined (SMD). Pads have solder-mask openings smaller than metals pads. 2- Non-Solder-Mask Defined (NSMD). Metal pads are smaller than solder mask openings.

Pad

SMD

Solder Mask  

Pad

Solder Mask 

NSMD

Better control of the copper etch process, as compared to the solder-mask etch process in the SMD pad definition, makes NSMD preferable. The SMD pad definition introduces stress concentration near the solder-mask overlap region that result in the solder joints cracking under extreme fatigue conditions. Smaller pad size in the NSMD definition provides more room for escape routing on PCB. The NSMD design circular copper pad size should be .010” +2/-0 mils and solder mask openings should be .013” +2/-0 mils. The PCB layout assumes 0.1mm (.004”) trace width and 1oz copper layer thickness. Copper pads should be finished with organic solderability preservative coating (OPS). For electroplated nickel-immersion gold-finish pads, the gold thickness must be less than 0.5 micron to avoid making the solder joints brittle.

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SMT Process Flow Incoming UCSP tape and reel inspection Solder Paste Printing on Board Chip Placement on Board Solder ReflowFlux Cleaning X-Rays Inspection Under Fill UCSP Pack and Ship

Solder paste deposition using a stencil printing process involves pressurized application of solder paste through predefined apertures. Three general methods exist for stencil fabrication 1- Chemical etching. 2- Laser cutting 3- Nickel plate-up. While all three have advantages in stencil PCB component-attach manufacturing, not all are suitable for generating fine pitch (0.5mm) bump-attach stencils. Chemical etching cannot support the fine geometries and tolerances required for UCSP stencils and is not considered a viable process for producing them. For laser-cut stencils a thin stainless steel foil is held flat while the apertures are cut with high powered laser. The observed tight tolerances on aperture dimensions, combined with smooth sidewalls, makes laser cutting stencils a desirable and popular process. In the nickel plate-up process, the stencil is grown by plating nickel onto a mandrel through a patterned dry film resist. This process also produces smooth sidewalls with tight shape and size tolerances. However, this process requires patterning and plating equipment that may increase the cost of stencil manufacturing. The aperture design can be either square or round. In the case of square aperture openings the corners must have at least a 50 micron radius. Temperature cycling board aperture design from .010” +2/-0 mils in diameter. Stencil thickness was optimized to .005”. It is recommended to offset apertures from the copper pad to maximize separation between deposited solder paste to avoid bridging.

Component Placement. UCSPs can be picked up and placed using standard Pick & place equipment. Minimum requirements of a P&P system include a vision system to recognize and position the part and a mechanical system to perform P&P operations. The placement accuracy of the system is dependent on either its vision system that locates chip edges or on individual bump of the UCSP. Using the bump as the placement and orientation reference tends to be accurate but is expensive and time consuming.

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Both methods are acceptable because during solder reflow, the UCSP aligns due to the self-centering feature of the solder joints. The maximum placement offset allowable during assembly is +/- 0.150mm (.006”) in the X and Y directions.

Solder Paste Reflow and Cleaning. The following are recommended for high-reliability solder joints resulting from successful solder reflow: 1- Selection of a suitable solder paste. Type 3 or finer paste is preferred. 2- Optimized stencil aperture and thickness. 3- Temperature profiling optimization. A thermal profile at specific board locations must be determined. A combination of temperature, reflow oven conveyor speed and convection flow rate needs to be varied to perform the optimization. During reflow, eutectic solder bumps and paste on the PCB melt in the presence of flux to form a cohesive shiny solder joint. A problematic temperature profile or solder paste will result in “ solder balling” or semi-reflowed solder paste. 4- Nitrogen purge is recommended during solder relow. 5- Level of nitrogen is kept low in the reflow chamber at least below 100ppm. A meter incorporated in the furnace will monitor the oxygen level. UCSP packages must not exceed three reflow cycles (at +235 °C peak temperature). Flux cleaning is dependent on the type of flux used in the solder paste. Solder paste with active flux is not recommended due to corrosion issues. Solder Joint Inspection After surface-mount assembly, transmission X-rays can be used for sample monitoring of the solder attachment process to identify defects such as bridging, opens, shorts and voids. Why Underfill? The primary reason for considering the use of underfill encapsulant is to reduce the impact of mismatches in global thermal expansion characteristics between the silicon die and the underlying substrate to which it is attached. With conventional chip packaging, these stresses are typically absorbed by the natural flexibility of the wire leads. However, with direct-attach methods such as solder ball arrays, the solder  joints themselves represent the weakest points in the structure and therefore are the most susceptible to stress failures. Unfortunately, they are also the most critical because a failure at any interconnect point destroys the functionality of the circuit. By tightly adhering to the chip, solder balls and substrate, the underfill material redistributes the stresses and strains from the coefficient of thermal expansion (CTE) mismatch and mechanical shock over the entire chip area.

Secondary benefits from underfilling are protection against moisture and other forms of contamination. On the negative side, the use of underfill adds cost to the manufacturing operation and makes rework  difficult. Because of this, many manufacturers conduct a quick functional test after reflow and prior to the underfill operation. Deciding When to Underfill 1 Because there are more than 50 different designs of CSPs , plus a myriad of variables and operating conditions involved in interconnect design, it is difficult to provide a definitive rule-of-thumb for when to _____________________________________________________________________________________________ INSERVCO, INC, P.O. Box 106, 110 Commerce Drive, LaGrange, Ohio 44050 41 of 42