Advanced 8086 Microprocessor Trainer Nvis 5586A
Learning Material Ver 1.0
Designed & Manufactured by:
141-B, Electronic Complex, Pardesipura, Indore- 452 010 India, Tel.: 91-731- 4211500, Telefax: 91-731-4202959, Toll free: 1800-103-5050, E-mail:
[email protected] Website: www.nvistech.com
Nvis 5586A
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Advanced 8086 Microprocessor Trainer Nvis 5586A Table of Contents 1.
Introduction
4
2.
Technical Specifications
5
3.
Safety Instructions
6
4.
Theory
7
5.
Capabilities
34
6.
Hardware Description
35
7.
Command Description
36
8.
Memory Address & Port Address
65
9.
Subroutines
68
10.
Serial Communication
95
11.
MASM Macro Assembler
100
12.
Sample Programs
104
13.
On-Board Interface
163
14.
Parallel Communication between two Nvis 5586A Trainers using 8255 in I/O mode
168
15.
Serial Communication between two Nvis 5586A Trainers
169
16.
Connector Details
170
17.
Jumper/DIP switch Details
178
18.
Frequently Asked Questions
180
19.
Warranty
188
20.
List of Service Centers
189
21.
References
190
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Introduction General Description: Nvis 5586A is a single board microprocessor training/development kit configured around the Intel‘s 16 bit Microprocessor 8086. This kit can be used to train engineers, to control any industrial process and to develop software for 8086 systems. The kit has been designed to operate in the maximum mode. Co-processor 8087 and I/O Processor 8089 can be added on board. The kit communicates with the outside world through an IBM PC compatible Keyboard with 20x2 LCD Display. The kit also has the capacity of interacting with PC. Nvis 5586A is packed up with powerful monitor in 128K Bytes of factory programmed EPROMS and 32K Bytes of Read/Write Memory. The total memory on the board is 144K Bytes. The system has 72 programmable I/O lines. The serial I/O Communication is made possible through 8251. For control applications, three 16 bit Timer/Counters are available through 8253. For real time applications, the 8 level of interrupt are provided through 8259. Nvis 5586A provides onboard battery backup for onboard RAM. This saves the user‘s program in case of power failure. The onboard resident system monitor software is very powerful. It provides various software commands like BLOCK MOVE, SINGLE STEP, EXECUTE, FILL etc which are helpful in debugging/developing software. An onboard line assembler provides user to write program in assembling language.
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Technical Specifications Central Processor
:
8086, 16 bit Microprocessor operating in max. mode.
Co-Processor Support:
Support 8087 Numeric Data Processor.
I/O Processor Support:
Support 8089 I/O Processor.
EPROM
:
128K Bytes of EPROM Loaded with monitor program.
RAM
:
32K bytes of CMOS RAM with Battery Backup using 3.6V Ni-Cd Battery.
Parallel
:
72 I/O lines using three nos. of 8255.
Serial
:
RS-232-C Interface using 8251.
Interrupt
:
8 different level interrupt using 8259.
Timer/Counter
:
Three 16 bit Timer/Counter using 8253.
Keyboard & Display :
105 IBM PC Keyboard & 20x2 LCD Display.
BUS
:
All address, data and control signals (TTL Compatible) available at 50 Pin & 20 Pin FRC Connector.
Power Supply
:
5V/ 2 Amps, ±12V/250mA
Physical Size
:
32.6cm x 25.2cm
Operating Temp.
:
0 to 50°C.
Included Accessories 26 Pin FRC Cable
3 No
50 Pin FRC Cable
1 No
RS232 Cable
1 No
SMPS Supply
1 No
Jumpers
4 No
Phoenix Connector
1No
Keyboard
1No
Keyboard Adaptor
1No
20PinFRC Cable
1No
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Safety Instructions
Read the following safety instructions carefully before operating the instrument. To avoid any personal injury or damage to the instrument or any product connected to the instrument. Do not operate the instrument if suspect any damage to it. The instrument should be serviced by qualified personnel only.
For your safety: Use proper Mains cord
: Use only the mains cord designed for this instrument. Ensure that the mains cord is suitable for your country.
Ground the Instrument
: This instrument is grounded through the protective earth conductor of the mains cord. To avoid electric shock, the grounding conductor must be connected to the earth ground. Before making connections to the input terminals, ensure that the instrument is properly grounded..
Use in proper Atmosphere : Please refer to operating conditions given in the manual.
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Do not operate in wet / damp conditions.
2.
Do not operate in an explosive atmosphere.
3.
Keep the product dust free, clean and dry.
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Theory It is a 16 bit microprocessor. 8086 has a 20 bit address bus can access upto 220 memory locations (1 MB). It can support upto 64K I/O ports. It provides 14, 16-bit registers. It has multiplexed address and data bus AD0- AD15 and A16 – A19. It requires single phase clock with 33% duty cycle to provide internal timing. 8086 is designed to operate in two modes, Minimum and Maximum. It can prefetches upto 6 instruction bytes from memory and queues them in order to speed up instruction execution. It requires +5V power supply. It is a 40 pin dual in line package. Minimum and Maximum Modes: The minimum mode is selected by applying logic 1 to the MN / MX* input pin. This is a single microprocessor configuration. The maximum mode is selected by applying logic 0 to the MN / MX* input pin. This is a multi microprocessor configuration.
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Pin diagram of 8086
Internal Architecture of 8086 8086 has two blocks BIU and EU. The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue. EU executes Nvis Technologies Pvt. Ltd.
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instructions from the instruction system byte queue. Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance. BIU contains Instruction queue, Segment registers, Instruction pointer, and Address adder. EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register. Bus Interface Unit: It provides a full 16 bit bidirectional data bus and 20 bit address bus. The bus interface unit is responsible for performing all external bus operations. Specifically it has the following functions: Instruction fetching, Instruction queuing, Operand fetch and storage, Address relocation and Bus control. The BIU uses a mechanism known as an instruction stream queue to implement pipeline architecture. This queue permits prefetch of up to six bytes of instruction code. Whenever the queue of the BIU is not full, it has room for at least two more bytes and at the same time the EU is not requesting it to read or write operands from memory, the BIU is free to look ahead in the program by prefetching the next sequential instruction. These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU fetches two instruction bytes in a single memory cycle. After a byte is loaded at the input end of the queue, it automatically shifts up through the FIFO to the empty location nearest the output. The EU accesses the queue from the output end. It reads one instruction byte after the other from the output of the queue. If the queue is full and the EU is not requesting access to operand in memory, these intervals of no bus activity, which may occur between bus cycles, are known as idle state. If the BIU is already in the process of fetching an instruction when the EU request it to read or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before initiating the operand read / write cycle. The BIU also contains a dedicated adder which is used to generate the 20 bit physical address that is output on the address bus. This address is formed by adding an appended 16 bit segment address and a 16 bit offset address. For example, the physical address of the next instruction to be fetched is formed by combining the current contents of the code segment CS register and the current contents of the instruction pointer IP register. Nvis Technologies Pvt. Ltd.
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The BIU is also responsible for generating bus control signals such as those for memory read or write and I/O read or write. Execution Unit: The Execution unit is responsible for decoding and executing all instructions. The EU extracts instructions from the top of the queue in the BIU, decodes them, generates operands if necessary, passes them to the BIU and requests it to perform the read or write bys cycles to memory or I/O and perform the operation specified by the instruction on the operands. During the execution of the instruction, the EU tests the status and control flags and updates them based on the results of executing the instruction. If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top of the queue. When the EU executes a branch or jump instruction, it transfers control to a location corresponding to another set of sequential instructions. Whenever this happens, the BIU automatically resets the queue and then begins to fetch instructions from this new location to refill the queue.
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Minimum Mode Interface When the Minimum mode operation is selected, the 8086 provides all control signals needed to implement the memory and I/O interface. The minimum mode signal can be divided into the following basic groups: address/data bus, status, control, interrupt and DMA. Address/Data Bus: These lines serve two functions. As an address bus is 20 bits long and consists of signal lines A0 through A19. A19 represents the MSB and A0 represents the LSB. A 20-bit address gives the 8086 a 1Mbyte memory address space.
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More over it has an independent I/O address space which is 64K bytes in length. The 16 data bus lines D0 through D15 are actually multiplexed with address lines A0 through A15 respectively. By multiplexed we mean that the bus work as an address bus during first machine cycle and as a data bus during next machine cycles. D15 is the MSB and D0 is the LSB. When acting as a data bus, they carry read/write data for memory, input/output data for I/O devices, and interrupt type codes from an interrupt controller.
Status signal: The four most significant address lines A19 through A16 are also multiplexed but in this case with status signals S6 through S3. These status bits are output on the bus at the same time that data are transferred over the other bus lines. Bit S4 and S3 together from a 2 bit binary code that identifies which of the 8086 internal segment registers is used to generate the physical address that was output on the address bus during the current bus cycle. Code S4S3 = 00 identifies a register known as extra segment register as the source of the segment address. Memory Segment Status Codes
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Status line S5 reflects the status of another internal characteristic of the 8086. It is the logic level of the internal enable flag. The last status bit S6 is always at the logic 0 level. Control Signals: The control signals are provided to support the 8086 memory I/O interfaces. They control functions such as when the bus is to carry a valid address in which direction data are to be transferred over the bus, when valid write data are on the bus and when to put read data on the system bus. ALE is a pulse to logic 1 that signals external circuitry when a valid address word is on the bus. This address must be latched in external circuitry on the 1-to-0 edge of the pulse at ALE. Another control signal that is produced during the bus cycle is BHE i.e. bank high enable. Logic 0 on this used as a memory enable signal for the most significant byte half of the data bus D8 through D1. These lines also serve a second function, which is as the S7 status line. Using the M/IO* and DT/R* lines, the 8086 signals which type of bus cycle is in progress and in which direction data are to be transferred over the bus. The logic level of M/IO* tells external circuitry whether a memory or I/O transfer is taking place over the bus. Logic 1 at this output signals a memory operation and logic 0 an I/O operation. The direction of data transfer over the bus is signaled by the logic level output at DT/R*. When this line is logic 1 during the data transfer part of a bus cycle, the bus is in the transmit mode. Therefore, data are either written into memory or output to an I/O device. On the other hand, logic 0 at DT/R* signals that the bus is in the receive mode. This corresponds to reading data from memory or input of data from an input port. The signals read RD and write WR indicate that a read bus cycle or a write bus cycle is in progress. The 8086 switches WR to logic 0 to intimate external device about valid write or output data are on the bus. On the other hand, RD indicates that the 8086 is performing a read of data of the bus. During read operations, one other control signal is also supplied. This is DEN (data enable) and it signals external devices when they should put data on the bus. There is one other control signal that is involved with the memory and I/O interface. This is the READY signal. READY signal is used to insert wait states into the bus cycle such that it is extended by a number of clock periods. This signal is provided by an external clock generator device and can be supplied by
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the memory or I/O subsystem to signal the 8086 when they are ready to permit the data transfer to be completed. Interrupt signals: The key interrupt interface signals are interrupt request (INTR) and interrupt acknowledge (INTA). INTR is an input to the 8086 that can be used by an external device to signal that it needs to be serviced. Logic 1 at INTR represents an active interrupt request. When an interrupt request has been recognized by the 8086, it indicates this fact to external circuit with pulse to logic 0 at the INTA output. The TEST input is also related to the external interrupt interface. Execution of a WAIT instruction causes the 8086 to check the logic level at the TEST input. If the logic 1 is found, the MPU suspend operation and goes into the idle state. The 8086 no longer executes instructions; instead it repeatedly checks the logic level of the TEST input waiting for its transition back to logic 0. As TEST switches to 0, execution resume with the next instruction in the program. This feature can be used to synchronize the operation of the 8086 to an event in external hardware. There are two more inputs in the interrupt interface: the non-maskable interrupt NMI and the reset interrupt RESET. On the 0-to-1 transition of NMI control is passed to a non-maskable interrupt service routine. The RESET input is used to provide a hardware reset for the 8086. Switching RESET to logic 0 initializes the internal register of the 8086 and initiates a reset service routine. DMA Interface signals: The direct memory access DMA interface of the 8086 minimum mode consist of the HOLD and HLDA signals. When an external device wants to take control of the system bus, it signals to the 8086 by switching HOLD to the logic 1 level. At the completion of the current bus cycle, the 8086 enters the hold state. In the hold state, signal lines AD0 through AD15, A16/S3 through A19/S6, BHE, M/IO*, DT/R*, RD, WR, DEN and INTR are all in the high Z state. The 8086 signals external device that it is in this state by switching its HLDA output to logic 1 level. Maximum Mode Interface: When the 8086 is set for the maximum-mode configuration; it provides signals for implementing a multiprocessor / coprocessor system environment. By multiprocessor environment we mean that one microprocessor exists in the system and that each processor is executing its own program. Usually in this type of system environment, there are some system resources that are common to all processors. They are called as global resources. There are also other resources that are assigned to specific processors. These are known as local or private resources. Coprocessor also means that there is a second processor in the system. In this, both processors does not access the bus at the same time. One passes the control of the system bus to the other and then may suspend its operation. In the maximum-mode 8086 system, facilities are provided for implementing allocation of global resources and passing bus control to other microprocessor or coprocessor.
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8086 Maximum Mode Block Diagram
8288 Bus Controller – Bus Command and Control Signals: 8086 does not directly provide all the signals that are required to control the memory, I/O and interrupt interfaces. Specially the WR*, M/IO*, DT/R*, DEN, ALE and INTA, signals are no longer produced by the 8086. Instead it outputs three status signals S0*, S1*, S2* prior to the initiation of each bus cycle. This 3- bit bus status code identifies which type of bus cycle is to follow. S2*S1*S0* are input to the external bus controller device, the bus controller generates the appropriately timed command and control signals. The 8288 chip receive the status signal S2*, S1* and S0* and the clock from 8086. Theses status signals are decoded to generate MRDC* (Memory read command), MWTC* (memory write command), IORC* (I/O read command), IOWC* (I/O write command), INTA* (Interrupt acknowledgement) signal. In addition, it can generate advanced memory and I/O write signals AMWC* (Advanced memory write command), AIOWC* (Advanced I/O write command) that are enabled one clock cycle earlier than the normal write control signals because some device require wider cycle.
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MRDC* MWTC* IORC* IOWC* INTA* AMWC* AIOWC* CEN IOB MCE/PDEN*
Memory ReaD Command Memory WriTe Command Input/Output Read Command Input/Output Write Command INTerrupt Acknowledge Advanced Memory Write Command Advanced Input/Output Write Command Command Enable Input/output Bus only Master Cascade/Peripheral Data Enable
The 8288 also can generate bus control signals DEN, DT/R*, ALE, MCE/ (PDEN)* i.e. Master Cascade/Peripheral Data Enable. The function of the 1 st three signals are the same as those in the minimum mode. The signal MCE/ (PDEN)* has 2-functions depending on the mode in which 8288 is operating. The 8288 can either operate in I/O bus mode or system bus mode. When CEN (command enable) and IOB (I/O bus) input pin are wired high, the 8288 operate in I/O bus mode. In this mode, the signal PDNE* functions in the same way as DEN but it is active only during I/O instruction. This facility enables 8288 to control 2 set of buses: System bus and I/O bus separately With AEN* (Address enable) and CEN inputs low, the 8288 functions in system bus mode. When multiple processors are sharing the same bus, active processors can be selected by
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enabling the corresponding 8288 via AEN* input. In this mode, the signal MCE (Master cascade enable) is used for selecting the appropriate interrupt controller. Bus Status Codes:
The 8288 produces one or two of these eight command signals for each bus cycles. For instance, when the 8086 outputs the code S2*S1*S0* equals 001; it indicates that an I/O read cycle is to be performed. In the code 111 is output by the 8086, it is signaling that no bus activity is to take place. The control outputs produced by the 8288 are DEN, DT/R* and ALE. These 3 signals provide the same functions as those described for the minimum system mode. This set of bus commands and control signals is compatible with the Multibus and industry standard for interfacing microprocessor systems. Queue Status Signals: Two new signals that are produced by the 8086 in the maximummode system are queue status outputs QS0 and QS1. Together they form a 2-bit queue status code, QS1QS0. Following table shows the four different queue status.
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Local Bus Control Signal: Request / Grant Signals: In a maximum mode configuration, the minimum mode HOLD, HLDA interface is also changed. These two are replaced by request/grant lines RQ/ GT0 and RQ/ GT1, respectively. They provide a prioritized bus access mechanism for accessing the local bus. Minimum Mode 8086 System In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its MN/MX* pin to logic 1. In this mode, all the control signals are given out by the microprocessor chip itself. There is a single microprocessor in the minimum mode system. The remaining components in the system are latches, transreceiver, clock generator, memory and I/O devices. Some type of chip selection logic may be required for selecting memory or I/O devices, depending upon the address map of the system. Latches are generally buffered output D-type flip-flops like 74LS373 or 8282. They are used for separating the valid address from the multiplexed address/data signals and are controlled by the ALE signal generated by 8086. Transreceiver are the bidirectional buffers and sometimes they are called as data amplifiers. They are required to separate the valid data from the time multiplexed address/data signals. They are controlled by two signals namely, DEN and DT/R*. The DEN signal indicates the direction of data, i.e. from or to the processor. The system contains memory for the monitor and users program storage. Usually, EPROM is used for monitor storage, while RAM for user‘s program storage. A system may contain I/O devices. The clock generator generates the clock from the crystal oscillator and then shapes it and divides to make it more precise so that it can be used as an accurate timing reference for the system. The clock generator also synchronizes some external signal with the system clock. It has 20 address lines and 16 data lines; the 8086 CPU requires three octal address latches and two octal data buffers for the complete address and data separation. The working of the minimum mode configuration system can be better described in terms of the timing diagrams rather than qualitatively describing the operations. The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized in two parts, the first is the timing diagram for read cycle and the second is the timing diagram for write cycle. The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and also M/IO* signal. During the negative going edge of this signal, the valid address is latched on the local bus. The BHE and A0 signals address low, high or both bytes. From T1 to T4, the M/IO* signal indicates a memory or I/O operation. At T2, the address is removed from the local bus and is sent to the output. The bus is then tristated. The read (RD)* control signal is also activated in T2. The read (RD)* signal causes the address device to enable its data bus drivers. After RD* goes low, the valid data is available on the data bus. The addressed device will drive the READY line high. When the processor returns the read signal to high level, the addressed device will again tristate its bus drivers.
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Read Cycle Timing Diagram for Minimum Mode A write cycle also begins with the assertion of ALE and the emission of the address. The M/IO* signal is again asserted to indicate a memory or I/O operation. In T2, after sending the address in T1, the processor sends the data to be written to the addressed location. The data remains on the bus until middle of T4 state. The WR* becomes active at the beginning of T2 (unlike RD* is somewhat delayed in T2 to provide time for floating). The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O word to be read or write. The M/IO*, RD* and WR* signals indicate the type of data transfer as specified in table below.
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Write Cycle Timing Diagram for Minimum Mode Hold Response sequence: The HOLD pin is checked at leading edge of each clock pulse. If it is received active by the processor before T4 of the previous cycle or during T1 state of the current cycle, the CPU activates HLDA in the next clock cycle and for succeeding bus cycles, the bus will be given to another requesting master. The control of the bus is not regained by the processor until the requesting master does not drop the HOLD pin low. When the request is dropped by the requesting master, the HLDA is dropped by the processor at the trailing edge of the next clock.
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Bus Request and Bus Grant Timings in Minimum Mode System Maximum Mode 8086 System In the maximum mode, the 8086 is operated by strapping the MN/MX* pin to ground. In this mode, the processor derives the status signal S2*, S1*, S0*. Another chip called bus controller derives the control signal using this status information. In the maximum mode, there may be more than one microprocessor in the system configuration. The components in the system are same as in the minimum mode system. The basic function of the bus controller chip IC8288, is to derive control signals like RD* and WR* (for memory and I/O devices), DEN, DT/R*, ALE etc. using the information by the processor on the status lines. The bus controller chip has input lines S2*, S1*, S0* and CLK. These inputs to 8288 are driven by CPU. It derives the outputs ALE, DEN, DT/R*, MRDC*, MWTC*, AMWC*, IORC*, IOWC* and AIOWC*. The AEN, IOB and CEN pins are specially useful for multiprocessor systems. AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The significance of the MCE/PDEN* output depends upon the status of the IOB pin. If IOB is grounded, it acts as master cascade enable to control cascade 8259A, else it acts as peripheral data enable used in the multiple bus configurations. INTA* pin used to issue two interrupt acknowledge pulses to the interrupt controller or to an interrupting device. IORC*, IOWC* are I/O read command and I/O write command signals respectively. These signals enable an IO interface to read or write the data from or to the address port. The MRDC*, MWTC* are memory read command and memory write command signals respectively and may be used as memory read or write signals. All these command signals instructs the memory to accept or send data from or to the bus. For both of these write command signals, the advanced signals namely AIOWC* and AMWC* are available. They also serve the same purpose, but are activated one clock cycle earlier than the IOWC* and MWTC* signals respectively. The maximum mode system timing diagrams are divided in two portions as read (input) and write (output) timing diagrams. The address/data and address/status timings are similar to the minimum mode. ALE is asserted in T1, just like minimum mode. The only difference lies in the status signal used and the available control and advanced command signals.
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Maximum Mode 8086 System Here the only difference between in timing diagram between minimum mode and maximum mode is the status signals used and the available control and advanced command signals. R0, S1*, S2* are set at the beginning of bus cycle. 8288 bus controller will output a pulse as on the ALE and apply a required signal to its DT / R* pin during T1. In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will activate MRDC* or IORC*. These signals are activated until T4. For an output, the AMWC* or AIOWC* is activated from T2 to T4 and MWTC* or IOWC* is activated from T3 to T4. The status bit S0* to S2* remains active until T3 and become passive during T3 and T4. If reader input is not activated before T3, wait state will be inserted between T3 and T4.
Timings for RQ/ GT* Signals: The request/grant response sequence contains a series of three pulses. The request/grant pins are checked at each rising pulse of clock input. When a request is detected and if the conditions for HOLD request are satisfied, the processor issues a grant pulse over the RQ/GT* pin immediately during T4 (current) or T1 (next) state. When the requesting master receives this pulse, it accepts the control of the bus; it sends a release pulse to the processor using RQ/GT* pin.
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Memory Read Timing in Maximum Mode
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Memory Write Timing in Maximum Mode
8086 CPU Registers The 8086 has four groups of the user accessible internal registers. They are the instruction pointer, four data registers, four pointer and index register, four segment registers. The 8086 has a total of fourteen 16-bit registers including a 16 bit register called the status register, with 9 of bits implemented for status and control flags. Most of the registers contain data/instruction offsets within 64 KB memory segment. There are four different 64 KB segments for instructions, stack, data and extra data. To specify where in 1 MB of processor memory these 4 segments are located the processor uses four segment registers:
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Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions. Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register can be changed directly using POP instruction. Data segment (DS) is a 16-bit register containing address of 64KB segment with program data. By default, the processor assumes that all data referenced by general registers (AX, BX, CX and DX) and index register (SI, DI) is located in the data segment. DS register can be changed directly using POP and LDS (Load pointer using data segment) instructions. Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with program data. By default, the processor assumes that the DI register references the ES segment in string manipulation instructions. ES register can be changed directly using POP and LES (Load pointer using extra segment) instructions. It is possible to change default segments used by general and index registers by prefixing instructions with a CS, SS, DS or ES prefix.
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All general registers of the 8086 microprocessor can be used for arithmetic and logic operations. The general registers are: Nvis Technologies Pvt. Ltd.
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Accumulator register consists of two 8-bit registers AL and AH, which can be combined together and used as a 16- bit register AX. AL in this case contains the low-order byte of the word, and AH contains the high-order byte. Accumulator can be used for I/O operations and string manipulation. Base register consists of two 8-bit registers BL and BH, which can be combined together and used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains the high-order byte. BX register usually contains a data pointer used for based, based indexed or register indirect addressing. Count register consists of two 8-bit registers CL and CH, which can be combined together and used as a 16-bit register CX. When combined, CL register contains the low-order byte of the word, and CH contains the high-order byte. Count register can be used in Loop, shift/rotate instructions and as a counter in string manipulation. Data register consists of two 8-bit registers DL and DH, which can be combined together and used as a 16-bitregister DX. When combined, DL register contains the low-order byte of the word, and DH contains the high order byte. Data register can be used as a port number in I/O operations. In integer 32-bit multiply and divide instruction the DX register contains highorder word of the initial or resulting number. The following registers are both general and index registers: Stack Pointer (SP) is a 16-bit register pointing to program stack. Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for based, based indexed or register indirect addressing. Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data address in string manipulation instructions. Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions. Other registers: • Instruction Pointer (IP) is a 16-bit register. • Flags are a 16-bit register containing 9 one bit flags.
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• Overflow Flag (OF): set if the result is too large positive number, or is too small negative number to fit into destination operand. • Direction Flag (DF): If set then string manipulation instructions will auto-decrement index register. If cleared then the index registers will be auto-incremented. • Interrupt-enable Flag (IF): Setting this bit enables maskable interrupts. • Single-step Trap Flag (TF): If set then single-step interrupt will occur after the next instruction. • Sign Flag (SF): Set if the most significant bit of the result is set. • Zero Flag (ZF): Set if the result is zero. •Auxiliary carry Flag (AF): Set if there was a carry from or borrow to bits 0-3 in the AL register. • Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result is even. • Carry Flag (CF) - set if there was a carry from or borrows to the most significant bit during last result calculation. • Auxiliary carry Flag (AF) - set if there was a carry from or borrows to bits 0-3 in the AL register. • Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result is even. • Carry Flag (CF) - set if there was a carry from or borrows to the most significant bit during last result calculation.
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The 8086 Addressing Modes Addressing mode indicates a way of locating data or operands. The addressing modes describe the types of operands and the way they are accessed for executing an instruction. 1. Immediate Addressing Mode: In this addressing mode, the data is provided in the instruction. Example: MOV AX, 0006H 2. Direct Addressing Mode: In this addressing mode, the instruction operand specifies the memory address where data is located. Example: MOV AX, [7000H] 3. Register Addressing Mode: In this addressing mode, the data is stored in a register and it is referred using the particular register. All the registers, except IP, may be used in this mode. Example: MOV BX, AX 4. Register indirect Addressing Mode: In this addressing mode, the offset address of data is in either BX or SI or DI registers. The default segment is either DS or ES. Example: MOV AX, [BX] Here data is present in a memory location in DS whose offset address is in BX. 5. Register Relative Addressing Mode: In this addressing mode, the data is available at an effective address formed by adding an 8-bit or 16-bit displacement with the content of any one of the registers BX, BP, SI and DI in the default (either DS or ES) segment. Example: MOV AX, 50H [BX] 6. Indexed Addressing Mode: In this addressing mode, the offset of the operand is stored in one of the index registers. DS and ES are the default segments for index registers SI and DI respectively. 8-bit or 16-bit instruction operand is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides. Example: MOV AX, [SI] 7. Based Indexed Addressing Mode: In this addressing mode, the effective address of data is formed by adding content of a base register (any one of BX or BP) to the content of an index register (any one of SI or DI), the resulting value is a pointer to location where data resides. The default segment register may be ES or DS. Example: MOV AX, [BX] [SI] 8. Relative Based Indexed Addressing Mode: The effective address is formed by adding an 8-bit or 16-bit displacement with the sum of to the contents of a base register (BX or BP) and index register (SI or DI), in a default segment. Example: MOV AX, 50 [BX] [SI] In Nvis 5586A Register relative, Based indexed and Relative based indexed addressing modes are only supported by entering opcode. Nvis Technologies Pvt. Ltd.
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Instruction Set of 8086: 1. Data Copy/ Transfer Instructions: This type of instructions is used to transfer data from source operand to destination operand. All the store, move, load, exchange, input and output instructions belong to this category. 2. Arithmetic and Logical Instructions: All the instructions performing arithmetic, logical, increment, decrement, compare and scan instructions belong to this category. 3. Branch Instructions: These instructions transfer control of execution to the specified address. All the call, jump, interrupt and return instructions belong to this class. 4. Loop Instructions: If these instructions have REP prefix with CX used as count register, they can be used to implement unconditional and conditional loops. The LOOP, LOOPNZ and LOOPZ instructions belong to this category. These are useful to implement different loop structures. 5. Machine Control Instructions: These instructions control the machine status. NOP, HLT, WAIT and LOCK instructions belong to this class. 6. Flag Manipulation Instructions: All the instructions which directly affect the flag register, come under this group of instructions. Instructions like CLD, SYD, CLI, STI etc. belong to this category of instructions. 7. Shift and Rotate Instructions: These instructions involve the bitwise shifting or rotation in either direction with or without a count in CX. 8. String Instructions: These instructions involve various string manipulation operations like load, move, scan, compare, store etc. These instructions are only to be operated upon the strings.
Memory Program, data and stack memories occupy the same memory space. As the most of the processor instructions use 16-bit pointers, the processor can effectively address only 64 KB of memory. • To access memory outside of 64 KB the CPU uses special segment registers to specify where the code, stack and data 64 KB segments are positioned within 1 MB of memory. • 16-bit pointers and data are stored as: Address: low-order byte Nvis Technologies Pvt. Ltd.
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Address+1: high-order byte • 32-bit addresses are stored in "segment: offset" format as: Address: low-order byte of segment Address+1: high-order byte of segment Address+2: low-order byte of offset Address+3: high-order byte of offset • Physical memory address pointed by segment: offset pair is calculated as: Address = ( * 16) + Program memory: Program can be located anywhere in memory. Jump and call instructions can be used for short jumps within currently selected 64 KB code segment, as well as for far jumps anywhere within 1 MB of memory. All conditional jump instructions can be used to jump within approximately +127 to -127 bytes from current instruction. Data memory: The processor can access data in any one out of 4 available segments, which limits the size of accessible memory to 256 KB (if all four segments point to different 64 KB blocks). Accessing data from the Data, Code, Stack or Extra segments can be usually done by prefixing instructions with the DS:, CS:, SS: or ES: (some registers and instructions by default may use the ES or SS segments instead of DS segment).Word data can be located at odd or even byte boundaries. The processor uses two memory accesses to read 16-bit word located at odd byte boundaries. Reading word data from even byte boundaries requires only one memory access. Stack memory can be placed anywhere in memory. The stack can be located at odd memory addresses, but it is not recommended for performance reasons. Reserved locations: • 0000H - 03FFH are reserved for interrupt vectors. Each interrupt vector is a 32-bit pointer in format segment: offset. • FFFF0H - FFFFFH - after RESET the processor always starts program execution at the FFFF0H address. Interrupts The dictionary meaning of the word ‗interrupt‘ is to break the sequence of operation. While the CPU is executing a program, an ‗interrupt‘ breaks the normal sequence of execution of instructions, diverts its execution to some other program called Interrupt Service Routine (ISR). After executing ISR, the control is transferred back again to the main program which was being executed at the time of interruption.
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Whenever a number of devices interrupt a CPU at a time, and if the processor is able to handle them properly, it is said to have multiple interrupt processing capability. In 8086s, there are two interrupt pins, NMI and INTR. The NMI is a non maskable interrupt input pin which means that any interrupt request at NMI input cannot be masked or disabled by any means. The INTR is of 256 types. The INTR types may be from 00 to FFH. If more than one type of INTR interrupt occurs at a time, then an external chip called Programmable interrupt controller is required to handle them. Interrupt Service Routines (ISRs) are the programs to be executed by interrupting the main program execution of the CPU, after an interrupt request appears. After the execution of ISR, the main program continues its execution further from the point at which it was interrupted. Broadly there are two types of interrupt in the 8086 microprocessor. The first out of them is external interrupt and second is internal interrupt. In external interrupt, an external device or a signal interrupts the processor from outside or, in other words, the interrupt is generated outside the processor, for example, a keyboard interrupt. The internal interrupt, on the other hand, is generated internally by the processor circuit, or by the execution of an interrupt instruction. The examples of this type are divide by zero interrupt, overflow interrupt, interrupts due to INT instructions, etc. Non-Maskable Interrupt The processor 8086 has a non maskable interrupt input pin (NMI) that has the highest priority among the external interrupts. TRAP is an internal interrupt having the highest priority amongst all the interrupts except the Divide by Zero (Type0) exception. The NMI pin should remain high for at least two clock cycles and is not needed to be synchronized with the clock for being sensed. When NMI is activated, the current instruction being executed is completed, and then the NMI is served. Maskable Interrupts The processor can inhibit certain types of interrupts by use of a special interrupt mask bit. This mask bit is part of the flags/condition code register, or a special interrupt register. In the 8086 microprocessor if this bit is clear, and an interrupt request occurs on the Interrupt Request input, it is ignored. The processor 8086 also provides a pin INTR, which has lower priority as compared to NMI. Further the priorities, within the INTR types are decided by the type of the INTR signal, which is to be passed to the processor through data bus by some external device like the Programmable Interrupt Controller (8255). The INTR signal is level triggered and can be masked by resetting the interrupt flag. It is internally synchronized with the high transition of CLK. For the INTR signal, to be responded to in the next instruction cycle, it must go high in the last clock cycle of the current instruction or before that. The INTR requests appearing after the last clock cycle of the current instruction will be responded to after the execution of Nvis Technologies Pvt. Ltd.
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the next instruction. The status of the pending interrupts is checked at the end of each instruction cycle
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Capabilities Keyboard Mode: 1.
Examine/Modify the memory byte locations.
2.
Examine/Modify the contents of any of internal register of 8086.
3.
Move a block of Data/Program from one location to another location.
4.
Fill a particular memory area with a constant.
5.
To execute the program in full clock speed.
6.
To execute program in single instruction execution.
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Installation To install Nvis 5586A the following additional things are required. 1.
Connect the External SMPS Power Supply to AC Power and 5 pin connector to the left side on Nvis 5586A Kit.
2.
Switch on the Power Supply at the rear end of SMPS supply.
3.
A message – NV5586A 8086 Mic.Tr. will come on display (Press RESET if you do not get - NV5586A 8086 Mic.Tr.
4.
Now Nvis 5586A Kit is ready for the user's experiments for Keyboard Mode commands.
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Hardware Description CPU: 8086 is a 16 bit, third generation microprocessor and is suitable for an exceptionally wide spectrum of microcomputer applications. This flexibility is one of most outstanding characteristics. 8086 has got 16 data lines and 20 address lines. The lower 16 address lines are multiplexed with 16 data lines. Hence it becomes necessary to latch the address lines. This is done by using 74 LS 373. In fact several of the 40 CPU pins have dual functions that are selected by a strapping pin. In this kit 8086 is used in the max. mode (MN/MX input held logically low). The 8088 is designed with an 8-bit external path to memory and I/O. Except that the 8086 can transfer 16 bits at a time, the two processors & software are identical in almost every respect. Software identical in almost every respect. Software written for one CPU will execute on the other without alteration. The two processors are designed to operate with the 8089 I/O processors and other processors in multiprocessing and distributed processing systems. The INTR, TEST & Hold Inputs to 8086 are pulled down and are brought out at PCB FRC connector. The mask able interrupt INTR is available to the peripheral circuits through the expansion Bus. To use the mask able interrupt an interrupt vector pointer must be provided on the data bus when INTA is active. An interrupt Controller Circuit is provided to take care of more than one source of interrupt. Co-Processor 8087: The 8087 Co-processor ―hooks‖ have been designed into the 8086 and 8088 so that these types of processor can be accommodated in the future. A co-processor differs from an independent processor in that it obtains its instructions from another processor, called a host. The co-processor monitors instructions fetched by the host and recognizes certain of these as its own and executes them. A co-processor, in effect, extends the instruction set of its host computer. I/O Processor 8089: The 8086 and 8088 are designed to be used with the 8089 in high performance I/O applications. The 8089 in conceptually resembles a microprocessor with two DMA channels and an instruction set specifically tailored for I/O operations. Unlike simple DMA controllers, the 8089 can service I/O devices directly, removing this task from the CPU. In addition, it can transfer data on its own bus or on the system bus, can match 8-bit or 16-bit peripherals to 8-bit or 16-bit buses, and can transfer data from memory to memory and from I/O devices to I/O device. 8089 has been used here in local mode. The system bus, can match 8-bit or 16-bit peripherals to 8-bit or 16-bit buses, and can transfer data from memory to memory and from I/O devices to I/O device. 8089 has been used here in local mode. Clock Generation:
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The clock generator circuit is an Intel‘s 8284 clock generator/driver. The circuit accepts a crystal input which operates at a fundamental frequency of 6.144 MHz. (6.14 MHz was selected since this frequency is a multiple of the baud rate clock and also provides a suitable frequency for the CPU). The clock generator/driver divides the crystal frequency by three to produce the 2MHz CLK signal required by the CPU. Additionally, the clock generator performs a further divide-by-two output called PCLK (peripheral clock) which is the primary clock signal used by the remainder of the circuits. The clock generator/driver provides two control signal outputs which are synchronized (internally) to the 2 MHz CLK signal; RDY (ready) and RST (reset). RST is used to reset the Nvis 5586A to an initialized state that occurs when the RES input goes low (when power first is applied or when the SYSTEM RESET key is pressed). The RDY output is active (logically high) when the RDY 1 input from the wait state generator is active. As will be explained in the next section, the RDY 1 input is active whenever onboard memory is addressed or when a selected number of ―wait states‖ occurs. The system can operate at either 2 MHz or 1 MHz. This is selected by a set of jumpers JP3 on the right hand side of the 8284 clock generator as shown below: 1. 2 MHz (UPPER) 2. CLK 3. 1 MHz (LOWER) The Nvis 5586A is supplied in 2 MHz configuration. Bus Controller: The 8288 is a Bus Controller which decodes status signals output by an 8089, or a maximum mode 8086. When these signals indicate that the processor is to run a bus cycle, the 8288 issues a bus command that identifies the bus cycle as memory read, memory write, I/O read, I/O write, etc. It also provides a signal that strobes the address into latches. The 8288 provides the drive level needed for the bus control lines in medium to large systems. Memory: Nvis 5586A provides 128K Bytes of EPROM loaded with monitor and 32K bytes of CMOS RAM. The total onboard memory can be configured as follows: EPROM
-
128K Bytes of EPROM using two 27C512.
RAM
-
32K Bytes of RAM.
The system provides two 28 Pin sockets for the EPROM area named as EVEN-ROM & ODDROM and two 28 Pin sockets for the RAM area named as EVEN-RAM & ODD-RAM. EVEN-ROM & ODD-ROM can be defined to have EPROM 27512. With the 20 bit address of 8086, a total of 1 Mega Bytes of memory can be addressed with the address slot as 00000 to FFFFF. Although the total onboard memory capacity is 180K Bytes 128K Bytes of EPROM and 32K Bytes of RAM. 8255: 8255 is a programmable peripheral interface (PPI) designed to use with 8086 Microprocessor. This basically acts as a general purpose I/O component to interface Nvis Technologies Pvt. Ltd.
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peripheral equipments to the system bus. It is not necessary to have an external logic interface with peripheral devices since the functional configuration of 8255 is programmed by the system software. It has got three input/output ports of 8 lines each (PORT-A, PORTB and PORT-C). Port-C can be divided into two ports of 4 lines each named as Port-C upper and Port-C lower. Any Input/Output combination of Port-A, Port-B, Port-C upper and PortC lower can be defined using the appropriate software commands. The Port addresses for these ports are given here. Nvis 5586A provides nine Input/Output ports of 8 lines each using three 8255 chips. These ports are brought out at connectors. 8253: This chip is a programmable interval timer/counter and can be used for the generation of accurate time delays under software control. Various other functions that can be implemented with this chip are programmable rate generator. Event Counter, Binary rate multiplier, real time clock etc. This chip has got three independent 16 bit counters each having a count rate of up to 2 MHz. The CLK, GATE & OUT signals of these timers are brought out at the connector. 8251: This chip is a programmable communication interface and is used as a peripheral device. This device accepts data characters from the CPU in parallel form and then converts them into a continuous serial data stream for transmission. Simultaneously it can receive serial data stream and converts them into parallel data characters for the CPU. This chip will signal the CPU whenever it can accept a new character for transmission or whenever it has received a character for the CPU. The CPU can read the complete status of it at any time. 8251 has been utilized in Nvis 5586A for RS-232-C serial interface. 8259: The 8259 is a device specifically designed for use in real time, interrupt driven microcomputer systems. It manages eight levels of requests and has built in features for expandability to other 8259‘s. It is programmed by system‘s software as an I/O peripheral. A selection of priority modes in which the requests are processed by 8259 can be configured to match his system requirements. The priority modes can be changed or reconfigured dynamically at any time during the main program. Battery Backup: The Nvis 5586A provides a battery backup for the onboard RAM area using 3.6V Ni-Cd Rechargeable battery. Nvis 5586A has facility for connecting +5V to the RAM area if the Ni-Cd battery fails. The selection for +5V or Battery supply Jumper (JP2). Display: This display contains 2 lines and each line consists of 20 words (20x2). This is a cursor LCD display modular. The CPU receives each 8 bits letter which is locked into the internal display data of RAM (data display of RAM 80 bytes (D.D.RAM) allows 80 characters to be stored), and transfer to 5x7 dot of array word and appear on the displayed.
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This LCD modular contains the word generator ROM that will supply 160 different 5x7 dot of array word and also a 64 bytes word generator RAM. Users can define 8 types 5x7 dot of array word. The position of word display goes into the LCD Modular through the data bus in CPU. Next through the instruction register and finally write the words into the data register to display on a specific location. The LCD Modular will automatically increase or decrease the words in order to move to different addresses. The user can therefore continue sending in word code. The cursor as to moved around or moved in the right of left direction. Specification of Display
:
Display data RAM
:
80 x 8 BLT (80 words)
Character generator ROM :
160 of 5x7 dot of array word
Character generator RAM :
8 different users programmed 5x7 dot of array
Kinds of instructions
Clear the display, send cursor home (HOME), ON/OFF display. Cursor ON/OFF, character blinking cursor move to another position, display change position.
:
When the internal power is on, the circuit is reset. Internal circuit vibrator:
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Functional Block Diagram Note: Some models incorporate a temperature compensation circuit within the bias voltage generator. The LCD0. modular has 2, 8-bits register-one instruction register (IR) and one data register (DR). The instruction register stores the instruction code and address information, which contains display data RAM and address of character generator RAM. However, the content of IR is only for read-in but not read-out. The data register can only temporary store data, the input data first goes through LCD and is stored in the data register. It will then automatically be transferred to display data RAM or character generator RAM. When the CPU read the data from the displayed RAM or from the Nvis Technologies Pvt. Ltd.
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character generator RAM, it wills also temporary store the data in the data register. When the address information is input into the instruction register, the relative data will be moved from display register RAM or character generator RAM to the data register. Then the data can be read from data register by using the output instruction of CPU. One way to select the two registers is to select the register signal (RS) like follow: RS
R/W
0
0
0
1
1
0
1
1
Function Data Bus —> instruction Register Read out busy flags (BUSY FLAG DB7) and address counter (DB0-DB6) Input into data register and execute the inner instruction: (D.R.RAM— > D.R. OR C.G.RAM — D.R.) Get the data out from register, and execute the inner instruction: (D.D.RAM—> D.R. OR C.G.RAM—> D.R.)
Busy Flag (B.F.): When busy flag is ―1‖, it indicates that the LCD Modular is executing the inner instruction and no other instruction can be accepted. The LCD Modular can only accept information when BF is lower to ―0‖. Address Counter (A.C.): The address counter is used to count the display data RAM, or address of character generator RAM. When the address setting instruction address will be sent into the address counter. When the data is sent into or read out from display register RAM or from the character generator RAM, the address counter will automatically add or subtract 1. When the content of address counter is in RS = 0 and R/W = 1, the output data line is DB0 DB6. Display Data RAM (D.D. RAM): This is an 80x8 bit RAM, which can store 80 8-bit character codes as the display data; it can be sent to CPU as the RAM data section without going through RAM section. Address setting of data display RAM is as followed: High level bus
Low level bus
AC6 AC5 AC4
AC3 AC2 AC1 AC0
Data displays RAM and display position of LCD is as followed: Character Position:
1
2
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3
4
5
6
7 8 9 10 11…19 20 42
Nvis 5586A
(Decimal) First Line: (Hexadecimal)
00 01 02 03 04 05 06 07
08 09 0A..16 17
Second Line: (Hexadecimal)
40 41 42 43 44 45 46 47
48 49 4A...56 57
Character Generator ROM (C.G. ROM): This ROM generates 5x7 dot of array character has 160 different 8-bit character code. The shape and code are shown in Table 2 and 3. Character Generator RAM (C.G.RAM): This RAM stores 8 different 5x7 dot of array character which allows the user to design the program. When the character codes are stored in the C.G.RAM, which are the same as the characters in Table 2 and 3, they will be sent to display data RAM. The display data and characters are shown in Table 4. Timing Generator: Sending signals into the inner register during generating process.
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Character Codes:
Note: 1.
The CG RAM generates character patterns in accordance with the user‘s program.
2.
Shaded areas indicate 5x10 dot character patterns.
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Character code:
Note : 1.
The CG RAM generates character patterns in accordance with the user‘s program.
2.
Shaded areas indicate 5x10 dot character patterns.
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Relationship among Character Code: (DD RAM), CG RAM Address, And Character Pattern (CG RAM) Character Pattern for 5x7
* Signifies a ―don‘t care‖ bit. Note: 1.
Character code bits 0-2 correspond to CG RAM address bits 3-5. Each of the 8 unique bit strings designated one of the 8 character patterns.
2.
A CG RAM address bit 0-2 designates the row position of each character pattern. The 8 the row is the cursor position. CG RAM data in the 8 the row is OR‘ed with the
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display cursor. Any ―1‖ bits in the 8 the row will result in the displayed dot regardless of the cursor status (ON/OFF). Accordingly, if the cursor is to be used, CG RAM data for the 8 the row should be set to ―0‖. 3.
CG RAM data bits 0-4 correspond to the column position of each character pattern bit 4 corresponding to the leftmost column of the character pattern CG RAM data bus are not used for displaying character patterns, but may be used as a general.
4.
As shown in tables 2 and 3, character patterns in the CG RAM are accessed by character codes with bits 4-7 equal to ―0‖. For example, the character code ―00‖ (HEX) or ―80‖ (HEX), since bit 3 of the character code is a don‘t care bit (i.e. can take either value ―0‖ or ―1‖).
5.
CG RAM data ―1‖ produces a dark dot, and data ―0‖ produces a light dot in the corresponding position on the display panel.
Functions of Reset: Using the Internal Reset Circuit to Start: LCD Modular internal has an automatic power supply to be used to RESET when the power rises. During RESET, the busy flag is set. When the voltage is raised to 4.5V in about 10ms, it is in the busy stage. The following instructions are then used to set the beginning stage of LCD. 1.
Clear display
2.
Function set
3.
4.
DL =
1
8-bit data length interface
N=
0
(single line display)
F=
0
The source of 5x7 dot of array character
Display ON/OFF control D=
1
Display OFF
C=
0
Cursor OFF
B=
0
Character flashing function OFF
Entry mode set I/D =
1
Increase mode
S=
0
Display OFF
Note : If the time for the power to increases from 0.2V to 4.5V is greater than 0.1ms but less than 10ms, the current cut-off will drop to 0.2V before it rises again. If it takes more than 1ms, the LCD modular will automatically RESET. Otherwise, it has to depend on an external software instruction to RESET (As describe below).
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Diagram of module RESET power. Instruction Set:
Note : Nvis Technologies Pvt. Ltd.
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1.
Symbol ―*‖ signifies a ―don‘t care‖ bit
2.
Correct input value for ―N‖ is predetermined for each model
Initialization by Instructions: If the power conditions for the normal operation of the internal reset circuit are not satisfied. LCD unit must be initialized by executing a sense of the instructions. The procedure fro this initialization process is as follows.
Instruction Description:
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When the LCD is controlled by the CPU, only the instruction register (IR) and the data register (DR) can be read directly by the CPU. The commands from outside the modular can decide the internal operation of LCD. These commands include the register selection (RS) signals, read/write (R/W) signals, and data buffering signals (DB0-DB6). Table 5 lists all the useful commands in the LCD modular and the execution time, these commands are divided into the following group: 1.
Commands of set LCD module
2.
Commands of internal set address RAM
3.
Commands of data transfer in or out from the internal RAM
4.
Other commands
When the LCD modular is executing a command it will reject other commands. Except the ―busy flag/read address counter, the internal counting period of busy flag is set to as ―1‖. If the CPU wants to send in other commands it will have to check the busy flag first, until it is cleared to ―0‖ before it send in. The explanation is as followed: Display Clear command: This command will put the display data into a empty space‖ code (20H), address counter will be cleared to 0. When executing this command, display OFF, the cursor or the character blinking function will be moved to the most left side if it is in the set condition. Display/Cursor Home: The address counter will be cleared to 0, content of D.D. RAM will not be influenced; but if the cursor or the character blinking function is in the set condition, it will be moved to the most left side position. Entry Mode Set: I/D bit = ―1‖, ―1‖ is added in the address counter after each time it read/write a display data RAM character code, so that the cursor or the character blinking function will move one place to the left and vice-versa when I/D=0. The read/write (R/W) character generator also has the same function. S bit = 1, but each time it read/write a display data RAM code, it will move to the display direction and move one space to the left (I/D=0) or one space to the right (I/D=1). When S=0, the display will not move. When data enters the character generator RAM, the display will not move. Display ON/OFF: D: C:
D=1
-
Display ON
D=0
-
Display OFF
C=1
-
Cursor display on the display address of the display counter
C=0
-
Cursor does not display
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B: B=1 Character blinking of cursor position at feq or fosc=250kHz freq, therefore all black points and character display will exchange with each other. Each character display and overshadow 409.6ms. Display/Cursor Shift: S/C
R/L
0
0
-
Cursor move to the left (AC AC-1)
0
0
-
Cursor move to the right (AC AC+1)
1
0
-
All the characters and cursor move to the left
1
1
-
All the characters and cursor move to the right
Note: When the display moves, the address counter will not move. Function Set: DL
:
Select data length for the interface circuit.
DL=1 -
Using the 8 bits data length.
DL=0 -
Using the 4 bits data length.
N
Select the display format (one or two lines)
:
C.G. RAM Address Set: Address counter and character generator RAM have address which is driven by the binary 6bit. When this instruction is driven in, data can be sent into the CPU and character generator -RAM. D.D. RAM Address Set: Address counter and display data RAM have addresses which are driven by the binary 7-bit. When this instruction is driven in, data can be sent into the CPU and the display data RAM. When N=0 (a single line display), binary code ADD between 00H and 4FH; when N=1 (a two lines display), the binary code ADD from 00H until 27H as the first line of from 40H until 67H as the second line. Read Busy Flag/Address Counter: The busy flag (BF) in LCD can be read from the CPU, using the instruction of LCD modular is the execution of the internal instruction BF = 1 represents the busy stage (execution of the internal instruction), it will not accept any instruction at this time until BF = 0. Content of address counter and the busy flag will be read out at the same time, it is a 7-bit binary, the address counter will instruct one of the addresses, either the character generator RAM or display data RAM. This is determined by the final input address set instruction. Send Data Into C.G. RAM/D.D. RAM:
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Data with 8-bit in length can be sent into the character generator RAM or the display data RAM. The address of the input data is instructed by the address counter, however, the address of address counter is influenced by the final input address set instruction. After data input whether the address counter add 1 or minus 1 is determined by the design of the module. It can also be designed as location movement of the display. Read Data Out of C.G. RAM/D.D. RAM: Character generator RAM with 8-bit in length or the display data RAM can be read by the CPU. The read out data address is instructed by the address counter. The address counter is instructed by the final input address set instruction. This instruction has to be set in C.G. RAM/D.D. RAM address, once shift cursor instruction of the C.G. RAM/D.D. RAM data is read out, no other instruction can be read out. The address setting instruction will read the data address into address counter. Shift cursor command will allow the previous address setting to be used again in order to read the D.D. RAM data. The data can be read from the C.G. RAM/D.D. RAM after the cursor shift. After the execution of data address counter add 1 or minus 1 will be set in the LCD modular. After the execution of data read out, the display will not shift. The operation of this device is similarly with the operation of IBM PC‘s DEBUG system. For convenience, the operation instructions will be displayed when the device is being switched on or RESET. This device also has memory ability to preserve data for future use. There is a memory indicator on the display once the data being kept after Reset. The system program starts from 0000:0000 after reset, in order to check the length of the RAM, there is a byte to be inverted and returned to the original for every 4K in length, the verifying procedure will be repeated until none of the byte can be inverted. During this period, avoid using the RESET to prevent the data from unable to return to the original setting. The RAM address is to be displayed by 4 positions and up to FFFFH, however, 5 positions will be used if it exceeds FFFFH. Operating Commands: After power ON the system, it will display as follows:
After pressing , the operating commands will be displayed:
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Command Description A – Assemble: This command is used to convert the input Assemble Language to the Machine Language in the memory. Once under this command, first set the address which is similar to the command ―D‖ followed by an Enter or an Arrow Down key to go to a new step. However, only a maximum of 35 words are allowed for input. The following are some useful keys used to move the cursor around: Move one space to the left. Delete the character at the cursor.
Ba ckSpa ce Spa ce
Simply Press the key ‗A‘. After the command, an ―A‖ will appear on the screen:
Assembly language can be input at this time. 1.
Only contains the Effective address but the Segment base is included A 400.
2.
Input includes the segment base and the Effective address A 0000:400.
3.
Totally depends on the built in Segment base and Effective address A.
If one of the above is used, 0400 will appear on the screen and ready for input data. Example: Clear second line, display DX value, and DX values are altered by key-in to be displayed at LCD.
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Address
Mnemonic
0:0400
MOV DL, C0
0:0402
CALL F000:F078
0:0407
MOV DH, 00C2
0:040A 0:040F
CALL F000:F068 CMP AL, 0D
0:0411
JNE
0:0413
HLT
040A
Before entering the above program connect the system to the power supply properly. Then the following menu will be displayed on LCD screen, if not, switch off the power supply and re-check.
The following steps are to be taken: 1.
Press the key A and the LCD display is as shown here:
2.
Now the user enter the segment address and effective address simultaneously as follows:
3.
Now press Enter key, the effective address will appear.
From now onwards user can enter the program in assembly language. First pick the first instruction.
While entering this instruction, the following mistakes may happen: 1.
If user has entered the wrong instruction as follows:
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As user press the Enter key, then above instruction will not be converted into machine language. And the cursor will point left side of the instruction as follows:
Now by using the the below of ‗C‘.
keys, user can move the cursor right side and indicate at
Delete the character by using keys.
Press Enter key, then this input assemble language will be converted into machine language in the memory and jump to the next memory location. 2.
Or user has entered the wrong instruction as follows:
As user press the key, then above instruction will not be converted into machine language. And the cursor will point left side of the instruction as follows:
Now just type again the correct instruction it will replace the previous characters. Press Enter key, then this input assemble language will be converted into machine language in the memory and jump to the next memory location. 3. Or user has entered the wrong instruction as follows:
As user press the Enter key, then above instruction will not be converted into machine language. And the cursor will point left side of the instruction as follows:
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And user wants to write whole instruction again, and then by using the keys, the content at the location 400 will be erased as follows:
Now by using key user can come back again to initial position Now enter the instruction again.
Press key, then this input assemble language will be converted into machine language in the memory and jump to the next memory location.
Now write the next instruction as follows:
In this way, user can enter the whole program, by pressing key.
Now by using GO command, the machine language statements can be executed and the value of DX will be displayed in the second line of the LCD. Note : When ―A‖ and ―U‖ are being used, the operation used: 0000:1E00 0000:1FFF as the buffer. D - Display or modify the RAM’s Hexadecimal:
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A.D.U. is the important commands in the compiling. The effective address or both the effective address and Segment base can be used during input. When the cursor is placed at the beginning, the key will immediately show ―F000‖ as the Segment base and the Effective address next. Syntax: D
(If no input, press Enter key or ARROW UP/DOWN key would allow the built-in address to be used)
D 0400
(Uses built-in Segment base but specify the Effective address)
D 0:0400
(Specify both the Segment base and Effective address)
If press the or the ARROW UP key after specifying the address, the memory will display the data. Press ARROW UP key will allowed the address to ADD 8 and store in the memory as a whole number. Otherwise, an ARROW DOWN key indicates an subtraction of 8 in the address and these changes in the memory (as a machine language). Syntax:
If address is not a whole number 8, the following will show:
The above data shown at the location 400 are the arbitrary data‘s. Example: If the user wants to see the codes of the above program, the following steps are to be taken: 1.
Press F7 key, the menu will display.
2.
Press D key, and write the effective address. The following will be displayed:
3.
Press key, then the following will be displayed:
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Use
key for further view.
F - Fill data into the RAM: By setting the starting, ending address and the details, an key will allow the data to enter the RAM. Syntax:
Once ‗F‘ is entered, the command can be preceded.
The ending position has to be bigger than or equal to the starting position, otherwise the smaller user will become the ending position and the bigger user is the starting position. G - Proceed to the address for execution: The GO command, which causes the machine language statements to be executed. This command executes the loaded program and allows the user to specify the addresses at which program execution will stop. The syntax is as followed:
When the ‗G‘ key has been applied, the procedure can be taken place.
It shows the address 0000:0400 by default if your program resides on another location than user have to change address. Once the ‗GO‘ command has been executed, it will completely leave the system and proceed to the user‘s program. Flowchart of G-Command
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I – Interrupt: Three Interrupts (Effective address) can be set in for the program execution; the CPU will continuously make a single-step subprogram for checking IP values. When the IP register has the same value as the Interrupt‘s address, it will enter the Interrupt‘s subprogram. Enter command ―I‖ will interrupt the program. Syntax:
The I key allows interruption to be shown on the screen.
Note: 1.
During interrupt setting, the address alternation register has commands like POP ES, MOV DS, AS, etc. to execute with the next command.
2.
The program will be delayed for due to the fact that CPU has to send each command individually into the subprogram.
3.
During the interruption, the commands GO would allow the program to execute until the next INTERRUPT.
Example: To break point at 0402, 0407 and 0411 in the example given on Page-3, the following steps are to be taken: 1.
Press the key F7 and the LCD display is as shown here:
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Nvis 5586A
2.
Now press the key I and the LCD display is as shown here:
Modify using and keys as follows:
3.
Press the key F7 and then G. The display will be as follows:
4.
Press the Enter key and then F7.
This indicates the first break-point is at 0402. To proceed further, press G, Enter, and then F7.
This indicates the second break-point is at 0407. To proceed further, press G, Enter, and then F7.
This indicates the third break-point is at 0411. One can use any commands including Examine Register by pressing the key R. Note: In above figure observe the command R is also displayed this command only appears during step execution of program or when Breakpoints are applied at some addresses using I command. Display Register: Command ―R‖ displays the content in the register. This command allows the user to examine the content of the register in the CPU. Each time during display, 4 registers will be shown. The following are some of the display and criteria of the register:
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The first group register (AX, BX, CX, and DX) will be shown first when enter the command ―R‖. The key will jump to the second group; the fourth group can return to the first group. When the content in the register is displayed, the cursor will not appear, the user therefore cannot change the content in the register M - Moving Data: The command MOVE is used to move data in the memory from a specified address to another address by input the starting address, the ending address and the desire address. A RETURN key is then used to execute the changes. Syntax: The ‗M‘ key allows the data to be moved to another address:
The ending address must be greater than or equal to the starting address. The sum of the starting address in plus the corrected ending address in the target cannot exceed FFFF. Otherwise, it will cause an input error and have to redo the whole procedure. T - Trace Program (an N-step designed command): This command is used for program execution. TRACE will enter the INTERRUPT subprogram every time the program execute. N has a decimal range from 1-99 with 10 as the rounding off number, and only operate if N is not 0; other-wise it will clear the function. Syntax: Nvis Technologies Pvt. Ltd.
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T
00 - STEP Decimal TRACE setting
Only 0-9 numerical keys are allowed to use to operate for this command but not any other keys. Example: Enter the following program using ‗A‘ 0000:0400 and press Enter key.
Now if user wants to see the process of the above program, then the procedure is as follows: 1.
After entering the above program, press F7 key, then the menu will be displayed as follows:
2.
Press the Key ‗T‘. The screen displays as follows:
3.
Now the user can view the program after the one instruction, two instructions, and so on by defining the number which is to be entered through keyboard.
Example: The instruction pointer stops after every single instruction.
After completion, press ‗F7‘ for a menu display.
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4.
Press the key ‗G‘, the menu will appear.
5.
Press Enter key.
6.
Press ‗F7‘ key, the single stepping will start and the following menu will be displayed: 1ST instruction is executed.
Press ‗G‘ key and next ‗F7‘ key for further view; the following results will be displayed: 2nd instruction is executed.
Press ‗G‘ key and next ‗F7‘ key for further view; the following results will be displayed: 3rd instruction is executed.
Press ‗G‘ key and next ‗F7‘ key for further view, the following results will be displayed: 4th instruction is executed.
Press ‗G‘ key and next ‗F7‘ key for further view; the following results will be displayed:
Here user can observe the process of program execution, because data 30 is greater than 20 so that carry will not generate and the program execution will jump to the desired label. Now again press ‗G‘ key and next ‗F7‘ key Anywhere during trace command, one can examine/modify the registers using ‗R‘ command (refer Register Command Description). Note: Refer to the INTERRUPT command for precaution. Nvis Technologies Pvt. Ltd.
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U – Unassemble: The UNASSEMBLE command decodes the value of a group memory location mnemonics, and display on the displayed. Once enter this command, input the proper design address. The following is the correct way to input address:
1.
The content of the Unassemble 0400 will start if only the starting address is entered. The built-in segment base is used here if it is not entered.
2.
The content of the Unassemble 0000:0400 will start if only the starting address is entered with segment address as 0000:0400.
Press ―U‖ key would enter the Unassemble design:
Display the address first, then display the machine code (if the machine code is too long, they will be continued on the second line). The second line displays the assemble program and the process is completely done. To see further press F7 key and then U again and then again enter next address. If the user needs to modify the instruction, press key ‗F7‘ will move to the command Assemble (A). And write the address of the instruction which is to be modified. Press Enter key and write the correct instruction and again press Enter key. Press key ‗F7‘ another time would bring the instruction back to the Unassemble. The ―U‖ command can be used to examine the program but not more than 127 instructions in forward direction. When the program reaches the end, the ―U‖ command can be used to decode the program again or forward. Example: The example entered earlier can be seen as follows:
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1.
Press ‗U‘ key, and enter the starting address of the program.
2.
Press Enter key, the following will be displayed:
3.
Press F7 and then ―U‖ and enter the next address for further view.
4.
If the user want to modify at the address 0404, then following steps are to be taken: a.
Press ‗F7‘ key, the menu will display.
b.
Press ‗A‘ key and enter the address 0404 as follows:
c.
Press Enter key and write the instruction again.
d.
Press Enter key so that the modifications has been taken place.
Note: When commands ―A‖ and ―U‖ are executed, the system program uses 0000:1E001FFF as the buffer, therefore during the execution of ―A‖ and ―U‖, this segment cannot be used.
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Memory Address & Port Address Memory Section: Address 0000:0000 0000:7FFF F000:0000 F000:FFFF
Purposes RAM AREA {ODD RAM & EVENRAM } ROM MONITOR AREA {ODD ROM & EVEN ROM}
I/O Address: The addresses of the various chips in I/O mapped in Nvis 5586A are as follows: Device No.
Port No.
8255-I
PPI 70
Port A
72
Port B
74
Port C
76
Control Word
8255-II
PPI 80
Port A
82
Port B
84
Port C
86
Control Word
8255-III
PPI 10
Port A
12
Port B
14
Port C
16
Control Word
8253
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Selected Device
PIT 00
Counter 0
02
Counter 1
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Nvis 5586A
8259
8251
04
Counter 2
06
Control Word Register
30
Interrupt controller Data Word
32
Command/Status Word
50
Data Register
52
Control Word Register
RAM Memory: Address
0000:0000
Purposes Interrupt Vector Section (INTI, INT2, INT3 have arranged the interrupt section and stack segment
0000:0390
Stack Segment BUFFER
0000:039B
SYSTEM DATA
0000:93E0
BUFFER (Only if needed)
0000:0400 to
USER‘S RAM AREA
0000:7FFF System Data of RAM: 0000:039B
-
Store 9B, will stop at the subprogram exit next to the WAIT command each time it leave the interrupt display subprogram, waiting for F2 to continue execution (is used in TRACE to convert to single-step hardware).
0000:039C 0000:039D
TRACE Buffer
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0000:039F
-
Flags, function of each byte is as followed:
BIT: 0
:
Enter NMI as 1, otherwise as 0
1
:
After the ―G‖ key, will be set to as 0, ‗SHIFT‘ + ‗F7‘
2
:
During subprogram, is set to as 1
3
:
Set to 1 after entering INTERRUPT
4
:
Use in interrupt system
5
:
Use in interrupt System
6
:
Set 0 to INTERRUPT, and set 1 to TRACE
7
:
Set TRACE or INTERRUPT as TF flags, timer 1 0000:03A0
Buffer of Interrupt setting
0000:03A5 0000:03AE
Preserved battery to test bit
0000:03AF 0000:039E -
Flags, use the command ―A‖
0000:03B0 0000:03D8
Data stored in the register monitor during interruption
Note: Address 4350 to 4900 is used for internal operation of trainer and this area in not user accessible.
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Subroutines Address
Text
Description
F000:F000
JMP BCBA
RECORDER PROGRAM
F000:F003
JMP BB00
RS-232 PROGRAM
Practical Use of Subprogram (ROM’S Content) Address
Text
F000:F040
CALL SI
F000:F044
CALL FEE0
WRITE AL‘S INSTRUCTION INTO LCD
F000:F048
CALL FEF0
WRITE AL‘S DATA INTO LCD
F000:F04F
CALL FF00
READ LCD AND STORE DATA IN AL
F000:F053
CALL FE7A
INPUT KEYS AND STORE VALUE IN AL
F000:F04C
CALL FE8A
CONVERT INPUT NUMERICAL VALUES INTO ASCII CODE AND STORE IN AL. IF IT IS NOT A NUMBER THAN IT WILL BE SET TO C-FLAGS AS ―1‖.
F000:F058
CALL FEA0
CONVERT THE INPUT ALPHABETICAL VALUES INTO ASCII CODE. IF IT IS NOT AN ALPHABET THEN IT WILL BE SET TO C-FLAGS AS ―1‖.
F000:F05C
CALL FEB5
CONVERT THE INPUT SYMBOLS INTO ASCII CODE AND STORE IN AL. IF IT IS NOT A SYMBOL THAN SET TO C-FLAGS AS ―1‖.
F000:F060
CALL FDF5
CONVERT THE INPUT FUNCTIONAL KEYS INTO ASCII CODE AND STORE IN AL. OTHERWISE, SET TO C- FLAGS AS ―1‖.
F000:F064
CALL FB35
CALL FOR THE ABOVE 4 SUB-PROGRAM AND CHANGE INPUT KEY INTO ASCII TO STORE IN AL.
F000:F068
CALL EA35
SAVE THE INPUT 4 DIGITS IN DX, DISPLAY POSITION FROM BL TO BH INSTRUCTION.
F000:F06C
CALL FAA0
STORE INPUT 4 DIGITS IN DX AS SEGMENT BASE AND ANOTHER 4 DIGITS AS THE EFFECTIVE ADDRESS IN DI (DX: DI).
F000:F070
CALL FE15
CONVERT THE ASCII CODE IN AL TO HEXADECIMAL.
F000:F074
CALL FE30
CONVERT THE HEXADECIMAL IN AL TO ASCII CODE AND STORE IN BETWEEN AH AND AL.
F000:F078
CALL FF2B
DELETE ONE LINE
F000:F07C
CALL FCD5
CLEAR THE SCREEN
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Description
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Nvis 5586A F000:F080
CALL FD20
CURSOR BLINKING MOVEMENT
F000:F084
CALL FDC0
INSERT THE LOWER 4 BITS INTO THE DX WITH BH INSTRUCTION
F000:F088
CALL FFOA
WRITE THE HEXADECIMAL IN AL INTO CURSOR ADDRESS
F000:F08C
CALL FF20
WRITE THE HEXADECIMAL IN AX INTO CURSOR ADDRESS
F000:F094
CALL F39A
WRITE THE HEXADECIMAL IN AX INTO BL DESIGNATED ADDRESS
F000:F098
CALL FD4A
READ IN 2 LETTERS FROM BL DESIGNATED POSITION,CHANGE TO HEXADECIMAL AND STORE IN AX
F000:F09C
CALL FD7A
READ IN 4 LETTERS FROM BL DESIGNATED POSITION, CHANGE TO HEXADECIMAL AND STORE IN AX
F000:F0A0
CALL FE55
BEEP
F000:F0A4
CALL FEDA
EXTENDED SUBPROGRAM CAN BE PLANNED. PLAN 8253 #2 COUNTER AS THE EXTENDED COUNTING AND CHECK KEY-IN WHEN LEAVING THE SUBPROGRAM
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Codes Table: The key-in code in transferred to ASCII and the ability to transfer the address, FF means empty codes that have not been defined. Character Code: (F000:FF60 - FF83) F000:FF60 : :FF70 :
FF80
:
ASCII
30
31
32
33
34
35
36
37
38
39
41
Number
0
1
2
3
4
5
6
7
8
9
A
ASCII
42
43
44
45
46
47
48
49
4A 4B 4C
C
D
E
F
G
H
I
J
K
L
50
51
52
53
54
55
56
57
P
Q
R
S
T
U
V
W
Alphabet B ASCII
4D 4E 4F
Alphabet M
N
O
ASCII
58
59
5A FF FF FF FF FF FF
Alphabet X
Y
Z
FF FF
Symbols Code: (F000:FF90-FFBF) F000:FF90
:
ASCII
FF
3C 3E
Symbols
<
>
26
2A 2B 28
&
*
ASCII :FFA0
:
:FFB0
:
FF 3D 5F
Symbols ASCII
29
FF
=
^
7E
2C 2E
FF 2F 2D 7F /
Symbols )
,
ASCII
3B 3A 22
FF FF
Symbols ASCII
21
Symbols !
-
?
+
;
:
23
24
25
#
$
%
FF FF
5B 5D 7B 7D FF [
"
2D
0D
]
{
FF
94
FI
DEL
D0
D1
D2
EDIT
LIST
SP 90
91
92
CLS GO
20 SP
0D
FF
D4 INS
D3
Note: Nvis Technologies Pvt. Ltd.
(
.
Functional key: (F000: FFBC-FF9B)
93
3F
71
}
Nvis 5586A
1. CTRL ON conditions have not been defined. 2. SP and
area use under the key SHIFT ON and OFF.
Checking section of interrupt vector position After RESET, the system program will allow the stored data to begin from 0:0000 until Interrupt vector position. FF is the undefined interrupt that for the user to decide. F000:FFC0
:
FFD0
:
FFE0
:
FF
FF
FF FF
CA
30
F7 INT2 FF FF FF FF
00 F0
1A INT3 FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
F7 INT1 F7
00
F0
00
F0
FF FF FF FF
FF FF FF FF
FF FF FF FF
Sub-Program: The 8086/8088 subprogram has both the same segment calling and the different segment calling. The different segment calling is used towards the different. The different segment calling is used towards the different segment of subprogram. The subprogram of this system program has to be all in the same segment in order to call the same subprogram (the same segment and different segment subprogram are different from RET command). For user convenience, the system program will start from F000:F040 as the catalog section of the subprogram. In the subprogram catalog segment, if the same segment subprogram RET is changed to different segment subprogram RET is changed to different segment subprogram RETF. The user can therefore choose the different segment calling from any segment to call one of the subprogram in the catalog segment. Another method of using system subprogram is to use the M command to move all the programs in the system into the user‘s segment. This allows direct access to the calling commands in the segment. Since there are other subprogram that can be called from the subprogram, all the programs have to be moved together in order to protect each other address (when every subprogram is being used in the catalog, it should start moving from F000:EA00-FF4F), it is therefore a waste of space. The user can add new program into the empty space of catalog section. Operation description of sub-program: 1. CALL F000:F040 The calling of the implied address will allow the subprogram address to be registered into the SI calling if a called program is not in the catalog section. Input Parameter : The calling of subprogram address is instructed by SI. However, others depend on the needs of the subprogram calling. Output Parameter : Depends on the execution of subprogram. 2. CALL F000:F044 Write all the commands in the AL into the LCD. Nvis Technologies Pvt. Ltd.
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Input Parameter Output Parameter
: :
AL stores the LCD modular orders that have been written in. None
3. CALL F000:F048 In this subroutine, we enter hex data in AL and get its ASCII equivalent into the cursor position of the LCD (the position of the address counter). Input Parameter Output Parameter
: :
Written data (hex) is stored in AL None
4. CALL F000:F04C Read out data from cursor position of LCD (the instructed position of address counter) into AL. Input Parameter : None Output Parameter : AL stores the read in data. 5. CALL F000:F050 Read out the key-in from 8279 (execute only when the key is pressed). Input Parameter : None Output Parameter : The key-in value is stored in AL. 6. CALL F000:F054 Change the numerical key-in value into ASCII code; clear the C-Flag to 0 for numerical key otherwise set 1 for non-numerical key without changing AL value. Input Parameter : The key-in value is stored in AL Output Parameter : If it is a numerical key, transfer into the relative ASCII values, store in AL and clear all flags. All non-numerical keys are set in C-Flag, and AL value changes. 7. CALL F000:F058 Change the alphabetical key-in value into ASCII code; clear the C-Flag to 0 for alphabetical keys otherwise set 1 for non-alphabetical keys without changing the AL value. Input Parameter : The key-in value is stored in AL Output Parameter : If is an alphabetical key, transfer to ASCII code to be stored in AL and clear the C-Flags. Otherwise, the AL value will not change. 8. CALL F000:F05C Change the signs key-in into ASCII code, the undefined signs key will be transferred to FF to be stored in AL, and clear the C-Flag to 0; otherwise set the flags to 1 without changing the AL values. Input Parameter
:
The key-in value is stored in AL.
Output Parameter : If it is a sign, transfer to ASCII code to be stored in AL and clear the C-Flag, otherwise, set the C-Flags to 1 without changing AL values.
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9. CALL F000:F060 Change the functional keys into the key-in values (Enter and SP keys as the ASCII code, whereas others are set by the system program), those undefined one will be stored as FF in AL and clear the C-Flag to 0. Input Parameter
:
The key-in codes are stored in AL.
Output Parameter : If it is functional key, transfer to key-in code to be stored in AL and clear the C-Flags, otherwise set the C-flags to 1 without changing AL values. 10. CALL F000:F064 A combination of (6) (7) (8) (9) function. Input Parameter
:
The key-in values are stored in AL.
Output Parameter : The AL not only transfers the code but also clear the C-Flags to 0. Otherwise set the C-Flag to 1 without changing AL values. 11. CALL F000:F068 Input a 4 digits number at the BX appointed location and store in DX in order to be displayed in LCD modular. BL will appoint the first position. BH will appoint BL where to start, BH has to be smaller than 4 & follows the address counter in the LCD modular. When BL=X0XX XXXX, it is the first line; when BL = X1XX XXXX, it is the second line. The exact location is the sum of BL and BH. If the key-in function is changed to key code, it will leave the subprogram after it is stored in AL. The BH is set to 0 for first time entry; the rest will be according to the key-in to determine the code. Input Parameter: DX
:
The first displayed number after the entry
BL
:
The display location of word at the most left side.
BH
:
Which location from BL the character starts.
Output Parameter: AL
:
The code used for storing functional key.
DX
:
Store the displayed numbers.
12. CALL F000:F06C The appointed location of BL and BH, the code of input section and effective address are stored consequently in DX and DI (i.e. DX: DI). The displayed location of most left side character is instructed by BL, BH instructs the position from the first character onwards. If BH is smaller than 9 but not equal to 4, BL add to BH will be the exact location of display location. Nvis Technologies Pvt. Ltd.
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The keys, are used to operate the cursor while input numbers. It will also allow the cursor to move between segment and effective address. Other than these three functional keys, the rest will transfer to code number and jump out of subprogram. Input parameter
:
BL
:
Instruct the most left side word to display location. The rules are the same as (1).
BH
:
Instruct the position starting from BL, first entry into the subprogram is set to 0, program execution will follow the operation whether to add or subtract.
Output Parameter :
AL stores the key-in code of functional keys.
13. CALL F000:F070 Transfer the numbers in AL from ASCII code to hexadecimal to be stored in lower 4 bits of AL, clear to C-Flag at the same time to 0. But set the C-Flag of non-numerical ASCII code to 1, without changing the code of AL. Input Parameter
:
ASCII code of numbers that are stored in AL.
Output Parameter
:
The ASCII code of the numbers in AL will be transferred to hexadecimal to be stored in the lower 4 bit, clear the C-flag to 0 otherwise set C-Flags to 1 with-out changing the AL code.
14. CALL F000:F074 After changing the ASCII in AL to HEX code, the higher level is stored in AH and the lower level is stored in AL. Input Parameter
:
AL stores the exchanged hexadecimal.
Output Parameter
:
AH stores the higher level ASCII, AL stores the lower level ASCII.
15. CALL F000:F078 Clear the first line display of the BL, display of D.D. RAM will be stored into the blank code ―20‖, and then the cursor will move back to the starting point. BL = X0XX XXXX means clearing the first line. BL = X1XX XXXX means clearing the second line. Input parameter
:
BL indicates the number of cleared lines.
Output Parameter
:
BL stores 80 (first line) or CO (second line).
16. CALL F000:F07C Nvis Technologies Pvt. Ltd.
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Nvis 5586A
Clear display (blank code ―20‖ is stored in the display) Input Parameter
:
None
Output Parameter
:
None
17. CALL F000:F080 The cursor blink, wait for the key to jump out. Input Parameter
:
None
Output Parameter
:
AL stores the key-in code from 8279.
18. CALL F000:F084 Insert the AL lower 4 bit hexadecimal into the DX, the location is determined by BH. BH must be smaller than r, BH = 0 represents it is inserted into the most left-sided position of DX. Input Parameter
:
The AL lower 4 bit means an insert into hexadecimal. DX - means inserted numbers. BH - indicates inserted location.
Output Parameter
:
DX is the code after insertion.
19. CALL F000:F088 Write the AL code into cursor location (inside the address of the address counter). Input Parameter
:
AL stores the code that is ready for input.
Output Parameter
:
None
20. CALL F000:F08C Write the AX code into the cursor location. Input Parameter
:
AX stores the code that is ready for input.
Output Parameter
:
None
21. CALL F000:F094 Write the AX code into the BL indicated location of LCD, BL indicates the first line or second line as in (11). Input Parameter
:
BL indicates the most left-sided location of the word. AX stores the codes that are ready for input.
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Nvis 5586A
Output parameter
:
None
22. CALL F000:F098 The LCD which instructed by BL read out 2-bit and change it to hexadecimal to be stored in AL, also clear the C-Flag as 0. If it is a non-numerical character, the C-Flag will be set to 1 and return once AL is back. The instruction of BL location is the same as (11). Input Parameter
:
BL indicates the read-in of the first word on the left.
Output Parameter
:
If read a number, then will transfer to hexadecimal to be stored in AL. The C-flag has to be cleared to 0, otherwise it is taken back to AL, and moreover the C-Flag is set to 1 in order to return.
23. CALL F000:F09C The LCD which is instructed by BL read out 4-bit, changes to hexadecimal to be stored in AX, and Clear the C-Flag to 0. If it is non-numerical code, the C-Flag is set to 1 and is also taken back into AX before it returns. BL instructed the number on the most left, the rule ins the same as in (11). Input Parameter
:
BL instructs the first word that is ready to read out from the most left side.
Output Parameter
:
The number read will be transfer to hexadecimal to be stored in AX, and clear the C-Flag to 0. Otherwise, the AL code will return and the C-Flag will be set to 1.
24. CALL F000:F0A0 Make a beep sound. Input Parameter
:
None
Output Parameter
:
None
25. CALL F000:F0A4 Delay subprogram that can be designed, the delay is counted by the counter # 2 of 8253. It will check the key at the end, in order to jump out the subprogram after it read. Input Parameter
:
Before input, counter # 2 of 8253 has to be programmed. The subprogram will check counter # 2 and Jump out once reach the end.
Output Parameter
:
AL—AL code 00 represents no key-in, otherwise AL code will be the key-in code. If AH is influenced, it will change (indefinite value).
Nvis Technologies Pvt. Ltd.
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Nvis 5586A
Practical Examples of Subprogram: Note: Programs in Assembly language directly compile on Trainer Assembler while writing program in Assembly language in Trainer do not add prefix Zero (0) or any postfix like H as shown in figure and use address of label names in place of Label name in trainer.
Example 1: Input alphabetical key, and display at LCD. Address
Opcode
Mnemonic
0:0400
B0 01
MOV
AL, 01
0:0402
9A 44 F0 00 F0
CALL
F000:F044
0:0407
B0 0D
MOV
AL, 0D
0:0409
9A 44 F0 00 F0
CALL
F000:F044
0:040E 0:0413
9A 50 F0 00 F0 9A 58 F0 00 F0
CALL CALL
F000:F050 F000:F058
0:0418
72 F4
JB
040E
0:041A
9A 48 F0 00 F0
CALL
F000:F048
0:041F
E9 EC FF
JMP
040E
0:0422
F4
HLT
Comment CLEAR DISPLAY COMMANDS TO BE STORED IN AL CALLING INSTRUCTION IS INPUT INTO LCD RAM COMMAND THAT DISPLAY ON/OFF IS STORED IN AL0D= 0000 1101 LETTER BLINKING CURSOR OFF DISPLAY ON DISPLAY ON/OFF ORDER CALL FOR WRITE-IN INSTRUCTION SUBPROGRAM CALL FOR THE READ KEY-IN CALL THE ALPHABETICAL KEY CODE AND TRANSFER INTO THE SUBPROGRAM IGNORE THE ALPHABETICAL KEY-IN, RETURN TO ORIGINAL KEY-IN; OTHERWISE EXECUTE THE NEXT INSTRUCTION. KEY-IN CODE ENTER INTO LCD MODULAR
Program input starts executing from 0400; the first word blinking can be seen at this time, they can be input again in order to be displayed on LCD. 21st to 41st word will exceed the first line display boundary; therefore they are stored in LCD modular but will not be shown. The 41st word will be the first letter on the second line. Similarly, 61st to 80th word will not be shown.
Nvis Technologies Pvt. Ltd.
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Nvis 5586A
Example 2: Clear second line, display DX value, and DX values are altered by key-in to be display at LCD. Address
Opcode
Mnemonic
Comment
400
BA 34 12
MOV
DX,1234
403
B0 01
MOV
AL, 01
CLEAR DISPLAY COMMANDS TO BE STORED IN AL
0405
B3 C0
MOV
BL,C0
WRITE THE SET LCD ADDRESS COUNTER COMMANDS INTO BL.CO=11000000 REPRESENT THE POSITION OF SECOND LINE
9A 78 F0 00 F0 BB C2 00
CALL MOV
F000:F078 BX, 00C2
CLEAR SECOND LINE INPUT PARAMETER OF SUBPROGRAM IS STORED IN BX.
0407 040C
B0-B5 set the word at the most left side to display position, B6=1 represents the second line, B7 can be any number. After entering subprogram, it is automatically set to 1 (B=Bit). BH as 00 instructs the cursor and the first word location, first time entering subprogram is set to 0, the rest will automatically add or subtract. Address
Opcode
Mnemonic
Comment
0:040F
9A 68 F0 00 F0
CALL
F000:F068
INPUT 4 BITS.
0:0414
3C 0D
CMP
AL, 0D
WHETHER IT IS ENTER KEY
0:0416
75 F5
JNZ
040A
0418
F4
HLT
NON-ENTER KEY WILL JUMP BACK TO INPUT SUBPROGRAM; OTHERWISE IT WILL EXECUTE THE NEXT COMMAND.
Program will clear the second line first, but display 4 bits (DX value) on the second line and wait for input. After the key-in numbers, the display value can be altered and stored in DX. Press Enter key would stop the program.
Nvis Technologies Pvt. Ltd.
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Example 3: Display 4 bits (AX value) on BL instructed location. Address
Opcode
Mnemonic
Comment
0400
B3 80
MOV
BL, 80
INPUT PARAMETER OF SUBPROGRAM IS STORED IN BL. B6=0 REPRESENTS 1ST LINE
0402
9A 78 F0 00 F0
CALL
F000:F078
CLEAR THE FIRST LINE.
0407
B8 88 80
MOV
AX, 8088
040A
9A 94 F0 00 F0
CALL
F000:F094
INPUT PARAMETER OF SUBPROGRAM IS STORED IN BL. AMONG 84=10000100, B0 TO B5 DISPLAY THE FIRST WORD ON THE MOST LEFT SIDE. B6 AS 0 REPRESENTS THE 1ST LINE DISPLAY, B7 CAN BE ANY VALUE THAT AUTOMATICALLY SET TO 1 ONCE ENTER THE SUBPROGRAM. IT IS THE D.D. RAM ADDRESS COMMAND. DISPLAY AX.
040F
F4
HLT
Program will first clear the first line, then store ―8088‖ into AX to display the first line. Input parameter of subprogram is stored in BL. B6=0 represents 1st line
Nvis Technologies Pvt. Ltd.
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Nvis 5586A
Example 4: Check table to display one line of letter. Address
Opcode
Mnemonic
0400 0402 0407
B3 C0 9A 78 F0 00 F0 B0 C2
MOV CALL MOV
BL,C0 F000:F078 AL,C2
0409
9A 44 F0 00 F0
CALL
F000:F044
040E
0E
PUSH
CS
040F
1F
POP
DS
0410
BE 00 06
MOV
SI,600
0413
B9 0A 00
MOV
CX,0A
0416
FC
CLD
0417
AC
LODSB
0418
9A 48 F0 00 F0
CALL
F000:F048
041D
E2 F7
LOOP
0416
041F
F4
HLT
Comment CLEAR THE SECOND LINE PARAMETER OF SUBPROGRAM STORED IN AL. B)-B5 IS WRITTEN INTO LCD ADDRESS COUNTER, INSTRUCTED THE WORD ON THE MOST LEFT SIDE. B6 AS 1 REPRESENTS THE SECOND LINE.B7 AS 1 REPRESENTS THE SET D.D. RAM ADDRESS INSTRUCTION. COMMANDS IN AL ARE WRITTEN INTO LCD SEGMENT VALUE SET FOR TABLE CHECKING STARTING ADDRESS OF TABLE CHECKING IS STORED INTO SI STORE TABLE CHECKING LENGTH IN CX CLEAR DIRECTIONAL FLAG READ IN DATA FROM TABLE CHECKING SECTION UNTIL AL. INPUT AL DATA INTO LCD MODULAR. CX NOT EQUAL TO 0 WOULD CONTINUE EXECUTION LOOP
Program execution at address 0:0600 is stored into the ASCII code of display data, like followed (can be set oneself): 0600 41 42 43 44 45 46 47 48 49 4A Program starts from 0:600 to be stored as ASCII data code and display on LCD modular i.e. A B C D E F G H I J.
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Example 5: To clear LCD display. Address
Opcode
Mnemonic
0400
9A 7C F0 00 F0
CALL
0402
F4
HLT
Nvis Technologies Pvt. Ltd.
F000:F07C
Comment CALL SUBROUTINE HALT
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Nvis 5586A
Example 6: To convert 8-bit hex data in ASCII code and display converted ASCII value. Address
Opcode
Mnemonic
Comment
0400
B0 45
MOV
AL, 45
MOVE 45 TO AL REGISTER
0402
9A 48 F0 00 F0
CALL
F000:F048
CALL SUBROUTINE
0407
F4
HLT
HALT
On executing this particular program displayed value is ‗E‘.
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Example 7: To write all the commands in the AL into the LCD modular. Address
Opcode
Mnemonic
Comment
0400
B0 01
MOV
AL, 01
CLEAR DISPLAY SCREEN
0402
9A 44 F0 00 F0
CALL
F000:F044
CALL SUBROUTINE
0407
F4
HLT
Address
Opcode
HALT
Mnemonic
Comment
0400
B0 01
MOV
AL, 0F
DISPLAY ON, CURSOR BLINKING
0402
9A 44 F0 00 F0
CALL
F000:F044
CALL SUBROUTINE
0407
F4
HLT
Address
Opcode
HALT
Mnemonic
Comment
0400
B0 01
MOV
AL, 10
SHIFT CURSOR POSITION TO LEFT
0402
9A 44 F0 00 F0
CALL
F000:F044
CALL SUBROUTINE
0407
F4
HLT
Address
Opcode
HALT
Mnemonic
Comment
0400
B0 01
MOV
AL, 08
DISPLAY OFF, CURSOR OFF
0402
9A 44 F0 00 F0
CALL
F000:F044
CALL SUBROUTINE
0407
F4
HLT
Address
Opcode
HALT
Mnemonic
Comment
0400
B0 01
MOV
AL, 14
SHIFT CURSOR POSITION TO RIGHT
0402
9A 44 F0 00 F0
CALL
F000:F044
CALL SUBROUTINE
0407
F4
HLT
Address
Opcode
HALT
Mnemonic
Comment
0400
B0 01
MOV
AL, 80
FORCE CURSOR TO BEGINNING OF FIRST LINE
0402
9A 44 F0 00 F0
CALL
F000:F044
CALL SUBROUTINE
0407
F4
HLT
Nvis Technologies Pvt. Ltd.
HALT
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Nvis 5586A
Example 8: Input Parameter: DX
:
The first displayed number after the entry
BL
:
The display location of word at the most left side.
BH
:
Which location from BL the character starts.
Output Parameter: AL
:
The code used for storing functional key.
DX
:
Store the displayed numbers.
Address
Opcode
Mnemonic
Comment
0400
9A 7C F0 00 F0
CALL
F000:F07C
CLEAR THE DISPLAY
0405
BB 00 00
MOV
BX,0000
MOV 0000H IN BX REGISTER
0408
9A 68 F0 00 F0
CALL
F000:F068
CALL SUBROUTINE
040D
88 36 50 04
MOV
[450], DH
MOVE DH CONTENT TO MEMORY LOCATION 450
0411
88 16 51 04
MOV
[451], DL
MOVE DL CONTENT TO MEMORY LOCATION 451
0415
F4
HLT
Nvis Technologies Pvt. Ltd.
HALT
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Nvis 5586A
Example 9: ASCII to HEX conversion. After changing the ASCII in AL to HEX code, the higher byte is stored in AH and the lower byte is stored in AL. Address
Opcode
Mnemonic
Comment
0400
B3 80
MOV
AL, 1A
MOVE 1A IN AL REGISTER
0402
9A 78 F0 00 F0
CALL
F000:F074
CALL SUBROUTINE
0407
B8 88 80
MOV
[450], AH
[450]31
040B
9A 94 F0 00 F0
MOV
[450], AL
[451]41
040F
F4
HLT
Nvis Technologies Pvt. Ltd.
HALT
86
Nvis 5586A
Example 10: To clear the first line of display. Address
Opcode
Mnemonic
Comment
0400
B3 80
MOV
BL, 80
INPUT PARAMETER OF SUBPROGRAM IS STORED IN BL. B6=0 REPRESENTS 1ST LINE
0402
9A 78 F0 00 F0
CALL
F000:F078
CLEAR THE FIRST LINE.
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Nvis 5586A
Example 11: To write the AL code into cursor location (inside the address of the address counter). Address
Opcode
Mnemonic
Comment
0400
B0 67
MOV
AL, 67
MOVE 67 IN AL REGISTER
0402
9A 88 F0 00 F0
CALL
F000:F088
CALL SUBROUTINE
0407
F4
HLT
Nvis Technologies Pvt. Ltd.
HALT
88
Nvis 5586A
Example 12: To write the AX code into the cursor location. Address
Opcode
Mnemonic
Comment
0400
B0 67
MOV
AX, 4567
MOVE 4567 IN AX REGISTER
0403
9A 88 F0 00 F0
CALL
F000:F088
CALL SUBROUTINE
0408
F4
HLT
Nvis Technologies Pvt. Ltd.
HALT
89
Nvis 5586A
Example 13: Write the AX code into the BL indicated location of LCD, BL indicates the first line or second line. Address
Opcode
Mnemonic
0400
B3 CC
MOV
BL, CC
0402
B8 67 45
MOV
AX, 4567
0405
9A 94 F0 00 F0
CALL
0F000:F09 4
040A
F4
HLT
Nvis Technologies Pvt. Ltd.
Comment MOVE CC IN BL REGISTER
DISPLAY AX. HALT
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Nvis 5586A
Example 14: HEX to ASCII conversion. After changing the HEX in AL to ASCII code, ASCII code is stored in AL. Conversion is valid for 30-39 H & 41-46 H. Address
Opcode
Mnemonic
Comment
0400
B0 41
MOV
AL, 41
; MOVE 41 IN AL REGISTER
0402
9A 70 F0 00 F0
CALL
F000:F070
CALL SUBROUTINE
0407
B8 88 80
MOV
[450], AL
[450]0A
040B
F4
HLT
Nvis Technologies Pvt. Ltd.
HALT
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Nvis 5586A
Example 15: Address
Opcode
Mnemonic
Comment
0400
9A 4C F0 00F0
CALL
F000:F04C
CALL SUBROUTINE
0405
9A 88 F0 00F0
CALL
F000:F088
CALL SUBROUTINE
040A
88 06 59 04
MOV
[459], AL
040E
F4
HLT
;MOVE AL CONTENT IN MEMORY LOCATION 0459 H HALT
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Example 16: Input numerical key, and display at LCD. Address
Opcode
Mnemonic
0:0400
B0 01
MOV
AL, 01
0:0402
9A 44 F0 00 F0
CALL
F000:F044
0:0407
B0 0D
MOV
AL, 0D
0:0409
9A 44 F0 00 F0
CALL
F000:F044
0:040E 0:0413
9A 50 F0 00 F0 9A 54 F0 00 F0
CALL CALL
F000:F050 F000:F054
0:0418
72 F4
JB
040E
0:041A
9A 48 F0 00 F0
CALL
F000:F048
0:041F
E9 EC FF
JMP
040E
0:0422
F4
HLT
Nvis Technologies Pvt. Ltd.
Comment CLEAR DISPLAY COMMANDS TO BE STORED IN AL CALLING INSTRUCTION IS INPUT INTO LCD RAM COMMAND THAT DISPLAY ON/OFF IS STORED IN AL0D= 0000 1101 LETTER BLINKING CURSOR OFF DISPLAY ON DISPLAY ON/OFF ORDER CALL FOR WRITE-IN INSTRUCTION SUBPROGRAM CALL FOR THE READ KEY-IN CALL THE NUMERICAL KEY CODE AND TRANSFER INTO THE SUBPROGRAM IGNORE THE NUMERICAL KEY-IN, RETURN TO ORIGINAL KEY-IN; OTHERWISE EXECUTE THE NEXT INSTRUCTION. KEY-IN CODE ENTER INTO LCD MODULAR HALT
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Nvis 5586A
Example 17: Input functional key, and display at LCD. Address
Opcode
Mnemonic
0:0400
B0 01
MOV
AL, 01
0:0402
9A 44 F0 00 F0
CALL
F000:F044
0:0407
B0 0D
MOV
AL, 0D
0:0409
9A 44 F0 00 F0
CALL
F000:F044
0:040E 0:0413
9A 50 F0 00 F0 9A 60 F0 00 F0
CALL CALL
F000:F050 F000:F060
0:0418
72 F4
JB
040E
0:041A
9A 48 F0 00 F0
CALL
F000:F048
0:041F
E9 EC FF
JMP
040E
0:0422
F4
HLT
Nvis Technologies Pvt. Ltd.
Comment CLEAR DISPLAY COMMANDS TO BE STORED IN AL CALLING INSTRUCTION IS INPUT INTO LCD RAM COMMAND THAT DISPLAY ON/OFF IS STORED IN AL0D= 0000 1101 LETTER BLINKING CURSOR OFF DISPLAY ON DISPLAY ON/OFF ORDER CALL FOR WRITE-IN INSTRUCTION SUBPROGRAM CALL FOR THE READ KEY-IN CALL THE FUNCTIONAL KEY CODE AND TRANSFER INTO THE SUBPROGRAM IGNORE THE FUNCTIONAL KEY-IN, RETURN TO ORIGINAL KEY-IN; OTHERWISE EXECUTE THE NEXT INSTRUCTION. KEY-IN CODE ENTER INTO LCD MODULAR HALT
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Nvis 5586A
Example 18: Input any key, and display at LCD. Address
Opcode
Mnemonic
Comment
0:0400
B0 01
MOV
AL, 01
0:0402
9A 44 F0 00 F0
CALL
F000:F044
0:0407
B0 0D
MOV
AL, 0D
0:0409
9A 44 F0 00 F0
CALL
F000:F044
0:040E 0:0413
9A 50 F0 00 F0 9A 64 F0 00 F0
CALL CALL
F000:F050 F000:F064
0:0418
9A 48 F0 00 F0
CALL
F000:F048
CLEAR DISPLAY COMMANDS TO BE STORED IN AL CALLING INSTRUCTION IS INPUT INTO LCD RAM COMMAND THAT DISPLAY ON/OFF IS STORED IN AL0D= 0000 1101 LETTER BLINKING CURSOR OFF DISPLAY ON DISPLAY ON/OFF ORDER CALL FOR WRITE-IN INSTRUCTION SUBPROGRAM CALL FOR THE READ KEY-IN CALL ANY KEY CODE AND TRANSFER INTO THE SUBPROGRAM CALL SUBROUTINE
0:041D
E9 EC FF
JMP
040E
KEY-IN CODE ENTER INTO LCD MODULAR
0:0420
F4
HLT
Nvis Technologies Pvt. Ltd.
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Nvis 5586A
Serial Communication Nvis 5586A has facility of Serial Interface with PC for any serial Transmission & Reception. Through this facility one can upload & download data from / to PC. For Downloading & Uploading microprocessor lab software is provided. Microprocessor lab is simple software for IBM-PC compatible computers. It allows the user to communicate with the computer through serial port with the facility of downloading & uploading of the data between the computer and the other serial devices. The user can communicate Nvis 5586A trainer with PC using software as below procedure mentioned.
First run the microprocessor lab software setup. After the installation is complete above window is appear on screen. Close the entire programs (like HyperTerminal) which use same com port. In software Nvis 5585 is set as default so its image appears on screen.
For selecting the com port of PC use selection button ―Select Com Port‖ as depicted in above figure. For connecting the Nvis 5586A use button ―Connect to port‖, and that particular button become red. For disconnect click on same button. Nvis Technologies Pvt. Ltd.
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Nvis 5586A
For selecting the trainer click button ―Connect Nvis 5586A‖ and it change to ―Disconnect Nvis 5586A‖.For disconnect the trainer click on same button. Uploading: Microprocessor lab software provides a feature by which the data stored in Nvis 5586A can be stored in the disk of PC. This can be achieved by following the instructions given as below: Example We are storing the program/data of Nvis 5586A from 0000:0400 (Starting address) to 0000:04FF (End address) as an example to demonstrate the UPLOADING features. 1. On Nvis 5586A, execute from F000:F003 using G command as follows:
Press Enter key and the following will come on the display:
Press ‗F7‘ key to come in the OUT mode.
1st location indicates the starting address (F000:0400) and the 2nd location indicates the end address (0400) of the memory area to be transmitted on to the Serial Port. Change this to 0000:0400 to 04FF as follows:
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Nvis 5586A
For uploading the file press ―Capture text‖ button on lower right of window as shown above and another window shown below is appears.
2.
Then give any name with extension .TXT and Click .
3.
After that press key of Nvis 5586A trainer.
4.
Now you will see Data on the ―Response‖ window.
5.
After file transfer complete click on button ―Save File‖ as depicted in above figure.
6.
Now your file is saved in the PC. By this procedure one can upload data in PC.
Downloading: The following procedure is to be adopted for downloading the file from PC to Nvis 5586A. For Down Loading the .KIT or .TXT from PC to Nvis 5586A trainer click button ―Send File‖ on right lower side of screen and screen appear for selecting the file form given location .And follow the procedure given below in section Downloading. Nvis Technologies Pvt. Ltd.
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Nvis 5586A
On Nvis 5586A, execute from F000:F003 using G command as follows:
Press Enter key and the following will come on the display:
Change the location from F000:0400 to 0000:0400. This is the 1st RAM location data will be received from the PC and this address will keep on incrementing on receipt of each Data Byte.
Press Enter key of trainer keyboard and then click on open button on screen appear on PC 1. Then type File to be downloaded i.e. ABC.TXT. 2. After that address field on Nvis 5586A will go on incrementing will display till the last address field at where user have saved ABC.TXT File.
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Nvis 5586A
MASM Macro-Assembler To use MASM Software and download generated file to Trainer please follow these steps Write program given in following format for 8086 Note: While writing Programs for MASM Compiler add prefix Zero (0) and postfix H as shown in figure and use label names.
; Test for 8255 EM03 to Generate Square Wave Output In this program the output will remain high until one half the counts has been completed (for even numbers) and go low for other half of the count. When the counter reaches terminal count, the state of the output is changed and the whole process is repeated. If the count is odd and the output is high the first clock pulse (after the count is loaded) decrements the count by 1. Subsequent clock pulses decrements the clock by 2. The time out, the output goes low and the full count is reloaded. In this way if the count is odd, the output will be high for (N+1)/2 counts and low for (N-1)/2 counts. CODE SEGMENT ASSUME CS: CODE, DS: CODE PROG PROC FAR Address Step-1 0400
Opcode B0 B6
Mnemonic START:
Comment
MOV
AL,B6H
;INIT 8 253 CWR IN MODE-3
0402 Step-2 0404
E6 06
OUT
0 6H,AL
;SET FOR COUNTER -2
B0 0A
MOV
AL ,0AH
;L OAD L SB COUNT I N A CC DATA 0AH
0406 Step-3 0408
E6 04
OUT
04H,AL
;OUT AT COUNTER-2
B0 00
MOV
AL ,00H
;L OAD MSB COUNT IN ACC DATA 00H
040A
E6 04
OUT
04 H,AL
;OUT AT C OU NTER-2
Step-4 040C
EB F1 FF
JMP
S TART
;JUMP TO START
PROG ENDP CODE ENDS Nvis Technologies Pvt. Ltd.
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Nvis 5586A
END Starting Portion and ending portion should be there. In between this we can write any instructions with initial address Org 400H program Note: We can write above file in any window or dos editor directly. And change extension to .ASM Step2>Save above file suppose file name ABC.ASM in same folder where the assembler is saved. Step3>Now do the following steps: Open command prompt window by typing cmd in run command
a window appears as shown below
Now enter into the cross assembler directory for my system it is in C: drive
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Nvis 5586A
Run MASM file in below mention format
Then press ―ENTER‖ key of PC keyboard four times .The PC screen will display SUCCESSFUL 0 WARNING & 0 SERVE ERROR Note: The ASM file should be in same folder where MASM assembler is placed Step4>Run LINK file in below mention format C :> LINK.exe ABC (No need to give any extension.) Then press ―ENTER‖ key of PC keyboard four times PC screen will display SUCCESSFUL 0 WARNING TO STACK SEGMENT. Step 5>Run EXE2BIN file in below mention format.
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C:>EXE2BIN.exe ABC (No need to give any extension) Then ENTER key of PC keyboard once. It will generate binary file of your program Step 6>Now run Ascbin.exe in the below mention format C:>Ascbin.exe then ENTER(from PC keyboard) This is a program to convert ASCII file to bin file & bin file to ASCII file After pressing ENTER it will show Press to exit program Press & to exit now Press & to continue Now Press C for continues. Step 7> Window will open asking for 1) BIN to ASCII 2) ASCII to BIN Select no 1 for BIN to ASCII then ENTER (from PC keyboard) Step 8>Again window will open asking for Enter the BIN filename? Enter the filename with extension ABC.bin Enter the BIN filename? ABC.bin After pressing ENTER it will again prompt for ASCII filename Enter the ASCII filename? ABC.ASC Note: In these fields extensions are necessary Enter origin? 0000:0400 then ENTER (from PC keyboard) Our ASCII file will be generated named ABC.asc down load this file into M8086—02 Connect HyperTerminal with kit then select transfer then send text file. Our file will be down loaded into kit.
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Sample Programs The monitor software of Nvis 5586A resides in 128K Byte of EPROM. The system software has certain useful routines, which can be utilized by the user for developing his programs. The address of these routines is given in the Subroutine chapter. Example The following sample programs are given here to make the user familiarize with the operation of Nvis 5586A. 1. 16-Bit Addition. 2. 16- Bit Subtraction. 3. 16-Bit Multiplication. 4. 32- Bit Division. 5. Program for addition of two numbers and display it on LCD. 6. Moving data form 500 memory locations to 600 memory locations. 7. Program for moving string form one memory location to other. 8. Searching a number in given array. 9. Program for comparing two strings 10. Program for moving the string for one memory location to other location with changed segment address. 11. To ADD two Binary numbers each 8 Bytes long 12. To find the maximum no. in a given string (16 Bytes long) and store it in location 0510. 13. To sort a string of a no. of bytes in descending order. 14. To multiply an ASCII string of eight numbers by a single ASCII digit. 15. To Divide a String of Unpacked ASCII Digits 16. A Data string of no. of bytes (to be specified in CX reg.) is located from the starting address 0500. This data string is to be converted to its equivalent 2' S complement Form and the result is to be stored from 0600 onwards. 17. Serial Port Programming 18. 8259 Interrupt Controller 19. BCD Addition of two bytes. 20. BCD Subtraction of two bytes. 21. Find whether a no is even or odd. 22. Find whether a no is positive or negative. 23. Find whether a no is even or odd and display it on LCD.
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24. Find whether a no is positive or negative and display it on LCD. 25. Hex to ASCII conversion (valid for 00 to FF) 26. Logical AND operation of two bytes. 27. Logical OR operation of two bytes. 28. Logical NOT operation of two bytes 29. Logical XOR operation of two bytes 30. Shift logical left 31. Shift logical right 32. Rotate Right without Carry 33. Rotate Left without Carry 34. Shift Arithmetic Right (SAR) 35. Rotate Right through Carry 36. Rotate Left with Carry 37. Software triggered strobe (8253) 38. Write a program to calculate N3= ÖN12 + N22 32 bit integer value stored at 300 H and 304H respectively. The result should be store at 308H. 39. Write a program to calculate Sin (Z) where Z - is defined in degrees. 40. Program for Port A, B, C of 8255-I generating square wave output at Connector 8255-I. Note: Programs in Assembly language directly compile on Trainer Assembler while writing program in Assembly language in Trainer do not add prefix Zero (0) or any postfix like H as shown in figure and use address of label names in place of Label name in trainer.
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Program 1: 16-Bit Addition. Address
Opcode
Mnemonic
400 403 406
B8 34 12 05 78 56 88 26 20 04
MOV AX,1234 ADD AX,5678 MOV [420],AH
40A
88 06 21 04
MOV [421],AL
40E
F4
HLT
Comment LOAD 1234 IN AX ADD 5678 TO CONTENT OF AX LOAD RESULT ON RAM LOCATION 420 LOAD RESULT ON RAM LOCATION 421 HLT
Input: 1234 + 5678 Result: Result at 420 and 421 = 68AC
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Program 2: 16- Bit Subtraction. Address
Opcode
Mnemonic
400 403
B8 43 43 2D 21 21
MOV AX,4343 SUB AX,2121
406
88 26 20 04
MOV [420],AH
40A
88 06 21 04
MOV [421],AL
40E
F4
HLT
Comment LOAD 4343 TO AX SUB CONTENT OF AX TO 2121 LOAD RESULT ON RAM LOCATION 420 LOAD RESULT ON RAM LOCATION 421
Input: 4343 - 2121 Result: Result at 420 and 421= 2222
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Program 3: 16-Bit Multiplication. Address
Opcode
Mnemonic
400 403 406 408
B8 DC FE BB 98 BA F7 E3 88 36 50 04
MOV AX, FEDC MOV BX, BA98 MUL BX MOV [450],DH
40c
88 16 51 04
MOV [451],dl
410
88 26 52 04
MOV [452],AH
414
88 06 53 04
MOV [453],AL
418
F4
HLT
Input:
Comment LOAD FEDC TO AX LOAD BA98 TO BX LOAD RESULT TO 450 MEMORY LOCATION LOAD RESULT TO 451 MEMORY LOCATION LOAD RESULT TO 452 MEMORY LOCATION LOAD RESULT TO 453 MEMORY LOCATION HALT
FEDC*BA98
Result: 450 & 451 = B9C3 452 & 453 = 2AA0.
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Program 4: 32- Bit Division. Address 400 403 406 408 40B 40F 413 417 41B
Opcode BA 00 00 B8 FF FF B9 FF FF F7 F1 88 26 50 04 88 06 51 04 88 36 52 04 88 16 53 04 F4
Input: Dividend: Divisor:
Mnemonic MOV DX,0000 MOV AX,FFFF MOV CX, FFFF DIV CX MOV [450],AH MOV [451],AL MOV [452],DH MOV [453],DL HLT
Comment LOAD DIVIDEND TO DX LOAD TO AX LOAD DIVISOR TO CX LOAD RESULT TO 450 RAM LOCATION LOAD RESULT TO 451 RAM LOCATION LOAD RESULT TO 452 RAM LOCATION LOAD RESULT TO 450 RAM LOCATION HALT
DX = 0000 AX = FFFF CX = FFFF
Result: 450 & 451 = 0001 452 & 453 = 0000
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Program 5: Addition of two number and display it on LCD. Address
Opcode
Mnemonic
400 403
B8 30 00 05 30 00
MOV AX,30 ADD AX,30
MOVE DATA IN AX ADD DATA TO CONTENT OF AX
Comment
406
88 C2
MOV DL,AL
408 40D
9A 78 F0 00 F0 88 E6
CALL F000:F078 MOV DH,AH
40F 414
9A 68 F0 00 F068 75 F2
CALL F000:F068 JNE 0408
416
F4
HLT
MOVE LOWER 8 BIT OF AX IN TO LOWER 8 BIT OF DX CALL TO DISPLAY FUNCTION MOVE HIGHER 8 BIT OF AX TO HIGHER 8 BIT OF DX CALL TO LCD DISPLAY FUNCTION UNCONDITIONAL JUMP TO 408 MEMORY LOCATION HALT
Here the data is break in to part because we can transfer 8 bit at a time on LCD using given function Operand 30+30 Result =60
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Program 6: Moving data form 500 memory locations to 600 memory locations. Address 400 403 406 409 40B 40D 40E 40F 410 412
Opcode BE 0005 BF 0006 B9 0F 00 8B 04 89 05 46 47 49 75 F7 F4
Mnemonic MOV SI, 500 MOV DI, 600 MOV CX, 000F MOV AX, [SI] MOV [DI],AX INC SI INC DI DEC CX JNE 409 HLT
Comment STARTING LOCATION DESTINATION LOCATION NO BYTE TO TRANSFER
INCREMENT SI INCREMENT DI DECREMENT CX HALT
Note: Press F7 button of keyboard (connected to techbook) and then press D, enter address (from where data is to be entered), press enter and start feeding data. Enter the data at memory location 500. Ex-01,02,03,04,05,06,07,08,09,10,11,12,13,14,15,16 And after running the code above data is transfer to memory location 600.
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Program 7: Moving a string form one memory location to other memory location. Address
Opcode
Mnemonic
400
8B 0E 00 05
MOV CX,[500]
404 408 40C 40D 40E 40F
8D 36 50 05 8D 3E 00 06 FC F3 A4 F4
LEA SI,[550] LEA DI,[600] CLD REP MOVSB HLT
Comment SIZE OF STRING IS STORE AT 500 LOCATION LOAD EFFECTIVE ADDRESS LOAD EFFECTIVE ADDRESS CLEAR DIRECTION FLAG MOVE STRING BYTE HALT
1. Enter the size of string on 500 memory location 2. Enter the string on 550 memory location 3. String copy to 600 memory location
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Program 8: Searching a number in given array. Address 400 403 406 408 409 40B 40C 40E 410 411 413 415 417 419 41B 41D 41F
Opcode BE 00 05 BF 00 06 8A 0C 46 8A 04 46 3A 04 74 09 46 FE C9 75 F7 B0 FF 88 04 8A 1C 88 1D CD 02 F4
Mnemonic
END:
Comment
MOV SI,500 MOV DI,600 MOV CL,[SI] INC SI MOV AL,[SI] INC SI CMP AL,[SI] JZ END INC SI DEC CL JNZ 40C MOV AL,0FFH MOV [SI],AL MOV BL,[SI] MOV [DI],BL INT 02H HLT
Note: Press F7 button of keyboard (connected to techbook) and then press D, enter address (from where data is to be entered), press enter and start feeding data. Input: 500 = 04H (Length of Array) 501 = 35H (Element to be search) 502 = 18H 503 = 35H 504 = 54H 505 = 72H Note: The element which one we want to search is stored at location 501h & The number of elements in an array is stored at location 500H. Result: 1. If the element which one we want to search is in an array, then it will be store at the location [600] i.e. 35 is stored 2. If the element which one we want of search is not in an array, then FF will be stored at location 600 to indicate ERROR condition.
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Program 9: Comparing two strings. Address
Opcode
400 404 408 40B 40C 40D 40E 410 412 416 417 419
8D 36 00 05 8D 3E 50 05 B9 03 00 FC F3 A6 75 07 B0 01 88 06 00 F4 B0 00 88 06 00 06
LEA SI, [500] LEA DI,[550] MOV CX,0003 CLD REPE CMPSB JNE 417 MOV AL,01 MOV [600], AL HLT MOV AL,00 MOV [600], AL
Mnemonic
41D
F4
HLT
Comment LOCATION OF 1 STRING LOCATION OF 2 STRING SIZE OF STRING
1 IF STRING ARE EQUAL STORE RESULT ON 600 LOCATION
STORE 0 RESULT ON 600 LOCATION IF NOT EQUAL
Note: Press F7 button of keyboard (connected to techbook) and then press D, enter address (from where data is to be entered), press enter and start feeding data. Enter the string at address 500. Ex-AA,BB,CC Enter the 2 string at address 550. Ex-AA,BB,CC If both string are same then result is 01 at 600 location and string are not matching then 00 at 600 memory location
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Program 10: Moving the string for one memory location to other location with changed segment address. This program is entered on 400 memory location but with different segment address. Here DS register is initialized to 10 and SI to 400, DI by 450, so both DI and SI added with DS and form the actual physical address. DS= 10H =10000B SI= 400H =10000000000B DI= 450H =10001010000B To form the actual physical address, segment address is shifted by 4 bit position and then added with offset address 10H
