Multiplexer,decoder and encoder.pdf

ECE 301 – Digital Electronics

Multiplexers, Decoders and Encoders (Lecture #16)

The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6th Edition, by Roth and Kinney, and were used with permission from Cengage Learning.

Multiplexers

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Multiplexers ●

●

A multiplexer has –

2n data inputs

–

n control inputs

–

1 output

A multiplexer routes (or connects) the selected data input to the output. –

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The value of the control inputs determines the data input that is selected. ECE 301 - Digital Electronics

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Multiplexers

Data inputs Control input Spring 2011

Z = A′.I0 + A.I1 ECE 301 - Digital Electronics

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Multiplexers

1

2

MSB

20

LSB

A 0

B 0

Z I0

0

1

I1

1

0

I2

1

1

I3

m0 = A'.B' m1 = A'.B m2 = A.B' m3 = A.B

Z = A′.B'.I0 + A'.B.I1 + A.B'.I2 + A.B.I3 Spring 2011

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Multiplexers

22

MSB

20

A

B

C

Z

0

0

0

I0

m0

0

0

1

I1

m1

0

1

0

I2

0

1

1

I3

m2 m3

1

0

0

I4

1

0

1

I5

m4 m5

1

1

0

I6

m6

1

1

1

I7

m7

LSB

Z = A′.B'.C'.I0 + A'.B'.C.I1 + A'.B.C'.I2 + A'.B.C.I3 + A.B'.C'.I0 + A.B'.C.I1 + A'.B.C'.I2 + A.B.C.I3 Spring 2011

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Multiplexers

2n-1

20

Z = Σ mi.Ii Spring 2011

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Decoders

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Decoders ●

A decoder has –

n inputs

–

2n outputs n

●

A decoder selects one of 2 outputs by decoding the binary value on the n inputs.

●

The decoder generates all of the minterms of the n input variables. –

Exactly one output will be active for each combination of the inputs. What does “active” mean?

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Decoders Z0

A

Z1 Z2

2-to-4 Decoder

msb

B

Zi = mi

Z3 active-high output

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A

B

Z0

Z1

Z2

Z3

0

0

1

0

0

0

0

1

0

1

0

0

m0 m1

1

0

0

0

1

0

m2

1

1

0

0

0

1

m3

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Decoders Z0

A

Z1 Z2

2-to-4 Decoder

msb

B

Zi = (mi)' = Mi

Z3 active-low output

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A

B

Z0

Z1

Z2

Z3

0

0

0

1

1

1

0

1

1

0

1

1

M0 M1

1

0

1

1

0

1

M2

1

1

1

1

1

0

M3

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Decoders msb

3-to-8 Decoder

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Decoder with Enable A

Z0

2-to-4 Decoder with Enable

B En

Z1 Z2 Z3

active-high enable

enabled

disabled Spring 2011

En

A

B

Z0

Z1

Z2

Z3

1

0

0

1

0

0

0

1

0

1

0

1

0

0

1

1

0

0

0

1

0

1

1

1

0

0

0

1

0

x

x

0

0

0

0

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Decoder with Enable A

Z0

2-to-4 Decoder with Enable

B En

Z1 Z2 Z3

active-low enable

enabled

disabled Spring 2011

En

A

B

Z0

Z1

Z2

Z3

0

0

0

1

0

0

0

0

0

1

0

1

0

0

0

1

0

0

0

1

0

0

1

1

0

0

0

1

1

x

x

0

0

0

0

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Encoders

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Encoders ●

An encoder has –

2n inputs

–

n outputs

●

Outputs the binary value of the selected (or active) input.

●

Performs the inverse operation of a decoder.

●

Issues

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–

What if more than one input is active?

–

What if no inputs are active? ECE 301 - Digital Electronics

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Encoders Y0

A

Y1 Y2

4-to-2 Encoder

B

Y3

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Y0

Y1

Y2

Y3

A

B

1

0

0

0

0

0

0

1

0

0

0

1

0

0

1

0

1

0

0

0

0

1

1

1

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Priority Encoders ●

If more than one input is active, the higher-order input has priority over the lower-order input. –

●

The higher value is encoded on the output

A valid indicator, d, is included to indicate whether or not the output is valid. –

Output is invalid when no inputs are active

–

d=0 Output is valid when at least one input is active ●

●

d=1 Why is the valid indicator needed?

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Priority Encoders msb 3-to-8 Priority Encoder Valid bit

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Circuit Design using Multiplexers

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n

Using a 2 -input Multiplexer ●

Use a 2n-input multiplexer to realize a logic circuit for a function with 2n minterms. –

n = # of control inputs = # of variables in the function

●

Each minterm of the function can be mapped to a data input of the multiplexer.

●

For each row in the truth table, for the function, where the output is 1, set the corresponding data input of the multiplexer to 1. –

●

That is, for each minterm in the minterm expansion of the function, set the corresponding input of the multiplexer to 1.

Set the remaining inputs of the multiplexer to 0.

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n

Using an 2 -input Mux

Example: Using an 8-to-1 multiplexer, design a logic circuit to realize the following Boolean function F(A,B,C) = Σm(2, 3, 5, 6, 7)

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n

Using an 2 -input Mux

Example: Using an 8-to-1 multiplexer, design a logic circuit to realize the following Boolean function F(A,B,C) = Σm(1, 2, 4)

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Using an 2 ●

●

-input Multiplexer

Use a 2(n-1)-input multiplexer to realize a logic circuit for a function with 2n minterms. –

●

(n-1)

n – 1 = # of control inputs; n = # of variables in function

Group the rows of the truth table, for the function, into 2(n-1) pairs of rows. –

Each pair of rows represents a product term of (n – 1) variables.

–

Each pair of rows is mapped to one data input of the mux.

Determine the logical function of each pair of rows in terms of the remaining variable.

If the remaining variable, for example, is x, then the Spring 2011 possible values are x, x', 0, and 1. –

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(n-1)

Using an 2

-input Mux

Example: F(x,y,z) = Σm(1, 2, 6, 7)

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(n-1)

Using an 2

-input Mux

Example: F(A,B,C,D) = Σm(1,3,4,11,12–15)

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Using a 2

(n-2)

-input Mux

A similar design approach can be implemented using a 2(n-2)-input multiplexer.

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Circuit Design using Decoders

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Using an n-output Decoder ●

Use an n-output decoder to realize a logic circuit for a function with n minterms.

●

Each minterm of the function can be mapped to an output of the decoder.

●

For each row in the truth table, for the function, where the output is 1, sum (or “OR”) the corresponding outputs of the decoder. –

●

That is, for each minterm in the minterm expansion of the function, OR the corresponding outputs of the decoder.

Leave remaining outputs of the decoder unconnected.

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Using an n-output Decoder

Example: Using a 3-to-8 decoder, design a logic circuit to realize the following Boolean function F(A,B,C) = Σm(2, 3, 5, 6, 7)

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Using an n-output Decoder

Example: Using two 2-to-4 decoders, design a logic circuit to realize the following Boolean function F(A,B,C) = Σm(0, 1, 4, 6, 7)

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Hierarchical Design

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Hierarchical Design ●

●

Several issues arise when designing large multiplexers and decoders (as 2-level circuits). –

Number of logic gates gets prohibitively large

–

Number of inputs to each logic gate (i.e. fan-in) gets prohibitively large

Instead, design both hierarchically

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–

Use smaller elements as building blocks

–

Interconnect building blocks in a multi-tier structure ECE 301 - Digital Electronics

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Hierarchical Design

Exercise: Design an 8-to-1 multiplexer using 4-to-1 and 2-to-1 multiplexers only.

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Hierarchical Design

Exercise: Design a 16-to-1 multiplexer using 4-to-1 multiplexers only.

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Hierarchical Design

Exercise: Design a 4-to-16 decoder using 2-to-4 decoders only.

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Questions?

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