Module 2_AVR_ATMega32_Architecture.pptx

Module 2

Chip

Introduction to AVR ATMega32 Architecture Plastic case

Pins

rocessor rc Organization • Architecture  – attributes of programmer

tecture

a

system

visible

to

a

 – these attributes have a direct impact on the logical execution of a program • Instruction set, number of bits used for data representation, I/O mechanisms, addressing techniues  – !esign issue" #hether a computer #ill have a speci$c instruction%

e%g% Is there a multiply instruction&

rocessor rc Organization • Architecture  – attributes of programmer

tecture

a

system

visible

to

a

 – these attributes have a direct impact on the logical execution of a program • Instruction set, number of bits used for data representation, I/O mechanisms, addressing techniues  – !esign issue" #hether a computer #ill have a speci$c instruction%

e%g% Is there a multiply instruction&

rocessor rc Organization

tecture

• Organization  – the operational units and their interconnections interconnectio ns that reali(e the architectural archite ctural speci$cations • )ho# features are implemented*  – hard#are details that are transparent to the programmers  – +ontrol signals, interfaces, memory technology  – !esign issue" ho# this instruction is to be implemented% • Is there a hard#are multiply unit or is it done by repe repeated ated addition&

rocessor rc Organization

tecture

• Many computer manufacturers o.er a family of computer models, all #ith the same architecture but #ith diferences in organization% •  his gives code compatibility compatibility )at least bac#ards* bac#ards*  – ll Intel x3 family share the same basic architecture  – he I4M ystem/'50 family share the same basic architecture • n architecture may survive many years, but its organi(ation changes #ith the changing technology%

6%g% the I4M ystems/'50 architecture, #ith fe#

Introduction to Atmel AVR • Atmel Corporation is a semiconductors, founded in 19%

manufacturer

of

• tmel introduced the $rst -bit :ash microcontroller in 199', based on the 081 core% • In 1993, a design o;ce #as started in rondheim, series of products% • Its products include microcontrollers )including 081 derivatives and 91M and 91+? >M-based micros*, and its o#n tmel => and =>'2 architectures%

Introduction to Atmel AVR •  he =>  architecture #as conceived by t#o students at the + oscillator

Port 0

Port A >eference voltagevoltage for upply for!+ !+ and port% +onnect it to =++

Port C

ATMega32 Pin out & 0escriptions

ATMega32 Pin out & 0escriptions

ATMega32 Pin out & 0escriptions !igital IO is the most fundamental mode of connecting a M+F to external #orld% he interface is done using #hat is called a ?O>% A port is the point *here internal data 1rom MC+ chip comes out or e;ternal data goes in% hey are present is form of ?I.it data addressing allo*ing it to address 2 4@  @BB3@ uni%ue addresses$ as three separate on>chip memories • 2 "RAM • 6 .its *ide used to store data • 4 PROM • 6 .its *ide used 1or persistent data storage • 32 /lash • 4@ .its *ide used to store

ega Memor'

rogrammer

4$ 2 "RAM  – Gor temporary data storage  – Memory is lost #hen po#er is shut o. )volatile*  – Gast read and #rite 2$ 4 PROM  – Gor persistent data storage  – Memory contents are retained #hen po#er is o. )non-volatile*  – Gast readK slo# #rite  – +an #rite individual bytes 3$ 32 /lash Program Memor'  – Fsed to store program code  – Memory contents retained #hen po#er is o. )nonvolatile*  – Gast to readK slo# to #rite  – +an only #rite entire

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ega Memor'

rogrammer

• => microcontrollers are @arvard architecture% his means, that in this architecture are separate memory types )program memory and data memory* connected #ith distinct buses% uch memory architecture allo#s processor to access program memory and data memory at the same time% his increases performance of M+F comparing to +I+ architecture, #here +?F uses same bus for accessing program memory and data memory% T'pe

/lash

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RAM

/D#0 type "ize,  itsRAM#0 • 6ach memory has o#n tmega L0GGG  L08G address space"

PROM

"ize, 

D#0

"ize, 

1

L1GG

0%8

Atmega3 2

E3///

32

E76B/

2

E3//

4

tmega3

L5GGG

3

L10GG



L5GG

2

tmega12

LGGGG

2

L 0

L

ega rogrammer Program Memor' /lash :a'out

Memor'

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ega Memor'

rogrammer

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ata

PROM • mega'2 contains 102 bytes of data 66?>OM memory% • It is organi(ed as a separate data space, in #hich single bytes can be read and #ritten% •  he 66?>OM has an endurance of at least 100,000 #rite/erase cycles% • !i.erent chip si(e Chip 'teshave Chip di.erent 'tes Chip of 66?>OM 'tes memory mega

812

mega13

812

mega'2

102

mega3

20

mega12

093

mega283 >

093

mega30

093

mega120

093

mega2830 093

ega Memor'

rogrammer

 he data memory is composed of three parts" • FPRs

(general purpose registers),

• "pecial

/unction Registers ("/Rs), and

• Internal

"RAM$

data

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ata

ega rogrammer Internal "RAM

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• Internal data >M is #idely used for storing data and parameters by => programmers and + compilers% • 6ach location of the >M can be accessed directly by its address% • 6ach location is  bit #ide and can be used to store any data #e #ant% • i(e of >M is vary from chip to chip, even among members of the same family%

ega Registers

rogrammer

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ega rogrammer Registers (FPRs)  he fast-access >egister $le contains '2 x -bit general purpose #oring registers #ith a single cloc cycle access time% his allo#s single-cycle rithmetic Dogic Fnit )DF* operation% In a typical DF operation, t#o operands are output from the >egister $le, the operation is executed,

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ega rogrammer Registers (FPRs) Cix of the '2 registers can be used as three 13-bit indirect address register pointers for !ata pace addressing Nenabling e;cient address calculations% One of the these address pointers can also be used as an address pointer for loo up tables in Glash ?rogram memory%  hese added function registers are the 13-bit

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ega rogrammer Registers (FPRs)

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 he

>23%%>'1 registers have some added functions to their general purpose usage% hese registers are 13-bit address pointers for indirect addressing of the !ata pace% he three indirect address registers , P, and  are sho#n above%



In the di.erent addressing modes these address registers have functions as $xed displacement, automatic increment, and automatic decrement

ega rogrammer Registers ("/Rs) •

•

• •

•

 he I/O memory is dedicated to speci$c functions such as status register, timers, serial communication, I/O ports, !+ and etc% Gunction of each I/O memory location is $xed by the +?F designer at the time of design% )because it is used for control of the microcontroller and peripherals* => I/O memory is made of  bit registers% ll of the =>s have at least 3 bytes of I/O memory location% )his 3 bytes section is called standard I/O memory* In other microcontrollers, the I/O

Address I/O

Mem.

$00

$20

Name

o e9 Address

Name

I /O

Mem.

TWB

$!(

$'( $') $'-

PTB

Address

Name

I/O

Mem.

P1NB

$2B

$#B

DDB

$2C

$#C

TCNT!

$2D

$#D

TCNT!&

C!A&

$0!

$2!

TW"

$!)

$02

$22

TWA

$!-

$0'

$2'

TWD

$!.

$'.

P1NA

$2/

$#/

TCC!B

$'A

DDA

$2

$#

TCC!A

$'0

$%0

"1

$0#

$2#

ADC

$!A

$0%

$2%

ADC&

$2(

ADC"A

$'B $'C

PTA

$0(

$!B $!C

$'D

//D

$'!

$%!

//C

CD

$0)

$2)

AD*+,

$!D

$0-

$2-

AC"

$!/

$'/

//A

$'2

$%2

$0.

$2.

+B

$!

$'

//A&

$''

$%'

TCC0

$0A

$2A

+C"B

+BC

$'#

$%#

*C+C"

$0B

$2B

+C"A

*C+C

$0C

$2C

$0D

$2D

$0/ $0

"CCA TCNT0

$20

$#0

+B&

$'%

$%%

+D

$2!

$#!

WDTC

$'(

$%(

TWC

"PC

$22

$#2

A""

$')

$%)

"P*C

$2/

"P"

$2'

$#'

C2

$'-

$%-

T1

$2

"PD

$2#

$##

TCNT2

$'.

$%.

T1*"3

$!0

$'0

P1ND

$2%

$#%

TCC2

$'A

$%A

41

$!!

$'!

DDD

$2(

$#(

1C!

$'B

$%B

41C

$!2

$'2

PTD

$2)

$#)

1C!&

$'C

$%C

C0

$!'

$''

P1NC

$2-

$#-

C!B

$'D

$%D

"P

$!#

$'#

DDC

$2.

$#.

C!B&

$'/

$%/

"P&

$!%

$'%

PTC

$2A

$#A

C!A

$'/

$%/

"/4

ega rogrammer Registers ("P)

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ega rogrammer Registers ("P)

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ega rogrammer Registers (PC)

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Program counter (PC, 4@>.it) 

@olds address of next instruction to be executed



utomatically incremented DF executes an instruction

program #hen

the

ega rogrammer Registers ("R)

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ega rogrammer Registers ("R)

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ega rogrammer Registers ("R)

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ega rogrammer Registers ("R)

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ega rogrammer Registers ("R)

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