Modern Digital Electronics- R P Jain- Solution Manual
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Solution Manual for Modern Digital Electronics Third Edition
R P Jain
CHAPTER 1 1.1 (a) Analog. The output of a pressure gauge is proportional to the pressure being measured and can assume any value in the given range. (b) Digital. An electric pulse is produced for every person entering the exhibition using a photoelectric device. These pulses are counted using a digital circuit. (c) Analog. The reading of the thermometer is proportional to the temperature being measured and can assume any value in the given range. (d) Digital. Inputs are given with the help of switches, which are converted into digital signals 1 and 0 corresponding to the switch in the ON or OFF position. These signals are processed using digital circuits and the results are displayed using digital display devices. (e) Analog. It receives modulated signals which are analog in nature. These signals are processed by analog circuits and the output is again in the analog form. (f) Digital. It has only two possible positions (states), ON and OFF. (g) Digital. An electric pulse is produced for every vote cast by pressing of switch of a candidate. The pulses thus produced for each candidate are counted separately and also the total number of votes polled are counted. 1.2 (a) (i)
(iii)
S1
S2
Bulb
OFF OFF ON ON
OFF ON OFF ON
OFF OFF OFF ON
S
Bulb
OFF ON
ON OFF
S1
S2
Bulb
0 0 1 1
0 1 0 1
0 0 0 1
S
Bulb
0 1
1 0
(ii)
(iv)
S1
S2
Bulb
OFF OFF ON ON
OFF ON OFF ON
OFF ON ON ON
S1
S2
Bulb
OFF OFF ON ON
OFF ON OFF ON
OFF ON ON OFF
S1
S2
Bulb
0 0 1 1
0 1 0 1
0 1 1 1
S1
S2
Bulb
0 0 1 1
0 1 0 1
0 1 1 0
(b) (i)
(iii)
(c)
(i) AND
(ii) OR
(ii)
(iv)
(iii) NOT
(iv) EX-OR
1.3 1 Input A 0
0
1
2
3
4
5
t(ms)
0
1
2
3
4
5
t(ms)
1 Input B 0
1 AND 0
1 OR 0
1 NAND 0
1 NOR 0
1 EX-OR 0
1.4 Inputs A
B
(a)
0 0 1 1
0 1 0 1
1 0 0 0
The operations performed are (a) NOR (b) NAND
(c) AND 2
Outputs of (b) (c) 1 1 1 0
(d) OR
0 0 0 1
(d) 0 1 1 1
1.5
For Fig. 1.6 (a)
(c)
A
Y
(b)
A
B
AB
Y
0 1
1 0
0 0 1 1
0 1 0 1
1 1 1 0
0 0 0 1
A
B
A
B
Y
0 0 1 1
0 1 0 1
1 1 0 0
1 0 1 0
0 1 1 1
A
Y
(b)
0 1
1 0
A
B
0 0 1 1
0 1 0 1
For Fig. 1.8 (a)
(c)
1.6
(a) NAND, NOR (c) NAND
1.7
(a)
A
B
A+B
Y
0 0 1 1
0 1 0 1
1 0 0 0
0 1 1 1
A
B
Y
1 1 0 0
1 0 1 0
0 0 0 1
(b) AND (d) OR
Inputs A
B
0 0 1 1
0 1 0 1
AB
AB
Output Y
0 0 1 0
0 1 0 0
0 1 1 0
(b) EX–OR (c) A
Y
B 3
Y = AB + A B
(d) \
Y = AB + A B = AB ⋅ A B
Y = Y = AB ⋅ AB = Y1 ⋅ Y2 where,
Y1 = AB
Y2 = AB
and
A Y1 Y
B
1.8
1.9
Y2
For simplicity, we shall consider 2-input gates, but the results are equally valid for any number of inputs. In the positive logic system, the higher of the two voltages is designated as 1 and the lower voltage as 0. On the other hand in the negative logic system, the lower of the two voltage is designated as 1 and the higher voltage as 0. Therefore, if 1s and 0s are interchanged, the logic system will change from positive to negative and vice-versa. (a) In the truth table of positive logic AND gate replace all zeros by ones and all ones by zeros. The resulting truth table is same as that of the OR gate. Similarly, if all ones and zeros are interchanged in the truth table of the OR gate, the resulting truth table will be same as that of the AND gate. (b) Repeat part (a) for NAND and NOR gates. (a) A + A B + A B = (A + A B ) + A B = A (1 + B ) + A B = A × 1 + AB = A + AB = (A + A ) (A + B) = A + B (b) AB + A B + A B = (A + A ) B + A B = B + A B = (B + A ) (B + B ) = A +B (c) A BC + A B C + AB C + ABC = A BC + A B C + AB (C + C ) = A BC + A B C + AB = A BC + A (B + B C) = A BC + A (B + B ) (B + C) 4
= A BC + AB + AC = C (A + A B) + AB = C (A + A ) (A + B) + AB = C (A + B) + AB = AB + BC + CA 1.10 (a) A
B
AB
AB
A + A B + AB
A+B
0 0 1 1
0 1 0 1
0 1 0 0
0 0 1 0
0 1 1 1
0 1 1 1
(b) A
B
AB
AB
AB
AB + A B + A B
A +B
0 0 1 1
0 1 0 1
0 0 0 1
0 1 0 0
1 0 0 0
1 1 0 1
1 1 0 1
(c)
1.11
A
B
C
A BC
AB C
AB C
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 0 0 1 0 0 0 0
0 0 0 0 0 1 0 0
0 0 0 0 0 0 1 0
ABC LHS 0 0 0 0 0 0 0 1
0 0 0 1 0 1 1 1
AB
BC
CA
RHS
0 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 1
0 0 0 1 0 1 1 1
(a) The realization of LHS requires, two inverters, two 2-input AND gates, and one 3-input OR gate, whereas the realization of RHS requires only one two input OR gate.
A A B B
(i)
(ii) 5
(b) The realization of LHS requires two inverters, three 2-input AND gates and one 3-input OR gate, whereas the realization of RHS requires only one inverter and one 2-input OR gate. A A B
B
(ii)
(i)
(c) The realization of LHS requires three inverters, four 3-input AND gates and one 4-input OR gate, whereas the realization of RHS requires only three 2-input AND gates and one 3-input OR gate.
A
B C
(i) A B
C
(ii)
1.12
(a) AB + CD = AB + CD = AB ⋅ CD
6
(b) (A + B) (C + D) = ( A + B) ⋅ ( C + D )
= ( A + B) + ( C + D ) (i) The left hand side of (a) can be realized by using two 2-input AND gates followed by one 2-input OR gate, while the right hand side is realizable by two 2-input NAND gates followed by another 2-input NAND gate. Hence an AND-OR configuration is equivalent to a NANDNAND configuration. (ii) The left hand side of (b) is realizable by two 2-input OR gates followed by a 2-input AND gate, while the right hand side is realizable by two 2-input NOR gates followed by another 2-input NOR gate. Hence an OR-AND configuration is equivalent to a NOR-NOR configuration. 1.13 (a)
A
A
B
B Y
C
C
D
D
Y
(i) (b)
(ii)
A
A
B
B Y
C
C
D
D
Y
(i)
(ii)
1.14 (a) Since A × B = B × A Therefore, the AND operation is commutative. If A × (B × C) = (A × B) × C, then the AND operation is associative. This can be proved by making truth table as given below: A
B
C
(A × B) × C
A × (B × C)
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 1
7
Since the last two columns of the truth table are identical, which proves that the AND operation is associative. (b) Since, A + B = B + A, therefore, OR operation is commutative. The associative property requires A + (B + C) = (A + B) + C which can be proved by making the truth table in a way similar to the truthtable of (a) above (c) Since, A Å B = B Å A, which means the EX-OR operation is commutative. The associative property requires (A Å B) Å C = A Å (B Å C) This can be proved by making truth table 1.15
(a) Since = A ⋅ B = B ⋅ A , therefore, the NAND operation is commutative. To verify whether the NAND operation is associative or not, we prepare the truth table as given below. From the Table we observe that the last two columns are not identical, which means A ⋅ ( B ⋅ C ) ≠ ( A ⋅ B) ⋅ C
This shows that the NAND operation is not associative. A
B
C
A ⋅ ( B ⋅ C)
( A ⋅ B) C
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
1 1 1 1 0 0 0 1
1 0 1 0 1 0 1 1
(b) Since, A + B = B + A , which means the NOR operation is commutative. By making a truth table similar to the truth table of (a) above we can verify that
( A + B) + C ≠ A + ( B + C ) 1.16 1.17
Therefore, the NOR operation is not associative. Two possible realizations are given on page 9: (i) If only one of the variables is 1 and all others are zero, then (1 Å 0) Å 0 Å 0 Å . . . = 1 Å 0 Å 0 Å . . . =1 Å0=1 (ii) If only two of the variables are 1 and all others are zero, then (since EXOR operation is commutative and associative) (1 Å 1) Å 0 Å 0 Å 0 Å . . . = 0 Å 0 Å 0 Å 0 Å . . . = 0 (iii) Similarly, if only three of the variables are 1, then (1 Å 1) Å 1 Å 0 Å 0 Å . . . =0 Å1Å0Å0Å0Å... =1 8
A
AÅB
B
AÅBÅC
C Y AÅBÅCÅD
D or A
AÅB
B Y AÅBÅCÅD
C D
CÅD Fig. 1.17
1.18
1.19
In the same way we can try higher number of ones. It is obvious from the above discussion that Z = 1, if an odd number of variables are 1 and Z = 0 if an even number of variables are 1. Since a logical variable can assume one of the two values (0 or 1) the number of possible combinations is 2N. Take an N-bit binary number bN–1 bN–2 . . . b2b1b0 and write all combinations from 00 . . . 000 to 11 . . . 111 in normal binary ascending order. (a) 7402 is a quad 2-input NOR gate. This means there are four identical 2-input NOR gates. Each gate requires three pins, two for inputs and one for output. Therefore, the four gates requires 3 ´ 4 = 12 pins. Two pins are required for the power supply (VCC and GND). Hence it is a 14-pin IC. (b) 7404 is a hex inverter. The number of pins = 2 ´ 6 + 2 = 14. (c) 7408 is a quad 2-input AND gate. The number of pins = 3 ´ 4 + 2 = 14. (d) 7410 is a triple 3-input NAND gate. The number of pins = 4 ´ 3 + 2 = 14. (e) 7411 is a triple 3-input AND gate. The number of pins = 4 ´ 3 + 2 = 14. (f) 7420 is a dual 4-input NAND gate. The number of pins = 5 ´ 2 + 2 = 12. Since 12-pin IC package is not used, therefore, it is packaged as 14-pin IC. Two pins are left free (NC). (g) 7427 is a triple 3-input NOR gate. The number of pins = 4 ´ 3 + 2 = 14. (h) 7432 is a quad 2-input OR gate. The number of pins = 3 ´ 4 + 2 = 14. 9
(i) 7486 is a quad EX-OR gate. The number of pins = 3 ´ 4 + 2 = 14. (a) (i) 7408 and 7432 (ii) 7400 (b) (i) 7432 and 7408 (ii) 7402 Logic Circuit A 0.4V = 0 2V = 1 Logic Circuit B –0.75V = 1 –1.55V = 0
1.20
1.21
1.22 Inputs
Output
A
B
C
AND Y1
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 0 0 0 0 0 0 1
1.23
OR Y2
NAND Y3
NOR Y4
0 1 1 1 1 1 1 1
1 1 1 1 1 1 1 0
1 0 0 0 0 0 0 0
Yes.
(a)
A B C
(b)
A B C
Y
or
A B C
Y
Logic 1 Y
or
A B C
Y
Logic 0 (c)
A B C
Y
or
A B C
Y
Logic 1 (d)
A B C
Y
or
A B C Logic 0
10
Y
1.24
1.25 1.26 1.27
Yes. AND — by connecting one of the inputs to logic 0 OR — by connecting one of the inputs to logic 1 NAND — by connecting one of the inputs to logic 0 NOR — by connecting one of the inputs to logic 1. (a) Active-high (b) Active-low (c) Active-high (d) Active-low (a) Active-low (b) Active-high (c) Active-low (d) Active-high (a) A B Y C
Y = A × B × C = (A × B) × (C) (b)
A B Y C
Y = A + B + C = (A + B) + (C) (c) A
AB
B
AB Y
C
C
Y = A ⋅ B ⋅ C = ( A ⋅ B) + C
= ( A ⋅ B) ⋅ C = A⋅ B⋅C
(d) A Y
B C 11
1.28
(a) A Å B = A B + A B A Å B = AB + A B
= AB + AB = A Å B (b) A ⊕ B = AB + AB A Å B = AB + A B = AB + AB
A Å B = AB + A B = AB + AB (c) B Å (B Å AC) = B Å B Å AC = 0 Å AC = AC
12
CHAPTER 2 2.1 (a) 111001
= 1 ´ 25 + 1 ´ 24 + 1 ´ 23 + 0 ´ 22 + 0 ´ 21 + 1 ´ 20 = 32 + 16 + 8 + 0 + 0 + 1 = (57)10
(b) 101001
= 1 ´ 25 + 0 ´ 24 + 1 ´ 23 + 0 ´ 22 + 0 ´ 21 + 1 ´ 20 = 32 + 0 + 8 + 0 + 0 + 1 = (41)10
(c) 11111110 = 1 ´ 27 + 1 ´ 26 + 1 ´ 25 + 1 ´ 24 + 1 ´ 23 + 1 ´ 22 + 1 ´ 21 + 0 ´ 20 = 128 + 64 + 32 + 16 + 8 + 4 + 2 + 0 = (254)10 (d) 1100100
= 64 + 32 + 0 + 0 + 4 + 0 + 0 = (100)10
(e) 1101.0011 = 1 ´ 23 + 1 ´ 22 + 0 ´ 21 + 1 ´ 20 + 0 ´ 2–1 + 0 ´ 2–2 + 1 ´ 2–3 + 1 ´ 2–4 = 8 + 4 + 0 + 1 + 0 + 0 + 0.125 + 0.0625 = (13.1875)10 (f) 1010.1010 = 8 + 2 + 0.5 + 0.125 = (10.625)10 (g) 0.11100
= 0.5 + 0.25 + 0.125 = (0.875)10 Quotient
2.2 (a)
37 2 18 2 9 2 4 2 2 2 1 2
Remainder
18
1
9
0
4
1
2
0
1
0
0
1 1
Thus (37)10 = (100101)2 Similarly, (b) (255)10 = (11111111)2 (c) (15)10 = (1111)2 13
0
0
1
0
1
(d) Integer part: (26)10 = (11010)2 Fractional part: 0.25 0.5 ´2 ´2 0.5 1.0 ¯ ¯ 0 1 Therefore, (26.25)10 = (11010.01)2 (e) Integer part: (11)10 = (1011)2 Fractional part: 0.75 0.5 ´2 ´2 1.5 1.0 ¯ ¯ 1 1 Thus (11.75)10 = (1011.11)2 (f) 0.1 0.2 0.4 0.8 0.6 0.2 0.4 0.8 ´2 ´2 ´2 ´2 ´2 ´2 ´2 ´2 0.2 0.4 0.8 1.6 1.2 0.4 0.8 1.6 ¯ ¯ ¯ ¯ ¯ ¯ ¯ ¯ 0 0 0 1 1 0 0 1... Thus, (0.1)2 = (0.00011001)2 The process may be terminated at the required number of significant bits. 2.3 (a)
(b)
1
1
¬ Carry
1 0 +1 1 1 1 0 Final carry
1 0 0
1 1 0
1
1
1
1
1
1
1 + 1 0 Final carry
0 1 0
1 0 0
0. 1. 0.
1 0 0
¬ Carry 1 1 0
0
1
0
1
2.4 (a)
01000 –01001
01000 + 10111 (2’s complement) 11111 Since the MSB of the sum is 1, which means the result is negative and it is in 2’s complement form. 2’s complement of 11111 = 00001 = (1)10 Therefore, the result is –1.
14
(b)
(c)
01100 Þ 01100 –00011 + 11101 (2’s complement) 101001 = + 9 Ignore 0011.1001 Þ 0011.1001 –0001.1110 +1110.0010 (2’s complement) 10001.1011 = + 1.6875 Ignore
2.5 (a) 375 8 46 8 5 8
Quotient
Remainder
46
7
5
6
0
5
5 Therefore, (375)10 = (567)8 = (101110111)2 (b) Quotient Remainder 249 31 1 8 31 3 7 8 3 0 3 8 3
(c)
2.6 (a)
(b) (c)
6
7
7
1
Therefore, (249)10 = (371)8 = (011111001)2 Integer part: (27)10 = (33)8 = (011011)2 Fractional part: 0.125 ´8 1.000 ¯ 1 Thus (0.125)10 = (0.1)8 = (0.001)2 Therefore, (27.125)10 = (33.1)8 = (011011.001)2 11 011 100.101 010 = (334.52)8 (334.52)8 = 3 ´ 82 + 3 ´ 81 + 4 ´ 80 + 5 ´ 8–1 + 2 ´ 8–2 = (220.65625)10 01 010 011.010 101 = (123.25)8 = (83.328125)10 10 110 011 = (263)8 = (179)10 15
2.7 (a) 375 16 23 16 1 16
Quotient
Remainder
23
7
1
7
0
1
1 7 7 Therefore, (375)10 = (177)16 (or 177H) = (0001 0111 0111)2 (b) Quotient Remainder 249 15 9 16 15 0 15 16 F 9 Therefore, (249)10 = (F9)16 (or F9H) = (1111 1001)2 (c) Integer part: Quotient Remainder 27 1 11 16 1 0 1 16 1 B Thus (27)10 = 1BH Fractional part: 0.125 ´ 16 2.000 ¯ 2 \ (0.125)10 = 0.2H \ (27.125)10 = (1B.2)16 = 1B.2H = (00011011.0010)2 2.8 (a) 1101 1100.1010 10 = (DC.A8)16 (DC.A8)16 = 13 ´ 161 + 11 ´ 160 + 10 ´ 16–1 + 8 ´ 16–2 = (220.65625)10 (b) 0101 0011.0101 01 = (53.54)16 = (83.328125)10 (c) 1011 0011 = (B3)16 = (179)10 2.9 For each decimal digit write its natural BCD code (a) 46 = 0100 0110 (BCD) (b) 327.89 = 0011 0010 0111.1000 1001 (BCD) (c) 20.305 = 00100000.0011 0000 0101 (BCD) 2.10 For each decimal digit write its 4-bit Excess-3 code. (a) 46 = 0111 1001 (Excess-3) (b) 327.89 = 0110 0101 1010.1011 1100 (Excess-3) (c) 20.305 = 0101 0011.0110 0011 1000 (Excess-3) 16
2.11 Starting from 4-bit Gray code given in Table 2.8 formulate 5-bit Gray code as given below in Table 1. Table 1 Decimal No. 0 1 2 : : 13 14 15 16 17 18 : : 29 30 31
Table 2
G4
G3
G2
G1
G0
0 0 0 : : 0 0 0 1 1 1 : : 1 1 1
0 0 0
0 0 1
0 1 1 3
1 1 1 1 1 1
0 0 0 : : 0 0 0 0 0 0
1 0 0 0 0 1
1 1 0 0 1 1
0 0 0
0 0 0
1 0 0
1 1 0
Decimal No. 0 1 2 0 : 17 : 30 31 32 33 : 46 : 62 63
G5
G4
G3
G2
G1
G0
0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
0 0 0
0 0 0
0 0 0
0 0 1
0 1 1
1
1
0
0
1
1 1 1 1
0 0 0 0
0 0 0 0
0 0 0 0
1 0 0 1
1
1
0
0
1
0 0
0 0
0 0
0 0
1 0
Similarly, form 6-bit Gray Code as given in Table 2. From Table 2, we obtain (46)10 = 111001 (Gray Code) 2.12 Writing the 6-bit code for each character (See Table 2.9), we obtain 100111 001011 000011 101100 101000 2.13 (a) Write the 7-bit ASCII code for each character (See Table 2.10) R.P. JAIN = 1010010 0101110 1010000 0101110 1001010 1000001 1001001 1001110 (b) Write the 8-bit EBCDIC code for each character (See Table 2.9) R.P. JAIN = 11011001 01001011 11010111 01001011 11010001 11000001 11001001 11010101 (c) Write the 6-bit internal code for each character (See Table 2.9) R.P. JAIN = 101001 011011 100111 011011 100001 010001 011001 100101 2.14 (a) Count the number of ones for every character from ASCII table and attach a 1 or 0 as the MSB for odd or even number of ones respectively. For example, the ASCII code for R is 1010010, which has three ones. Therefore, a 1 is to be attached as MSB and the resulting 8-bit code with even parity will be 11010010 Similarly, the code for l is 0101110 which has four ones. Therefore, a 0 is to be attached as MSB and the resulting 8-bit code with even parity will be 00101110. 17
In a similar way parity bit can be attached to every character. (b) Repeat part (a) for EBCDIC code. 2.15 (a) Attach 0 or 1 as MSB to make the number of ones odd. For example, 8-bit ASCII code for R with odd parity is 01010010 (b) Repeat part (a) for EBCDIC code. 2.16 (a) Since, 25 = 32 and 26 = 64, therefore, the minimum number of bits required to encode 56 elements of information is 6. (b) 27 < 130 < 28 Therefore, 8 bits are required to encode 130 elements of information. 2.17 In the 8 bit ASCII code with the parity bit, if binary to hexadecimal conversion is used, the resulting format will be hexadecimal. For example, R = 11010010 = D2 H and l = 00101110 = 2EH for even parity and R = 01010010 = 52H and l = 10101110 = AEH for odd parity. 2.18 Consider the following examples: (i) 7 0111 Þ 0111 –3 –0011 + 1100 (1’s complement) 4 10011 1 End-Around Carry (EAC) 0100 = 4 (ii) 3 0011 Þ 0011 –7 – 0111 + 1000 (1’s complement) –4 1011 = –4 in 1’s complement form From the above examples the rules of subtraction can be summarized as: (a) Add ones complement of the subtrahend to the minuend. (b) If a carry is produced, add end-around carry (EAC) (c) If the MSB of the sum is 0, the result is positive (d) If the MSB of the sum is 1, the result is negative and it is in one’s complement format. 2.19 100 ´ 20 ´ 8 bits. 2.20 132 ´ 7 bits. 2.21 Let us consider the BCD code for 9 and find out its Hamming code for error correction. Decimal digit 9
Position
®
BCD odd parity for 1,3,5,7 requires p1 = 1 odd parity for 2,3,6,7 requires p2 = 1 odd parity for 4,5,6,7 requires p3 = 1
1 p1
2 p2
Hamming Code 3 4 5 n1 p3 n2
6 n3
7 n4
: : : 1 : 1 : 1
: : : : : 1 : 1
1 : : 1 : 1 : 1
0 : : 0 : 0 : 0
1 : : 1 : 1 : 1
18
: : : : : : : 0
0 : : 0 : 0 : 0
Therefore, Hamming code for decimal digit 9 is 1 1 1 0 0 0 1. Similarly, Hamming code is determined for each BCD digit and the complete sequence is given below. Decimal digit 0 1 2 3 4 5 6 7 8 9
Position
®
1 p1
2 p2
Hamming code 3 4 5 n1 p3 n2
6 n3
7 n4
1 0 1 0 0 1 0 1 0 1
1 0 0 1 1 0 0 1 0 1
0 0 0 0 0 0 0 0 1 1
0 0 1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1 0 1
19
1 0 0 1 0 1 1 0 1 0
0 0 0 0 1 1 1 1 0 0
CHAPTER 3 3.1 (a) The number of covalent bonds breaking away increases with temperature, which decreases the resistivity of the semiconductor material, whereas in a metal an increase in the temperature results in a greater thermal motion of the ions, and hence decreases the mean free path of the free electrons. This results in a decrease in the mobility and hence resistivity increases with temperature. (b) All the covalent bonds are intact at 0 K and hence there are no free charge carriers, whereas at room temperature some of the covalent bonds break away resulting in small conductivity. 3.2 (a) Using the V-I relation of the diode, we obtain
» I0 exp (V1/hVT) I2 = 2I1 » I0 exp (V2/hVT) I1
and
From Eqs. (3.1) and (3.2), 2 = exp (V2 – V1/hVT) V2 – V1 = hVT 1n 2 = 2 ´ 26 ´ 0.693 mV » 36 mV
or (b)
Since, V1 = 700 mV Therefore, V2 = 700 + 36 = 736 mV Percentage change =
736 − 700 × 100% 700
= 5.14% 3.3
From the V–I relation of the diode, we obtain I1 » I0 exp (700/hVT) I2 » I0 exp (750/hVT)
and
(b)
\
I2/I1 = exp (50/2 ´ 26) = 2.616
or
I2 = 2.616 ´ 2 = 5.232 mA 5. 232 − 2 × 100% 2 = 161.6%
Percent change =
I2 = 10 = e {(V2 – V1)/2 ´ 26} I1
3.4
or V2 – V1 = 52 1n 10 = 119.73 mV 3.5 (a) The circuit will be under steady-state at t = 20ms, i.e.,
dQ =0 dt 20
(3.1) (3.2)
V1 R
∴ I1 ≈
=
10 = 1mA 10
Since,
Q =I t
\
Q = 1 ´ 10–6 ´ 10–3 = 10–9 C
(b) The diode will turn off when excess minority charge has been removed.
VR = 5 = 0. 5 mA R 10 The differential equation is dQ Q + = − 0. 5 × 10 −3 dt τ IR ≈
Solving this with initial condition Q(0) = 10–9 C (part (a)), we obtain Q = – 0.5 ´ 10–9 + 1.5 ´ 10–9 e–t Set Q = 0 for cut-off \ t = 1.099 ms (c) The various waveforms are given below. The recovery time constant tR = RCO = 10 ´ 103 ´ 10 ´ 10–12 = 0.1 ms Vi V1 = 0V 0
t
-V2 = -5V Vd 0.7V 0 -5V
tR
t
Id 1 mA 0
t tR
-0.5 mA Excess Q Minority Charge 0
t 0
1.099 ms 21
t
3.6 (a) Since the E-B junction is forward-biased, therefore, the transistor is conducting (i.e., IC is flowing). It may either be operating in the active region or in the saturation region. Let us assume that the transistor is operating in the saturation region. Then the base and collector voltages will be VBE, sat (= 0.8 V) and VCE, sat (= 0.1 V) respectively. Therefore, the collector current IC and the base current IB are given by IC = and IB =
VCC − VCE , sat RC V BB − V BE , sat RB
=
10 − 0. 1 = 3. 33 mA 3
=
5 − 0. 8 = 21 µA 200
⋅
hFE IB = 21 ´ 100 = 2.1 mA Since IC>hFE IB, therefore the transistor cannot be in saturation. Hence it is conducting in the active region. with VCC = 6V, let us again assume that the transistor is operating in the saturation region. Therefore,
6 − 0.1 ≈ 2 mA 3 The current IB remains same as in part (a). Therefore, now IC < hFEIB which means the transistor is certainly operating in the saturation region. (b) The value of RC required for the transistor to be in saturation is given by IC =
VCC − VCE , sat RC
≤ h FE I B
or RC ≥ 10 − 0. 1 kW 2. 1 ³ 4.7 kW \ The value of Rc just sufficient for saturation will be 4.7 kW. If the value of RC used is more than 4.7kW, the transistor will continue to be operating in the saturation region. (c) The value of RB required to drive the transistor into saturation is given by IC ≤ h FE × or RB ≤ 100 ⋅
V BB − V BE , sat RB
5 − 0. 8 kW 3. 3
£ 127.27 kW 22
The value of RB just sufficient to drive the transistor into saturation will be 127.27 kW. If a smaller value of RB than the value calculated above is used, the transistor will be driven deeper into saturation. 3.7 (a) For the transistor to be in the cut-off region, the voltage VBB £VBE, cut–in £ 0.5 V (b) For active region operation VCE − VCE , sat RC
VBB <
or,
≥
V BB − V BE , sat RB
⋅ h FE
R B VCC − VCE , sat ⋅ + V BE , sat RC h FE
5 − 0.1 < 100 ⋅ + 0. 8 2 100 < 3.25 V Therefore, the range of VBB for active region is 0.5 V < VBB < 3.25 V (c) The range of VBB for saturation region is VBB ³ 3.25 V 3.8 For the transistor to be in saturation
VCC − VCE , sat RC
≤
V BB − V BE , sat RB
⋅ h FE
R B VCC − V CE, sat or, hFE (min) = R ⋅ V C BB − V BE , sat 5 − 0. 1 = 200 ⋅ 1 5 − 0. 8 = 233.3 3.9 Assume the transistor to be in saturation. Writing KVL equations for the collector and base circuits, RCIC + VCE, sat + RE (IC + IB) = VCC and
RBIB + VBE, sat + RE (IC + IB) = VBB
Substituting the values, we obtain, 53 IC + 50 IB = 4.8 23
and 50 IC + 100 IB = 4.2 Solving these equations, IC = 0.096 mA and IB = –6.214 mA Since IB comes out to be negative, hence the transistor is not in saturation. Assuming VBE = 0.7 V in the active region, KVL for the base circuit will be [RB + (1 + hFE) RE] IB = 5 – 0.7 or, IB = 8.43 ´ 10–4 mA \ IC = hFE IB = 8.43 ´ 10–2 mA and IE » –8.43 ´ 10–2 mA 3.10 The equivalent circuit at the input of a transistor consists of input resistance Ri in parallel with the input capacitance Ci as shown in Fig. given below: C B
+
RB
Vi
Ri
Ci
– Equivalent circuit at the transistor input
When fast changes occur in Vi, the voltages at B change with the time constant Ci (RB||Ri) If a capacitor C is connected across RB, the voltage at B will change as soon as Vi changes because of the capacitive voltage divider. This helps in improving the switching speed of transistor circuit. 3.11 (a) For the load transistors IC,sat =
5V = 2.5 mA 2 kW
IB,sat =
2. 5 mA = 2. 5 µA 100
\ The minimum value of Vi required for the load transistors to be in saturation is Vi(min) = 25 ´ 10–3 ´ 10 + 0.8 = 1.05 V
24
(b) Assuming the load transistors to be in saturation the equivalent circuit at their input will be as shown in Fig. (a), which reduces to the circuit shown in Fig. (b). Now, the voltage Vi = VO can be determined using the principle of superposition and is given by 5 2 ´5+ ´ 0.8 5+2 5+2
Vi = VO = = 3.8 V 10 kW Vi
0.8 V
Vi 5 kW
10 kW
0.8 V
0.8 V (a)
(b)
(c) The base current IB1 = I B2 =
3. 8 − 0. 8 mA 10
= 0.3 mA 3.12 (a) When both the transistors are cut-off, there is no current drawn from the supplies, and the voltage at Y is 5 V. (b) When both the transistors are in saturation, the voltage at Y is 0V. (c) Assume T1 to be cut-off and T2 to be in saturation. Since T2 is in saturation,
æ VCC ö the voltage at Y will be 0 V. The currents I1 and I2 will be same ç = è RC ÷ø and IC2 = I1 + I2. Similarly, if T1 is in saturation and T2 is cut-off then IC1 = I1 + I2 (d)
V1
V2
Y
0V 0V 5V 5V
0V 5V 0V 5V
5V 0V 0V 0V
It performs NOR operation. 3.13 (a) Assume the transistor to be in saturation.
5 − 0. 8 Therefore, IC = 5 = 5 mA, I B = = 0. 042 mA 1 100 hFE IB = 150 ´ 0.042 = 6.3 mA Since IC < hFE IB, therefore, the transistor is definitely in saturation. 25
(b) When S1 is closed, I1 = (5 – 0.7/4) = 1.075 mA assuming the transistor to be in saturation. Therefore,
IC = I + I1 = 5 + 1.075 = 6.075 mA
Since
IC < hFE ⋅ IB
Therefore, the transistor continues to remain in saturation. (c) When both S1 and S2 are closed, if we again assume the transistor to be in saturation, I C = I + I1 + I2 = 5 + 2 ´ 1.075 = 7.15 Now
IC VOL (CMOS) which shows that the input of the translator is compatible with CMOS. Since the output of the translator is compatible with ECL, therefore, CMOS-to-ECL interfacing is possible using TTL-to-ECL translator. 4.34 The output logic levels of MC10H125 translator and the input logic levels of CMOS (74HCT & 74 ACT) are shown in Fig. Prob. 4.34.
43
VOH
VOL
2.5V VIH
2V
VIL
0.8V
0.5V
CMOS (74HCT & 74ACT)
MC10H125 Translator (a)
(b)
Fig. Prob. 4.34
From these logic levels, we observe, VIH (CMOS) < VOH (Translator) VIL (CMOS) > VOL (Translator) Therefore, the output of the translator is compatible with these CMOS devices. Since the input of the translator is compatible with ECL, therefore, ECL-toCMOS interfacing is possible. For CMOS 74 HC, and 74 AC series VIL = 1.35V VIH = 3.85V and for CMOS 74 C series VIL = 1.5V VIH = 3.5V For these CMOS ICs, VIL (CMOS) > VOL Translator but
VIH (CMOS) < VOH (Translator)
Therefore, a resistance R and VCC are required to be connected to pull up the voltage at P corresponding to VOH (Translator) VCC R P MC10H125 Translator
CMOS (c) Fig. Prob. 4.34
44
CHAPTER 5 5.1 Let S1 and S2 be the two switches. The circuit diagram of the system is shown in Fig. Prob. 5.1(a): 0
0
1 L
S1
S2 ON = 1 OFF = 0
Bulb
Supply Fig. Prob. 5.1(a)
1
(a) The truth table is given below: S1
S2
L
0 0 1 1
0 1 0 1
0 1 1 0
(b) The logic equation is L = S 1 S2 + S1 S 2 (c) The AND-OR realization is given in Fig. Prob. 5.1(b): S1 S2 L
Fig. Prob. 5.1(b)
(d) Replace each of the AND gates and the OR gate in the above figure by NAND gates. The resulting circuit will be NAND-NAND realization. 5.2 (a)
Inputs
Output
A
B
C
D
f
0 0 0 0 0 0 0
0 0 0 0 1 1 1
0 0 1 1 0 0 1
0 1 0 1 0 1 0
0 0 0 0 0 1 1 (Contd.)
45
(Contd.) Inputs
Output
A
B
C
D
f
0 1 1 1 1 1 1 1 1
1 0 0 0 0 1 1 1 1
1 0 0 1 1 0 0 1 1
1 0 1 0 1 0 1 0 1
1 0 0 0 0 0 1 1 1
(b) The K-map is given in Fig. Prob. 5.2. The simplified expression is f = BC + BD CD
AB 00
01
11
01
1
1
11
1
1
10
1
1
10
B
00
C BD
f B
BC
(b)
D
(a) Fig. Prob. 5.2
5.3 (a) f1 = (A + B + C + D ) ( A + B + C + D) ( A + B + C + D) (A + B + C + D ) (A + B + C + D ) (A + B + C + D) (A + B + C + D) ( A + B + C + D) ( A + B + C + D ) f2 = (A + B + C + D) (A + B + C + D ) (A + B + C + D ) (A + B + C + D ) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (b) The K-maps for f1 and f2 are given in Fig. Prob. 5.3(a) and (b) respectively. The minimized expressions are: CD
AB 00 00 01
0
11
0
10
01
11
10
0
0
0
CD
0 0 0
0 (a)
AB 00
01
00
0
01
0
11
0
0
10
0
0 (b)
Fig. Prob. 5.3 46
11
10
0
0 0
f1 = ( B + C + D) ( A + B + C) ( A + B + D) (A + B + D ) (A + B + C ) f2 = (A + C ) (A + B) ( A + C + D ) (B + D ) (c) The OR-AND realizations are shown in Fig. Prob. 5.3(c) and (d) for f1 and f2 respectively. A
B C D
C
A B C
A B
A B D
f2
f1 B
A B D
D
A B C
A C D
(c)
(d)
Fig. Prob. 5.3
(d) Replace all the AND and OR gates in figures (A) and (B) by NOR gates to obtain realizations using only NOR gates. 5.4 (a) A B C D B C
f
B D A D
A B Fig. Prob. 5.4(a)
47
(b)
A B C D A B C f A B D
A B D Fig. Prob. 5.4(b)
(c) Realization for (a) requires 7400 – 1 7420 – 1/2 7430 – 1 a total of three chips. Realization for (b) requires 7427 – 1 74260 – 1 a total of only two chips. 5.5 (a)
7410
A C A C D
Y
B
(b) A B C
A B C
Y 1/
B C D
7427 Fig. Prob. 5.5 48
3 7427
(c) Realization of (a) requires only one chip whereas (b) requires two chips. 5.6 3/4
A
7402
D
C
f
D
B Fig. Prob. 5.6
5.7 (a) CD
AB 00
01 11
10
00
1
1
01
1
1
11
1
1
1
1
10
1
1
1
1
A
C Fig. Prob. 5.7(a)
(b) f = å m (2, 3, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15) (c) f = A + C A f B Fig. Prob. 5.7(b)
5.8 (a) Figure Prob. 5.8 (i) below gives the K-map. Using offset adjacencies shown in the K-map, the expression for f1 can be written as f1 = (C ¤ D) (A ¤ B) + (C ⊕ D) (A ⊕ B) = (A ⊕ B) ¤ (C ⊕ D) CD
AB C D (A ¤ B) 00 01 11 10
00
1
01 11 10
C D (A Å B)
1 1
1
1 1
1
CD (A ¤ B) C D (A Å B)
1
Fig. Prob. 5.8(i) 49
A B f1
C D Logic 1 Fig. Prob. 5.8(ii)
Its realization using EX-OR gates is given in Fig. Prob. 5.8(ii). This realization requires only one 7486 IC chip. (b) Its K-map is given in Fig. Prob. 5.8(iii) The minimized expression is f2 = A B + AB D + ACD The realization using NAND gates is given in Fig. Pro. 5.8(iv). This requires one 7410 chip and one gate of 7400 chip. AB 00
01 11
00
1
1
01
1
11
1
1
10
1
1
CD
A 10
1
B A B D
f2
A C D
(iii)
(iv)
Fig. Prob. 5.8
5.9 Truth table of BCD-to-Excess-3 code converter is given below. BCD
Excess-3
D
C
B
A
E3
E2
E1
E0
0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 1 1 1 0 0
0 0 1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1 0 1
0 0 0 0 0 1 1 1 1 1
0 1 1 1 1 0 0 0 0 1
1 0 0 1 1 0 0 1 1 0
1 0 1 0 1 0 1 0 1 0
Here only ten out of sixteen combinations are used and the other six are taken as don’t-care conditions. The K-maps for the outputs E0, E1, E2 and E3 are given in Fig. Prob. 5.9. The minimized expressions are: E0 = A 50
BA
DC 00
01 11
10
BA
DC 00
01 11
10
00
1
1
´
1
00
1
1
´
1
01
0
0
´
0
01
0
0
´
0
11
0
0
´
´
11
1
1
´
´
10
1
1
´
´
10
0
0
´
´
BA
DC 00
E0
E1
(a)
(b)
01 11
10
BA
DC 00
01 11
10
00
0
1
´
0
00
0
0
´
1
01
1
0
´
1
01
0
1
´
1
11
1
0
´
´
11
0
1
´
´
10
1
0
´
´
10
0
1
´
´
E2 (c)
Fig. Prob. 5.9
E3 (d)
E1 = BA + B A E2 = CB A + C A + C B E3 = D + CA + CB The circuit can be drawn using NAND gates. 5.10 Truth table of Excess-3-to-BCD converter can be prepared using the truthtable of Prob. 5.9. The K-maps can then be prepared and minimized. The minimized expressions are given below. A = E0 B = E1 E 0 + E1 E 0 C = E 2 E 1 + E2 E1 E0 + E3 E1 E 0 D = E3 E2 + E3 E1 E0 The circuit can now be drawn using NAND gates. 5.11 (a) The K-map is shown in Fig. Prob. 5.11(a). The minimized expression is f1 = C D = C + D
(b) The K-map is shown in Fig. Prob. 5.11(b). The minimized expression is f 2 = ( A + B + D) ( B + C + D ) ( A + C )
(c) The K-map is shown in Fig. Prob. 5.11(c). The minimized expression is f 3 = ( A + B + C + D ) ( B + C + D) ( A + B + C ) ( A + C + D )
The circuits for f1, f2, and f3 can be drawn using NOR gates. 51
CD
AB 00
01 11
AB 00
CD
10
01
0
0
0
0
01
11
0
0
0
0
11
10
0
0
0
0
10
10
0
00
00
01 11
0
0
0
(a)
0
0
0
0
(b) CD
AB 00
01 11
10
0
0
00
0
01 0
11 10
0
0
(c) Fig. Prob. 5.11
5.12 The K-map for f1 is shown in Fig. Prob. 5.12 and the minimized expression is f 1 = A BE + AC E + ABD + BC + AB CD E
This can be realized using NAND gates. Similarly, the minimized expression for f2 is f 2 = C E + ABD + ADE + AD E + B CE + CDE + AB E
which can be realized using NAND gates. A = 0 BC DE 00
01 11
00
10
DE
00
1
00
01
1
1
01
11
1
1
11
10
A = 1 AB CDE
BC
10
1 A BE
01 11
1
5.13 (a) Its K-map is given in Fig. Prob. 513(a). 52
10 1
1
1
BC Fig. Prob. 5.12
AC E
1
1
1
1
ABD
(a)
CD
AB 00
01 11 0
00 01
1
1
11 10
10
1
1
0
1
0
0
0
0
Fig. Prob. 5.13(a)
The minimized expression is Y = AC D + B C D + ACD A C D B C D
Y
A C D
Fig. Prob. 5.13(b)
(b) The K-map is given in Fig. 5.18 of the book and Y = C D + CD (c) Realization of part (a) requires 2 IC chips (7410) whereas for part (b) one IC chip (7400) only is required. C D Y C D
Fig. Prob. 5.13(c)
5.14 (a) Figure Prob. 5.14(a) and (b) show the K-maps of f1 for NAND and NOR realizations respectively. The minimized expressions are f1 = ABC + CD + BD + AD
(SOP)
and f1 = ( A + B + C ) (C + D) ( B + D) ( A + D) (POS) Circuits using NAND and NOR gates can be designed using the above expressions. (b) Similar to part (a), the minimized expressions are obtained which are given below. f2 = A C D + BC + AB 53
(SOP)
f2 = ( A + B ) ( B + D ) ( B + C ) ( A + C )
and
(POS)
These equations can be used to design circuits with NAND and NOR gates. AB
AB CD
00
01
11
00 01
1
11
1
10
´
1
CD
10 1
00
´
1
01
1
1
11 10
00
01
11
0
0
0
10
´ 0 ´
0
(a)
0
0
(b) Fig. Prob. 5.14
5.15 Its K-map and circuit realization are given in Fig. Prob. 5.15. (a)
A C (B Å D) AB CD 00
01 11
10
1
00
1
A B
1
01
1 D
11 10
f1
C A C (B ¤ D)
(b)
AB CD 00 00
B 01 11
11
1
10
1
C
1 1
01
10
1
1
A
f2
A 1 A(C Å D) A (B Å C)
1 C D
54
(c) AB CD 00 00
01 11
10 A
1
11
C
1
01
f3
A C (BÅD)
1
B 1
10
D
A C(B Å D)
Fig. Prob. 5.15
5.16 Its truth table is given in Table Prob. 5.16. Table Prob. 5.16 A
4-bit word B C
D
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Odd parity bit PO 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1
Even parity bit PE 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0
The K-map for Po is given in Fig. Prob. 5.16(a), from which Po is obtained as Po = AC (B ¤ D) + A C (B Å D) + A C (B Å D) + AC (B ¤ D) = (A Å C) ¤ (B + D) Its realization using EX-OR and EX-NOR gates is given in Fig. Prob. 5.16(b). AB CD 00
01 11 1
10
00
1
0
0
01
0
1
0
1
11
1
0
1
0
1
0
1
A C Po B
10
0
D
(a)
(b) Fig. Prob. 5.16 55
5.17 From the truthtable given in Prob. 5.16, K-map is prepared and the circuit is designed. These are given in Fig. Prob. 5.17. PE = A ⊕ B ⊕ C ⊕ D AB CD 00
1
00 01
10 1
1
11 10
01 11
B
1 1
1
1
A
1
C PE
D
(a)
Fig. Prob. 5.17
(b)
5.18 (a) The K-map using 1’s is given in Fig. Prob. 5.18(a). The minimized expression for f1 is f 1 = ABC D E + ABCD F + CEF + A B C DEF
The circuit for f1 can be realized using NAND gates. Similarly, we can minimize using 0’s which will lead to a circuit realizable by NOR gates. (b) The K-map using 0’s is given in Fig. Prob. 5.18(b). The minimized expression for f2 is f2 = (A + B + C + D + E + F ) ( A + B + D + E + F) ( A + B + C + E + F ) (A + C + D + E + F) (A + B + C + E + F) (A + B + C + E + F) (A + B + C + E + F) (A + B + C + D ) (A + B + D + E) (B + C + D + E) (B + C + D + F ) (A + B + C + D) The circuit for f2 can be realized using NOR gates. Similarly, we can minimize the function using 1s which will lead to a circuit realizable by NAND gates. 5.19 Let the augend, addend, and the carry inputs to the full-adder be An, Bn, and Cn – 1 respectively and Sn, and Cn be the sum and carry outputs respectively. (a) An and Bn are applied at the two inputs of first half-adder HA – 1. Its outputs are S1 (Sum) and C1 (Carry). Its truth table is given in Table Prob. 5.19. Table Prob. 5.19(a) An
Bn
S1
C1
0 0 1 1
0 1 0 1
0 1 1 0
0 0 0 1
56
A
B
1
0 CD 00
EF
01 11
EF
10
01 11
10
1
1
01 11
10
1
1
01 11
10
00
00 1
01
0
CD 00
01
1
11
11
10
1
10
AB CDEF CD 00
EF
CEF 01 11
00 1
11
1
10
1
A CD 00
1
11
ABCDF Fig. Prob. 5.18(a) 1 CD
01 11
EF
10
00
00
00
0
0
01
0
0
11
0
11
0
10
10
EF
1
01
0 EF
0
1
10
ABC D E
B
00
00
01
1
CD EF
10
CD 00
01 11
00
0
0
01
0
11
0
10
0
0
0
0
01
EF
10
0
01 11
0
10 Fig. Prob. 5.18(b) 57
0 0
CD 00
00
0
0 0
01 11
10
An
Cn – 1
Bn
HA – 1 C1
S1 HA – 2 C2
S2 = Sn
Cn Fig. Prob 5.19(a)
Truth table of the full-adder using input variables S1, C1, and Cn – 1 is given below: Table Prob. 5.19(b) C1
S1
Cn – 1
Cn
Sn
0 0 1 0 0 1
0 1 0 0 1 0
0 0 0 1 1 1
0 0 1 0 1 1
0 1 0 1 0 1
K-maps for Cn and Sn are shown below: Cn – 1
C 1 S1 00
01
11
10
0
0
0
´
1
1
0
1
´
1
Cn – 1
K-map for Cn
C1 S1 00
01
11
10
0
0
1
´
0
1
1
0
´
1
K-map for Sn
Cn = C1 + S1 × Cn – 1 Sn = S1 C n - 1 + S 1 Cn – 1 = C1 + C2 = S1 Å Cn – 1 Sn and Cn are generated using HA –2 and an OR gate as shown in the block diagram.
58
(b)
EX–OR(1)
An Bn
EX–OR(2)
S1
S2 = Sn C2 C1 AND-2 AND–1
OR
Cn–1
Cn
Fig. Prob. 5.19(b)
5.20 Propagation delay time for Sn = tpd [EX-OR(1)] + tpd [EX –OR(2)] = 20 + 20 = 40 ns. Propagation dealy time for Cn = tpd [EX-OR(1) + tpd (AND-2) + tpd(OR) = 20 + 10 + 10 = 40 ns. Since the propagation delay time (tpd) of AND–1 is less than the tpd of EX-OR(1), therefore, it is not counted. 5.21 f (A, B, C, D) = p M(2, 7, 8, 9, 10, 12) = S m (0, 1, 3, 4, 5, 6, 11, 13, 14, 15) Table (a) Group
Grouping of minterms according to number of 1’s.
Minterm A
Variables B C D
Check for inclusion in groups of 2
0
0
0
0
0
0
ü
1
1 4
0 0
0 1
0 0
1 0
ü ü
2
3 5 6
0 0 0
0 1 1
1 0 1
1 1 0
ü ü ü
3
11 13 14
1 1 1
0 1 1
1 0 1
1 1 0
ü ü ü
4
15
1
1
1
1
ü
Table (b) Group
Grouping of two minterms
Minterms A
0
Variables Check for inclusion B C D in groups of 4
0, 1 0, 4
0 0
0 —
0 0
— 0
ü ü
1, 3 1, 5
0 0
0 — — 0
1 1
ü (Contd.)
59
(Contd.) Group
Minterms
Variables Check for inclusion B C D in group of 4
A 1
2
3
4,5 4, 6 3, 11 5,13 6, 14
0 0 — — —
1 1 0 1 1
0 — 1 0 1
— 0 1 1 0
11, 15 13, 15 14, 15
1 1 1
— 1 1
1 — 1
1 1 —
ü
Table (c) Grouping of 4 minterms Group
Minterms
Variables B C
A 0
0, 1, 4, 5 0, 4, 1, 5
0 0
— —
D
0 0
— —
Table (d) PI table PI terms
Decimal numbers
0
1
3
0, 1, 4, 5 Ä AC ü 1, 3 AB Dü 4, 6 A B Dü B CDü 3, 11 BC Dü 5,13 BC D ü 6, 14 ACD ü 11, 15 ABD 13, 15 ABC 14, 15
´ ´
´
ü
Minterms 4 5 6 11 13 14 15 ´
´
´
´
´
´ ´
´ ´
ü
´
´ ´
´
´ ´ ´
ü ü ü ü ü
From the PI table, we see that the column for minterms 0 contains only one ´, therefore, A C is an essential prime-implicant. All the other columns contain 2 or more Xs. Therefore, starting from the prime-implicant A B D, we see the minterms that are covered by each prime-implicant and find the minimum number of prime-implicants that will cover all the minterms. Depending upon the prime-implicants selected above, the minimized function is f (A, B, C, D) = AC + ABD + ABD + B CD + BC D + BCD + ACD There can be other options also.
60
5.22 f (A, B, C, D) = Sm (1, 3, 5, 8, 9, 11, 15) + d(2, 13) Table (a) Grouping of minterms/don’t care terms according to number of 1’s. Group
Minterm/ don’t care term
A
1
1 2* 8
0 0 1
0 0 0
2
3 5 9
0 0 1
3
11 13*
4
15
Table (b) Group
Check for inclusion in group of 2
0 1 0
1 0 0
ü ü ü
0 1 0
1 0 0
1 1 1
ü ü ü
1 1
0 1
1 0
1 1
ü ü
1
1
1
1
ü
Grouping of 2 minterms/don’t care terms A
Variables B C
D
1, 3 1, 5 1, 9 2*, 3 8, 9
0 0 — 0 1
0 — 0 0 0
— 0 0 1 0
1 1 1 — —
ü ü ü
3, 11 5, 13* 9, 11 9, 13*
— — 1 1
0 1 0 —
1 0 — 0
1 1 1 1
ü ü ü ü
11, 15 13, 15
1 1
— 1
1 —
1 1
ü ü
2 3
Table (c) Group
2
D
Minterms/ don’t care terms
1
1
Variables B C
Check for inclusion in group of 4
Grouping of 4 minterms/don’t care terms Minterms/ don’t care terms
A
Variables B C
D
1, 3, 9, 11 1, 5, 9, 13* 1, 9, 3, 11 1, 9, 5, 13*
— — — —
0 — 0 —
— 0 — 0
1 1 1 1
9, 11, 13*, 15 9, 13*, 11, 15
1 1
— —
— —
1 1
There are a total of 5 prime-implicants BD , CD, and AD from Table (c) and AB C and AB C from Table (b).
61
Table (d) PI Table PI terms
Decimal numbers
1
BD 1, 3, 9, 11 ´ CD 1, 5, 9, 13* ü ´ AD 9, 11, 13*, 15 ü ABC 2*, 3 AB C 8, 9 ü
2*
Minterms/don’t care terms 3 5 8 9 11 13* ´
´ ´ ´
Ä
´
15
´ ´ ´
´
Ä
´ ü
´
Ä ü
ü
The essential prime- implicants are: CD, AD, and ABC . Except the minterm 3 all the other minterms have heen covered by the essential prime-implicatns. Therefore, B D is to be included in the minimized expression. The minimized function is f (A, B, C, D) = B D + C D + AD + AB C . 5.23 f (A, B, C, D, E) = Sm (8, 9, 10, 11, 13, 15, 16, 18 , 21, 24, 25, 26, 27, 30, 31) Table (a) Group
Grouping of minterms according to number of 1’s
Minterm
Variables C D
E
Check for inclusion in group of 2
0 0
0 0
ü ü
0 0 0 0
0 1 1 0
1 0 0 0
ü ü ü ü
1 1 0 1 1
0 1 1 0 0
1 0 0 0 1
1 1 1 1 0
ü ü ü ü
0 1 1
1 1 1
1 0 1
1 1 1
1 1 0
ü ü ü
1
1
1
1
1
ü
A
B
8 16
0 1
1 0
0 0
9 10 18 24
0 0 1 1
1 1 0 1
11 13 21 25 26
0 0 1 1 1
4
15 27 30
5
31
1
2
3
Table (b) Group
1
Grouping of 2 minterms
Minterms 8, 9 8, 10
A
B
0 0
1 1
Variables C D 0 0
0 —
E
Check for inclusion in group of 4
— 0
ü ü (Contd.)
62
(Contd.) Group
Minterm 8, 24 16, 18 16, 24 9, 11 9, 13 9, 25 10, 11 10, 26 18, 26 24, 25 24, 26 11, 15 11, 27 13, 15 25, 27 26, 27 26, 30 15, 31 27,31 30, 31
2
3
4
Variables C D
A
B
— 1 1 0 0 — 0 — 1 1 1 0 — 0 1 1 1 — 1 1
1 0 — 1 1 1 1 1 — 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 — 0 0 0 0 0 0 — 0 1 0 0 — 1 — 1
0 — 0 — 0 0 1 1 1 0 — 1 1 — — 1 1 1 1 1
E
Check for circlusion in group of 4
0 0 0 1 1 1 — 0 0 — 0 1 1 1 1 — 0 1 1 —
ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü
Table (c) Grouping of 4 minterms Group
1
2
3
Minterms
Variables C D
A
B
8, 9, 10, 11 8, 9, 24, 25 8, 10, 9, 11 8, 10, 24, 26 8, 24, 9, 25 8, 24, 10, 26 16, 18, 24, 26 16, 24, 18, 26
0 — 0 — — — 1 1
1 1 1 1 1 1 — —
0 0 0 0 0 0 0 0
— 0 — — 0 — — —
— — — 0 — 0 0 0
9, 11, 13, 15 9, 11, 25, 27 9, 13, 11, 15 9, 25, 11, 27 10, 11, 26, 27 10, 26, 11, 27 24, 25, 26, 27 24, 26, 25, 27
0 — 0 — — — 1 1
1 1 1 1 1 1 1 1
— 0 — 0 0 0 0 0
— — — — 1 1 — —
1 1 1 1 — — — —
11, 11, 26, 26,
— — 1 1
1 1 1 1
— — — —
1 1 1 1
1 1 — —
15, 27, 27, 30,
27, 15, 30, 27,
31 31 31 31
63
E
Check for inclusion in group of 8 ü ü ü ü ü
ü ü ü ü ü ü
Tabe (d) Group 1
Grouping of 8 minterms
Minterms 8, 9, 10, 11, 24, 25, 26, 27
A
B
—
1
Variables C D 0
E
—
—
Tabe (e) PI Table PI terms
Decimal numbers
8
21 AB CDE ü ü 16, 18, 24, 26 ACE ü 9, 11, 13, 15 ABE BDE 11, 15, 27, 31 ABD ü 26, 27, 30, 31 ü 8, 9, 10, 11, 24, ´ BC 25, 26, 27
Minterms 9 10 11 13 15 16 18 21 24 25 26 27 30 31
´
´ ´
´ Ä ´
´ ´
Ä
´
Ä
´ ü
ü
´
´
´ Ä
´ ´
ü
The minimized function is f (A, B, C, D, E) = A B C D E + A C E + A BE + ABD + B C
64
ü
´ ´ ´ Ä ´ ´ ü
CHAPTER 6 6.1 (a) In the 16:1 multiplexer IC 74150, the data output is inverted input, i.e., complement of the data input line selected. Since the data output is 1 when the input variables correspond to decimal numbers 2, 4, 6, 7, 9, 10, 11, 12 and 15, therefore, the data input lines corresponding to these decimal numbers are to be connected to logic 0 and the data input lines 0, 1, 3, 5, 8, 13, and 14 are to be connected to logic 1. The circuit is shown in Fig. Prob. 6.1. Logic 0
Logic 1 0 1 2 3 4 5 6 7 16:1 8 9 Multiplexer 10 74150 11 12 13 14 15 G S3 S2 S1 S0
Y
Logic 0 (MSB) A B C D (LSB) Fig. Prob. 6.1
(b) To realize a four variable truthtable or logic expression using an 8:1 multiplexer the truth table is partitioned as shown by dotted lines (Table 6.3). In this, the inputs A, B, and C are to be connected to S2, S1 , and S0 Table Prob. 6.1(b) A
Inputs B
C
Output Y
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 D D 1 D 1 D D
65
select inputs respectively. Now, we observe the relationship between input D and output Y for each group of two rows. There are four possible values of Y and these are 0, 1, D, and D . These are given in Table Prob. 6.1(b). From this table, we note the output Y for each of the combinations of A, B, and C and then make the connections accordingly. The implementation of this function using a 74152 IC is shown in Fig. Prob. 6.1(b). This IC also has the data output which is complement of the data input line selected. Logic 1 0 1
D
2 3
D
4
74152
Y
5
Logic 0
6 7
S2
S1
A B Fig. Prob. 6.1(b)
S0
C
6.2 A 32:1 multiplexer can be designed using two 16:1 multiplexers following any one of the following approaches. (i) A 32:1 multiplexer will have five selection lines, say, A, B, C, D, and E, where A is the MSB. If A is connected to the Enable input of one of the 16:1 multiplexers, while the enable input of the other multiplexer is connected to A , then for A = 0, the first multiplexer is enabled and for A = 1 the second multiplexer is enabled. Thus for the first 16 of the 32 data inputs one multiplexer gives output depending upon the select inputs while for the remaining 16 data inputs the other multiplexer gives the output. Now if the two outputs are ORed together, the system will function as a 32:1 multiplexer. The complete circuit is shown in Fig. Prob. 6.2(i). (ii) Another method can use two 16:1 multiplexers with their select lines connected together. This is followed by a 2:1 multiplexer to select one of the two outputs. The select line of the 2 : 1 multiplexer is driven from input A. The complete circuit is shown in Fig. Prob. 6.2(ii). 6.3 The truth table of a full-adder in given in Table Prob. 6.3. To realize this, using 8:1 multiplexers requires one multiplexer for Sn and one for Cn output. Assuming 74152 IC, the circuit is shown in Fig. Prob. 6.3.
66
0 1 2
ì ïï Data í inputs ï ïî
M 1 Y1
15 16 : 1 G1
S3 S2 S1 S0
E (LSB) D
Output F (A, B, C, D, E)
C S3 S2 S1 S0
B
16 17 M2 18
ì ï Data ï í inputs ï ïî A (MSB)
·
Y2
16 : 1 31 G2 Fig. Prob. 6.2(i) 0 1 2
ì ïï Data í inputs ï ïî
M1 Y1 15
16 : 1 A(MSB)
G1 Logic 0
S3 S2 S1 S0
B C
S 0
Output M3 Y 1 2 : 1 F (A, B, C, D, E) G3
D E (LSB)
S3 S2 S1 S0 16 17 18
ì ï Data ï inputsí ï ïî
M2 16 : 1
Logic 0 Y2
31 G2
Logic 0 Fig. Prob. 6.2(ii) 67
Table Prob. 6.3 Inputs Bn
An 0 0 0 0 1 1 1 1
Outputs Cn–1
Sn
Cn
0 1 0 1 0 1 0 1
0 1 1 0 1 0 0 1
0 0 0 1 0 1 1 1
0 0 1 1 0 0 1 1
The gates required for NAND-NAND realization are: 4-input NAND gate 1 3-input NAND gates 5 2-input NAND gates 3 Inverters 3 Logic 1 0 1 2 3 4
74152 IC1
5
Sn
6 7 Logic 0
S2
S1
S0
S2
S1
S0
An Bn Cn–1 Logic 1 0 1 2 3 4 5
74152 IC2
6 7 Logic 0 Fig. Prob. 6.3 68
Cn
Therefore, the following IC packages will be required: 7420 – 1 7410 – 2 7400 – 1 In contrast to four packages required in NAND-NAND realization, the realization using 8:1 multiplexers require only 2 IC packages. 6.4 The A inputs are applied directly to the adder, whereas the B inputs are applied through EX-OR gates. When the switch S is in ADD position the outputs of the EX-OR gates will be same as the B inputs. Also Cin = 0. Therefore, the circuit functions as a 4-bit adder. On the other hand, when S is in SUB position, the EX-OR gates function as inverters. Also Cin = 1, therefore, the circuit adds A to the 2’s complement of B and hence functions as a 4-bit subtractor. The complete circuit is shown below. B Input
64444 4744444 8 B2
B3
B1
B0
A input
64748
A3 A2 A1 A0
ADD
7 4 8 3 4-bit Adder
Cin
S
SUB VCC
C0
S3
S2
S1
S0
6.5 Table Prob 6.5 (i) gives the truth table of Gray-to-BCD code converter. Table Prob. 6.5(i) G3
Gray code G2 G1
G0
D
C
0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 1 1 1 1 1
0 1 1 0 0 1 1 0 0 1
0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 1 1 1 0 0
0 0 1 1 1 1 0 0 0 0
69
BCD code B 0 0 1 1 0 0 1 1 0 0
A 0 1 0 1 0 1 0 1 0 1
(a) For A output (i) When G3 G2 = 00
(ii) When G3G2 = 01
G1
G0
A
G1
G0
A
0 0 1 1
0 1 1 0
0 1 0 1
1 1 0 0
0 1 1 0
0 1 0 1
\ A = G1 ⊕ G0 (iii) When G3 G2 = 10
\ A = G1 ¤ G0 (iv) When G3 G2 = 11
G1
G0
A
G1
G0
A
1 1 0 0
0 1 1 0
X X X X
0 0 1 1
0 1 1 0
0 1 X X
\A= X \ A = G1 ⊕ G0 Similarly, we can obtain the expressions for the D, C, and B outputs. These are given in Table Prob. 6.5 (ii). Table Prob. 6.5(ii) G3
G2
D
C
B
A
0
0
0
0
G1
G1 ⊕ G0
0 1 1
1 0 1
0 X 1
1 X 0
G1 X 0
G 1 ¤ G0 X G1 ⊕ G0
The G3 and G2 are used as the select inputs. The complete circuit can be drawn which requires two 74153 packages and one 7486 package. (b) The complete circuit is shown in Fig. Prob. 6.5(b). It requires one 74154, one 7430, one 7420, and one 7400 IC packages. 6.6 The truth table of BCD-to-7-segment decoder is given in Table Prob. 6.6(i) and Fig. Prob 6.6(i) shows a common-anode 7-segment display device. Table Prob. 6.6(i) D
C
0 0 0 0 0 0
0 0 0 0 1 1
BCD Inputs B A 0 0 1 1 0 0
0 1 0 1 0 1
a
b
Seven-Segment Outputs c d e f
0 1 0 0 1 0
0 0 0 0 0 1
0 0 1 0 0 0
70
0 1 0 0 1 0
0 1 0 1 1 1
0 1 1 1 0 0
g 1 1 0 0 0 0 (Contd.)
Table Prob. 6.6(i) (Contd.) D
C
0 0 1 1 1 1 1 1 1 1
1 1 0 0 0 0 1 1 1 1
BCD Inputs B A 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1
a
b
Seven-Segment Outputs c d e f
g
1 0 0 0 X X X X X X
1 0 0 0 X X X X X X
0 0 0 0 X X X X X X
0 1 0 0 X X X X X X
0 1 0 1 X X X X X X
0 1 0 1 X X X X X X
0 1 0 0 X X X X X X
Y0 Y1
Aü (LSB)ï ï ï ï ï ï Bï ï ï ï ïï BCD ýoutputs ï ï Cï ï ï ï ï ï ï ï Dï (MSB) ï þ
Y2 Y3 Y4 Y5 G1
74154
G0
Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14
S3
S2
S1
Y15 S0
G
G
G
G
2 2444 1 0 13444 3
Gray code inputs Fig. Prob. 6.5(b)
(a) From Table Prob. 6.6(i), we can prepare Table Prob. 6.6(ii) which gives outputs in terms of A and B inputs for each combination of D and C inputs. The circuit for generating data inputs for the multiplexers corresponding to Table Prob. 6.6 (ii) is shown in Fig. Prob. 6.6 (ii). The ICs required are: 74153 3 1 packages 2 71
7408
3/4 package
7432 7404
3/4 package 1/2 package Anode
a b
a
c d
f
e
e
f g
b g c · DP
d
DP
Fig. Prob. 6.6(i)
Table Prob. 6.6(ii) D
Inputs C
Outputs d
a
b
c
BA 0 0 X
0
0
BA
0
0 1 1
1 0 1
A 0 X
B⊕ A 0 X
e
f
g
BA
A
A+B
B
B¤A A X
A+ B A X
AB 0 X
AB 0 X
A+ B
B
B
BA
A+B
BÅA AB
B¤A
BA
A A Fig. Prob. 6.6(ii)
(b) The circuit is designed in a way similar to Prob. 6.5. The ICs required are: 74154 one package 7420 one package 7410 one package 72
7430 one package 7404 1/6 package (c) The IC 7442 is a BCD-to-decimal decoder circuit with active-low outputs. These outputs are to be connected exactly in the same way as in the case of part (b) realization. The IC packages required are same as in part (b) with 74154 replaced by 7442. (d) From the IC packages requirements for parts (a), (b), and (c), we observe the savings in hardware when demultiplexers/decoders are used for the realization of multiple output systems. 6.7 Table Prob. 6.5(i) can be rearranged suitably to give the truth table of BCD-toGray code converter. (a) From the truth table, Table Prob. 6.7 (a) is obtained following the procedure used in Prob. 6.1(b). Table Prob. 6.7(a) D
C
B
G3
G2
G1
G0
0
0
0
0
0
0
A
0 0
0 1
1 0
0 0
0 1
1 1
A A
0 1
1 0
1 0
0 1
1 1
0 0
A A
The circuit can now be designed using four 74151A ICs (one for each of the outputs). The D, C, and B inputs are to be applied to the S2, S1, and S0 select inputs respectively. (b) Table Prob. 6.7(b) can be obtained from the truth table following the procedure of Prob. 6.5 (a). The circuit can now be designed using two 74153 ICs and two EX-OR (7486) gates. Table Prob. 6.7(b) D
C
G3
G2
G1
G0
0 0 1 1
0 1 0 1
0 0 1 X
0 1 1 X
B B 0 X
A⊕ B A⊕ B A X
(c) Following the approach similar to (b), we obtain Table Prob. 6.7 (c). Here eight rows of the truth table are grouped together. Table Prob. 6.7(c) D
G3
G2
G1
G0
0 1
0 1
C 1
B⊕ C 0
A ⊕ B A
73
The circuit can now be designed using one 74157 (Quad 2:1 multiplexer) IC and two EX-OR gates of 7486. (d) Following the procedure used in Example 6.3, the circuit can be designed using one BCD-to-decimal decoder IC 7442 and NAND gates (2-, 4-, 5-, and 6-input). (e) The minimized expressions are G3 = D G2 = C + D G1 = C B + C B G0 = B A + B A The realization will require eleven 2-input NAND gates. (f) The package count for each part are given in Table Prob 6.7(d) Table Prob. 6.7(d) Part
No. of IC packages
a b c d e
74151A – 4, 7404 – 1 74153 – 2, 7486 – 1 75157 – 1, 7486 – 1 7442 – 1, 7430 – 2, 7420 – 1 7400 – 3
6.8 The truth table for f1, f2, and f3 outputs is given in Table Prob. 6.8(i) (a) The truth table is reduced to Table Prob. 6.8(ii) for realization using 8 : 1 multiplexers. The circuits can now be designed for f1, f2, and f3 outputs using multiplexers and inverters. (b) Using the truth table the circuits for f1, f2, and f3 can be designed following the procedure outlined in Example 6.1. The realizations will require one 16 : 1 multiplexer for each output. (c) The circuit can be designed using one demultiplexer and two 8-input and one 6-input NAND gates. Table Prob. 6.8(i) D
Inputs C
B
A
f1
Outputs f2
f3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1
1 1 1 1 0 0 0 0 0 0 0 1 1 0 1 1
0 0 1 0 1 1 1 0 1 0 0 0 1 0 0 0
74
Table Prob. 6.8(ii) D
C
B
f1
f2
f3
0 0 0
0 0 1
0 1 0
A A A
1 1 0
0 A 1
0 1 1
1 0 0
1 0 1
A A A
0 0 A
1 1
1 1
0 1
A A
A 1
A A 0 A 0
6.9 In a 40:1 multiplexer, there are 40 data input lines (I0 through I39), 6 select lines FEDCBA. The lower order three select bits C, B, and A are used as S2, S1, S0 select inputs respectively for 8:1 multiplexers M1 through M5. The higher order three select bits F, E, and D are used as select inputs S2, S1, and S0 for the multiplexer M6, which selects output of one of the multiplexers M1 through M5. I0 – I7
M1 G
S2 S1 S0 C B A S2 S1 S0
I8 – I15
G
I16 – I23
M2
0 1 2 3 4 M6 5 6 7 G S2 S1 S0
M3 G
S2 S1 S0 C B A
I24 – I31
F E (MSB)
S2 S1 S0 M4 G C B A (LSB)
I32 – I39 Enable
S2 S1 S0 G
M5 Fig. Prob. 6.9 75
D
Y
For example if the select inputs are 011111, data input 7 of M2 (I15) will appear at the output Y. 6.10 The BCD-to-decimal decoder is to be used as an 1 : 8 demultiplexer. The address inputs for demultiplexers D1 through D6 are C, B, and A. D is active-
D X2
C
X1
B
X0 (LSB)
A
D1 7442
D X2 X1 X0
Enable
0 1 2 3 D6 4 D 7442 5 6 7 8 C B A9
D2
C B
7442
A
D X2 X1 X0 (
X5 X4 X3 (MSB)
C B
D3 7442
A
D X2 X1 X0
D4
C B
7442
A
D X2
C
X1
B
X0
A
D5 7442
Fig. Prob. 6.10 76
0 1 2 3 4 5 6 7 8 9
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7 8 9
8 9 10 11 12 13 14 15
0 1 2 3 4 5 6 7 8 9
16 17 18 19 20 21 22 23
0 1 2 3 4 5 6 7 8 9
24 25 26 27 28 29 30 31
0 1 2 3 4 5 6 7 8 9
32 33 34 35 36 37 38 39
low input for demultiplexer function. The outputs 8 and 9 of D1 through D5 are not used in this configuration. The lower order three bits of the address X2, X1, and X0 are applied at the C, B, A select inputs respectively of each decoder chip D1 through D5. The higher order three bits of the address X5, X4, and X3 are applied at the C, B, and A select inputs respectively of D6. For example, if the 6-bit select inputs are 001111, then output 1 of D6 is activated, which activates decoder D2 and the output 7 of this decoder goes low. This corresponds to output on line 15 (which is same as the decimal equivalent of 001111). The complete circuit is shown in Fig. Prob. 6.10. 6.11 For the full-adder circuit designed using half-adder circuits shown in Fig. Prob. 6.11. EX–OR(1) An Bn
EX–OR(2)
S1
S2 = Sn C1 AND-2
C2 OR
AND–1
Cn
Cn–1 Fig. Prob. 6.11
The propagation delay time for Cn is tpd = tpd [EX-OR(1)] + tpd (AND-2) + tpd (OR) = 20 + 10 + 10 = 40 ns This is the propagation delay time for carry to travel one full-adder. For an nbit adder, this carry has to ripple through all the n adders. Therefore, the propagation delay time for the carry to propagate from C–1 to Cn–1 in the circuit of Fig. 6.12 (a) will be n ´ 40 = 40 ns. 6.12 Let the four digits BCD numbers be P4P3P2P1 and Q4Q3Q2Q1. P4 and Q4 are applied at the A and B inputs respectively of adder # 4 and similarly the other inputs are applied as shown below. Q4
P4
BCD adder #4 C¢¢¢¢ C2 0
C0
S15–S12
Q3
P3
Q2
P2
Q1
P1
BCD adder #3 C¢¢¢ C1 0
BCD adder #2 C¢¢0 C0
BCD adder #1 C¢0 C–1
S11–S8
S7–S4
S3–S0
144444444444444 42444444444444444 3 5-digit output
Fig. Prob. 6.12 77
6.13 Its truth table is given in Table Prob. 6.13. Using K-maps the minimized expressions given below are obtained. Table Prob. 6.13 A1
A0
Inputs B1
B0
A>B
Outputs A=B
A B = A0 B 1 B0 + A1 A0 B 0 + A1 B 1 A = B = A1 B 1 (A0 ¤ B0) + A1B1 (A0 ¤ B0) = (A0 ¤ B0) (A1 ¤ B1) A < B = A 1 A 0 B0 + A 0 B1B0 + A 1B1 The complete circuit can be drawn using gates. 6.14 The comparator C1 compares the least significant four bits. Its A > B, A = B, and A < B outputs are connected to the corresponding cascading inputs of C2 respectively. The complete circuit is shown below. A4 – A7
A0 – A3 B0 – B3
A>B C1
A=B
A>B B4 – B7
C2
AB
A>B A=B A C3. 11.11 During the interval when f1 = 1, C charges to logic 1 through T3, independently of data input (since f2 = 0, therefore, T2 is OFF). This logic level remains on C after f1 returns to logic 0. Now, if the data input is 1, then during f2 = 1, T1 and T2 will conduct and C will get discharged to logic 0 level. On the other hand, if the input is at logic 0, T1 will be OFF and C will continue at logic 1 level. In general, the logic level of C will be complement of input logic level. Similarly, during f3 and f4 phases, the complement of logic level on C will be transferred to output capacitor (between drain of T6 and ground). 11.12 (i) Association Operation: When A1A0 = 11, outputs of the OR gates are 1 irrespective of the logic level at W (i.e., W = X). The outputs of the NOR gates will be 0, which will disable the latches. The output of the EX-OR gate will be 0, if the data input bit is same as the bit stored (Q0), otherwise it is 1. Therefore, the output of the AND gate is 1 for mismatch and 0 for match. The output Y of the wired-OR gate will be 0 if both the data inputs match with the bits stored, otherwise it will be 1. The data outputs D1 and D0 are both 0. (ii) Associate Operation with Higher Bit Masked: When A1A0 = 01, and
W = 1, the operation of the circuit will be similar to the operation explained in (i) above except that the output of the AND gate on the I1 side will always be 0, therefore, match condition will be checked only for I0 bit. The AND gate of D1 output is enabled. (iii) Associate Operation with Lower Bit Masked: The operation is similar to the operation of (ii) above. (iv) Read Operation: When A1A0 = 00, and W = 1, the latches are disabled. Depending upon which Y is selected by making it 0, the output Q0 of the latch appears at the corresponding D output. It is also possible to read more than one location at a time. This happens when more than one address input is made 0. The output will be OR operation performed on all the selected outputs. (v) Write Operation: When A1A0 = 00, and W = 0, the latches are enabled for the location by making the Y input 0. The same data also appears at the D outputs following the arguments of (iv) above. 140
(vi) Associate and Write at the Match Addresses: (a) When A1A0 = 01 and W = 0, the association operation is performed for the lower bit (ii) above. The outputs will be 0 for matched conditions and 1 for mismatch conditions. When there is matching, the corresponding higher bit (I1) is latched into the latch and it also appears at the D1 output. (b) When A1A0 = 10 and W = 0, the operation will be similar to the operation of part (a) above. The matching will be performed for higher bits and the lower bit (I0) will be stored in the locations for which I1 match. 11.13 Since 16 ´ 2 = 2 ´ (8 ´ 2), therefore, it requires two chips. The data inputs, data outputs, and mode control inputs of two 8 ´ 2 CAMs are connected as shown in Fig. Prob. 11.13. The resulting system has 16 address inputs (Y0 – Y15). Thus, it becomes a CAM of sixteen 2-bit words. I1 I0 A1 A0
A0
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
8´2 CAM IC1
A1 I0 I1
W
D1
D0 D0 D1
W
W
D1
D0
A0 A1 I0
8´2 CAM IC2
I1
Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15
Fig. Prob. 11.13
11.14 8 ´ 8 = 4 ´ (8 ´ 2) Therefore, the number of chips required is four. Since the number of words is 8, therefore, Y0 – Y7 of each chip are connected to a common bus. The circuit of 8 ´ 8 CAM is shown in Fig. Prob. 11.14. 11.15 16 ´ 8 = 2 ´ (8 ´ 8) Therefore, for designing a 16 ´ 8 CAM, two 8 ´ 8 CAMs as shown in Fig. 11.14 can be connected as shown in Fig. Prob. 11.15. 11.16 It is a 16-word, 8-bit word CAM. The first operation is to interrogate the MSB of all words for a 1 with all other bits masked, i.e., the key is 141
Y0 – Y7
W
A7 A6 I7 I6
A5 A4 I5 I4
A3 A2 I3 I2
A1 A0 I1 I0
A1 A0 I1 I0
A1 A0 I1 I0
A1 A0 I1 I0
A1 A0 I1 I0
8´2 CAM
8´2 CAM
8´2 CAM
8´2 CAM
Y0 – Y7
Y0 – Y7
Y0 – Y7
W D1
D0
W D1
D0
W D1
D0
W D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Fig. Prob. 11.14
I7
I0 Y0-Y7
8 ´ 8 CAM
D7 D6 D5 D4 D3 D2 D1 D0
A7 A6
D0 D1 D2 D3 D4 D5 D6 D7
A5 A4 A3
W
A2 A1 A0
Y0-Y7
D7 D6 D5 D4 D3 D2 D1 D0
Y8-Y15
8 ´ 8 CAM Y0-Y7
I7
I0
Fig. Prob. 11.15
1XXXXXXX. If only one word indicates a match, then the maximum valued word search is complete. However, if several words indicate a match, then the CAM is to be interrogated again with key as 11XXXXXX. In case no match occurs when the MSB is interrogated, then the next key has to be 142
11.17 11.18
11.19
11.20
01XXXXXX. This process is to continue till at the most all the bits of the words are interrogated. In any case no more than 8 interrogation cycles will be required to determine the maximum valued word. In the case of RAM, each word is to be compared sequentially. Therefore, the time required for the search will be dependent on the number of words stored which is sixteen in this case. The operation is similar to the operation of Prob. 11.16 with 1’s replaced by 0’s in the search process. A CAM is ideal for this. Because of the parallel search operation in CAM, just in one cycle, we can find out whether the word is already stored or not. If not, it can be stored in the next location available. In contrast to this, the search process is serial in a RAM which is time consuming and hence a RAM is not suitable for this purpose. The inputs and the outputs of all the CCDs are to be connected in parallel. The additional address bits are decoded and used to select one of the CCDs for read/write operation. The clock and write enable are also connected in parallel. For expanding word length, the address, chip select, write enable, and clock inputs of all the devices are connected in parallel. The number of data inputs and outputs are used independently. The number of inputs/outputs will be equal to the number of CCDs.
143
CHAPTER 12 12.1 The BCD-to-Excess-3 code converter’s truth table is given below. A
B
BCD C
D
E3
Excess-3 E2 E1
E0
0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 1 1 1 0 0
0 0 1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1 0 1
0 0 0 0 0 1 1 1 1 1
0 1 1 1 1 0 0 0 0 1
1 0 1 0 1 0 1 0 1 0
1 0 0 1 1 0 0 1 1 0
(a) For the design using PROM, a PROM of size 10 ´ 4 is required, but since PROM of this size does not exist, therefore, a PROM of size 16 ´ 4 is to be used. Data is to be stored in the PROM at the addresses corresponding to the BCD code, the data is Excess-3 code. For example at the address 0000, the data stored is 0011 and at the address 1001 the data stored is 1100. (b) Logical expressions can be written for E3, E2, E1, and E0 outputs in terms of A,B,C, and D inputs. To reduce the hardware requirements, these expressions can be minimized using K-maps. A B C D
E3 E2 E1 E0 Fig. Prob. 12.1 (b)
The simplified expressions are: E3 = A + BC + BD E2 = B C D + B C + B D E1 = C D + CD E0 = D 144
The size of PLA required is No. of inputs =4 No. of outputs =4 No. of product terms =9 The circuit is given in Fig. Prob. 12.1(b). (c) The required size of PAL is No. of inputs =4 No. of outputs =4 Minimum number of =3 AND gates for each output The circuit is given in Fig. Prob. 12.1(c). A E3 B E2 C E1 D E0
Fig. Prob. 12.1 (c)
12.2 Follow similar procedure as given in Prob. 12.1. 12.3 Prepare truth table and follow similar procedure as given in Prob. 12.1. 12.4 The inputs of two 82S100 devices are to be connected in parallel. This will result in 8 + 8 = 16 outputs. 12.5 The inputs I0 to IM-1 are common for all the PLAs. Depending on the values of IM to IM+Q-1, one of the output lines of the decoder will go LOW activating the corresponding PLA and disabling all the other PLAs. Hence, the number of inputs increases. 12.6 Architecture of a PLD refers to the attributes of the device significant to the logic of a design to be implemented. It includes. · Configuration of pins. · The size and the arrangement of the programmable array(s). · Configuration of the input and output interface logic. 145
12.7
12.8
Input
Column
Input/output
Column
I1
2
IO2
6
I1 I2
3 0
IO 2 IO3
7 10
I2 I3
1 4
IO 3 IO4
11 14
I3 I4
5 8
IO 4 IO5
15 18
I4 I5
9 12
IO 5 IO6
19 22
I5 I6
13 16
IO 6 IO7
23 26
I6 I7
17 20
IO 7
27
I7 I8
21 24
I8 I9
25 28
I9 I10 I 10
29 30 31
Input
Column
Input/output
Column
I1
0
IO1
2
I1 I2
1 4
IO 1 IO8
3 30
I2 I3
5 8
IO 8 O2
31 6
I3 I4
9 12
O2 O3
7 10
I4
13 16
O3 O4
11 14
I6
17 20
O4 O5
15 18
I6
21
O5
19
I7
24
O6
22
I7 I8
25 28
O6 O7
23 26
I8
29
O7
27
I5 I5
146
12.9 It has four multiplexers, MUX–1, MUX–2, MUX–3 and MUX–4. Each one may be programmed to be in 0 or 1, which means its output will be either same as input 0 or input 1. Table below gives all the possible conditions. MUX – 1 MUX – 2 MUX – 3 MUX – 4
No. of product Terms
0 0 0
0 0 0
0 0 1
0 1 0
8 8 8
0 0 0 0
0 1 1 1
1 0 0 1
1 0 1 0
8 8 8 8
0
1
1
1
8
1 1 1
0 0 0
0 0 1
0 1 0
7 7 7
1
0
1
1
7
1 1 1
1 1 1
0 0 1
0 1 0
7 7 7
1
1
1
1
7
Output Enable pin-11 pin-11 Term Controlled Term Controlled pin-11 pin-11 Term Controlled Term Controlled pin-11 pin-11 Term Controlled Term Controlled pin-11 pin-11 Term Controlled Term Controlled
Output
Output pin/FF output
Reg. Comb. Reg.
feedback input feedback
Comb. Reg. Comb.
input feedback input
Reg.
feedback
comb. Reg. Comb.
input feedback input
Reg.
feedback
Comb. Reg. Comb.
input feedback input
Reg.
feedback
Comb.
input
12.10 These are given in Fig. Prob. 12.10. 12.11 Here the output of an AND gate controls the output. (a) Open all the inputs to the controlling AND gate. (b) Keep all the inputs intact (connected) to the controlling AND gate. (c) Keep the connections corresponding to the inputs A, B, C, D, E , F , G and H intact to the controlling AND gate and open all other connections. 12.12 When x1 = 0, f will be obtained from the upper multiplexer. For x2 = 0, topmost cell will be selected and f will be 1; whereas for x2 = 1, the cell second from the top will get selected and f = 0. Similarly, for x1 =1 when
x2 = 1, f = 0
and when
x2 = 1, f = 1
147
Registered output B = 1
Combinational output B = 0
BI-DIRECTIONAL I/O CD = 11
A=1 AR D Q SP
AR D Q
A=1
COMBINATIONAL FEEDBACK CD = 10
SP
AR D Q SP
AR D Q
A=0
SP
AR D Q
AR D Q
A=1
SP
SP
A=0
AR D Q
AR D Q
SP
SP
Fig. Prob. 12.10 148
Q
Q
REGISTER FEEDBACK CD = 00
A=0
Therefore, the truth table will be as given below. x1
x2
f
0 0 1 1
0 1 0 1
1 0 0 1
12.13 The truth table of the given function f is x1
x2
x3
f
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 1 1 0 1 0 0 1
when x1 = 0, f will be obtained from output of top multiplexers’ structure, when x1 = 1, f will be obtained from output of bottom multiplexers’ structure. Now, when x2 = 0, the output will be obtained from the top-most multiplexer and when x2 = 1, it will be obtained from the next multiplexer. When x3 = 0, the output will be from the top-most cell, and when x3 = 1 it will be from be next cell. Similarly, the complete circuit can be analyzed. The bits to be stored will be 0 1 1 0 1 0 0 1
149
CHAPTER 13 13.1 The memory address space is given by M = 2P where, P is the address bus width. The memory address space for the mPs are given below. Microprocessor
Memory address space
8080A 6800 8086 9900 Z8000
64 K bytes 64 K bytes 1 M bytes 64 K bytes 8 M bytes
13.2 The number of distinct combinations of 8-bit words = 28 = 256 Therefore, the total number of instruction codes, assuming single byte op code = 256. The total number of instruction codes in 8085A mP is 246. 13.3 (a) 2142 is a 1024 ´ 4 bits RAM Therefore, 4 K bytes = 4 K ´ 8 bits = 4 ´ 2 ´ (1 K ´ 8) bits = 8 chips 2716 is a 2 K ´ 8 bits EPRPM. Therefore, only one 2716 chip is required. (b) Let the first 2 K bytes be in EPROM and next 4 K bytes be in the RAMs. The relevant connections are shown below. A8 – A15 8085 A
WR RD
AD0 – AD7 ALE A0 – A7 8212
CLR
DS2 MD DS 1
+VCC Fig. Prob. 13.3(a) 150
Other connections are indicated below: A0 – A10 from mP to A0 – A10 of 2716 A0 – A9 from mP to A0 – A9 of each of 2142 CS2 of each 2142 to Vcc WR from mP to WE of each 2142
RD from mP to OD of each 2142 A10
A0
0
A11
A1
1
A12 (from mP)
A2
2
To CS 1 of RAM set 1
3 4
To CS 1 of RAM set 2 To CS 1 of RAM set 3
E1
5
To CS 1 of RAM set 4
E2 E3
6
8205 A13 A14 A15 (from mP)
To CS of 2716
7
Fig. Prob. 13.3(b)
(c) The address of various chips are given below. Memory chips EPROM RAM pair RAM pair RAM pair RAM pair
Starting address in hex.
Last address in hex.
0000 0800 0C00 1000 1400
07FF 0BFF 0FFF 13FF 17FF
1 2 3 4
13.4
(i) MVI A, 00H ; Load accumulator with zero (ii) SUB A ; Subtract A from A (iii) ANI 00H ; AND A with zero (iv) XRA A ; A EX-OR A Note that the information beyond semicolon (;) are comments. 13.5 Let D-E and H-L pairs be pointers to source and destination memory locations respectively. The program is given below: LXI D, 0F00 H ; Initialize source pointer LXI H, 1F00 H ; Initialize destination pointer LXI B, 100H ; Initialize counter LOOP: LDAX D ; Load A with contents of source memory CMA ; Complement A MOV M, A ; Store in destination memory INX D ; Increment pointers INX H 151
DCX B MOV A, C ORA B JNZ LOOP
; Decrement counter ; Check counter for zero
NEXT: 13.6 The program is given below: LXI H, 0A02H ; Store destination address in H-L pair LDA 0A00H ; Load A with first number MOV B, A ; Transfer to B LDA 0A01H ; Load A with second number CMP B ; Compare A and B JZ FINIS ; Go to FINIS if the two numbers are equal JC GREAT ; If CY = 1, (A) < (B) MOV M, A ; Otherwise (A) > (B) JMP FINIS GREAT: MOV M, B FINIS : 13.7 The following instructions will clear the memory location. LXI H, 01A0H MVI M, 00H 13.8 LXI H, A001H ; Initialize pointer MOV C, M ; Get the number of bytes in C INX H ; Increase pointer by 1 START : MOV A, M ; Get a byte of data in A REP : DCR C JZ STOP ; Stop at end of data INX H CMP M ; Compare JC REP ; If (A) < (M), try next number JMP START STOP: STA FF00H ; Store the smallest element END 13.9 ANI 0FH 13.10 LOOP: DCR 0 JZ FINIS IN DATA MOV M, A INX H JMP LOOP FINIS: MOV B, A
152
SOLUTION The operation performed by each instruction is given below: START: LXI H, BUFR ; Initialize H-L pair with address BUFR MOV C, 0BH ; Initialize counter with decimal 11 LOOP: DCR C ; Decrease counter by one JZ FINIS ; Go to FINIS if counter = 0 IN DATA ; Input a byte from DATA port MOV M, A ; Move the byte to memory ; location pointed to by H-L pair INX H ; Advance the pointer by one JMP LOOP ; Go to loop FINIS: MOV B, A ; Move the contents of A to B The operation performed by this program is to input ten bytes from input port DATA and store them in memory locations starting from BUFR. 13.11 N=3+3+1+1+1+1+1+1 = 12 bytes 13.12 (A) 0000 1000 (B) 1001 0011 ADD B 1001 1011 The result is not a valid BCD number. ADD B instruction must be followed by DAA instruction. The effect of this is given below: 1001 1011 0000 0110 Add 6 because the least-significant four bits do not represent a valid BCD digit 1010 0001 0110 0000 Add 60 because the most-significant four bits do not represent a valid BCD digit 10000 0001 = (101)10 13.13 Assume a set of ten keys for entering BCD number and a 7-segment display for displaying this number. It is also assumed that BCD-to-7-segment codes are stored in memory from the starting address 00XXH. The block diagrams for the input and output devices are shown in Fig. Prob. 13.13(a) and (b) respectively. Assume 01H and 02H as the port addresses of the input device and output device respectively. The addresses are decoded and proper signals are generated for Enable and Device Select terminals for reading and writing. The program can be written as MVI B, XXH LXI H, 0000H IN 01H ADD B MOV L, A MOV A, M OUT 02H 153
VCC
D (MSB) C
Inverting Tristate Buffer
D2 Data bus of mP
Decimal-toBCD Encoder (Inputs & outputs active-low)
D3
B D1 A D0
Enable (a) Current limiting resistors
VCC Common anode
Data bus
a b c f d e e f g
D-type Latch
Device Select
(b)
Fig. Prob. 13.13
13.14 The last six instructions will be POP PSW POP H POP D POP B EI RET 154
a g
b c
d
Here it is assumed that the interrupts are kept disabled during the execution of the sub-routine. 13.15 The ASCII code for decimal 0 is 0110000 and for? is 0111111. The program is given below: LXI H, 00F1H LDA 00F0H CPI 0AH JNC QUE ADI 00110000 B MOV M, A JMP STOP QUE : MVI M, 00111111 B STOP: END 13.16 Refer to Table 13.3 mP
Address bus width
8086 80186 80286 80386SL 80386 DX 80486 DX Pentium
20 20 24 25 32 32 32
13.17 Eight 8-bit or four 16-bit AX: AH, AL BX: BH, BL CX: CH, CL DX: DH, DL 13.18 Four zeros at the least-significant four bit positions are appended to the 16bit segment register, making it 20-bit address. Actual physical 20-bit address is this 20-bit data plus the contents of the pointer register. 13.19 CS = 2000H IP = 1A00H 20-bit address of the next instruction byte will be fetched from 20000 + 1A00 21A00 H 13.20 20-bit current address of the stack will be 24000 + A000 2E000 H
155
CHAPTER 14 14.1 (a) (b) (c) (d) (e) (f) 14.2 (a)
Yes. It contains all the allowed characters. No. character ‘ ’ is not permitted. No. starting character can not be a numeral. Yes. Upper and lower case characters can be mixed. No. Hyphen (–) is not allowed. No. Two consecutive underscores are not allowed. ENTITY NAND 2 IS PORT (X, Y : IN BIT; Z : OUT BIT); END NAND 2; (b) ENTITY NAND 3 IS PORT (A, B, C : IN BIT; Y : OUT BIT); END NAND 3; 14.3 A 4:1 multiplexer is shown in Fig. Prob. 14.3. It has four data inputs I0, I1, I2, and I3 and two select inputs A and B. There is one output Y. I0 I1
Y
I2 I3 AB Fig. Prob. 14.3
The entity declaration is LIBARY IEEE; USE IEEE STD-LOGIC; 1164 ALL; ENTITY MULTI-4 IS PORT (IO, I1, I2, I3, A, B ; IN STD-LOGIC; Y: OUT STD-LOGIC); END MULTI_4; 14.4 (a) For 2-input NAND gate ARCHITECTURE df_nand 2 OF NAND 2 IS BEGIN Z Ü NOT (X AND Y) AFTER 10 ns; END df-nand 2; (b) For 3-input NAND gate ARCHITECTURE df_nand 3 OF NAND 3 IS BEGIN Y Ü NOT (A AND B AND C) AFTER 10 ns; END df_nand 3; 14.5 LIBRARY IEEE; USE IEEE. STD_LOGIC_1164. ALL; -- Name of entity chosen is F_A 156
ENTITY F-A IS PORT (A, B, CIN: IN STD_LOGIC; S COUT: OUT STD_LOGIC); END F_A; ARCHITECTURE FA_STR OF F_4 IS COMPONENT NAND 3 PORT (X1, X2, X3 : IN STD-LOGIC; Y: OUT STD_LOGIC); END COMPONENT; COMPONENT NAND 4 PORT (X4, X5, X6, X7 : IN STD-LOGIC; Z: OUT STD_LOGIC); END COMPONENT; COMPONENT INV PORT (P : IN STD_LOGIC; Q : OUT STD_LOGIC); END COMPONENT; COMPONENT NAND2 PORT (X8, X9 : IN STD_LOGIC; R : OUT STD_LOGIC); END COMPONENT; SIGNAL AB, BB, CINB, S1, S2, S3, S4, S5, S6, S7 : STD_LOGIC; BEGIN I1 : INV PORT MAP (A, AB); I2 : INV PORT MAP (B, BB); I3 : INV PORT MAP (CIN, CINB); N1 : NAND3 PORT MAP (AB, B, CINB, S1); N2 : NAND3 PORT MAP (AB, BB, CIN, S2); N3 : NAND3 PORT MAP (A, BB, CINB, S3); N4 : NAND3 PORT MAP (A, B, CIN, S4); N5 : NAND4 PORT MAP (S1, S2, S3, S4, S); N6 : NAND2 PORT MAP (A, B, S5); N7 : NAND2 PORT MAP (B, CIN, S6); N8 : NAND2 PORT MAP (A, CIN, S7); N9 : NAND3 PORT MAP (S5, S6, S7 COUT); END FA_STR; 14.6 LIBARY IEEE; USE IEEE. STD_LOGIC-1164. ALL; ENTITY F-A IS PORT (A, B, CIN: IN STD_LOGIC; S, COUT: OUT STD_LOGIC) END F-A; ARCHITECTURE FULL_ADDER OF F_A IS; BEGIN S Ü ((NOT A) AND B AND (NOT CIN)) OR ((NOT A) AND (NOT B) AND CIN) OR (A AND (NOT B) AND (NOT CIN)) OR (A AND B AND CIN) AFTER 15 ns; C OUT Ü (A AND B) OR (B AND CIN) OR (A AND CIN) AFTER 10 ns; END FULL_ADDER;
157
A
B
CIN
I2
I1 AB
S1
I3 N 1 BB
CINB S2
N2
N5 S3
N3
S4
N4 A B B CIN A CIN
S
S5
N6
S6
N7
S7
N8
Fig. Prob. 14.5
158
N9
COUT
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