Microprocessor Complete
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MICROPROCESSOR & INTERFACES (CSE & IT SEM -V) Prepared By: SUDHA NAIR LECTURER(E&TC) R.C.E.T,BHILAI. MYcsvtu Notes
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UNIT- I Microprocessor Architecture
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Introduction to Microprocessors
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What is a microprocessor? A microprocessor is a programmable digital electronic
component that incorporates the functions of a central processing unit or CPU on a single semi conducting integrated circuit.
One or more typically serve as the CPU in computer
systems, embedded devices, or handheld devices.
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What is a microprocessor? That means your laptop at home and the PC in your
computer lab! The advent of the microprocessor astounded many
people. It was an entire computation engine on one tiny chip.
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Going from the ENIAC which filled an entire room and used over 18,000 vacuum tubes to a 1/8th by 1/6th of an inch (fingernail size) mega chip!
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The First Microprocessor: Intel 4004 Transistor count Today's Intel® Core™2 Duo processors contain over
291 million transistors.
This is 100,000 times the number of transistors than
were in the 4004, which had 2,300 transistors when it was introduced in 1971.
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The First Microprocessor: Intel 4004 A human hair
The Intel 4004 microprocessor circuit line width was 10 microns or 10,000 nanometers. Today Intel's microprocessors have circuit line widths of .065 microns or 65 nanometers. A nanometer is one billionth of a meter. By comparison, a human hair is approximately 100 microns or 100,000 nanometers.
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The First Microprocessor: Intel 4004 Manufacturing The Intel 4004 microprocessor was produced on 2" wafers
initially and then on 3" wafers. Today's microprocessors are produced on 12" or 300mm wafers.
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The First Microprocessor: Intel 4004 The Intel 4004 microprocessor is unique in that, if it is
not the smallest, it is one of the smallest microprocessor designs that ever went into commercial production. The 4004 microprocessor is composed of 5 layers.
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Intel 4004
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Who invented the microprocessor and when? In November 1971, a company called Intel, which we
are all familiar with today, is given most of the credit for inventing the first microprocessor (Intel 4004).
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Who invented the microprocessor and when?
Three Intel engineers named Federico Faggin, Ted Hoff and Stan Mazor are said to be the brilliant minds behind the microprocessor.
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Why was the microprocessor invented? The microprocessor reduced the word size of the CPU
from 32 bits to 4 bits so that the transistors of its logic circuits would fit onto a single part.
Before the microprocessor, electronic CPUs were
typically made of big discrete switching devices containing only a few transistors.
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Why was the microprocessor invented? The microprocessor greatly reduced the cost of
processor power and the physical size of the CPU.
The evolution of microprocessors has been known to
follow Moore‟s Law which states that the complexity of an integrated circuit, with respect to minimum component cost, doubles every 24 months.
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Why was the microprocessor invented? This has held true throughout the years……………….
………………………. ever since the microprocessor was created.
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The “building block” Microprocessors forever changed the way that
computing systems are made.
This breakthrough invention powered the calculator and
paved the way for embedding intelligence in inanimate objects as well as the personal computer.
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Applications of microprocessors Without this amazing invention, we would not be as
technologically advanced in computers as we have become today. Embedded intelligence brought by microprocessors
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Microprocessor’s interference in day to day life……
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Automation
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Communication
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Brief history of microprocessor Intel i4004 processor Identification Model name: i4004.
Supplier: Intel. Component class: CPU.
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Intel i4004 processor Architecture
4 bit data bus.
12 bit address bus (multiplexed). Separate address space for instructions and data (Harvard architecture).
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Intel i4004 processor Physics
Manufacturing technology: PMOS. Number of transistors: 2250. Die size: 24 mm2. Packaging: 16 pin CerDIP. Dates Introduction date: 1970. First microprocessor ever built. MYcsvtu Notes
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Intel i4040 processor Identification Model name: i4040.
Supplier: Intel. Component class: CPU.
Compatibility Intel i4004 CPU with extra features: more instructions, interrupt support.
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Intel i4040 processor Architecture 4 bit data bus.
12 bit address bus (multiplexed). Separate address space for instructions and data (Harvard architecture).
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Intel i4040 processor Physics
Manufacturing technology: PMOS Packaging: 24 pin CerDIP. Dates Introduction date: 1972
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Intel i8008 processor Identification Model name: i8008.
Supplier: Intel. Component class: CPU.
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Intel i8008 processor Architecture
8 bit data bus.
14 bit address bus (multiplexed). Separate address space for instructions and data (Harvard architecture). Clock speed300 kHz
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Intel i8008 processor Physics
Manufacturing technology: PMOS. Number of transistors: 3300. Packaging: 18 pin CerDIP. Dates Introduction date: April 1972.
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Intel i8080/i8080A processor Identification Model name: i8080/i8080A.
Supplier: Intel. Component class: CPU.
Generation Generation: 8080. Compatibility Intel i8008 CPU with stack. MYcsvtu Notes
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Intel i8080/i8080A processor Architecture
8 bit data bus.
16 bit address bus. Separate address space for instructions and data (Harvard architecture). Physics Packaging: 40 pin CerDIP. Introduction date: April 1974.
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Intel i8085A/i8085AH processor Identification Model name: i8085A/i8085AH.
Supplier: Intel. Component class: CPU.
Generation Generation: 8080. Compatibility Intel i8080 CPU upward instruction compatible.
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Intel i8085A/i8085AH processor
Extra instructions: SIM (Set Interrupt Mask) RIM (Read Interrupt Mask) Extra interrupt lines, including NMI (Non-Maskable Interrupt).
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Intel i8085A/i8085AH processor Architecture
8 bit data bus.
16 bit address bus. Data and address bus are multiplexed. Separate address space for instructions and data .
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Intel i8085A/i8085AH processor Clock speed Physics
Clock speed
Model
Manufactu ring technolog y
3 MHz
Intel I8085a Intel iM8085A
NMOS NMOS
5 MHz
Intel i8085AH-2
HMOS
6 MHz
Intel i8085AH-1 Intel iM8085AH
HMOS HMOS
Number of transistors:
6200. Packaging: 40 pin CerDIP.
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Major designers
Intel Advanced Micro Devices (AMD) IBM Microelectronics AMCC Freescale Semiconductor ARM Holdings
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Major designers
MIPS Technologies Texas Instruments Semiconductors Renesas Technology VIA Technologies Western Design Center STMicroelectronics Sun Microsystems CPU Tech
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Microprocessor based system
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Microprocessor based system The typical processor system consists of:
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CPU (central processing unit) ALU (arithmetic-logic unit) Control Logic Registers, etc… Memory Input / Output interfaces
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Microprocessor based system Interconnections between these units:
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Address Bus Data Bus Control Bus
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Basic definitions Bus: A shared group of wires used for communicating signals among devices address bus: the device and the location within the device that is being accessed data bus: the data value being communicated control bus: describes the action on the address and data buses
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Basic definitions Memory: Where instructions (programs) and data are stored Organized in arrays of locations (addresses), each storing one byte (8 bits) in general A read operation to a particular location always returns the last value stored in that location
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Basic definitions
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Basic definitions Semiconductor Memories are classified according to
the type of data storage and the type of data access mechanism into the following two main groups:
Non-volatile Memory (NVM) also known as Read-Only
Memory (ROM) which retains information when the power supply voltage is off. With respect to the data storage mechanism NVM are divided into the following groups:
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Basic definitions Mask programmed ROM. The required contents of
the memory is programmed during fabrication.
Programmable ROM (PROM). The required contents
is written in a permanent way by burning out internal interconnections (fuses). It is a one-off procedure.
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Basic definitions Erasable PROM (EPROM). Data is stored as a charge
on an isolated gate capacitor (“floating gate”). Data is removed by exposing the PROM to the ultraviolet light. Electrically Erasable PROM (EEPROM) also known as Flash Memory. It is also based on the concept of the floating gate. The contents can be re-programmed by applying a suitable voltages to the EEPROM pins.
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Basic definitions Read/Write (R/W) memory, also known as Random
Access Memory (RAM). From the point of view of the data storage mechanism RAM are divided into two main groups:
Static RAM, where data is retained as long as there is
power supply on.
Dynamic RAM, where data is stored on capacitors and
requires a periodic refreshment.
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Basic definitions I/O devices: Enable system to interact with the world. Interface between the computer and other peripherals or human.
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Basic definitions Can be classified by: Type of data stream: Serial or parallel Type of interaction with the processor: Programmed I/O, Interrupt Driven, or DMA Type of connection to the processor: Memory-mapped I/O or I/O-mapped I/O
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Basic microprocessor architecture A microprocessor consists of:
ALU – performs arithmetic and logic calculation Registers – temporarily store data Control Unit – Synchronizes the operations of all
components
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8085 Microprocessor-Features The Intel 8085 microprocessor is an NMOS 8-bit device. Sixteen address bits provide access to 65,536 bytes of
8 bits each.
Eight bi-directional data lines provide access to a
system data bus.
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8085 Microprocessor-Features Control is provided by a variety of lines which support
memory and I/O interfacing, and a flexible interrupt system. The 8085 provides an upward mobility in design from the 8080 by supporting all of the 8080‟s instruction set and interrupt capabilities. It requires only a 5 volt supply. In addition, the 8085 is available in two clock speeds.
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8085 Microprocessor-Features The 8085 comes in two models, the 8085A and the
8085A-2. 8085A -clock frequency of 3 MHz (single phase square wave. ) 8085A-2 - clock frequency of 5 MHz. (single phase square wave. ) This single clock is generated within the 8085 itself, requiring only a crystal externally.
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8085 Microprocessor-Features The 8085 supports the interrupt structure of the 8080.
Includes the RST instruction and the eight vectors. Has additional four more interrupts(3 masked and use
vector areas between the existing ones of the 8080.)
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8085 Microprocessor-Features The 8085 has two pins dedicated to the generation or
reception of serial data. (allow the MP to send and receive serial bits with a large software program. Hence 8085 is useful as a complete control device for remote control applications.) The 8085 supports the entire 8080 instruction set. In addition, two new instructions are added- RIM and SIM.
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8085 Microprocessor-Features Unlike the 8080 , 8085 makes use of multiplexing of the
lower 8 bits of the address with the data bits on the same 8 pins. The 8085 has many new support devices to ease design work. These include the 8259 Programmable Interrupt controller, the 8202 Dynamic RAM controller, several new I/O devices with various amounts of RAM, ROM, parallel I/O and timer-counters. MYcsvtu Notes
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8085 Microprocessor Architecture Internal architecture description
Control Unit Generates signals within microprocessor to carry out
the instruction, which has been decoded.
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Internal architecture description Arithmetic Logic Unit The ALU performs the actual numerical and logic
operation such as „add‟, „subtract',' AND‟, „OR‟, etc. Uses data from memory and from Accumulator to perform arithmetic. Always stores result of operation in Accumulator
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Internal architecture description Registers The 8085/8080A-programming model includes six
registers, one accumulator, and one flag register. In addition, it has two 16-bit registers: the stack pointer and the program counter.
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Internal architecture description The 8085/8080A has six general-purpose registers to
store 8-bit data; these are identified as B,C,D,E,H, and L. They can be combined as register pairs - BC, DE, and HL - to perform some 16-bit operations. The programmer can use these registers to store or copy data into the registers by using data copy instructions.
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Internal architecture description Accumulator
The accumulator is an 8-bit register that is a part of
arithmetic/logic unit (ALU). This register is used to store 8-bit data and to perform arithmetic and logical operations. The result of an operation is stored in the accumulator. The accumulator is also identified as register A.
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Internal architecture description Flags The ALU includes five flip-flops, which are set or reset
after an operation according to data conditions of the result in the accumulator and other registers.
They are called Zero (Z), Carry (CY), Sign (S), Parity
(P), and Auxiliary Carry (AC) flags.
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Internal architecture description The most commonly used flags are Zero, Carry, and
Sign. The microprocessor uses these flags to test data conditions. For example, after an addition of two numbers, if the sum in the accumulator is larger than eight bits, called the Carry flag (CY) is set to one. When an arithmetic operation results in zero, the flipflop called the Zero (Z) flag is set to one.
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Internal architecture description The 8-bit register, called the flag register is adjacent to
the accumulator.
However, it is not used as a register; five bit positions
out of eight are used to store the outputs of the five flipflops.
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Internal architecture description The flags are stored in the 8-bit register so that the
programmer can examine these flags (data conditions) by accessing the register through an instruction
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Internal architecture description These flags have critical importance in the decision-
making process of the microprocessor.
The conditions (set or reset) of the flags are tested
through the software instructions.
For example, the instruction JC (Jump on Carry) is
implemented to change the sequence of a program when CY flag is set.
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Internal architecture description Program Counter (PC) This 16-bit register deals with sequencing the execution
of instructions. This register is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a16-bit register. The microprocessor uses this register to sequence the execution of the instructions.
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Internal architecture description Program Counter (PC) The function of the program counter is to point to the
memory address from which the next byte is to be fetched.
When a byte (machine code) is being fetched, the
program counter is incremented by one to point to the next memory location
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Internal architecture description Stack Pointer (SP) The stack pointer is also a 16-bit register used as a
memory pointer. It points to a memory location in R/W memory, called the stack. The beginning of the stack is defined by loading 16-bit address in the stack pointer.
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Internal architecture description Instruction register & Decoder
An Instruction Register and decoder system interpret
the programmer‟s instructions and implement them via nano code. Temporary store for the current instruction of a program. Latest instruction sent here from memory prior to execution. Decoder then takes instruction and „decodes‟ or interprets the instruction. Decoded instruction then passed to next stage. MYcsvtu Notes
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Programming model of 8085
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8085 System Bus A typical microprocessor communicates with memory
and other devices (input and output) using three busses:
Address Bus Data Bus and Control Bus.
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8085 System Bus Address Bus: One wire for each bit, therefore 16 bits = 16 wires. Address Bus consists of 16 wires, therefore 16 bits. Its "width" is 16 bits.
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8085 System Bus- Address Bus A 16 bit binary number allows 216 different numbers, or
32000 different numbers, ie 0000000000000000 up to 1111111111111111.
Because memory consists of boxes, each with a unique
address, the size of the address bus determines the size of memory, which can be used.
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8085 System Bus- Address Bus To communicate with memory the microprocessor
sends an address on the address bus, eg 0000000000000011 (3 in decimal), to the memory.
The memory the selects box number 3 for reading or
writing data.
Address bus is unidirectional, ie numbers only sent from
microprocessor to memory, not other way.
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8085 System Bus- Address Bus Question?: If you have a memory chip of size 256
kilobytes (256 x 1024 x 8 bits), how many wires does the address bus need, in order to be able to specify an address in this memory?
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8085 System Bus Data Bus: Data Bus: carries „data‟, in binary form, between
microprocessor and other external units, such as memory. Typical size is 8 or 16 bits.
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8085 System Bus -Data Bus The Data Bus typically consists of 8 wires. Therefore,
28 combinations of binary digits. Data bus used to transmit "data“ , ie information, results
of arithmetic, etc, between memory and the microprocessor.
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8085 System Bus -Data Bus Bus is bi-directional. Size of the data bus determines what arithmetic can be
done. If only 8 bits wide then largest number is 11111111 (255 in decimal). Therefore, larger number have to be broken down into chunks of 255. This slows microprocessor.
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8085 System Bus -Data Bus Data Bus also carries instructions from memory to the
microprocessor. Size of the bus therefore limits the number of possible
instructions to 256, each specified by a separate number.
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8085 System Bus Control Bus: Control Bus are various lines which have specific
functions for coordinating and controlling microprocessor operations.
Eg: Read/Not Write line, single binary digit.
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8085 System Bus Control whether memory is being „written to‟ (data
stored in memory) or „read from‟ (data taken out of memory) 1 = Read, 0 = Write.
May also include clock line (s) for timing/synchronizing,
„interrupts‟, „reset‟ etc.
Cannot function correctly without these vital control
signals.
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8085 System Bus- Control Bus The Control Bus carries control signals partly
unidirectional, partly bi-directional. Control signals are things like "read or write". This tells
memory that we are either reading from a location, specified on the address bus, or writing to a location specified.
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8085 System Bus- Control Bus In the microprocessor the three busses are external to
the chip (except for the internal data bus). In case of external busses, the chip connects to the busses via buffers, which are simply an electronic connection between external bus and the internal data bus.
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Example: Memory Read Operation
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Example: Instruction Fetch Operation
Instructions (program steps) are stored in memory.
To run a program, the individual instructions must be read from the memory in sequence, and executed.
Program counter puts the 16-bit memory address of the instruction on the address bus.
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Instruction Fetch Operation
Control unit sends the Memory Read Enable signal to access the memory.
The 8-bit instruction stored in memory is placed on the data bus and transferred to the instruction decoder.
Instruction is decoded and executed.
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Example: Instruction Fetch Operation
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Example: Instruction Fetch Operation
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De multiplexing Address & Data Lines From the above description, it becomes obvious that the AD7– AD0 lines are serving a dual purpose and that they need to be demultiplexed to get all the information. The high order bits of the address remain on the bus for three clock periods. However, the low order bits remain for only one clock period and they would be lost if they are not saved externally. Also, notice that the low order bits of the address disappear when they are needed most.
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De multiplexing Address & Data Lines To make sure we have the entire address for the full three clock cycles, we will use an external latch to save the value of AD7– AD0 when it is carrying the address bits. We use the ALE signal to enable this latch. Given that ALE operates as a pulse during T1, we will be able to latch the address. Then when ALE goes low, the address is saved and the AD7– AD0 lines can be used for their purpose as the bidirectional data lines.
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Demultiplexing Address & Data Lines
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Generating Control Signals The 8085 generates a single RD signal. However, the
signal needs to be used with both memory and I/O. So, it must be combined with the IO/M signal to generate different control signals for the memory and I/O. Keeping in mind the operation of the IO/M signal we can use the following circuitry to generate the right set of signals:
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Generating Control Signals
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8085 Functional Block Diagram
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8085 Pin description
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8085 Pin description Pin Description ADDRESS LINES A8 - A15: These tri state lines are outbound only. They provide the upper 8 bits of the 16-bit-wide address
which identifies one unique 8-bit byte within the MP‟s address space, or the 8-bit address of an I/O device. Sixteen address lines provide an address space of 65,536 locations.
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8085 Pin description ADDRESS-DATA LINES AD0 - AD7: These tri state lines may by either inbound or outbound. They provide a multiplexing between the lower 8 bits of
the 16-bit-wide address early in a machine cycle and 8 data bits later in the cycle.
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8085 Pin description ADDRESS-DATA LINES AD0 - AD7:
When containing addresses, these lines are outbound
only; when containing data, they may be either inbound or outbound, depending upon the nature of the machine cycle. They also will contain the 8 bits of an I/O device
address during an I/O operation.
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8085 Pin description ALE Address Latch Enable: It occurs during the first clock cycle of a machine state
and enables the address to get latched into the on chip latch of peripherals.
The falling edge of ALE is set to guarantee setup and
hold times for the address information.
ALE can also be used to strobe the status information.
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8085 Pin description ALE Address Latch Enable: ALE is never 3stated . This signal appears outbound early in a machine cycle
to advise the external circuitry that the AD0 - AD7 lines contain the lower 8 bits of a memory address.
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8085 Pin description ALE Address Latch Enable: It should be used to clock a catch-and-hold circuit such
as a 74LS245 or 74LS373, so that the full address will be available to the system for the rest of the machine cycle.
The falling edge of ALE is the point at which the signals
on the AD lines, as well as the S0, S1, and I-O/M lines will be stable and may be taken by the external circuitry.
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8085 Pin description STATUS LINES S0, S1, & I-O/M:
These three status lines serve to indicate the general
status of the processor with respect to what function the MP will perform during the machine cycle. The S0 and S1 lines are made available for circuits which need advanced warning of the ensuing operation, such as very slow RAM or other specialized devices.
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8085 Pin description STATUS LINES S0, S1, & I-O/M: The system may not normally need to monitor these
lines. The I-O/M line approximates in one line what the S0 and S1 lines do in two.
It indicates whether the operation will be directed
toward memory (line is low), or toward I/O (line is high).
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8085 Pin description Data Bus Status. Encoded status of the bus cycle:
S1
S0 Operation 0 0 HALT 0 1 WRITE 1 0 READ 1 1 FETCH S1 can be used as an advanced R/W status.
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8085 Pin description READ & WRITE (/RD & /WR): These lines indicate which direction the MP expects to
pass data between itself and the external data bus. These lines also serve to time the event, as well as identify its direction.
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8085 Pin description READ & WRITE (/RD & /WR): RD -READ; indicates the selected memory or 1/0
device is to be read and that the Data Bus is available for the data transfer.
WR-WRITE; indicates the data on the Data Bus is to be
written into the selected memory or I/O location. Data is set up at the trailing edge of WR. 3stated during Hold and Halt modes.
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8085 Pin description READY : If Ready is high during a read or write cycle, it indicates
that the memory or peripheral is ready to send or receive data. If Ready is low, the CPU will wait for Ready to go high before completing the read or write cycle.
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8085 Pin description This is an input line which may be used as a signal from
external RAM that a wait state is needed, since the RAM is not able to provide the data or accept it in the time allowed by the MP.
The negation of Ready, by being pulled low, will cause
the 8085 to enter wait states.
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8085 Pin description HOLD : These lines provide the 8085 with a DMA capability by
allowing another processor on the same system buses to request control of the buses. It indicates that another Master is requesting the use of the Address and Data Buses. The CPU, upon receiving the Hold request. will relinquish the use of buses as soon as the completion of the current machine cycle.
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8085 Pin description HOLD : Internal processing can continue. Upon receipt of HOLD, the „ 85 will tri state its address,
data, and certain control lines, then generate HLDA. This signals the other processor that it may proceed. The „85 will remain off the buses until HOLD is negated.
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8085 Pin description During this cycle a RESTART or CALL instruction can
be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by software. The processor can regain the buses only after the Hold is removed. When the Hold is acknowledged, the Address, Data, RD, WR, and IO/M lines are 3stated.
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8085 Pin description HLDA :
HOLD ACKNOWLEDGE- indicates that the CPU has
received the Hold request and that it will relinquish the buses in the next clock cycle. HLDA goes low after the Hold request is removed. The CPU takes the buses one half clock cycle after HLDA goes low.
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8085 Pin description INTR : INTERRUPT REQUEST: This line provides a vectored interrupt capability to the
8085.
Upon receipt of INTR, the „85 will complete the
instruction in process, then generate INTA as it enters the next machine cycle.
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8085 Pin description INTR :
The interrupting device will jam a Restart (RST)
instruction onto the data bus, which the „85 uses to locate an interrupt vector in low RAM. is used as a general purpose interrupt. It is sampled only during the next to the last clock cycle
of the instruction.
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8085 Pin description INTR :
If it is active, the Program Counter (PC) will be inhibited
from incrementing and an INTA will be issued. It is disabled by Reset and immediately after an
interrupt is accepted.
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8085 Pin description INTA :
INTERRUPT ACKNOWLEDGE- is used instead of (and
has the same timing as) RD during the Instruction cycle after an INTR is accepted. It can be used to activate the 8259 Interrupt chip or
some other interrupt port.
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8085 Pin description RST 5.5, 6.5, 7.5: These three lines are additional interrupt lines which
generate an automatic Restart, without jamming, to vectors in low RAM which are between those used by the normal INTR instruction.
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8085 Pin description RST 5.5, 6.5, 7.5:
The 5.5 line, for example, will cause an automatic
restart to a 4-byte vector located between 5 and 6 of the normal vectors used by INTR. These lines have priority over the INTR line, and each
other.
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8085 Pin description RST 5.5, 6.5, 7.5: They also have certain electrical characteristics for
assertion, and may be masked off or on by software.
These three inputs have the same timing as
INTR except they cause an internal RESTART to be automatically inserted.
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8085 Pin description RST 7.5 - Highest Priority RST 6.5 RST 5.5 - Lowest Priority The priority of these interrupts is ordered as shown
above.
These interrupts have a higher priority than the INTR
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8085 Pin description TRAP: This is an un maskable interrupt with a fixed vector in
low RAM. Trap interrupt is a non maskable restart interrupt. It is recognized at the same time as INTR. It is unaffected by any mask or Interrupt Enable. It has the highest priority of any interrupt MYcsvtu Notes
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8085 Pin description RESET IN :
These lines provide for both MP and system reset. The reset circuitry in the 8224, used with the 8080, has
been brought inside the MP. The RESET IN line is generated asynchronously by some sort of external circuit, such as an RC network or Reset switch.
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8085 Pin description RESET IN :
Upon receipt of this signal, the „85 will internally
synchronize the Reset with the clock of the processor, then generate RESET OUT for other devices in the system. Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip flops.
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8085 Pin description RESET IN :
None of the other flags or registers (except the
instruction register) are affected. The CPU is held in the reset condition as long as Reset
is applied.
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8085 Pin description RESET OUT: Indicates CPU is being reset. Can be used as a system RESET. The signal is synchronized to the processor clock.
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8085 Pin description X1, X2 :
Crystal or R/C network connections to set the internal
clock generator. The input frequency is divided by 2 to give the internal operating frequency. These two pins provide connection for an external frequency determining circuit to feed the 8085‟s clock.
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8085 Pin description X1, X2 :
This is normally a crystal, although other resonant
circuits may be used. X1 alone may be used as a single input from an external oscillator. The internal oscillator of the „85 will divide the frequency
by two for the system clock.
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8085 Pin description CLK :
Clock Output for use as a system clock when a crystal
or R/ C network is used as an input to the CPU. The period of CLK is twice the X1, X2 input period. This line provides a system clock signal to external circuits which need to be in synchronization with the MP.
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8085 Pin description IO/M : IO/M indicates whether the Read/Write is to memory or
l/O. Tri stated during Hold and Halt modes
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8085 Pin description SID: Serial input data line . The data on this line is loaded into accumulator bit 7
whenever a RIM instruction is executed.
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8085 Pin description SOD :
Serial output data line. The output SOD is set or reset as specified by the SIM
instruction.
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8085 Pin description SID and SOD: These two lines provide for a single serial input or
output line to/from the 8085.
These lines are brought into the device as D7, and may
be tested or set by the Read Interrupt Mask (RIM) or Set Interrupt Mask (SIM) instructions.
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8085 Pin description SID and SOD:
These two instructions also have control over the mask
which controls the RST 5.5, 6.5, and 7.5, and TRAP, interrupts. The SID and SOD lines are simple single bit I/O lines; any timing required to provide external communication via them must be provided by the software.
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8085 Pin description Vcc:
+5 volt supply. Vss:
Ground Reference.
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8085 Functional Description The 8085A is a complete 8 bit parallel central
processor.
It requires a single +5 volt supply. Its basic clock speed is 3 MHz thus improving on the
present 8080's performance with higher system speed.
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8085 Functional Description Also it is designed to fit into a minimum system of three
IC's: The CPU, a RAM/ IO, and a ROM or PROM/IO chip
The 8085A uses a multiplexed Data Bus. The address is split between the higher 8bit Address
Bus and the lower 8bit Address/Data Bus.
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8085 Functional Description During the first cycle the address is sent out. The lower 8bits are latched into the peripherals by the
Address Latch Enable (ALE).
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8085 Functional Description During the rest of the machine cycle the Data Bus is
used for memory or I/O data.
The 8085A provides RD, WR, and IO/Memory signals
for bus control.
An Interrupt Acknowledge signal (INTA) is also
provided. Hold, Ready, and all Interrupts are synchronized.
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8085 Functional Description The 8085A also provides serial input data (SID) and
serial output data (SOD) lines for simple serial interface. In addition to these features, the 8085A has three
maskable, restart interrupts and one non-maskable trap interrupt. The 8085A provides RD, WR and IO/M signals for Bus control.
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8085 Functional Description Status Information: Status information is directly available from the 8085A. ALE serves as a status strobe. The status is partially encoded, and provides the user
with advanced timing of the type of bus transfer being done.
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8085 Functional Description Status Information
IO/M cycle status signal is provided directly also. Decoded So, S1 Carries the following status
information: HALT, WRITE, READ, FETCH
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8085 Functional Description Status Information
S1 can be interpreted as R/W in all bus transfers. In the
8085A the 8 LSB of address are multiplexed with the data instead of status. The ALE line is used as a strobe to enter the lower half of the address into the memory or peripheral address latch. This also frees extra pins for expanded interrupt capability. MYcsvtu Notes
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8085 Functional Description Interrupt and Serial l/O
The 8085A has5 interrupt inputs: INTR, RST5.5,
RST6.5, RST 7.5, and TRAP. INTR is identical in function to the 8080 INT. Each of the three RESTART inputs, 5.5, 6.5,7.5 has a programmable mask. TRAP is also a RESTART interrupt except it is non maskable.
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8085 Functional Description Interrupt and Serial l/O The three RESTART interrupts cause the internal
execution of RST (saving the program counter in the stack and branching to the RESTART address) if the interrupts are enabled and if the interrupt mask is not set.
The non-maskable TRAP causes the internal execution
of a RST independent of the state of the interrupt enable or masks.
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8085 Functional Description The interrupts are arranged in a fixed priority that
determines which interrupt is to be recognized if more than one is pending as follows:
TRAP highest priority, RST 7.5,RST 6.5, RST 5.5, INTR
lowest priority.
This priority scheme does not take into account the
priority of a routine that was started by a higher priority interrupt.
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8085 Functional Description RST 5.5 can interrupt a RST 7.5 routine if the interrupts
were re-enabled before the end of the RST 7.5 routine.
TRAP: The TRAP interrupt is useful for catastrophic errors
such as power failure or bus error. The TRAP input is recognized just as any other interrupt but has the highest priority. It is not affected by any flag or mask. The TRAP input is both edge and level sensitive. MYcsvtu Notes
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8085 Timings Instruction Cycle – The time required by the 8085 to fetch and execute one
machine language instruction is defined as an Instruction Cycle.
As in the 8080, the instructions may be of different
complexities, with the result that the more complicated instructions take longer to execute.
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8085 Timings Instruction Cycle –
The 8085‟s method of instruction execution inside the
MP is more organized, however, and so the time required to execute any instruction is more predictable and more regular.
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8085 Timings Machine Cycle –
Each instruction is divided into one to five Machine
Cycles. Each machine cycle is essentially the result of the need, by the instruction being executed, to access the RAM. The shortest instruction would require just one machine cycle, in which the instruction itself is obtained from RAM.
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8085 Timings The longest, of five machine cycles, would consist of
five RAM accesses, the first to obtain the instruction byte itself, and the remaining four to be divided into fetching and saving other bytes.
For example, cycles numbers 2 & 3 may be needed to
fetch two more bytes of an address, while numbers 4 & 5 may be needed to save a 2-byte address somewhere else in RAM.
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8085 Timings The type of machine cycle being executed is specified
by the status lines I-O/M, S0, and S1, and the control lines /RD, /WR, and /INTA.
These six lines can define seven different machine
cycle types as follows.
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Types of machine cycle OPCODE FETCH: This is the first machine cycle of any instruction. It is defined with S0 and S1 asserted high, and I-O/M
and /RD low. It is a read cycle from RAM to obtain an instruction byte.
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Types of machine cycle MEMORY READ:
This is a normal read cycle of any byte except the OP
code. It is defined with S0 and S1 set to 0, 1 respectively, and I-O/M and /RD low. It is a read cycle from RAM to obtain a data or address byte.
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Types of machine cycle MEMORY WRITE: This is a normal write cycle to memory. It is defined with S0 and S1 set to 1, 0 respectively, and
I-O/M and /WR low. It is a write cycle to RAM to store one byte in the specified address
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Types of machine cycle I/O READ:
This is a normal read cycle from an I/O device. It is defined with S0 and S1 set to 0, 1 respectively, and
with I-O/M high and /RD low. It is a read cycle which will bring one byte into the MP from the input device specified.
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Types of machine cycle I/O WRITE: This is a normal write cycle to an I/O device. It is defined with S0 and S1 set to 1, 0 respectively, and
with I-O/M high and /WR low. It is a write cycle which will send one byte outbound from the MP to the specified output device.
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Types of machine cycle INTERRUPT ACKNOWLEDGE:
This is a response to an interrupt request applied to the
MP via the INTR line. It is defined with S0 and S1 set to 1, 1 respectively, IO/M set high, and both /RD and /WR also high.
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Types of machine cycle The Interrupt Acknowledge pin is also held to a low
asserted level. It is neither a read nor write cycle, although the interrupting device will jam an interrupt vector onto the D0-D7 lines on the next machine cycle.
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Types of machine cycle BUS IDLE:
This is an idle cycle in which no specific bus activity is
defined. It occurs under three differently defined conditions:
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8085 Timings-Special instructions Double Add Instruction (DAD):
This instruction requires enough execution time to merit
its own Idle cycle. It is defined with S0 and S1 set to 0, 1 respectively, IO/M set low, and neither /RD nor /WR asserted (both high). Since neither a read nor a write are specified, no bus action takes place.
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8085 Timings-Special instructions Acknowledge of Restart or Trap:
This idle cycle allows time for the „85 to cope with a
RST or Trap interrupt request. All bits are held high.
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8085 Timings-Special instructions Halt: This idle cycle indicates that the MP has executed a
Halt instruction. The I-O/M, /RD, and /WR lines are all tri stated, which would allow them to be controlled by other devices. INTA is held inactive, but not tri stated. The Hold line is really the proper one to use for DMA or multiple processors.
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8085 Timings-T-states T-states Each of the machine cycles defined above, during
which an access of a RAM address or an I/O device is made (except the idle cycles), is further divided into Tstates. Each T-state, for an „85 with a 3 MHz clock, will be about 333 nanoseconds in length. The first machine cycle, during which the OP code is being fetched, will be either 4 or 6 T-states in length.
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8085 Timings-T-states T-states-
Whether 4 or 6 T-states are used depends upon
whether the instruction needs further information from RAM, or whether it can be executed to completion straight away . If multiple accesses are needed, the cycle will be 4 states long; if the execution can run to completion, 6 states are required.
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8085 Timings-T-states The actions of the major signals of the „85 during each
of the 10 possible types of T-states. It may be summarized as follows:
T1 STATE: This state is the first of any machine cycle. S0-S1 lines, I-O/M, A8-A15, and AD0-AD7 contains
whatever would be appropriate for the type of instruction being executed.
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8085 Timings-T-states T1 STATE: The S0-S1 and I-O/M lines will define, at this early point
in the machine cycle, whether the MP is attempting to address a RAM location or an I/O device.
The address lines will identify the location or I/O device
to be dealt with.
.
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8085 Timings-T-states T1 STATE: The Address Latch Enable (ALE) line will allow some
sort of external circuitry to catch and hold the contents of the AD0-AD7 lines to be used as the low byte of the address.
The /RD, /WR, and /INTA lines are all negated at this
time.
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8085 Timings-T-states T1 STATE: Since the AD0-AD7 lines are being used to present an
address byte, it would be inappropriate to move data on the data bus; besides, it‟s too early to do so. It‟s also too early for /INTA. ALE, however, is asserted, since this is the time that the AD0-AD7 contents will contain the lower address byte, which must be caught and held outside the „85 for use by the following Tstates.
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8085 Timings-T-states T2 STATE: All lines except ALE (which will be inactive for the rest
of the machine cycle) will assume the proper level for the type of instruction in progress. The address lines retain the bit pattern selecting one byte from RAM or an I/O device; The AD0-AD7 lines will now prepare to either accept or present a data byte (they are in a state of transition during T2).
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8085 Timings-T-states T2 STATE:
I-O/M and the S0, S1 lines are still displaying the
original settings of T1. Either /RD or /WR will assert during T2, to indicate the nature of the data transaction. INTA will assert at T2 if an interrupt cycle has started.
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8085 Timings-T-states WAIT STATE: If the Ready line was negated during T2, a Tw is
inserted to allow the external circuitry more time to prepare for data transmission. A specific point in T2 is defined, after which a late negation of Ready will not cause the Tw to be inserted. This corresponds to the same actions in the 8080 device. All signals set up during T2 will remain constant during Tw.
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8085 Timings-T-states T3 STATE:
All lines set up during T2 will remain the same in T3,
except the AD0-AD7 lines, which will be conducting data either into or out of the 8085. At the end of T3, the /RD or /WR line will negate to indicate the end of the active function. This will cause the data byte standing on AD0-AD7 to disappear
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8085 Timings-T-states T4 - T6 STATES: These states are required for time to permit the 8085 to
continue processing internally.
No bus actions are required. The S0 & S1 lines are both asserted, while I-O/M is
negated, which specifies that the „85 is involved in an Opcode fetch.
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8085 Timings-T-states T4 - T6 STATES:
Since T4 through T6 will exist only on the first machine
cycle of an instruction, this corresponds correctly with the Machine Cycle chart. The AD0-AD7 lines are tri stated; the A8-A15 retain their original setting; the /RD, /WR, and INTA lines are all negated.
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8085 Timings-Special conditions Special conditions: In addition to the T-states described above, there are
also various conditions during states involved in Resets, Halts, and Holds.
It must be kept in mind that during any of these, the MP
clocks are still running, and the „85 is alive inside; it has simply shut itself off the buses to allow external events to occur.
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8085 Timings-Special conditions Special conditions:
These states tri state the address, AD, I-O/M, /RD, and
/WR lines to allow external devices to control them. The other lines are held at inactive levels except the S0 & S1 lines, which do indicate what type of machine cycle the system is in, i.e., whether it is a Reset, Hold, or Halt
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8085 Timings-Special conditions HOLD AND HALT STATES :
The 8085 has provisions for the execution of a Halt
instruction, which causes the system to go into T-halt states. During this time, the „85 is simply waiting for something to occur. There are three ways out of a Halt: A Reset, a Hold Request, and an enabled interrupt.
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8085 Timings-Special conditions HOLD AND HALT STATES :
If a Hold Request occurs during a Halt, the „85 will
honor it by going into T-hold cycles as long as the Hold line remains asserted. It will return to the halt condition when Hold negates. If an interrupt occurs during a halt, the MP will go into an interrupt cycle if the interrupt was enabled.
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8085 Timings-Special conditions HOLD AND HALT STATES :
It will be ignored if it was not enabled. An enabled interrupt during a hold state will have to wait
until the hold clears before being given control of the system.
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8085 Timings- Example The instruction code 0100 1111 (4FH – MOV C, A) is
stored in memory location 2005H. Illustrate the steps and the timing of data flow when it is being fetched
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Example Mp Communication
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Timing Diagram
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Some Terminologies: After observing timing diagram we can say,
4FH is a one – byte instruction One external operation – fetching 4F from 2005H Entire operation needs 4 clock periods
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UNIT- II INSTRUCTION SET & PROGRAMMING WITH 8085
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Instruction An instruction is a binary pattern designed inside a
microprocessor to perform a specific function.
The entire group of instructions, called the instruction
set, determines what functions the microprocessor can perform.
The 8085‟s instructions are made up of bytes.
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Instruction In microprocessor parlance, a byte is described as 8
contiguous binary bits treated as a unit.
The least significant bit is on the right, and is labeled Bit
0.
The most significant bit is on the left, and is Bit 7. Thus,
the machine coding is "origin zero", unless noted otherwise.
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Instruction Note also that there is no parity bit, or provision for it, as
would be found in larger systems. The 8085‟s instructions are either one, two, or three bytes long. In all cases, the first byte contains the essential information, such as the OP code. The second and third bytes, if included, provide operand information that won‟t fit in the first byte.
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Instruction Set Classification These instructions can be classified into the following
five functional categories:
data transfer (copy) operations arithmetic operations, logical operations, branching operations, and machine-control operations.
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Data Transfer (Copy) Operations Data Transfer (Copy) Operations This group of instructions copy data from a location
called a source to another location called a destination, without modifying the contents of the source. In technical manuals, the term data transfer is used for this copying function. The various types of data transfer (copy) are listed below together with examples of each type:
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Data Transfer (Copy) Operations Copy from source to destination
MOV Rd, Rs This instruction copies the contents of the source M, Rs
register into the destination register; the contents of Rd, M the source register are not altered. If one of the operands is a memory location, its location is specified by the contents of the HL registers. Example: MOV B, C or MOV B, M
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Data Transfer (Copy) Operations Move immediate 8-bit
MVI Rd, data The 8-bit data is stored in the destination register or M,
data memory. If the operand is a memory location, its location is specified by the contents of the HL registers. Example: MVI B, 57H or MVI M, 57H
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Data Transfer (Copy) Operations Load accumulator
LDA 16-bit address The contents of a memory location, specified by a16-bit
address in the operand, are copied to the accumulator. The contents of the source are not altered. Example: LDA 2034H
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Data Transfer (Copy) Operations Load accumulator indirect
LDAX B/D Reg. pair The contents of the designated register pair point to a
memory location. This instruction copies the contents of that memory location into the accumulator. The contents of either the register pair or the memory location are not altered. Example: LDAX B
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Data Transfer (Copy) Operations Load register pair immediate
LXI Reg. pair, 16-bit data The instruction loads 16-bit data in the register pair
designated in the operand. Example: LXI H, 2034H or LXI H, XYZ
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Data Transfer (Copy) Operations Load H and L registers direct
LHLD 16-bit address The instruction copies the contents of the memory
location pointed out by the 16-bit address into register L and copies the contents of the next memory location into register H. The contents of source memory locations are not altered. Example: LHLD 2040H MYcsvtu Notes
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Data Transfer (Copy) Operations Store accumulator direct STA 16-bit address The contents of the accumulator are copied into the
memory location specified by the operand. This is a 3-byte instruction, the second byte specifies the low-order address and the third byte specifies the high-order address. Example: STA 4350H
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Data Transfer (Copy) Operations Store accumulator indirect
STAX Reg. pair The contents of the accumulator are copied into the
memory location specified by the contents of the operand (register pair). The contents of the accumulator are not altered. Example: STAX B
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Data Transfer (Copy) Operations Store H and L registers direct SHLD 16-bit address The contents of register L are stored into the
memory location specified by the 16-bit address in the operand and the contents of H register are stored into the next memory location by incrementing the operand. This is a 3-byte instruction, the second byte specifies the low-order address and the third byte specifies the high-order address. Example: SHLD 2470H MYcsvtu Notes
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Data Transfer (Copy) Operations Exchange H and L with D and E
XCHG none The contents of register H are exchanged with the
contents of register D, and the contents of register L are exchanged with the contents of register E. Example: XCHG
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Data Transfer (Copy) Operations Copy H and L registers to the stack pointer
SPHL none The instruction loads the contents of the H and L
registers into the stack pointer register, the contents of the H register provide the high-order address and the contents of the L register provide the low-order address. The contents of the H and L registers are not altered. Example: SPHL
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Data Transfer (Copy) Operations Exchange H and L with top of stack
XTHL none The contents of the L register are exchanged with the
stack location pointed out by the contents of the stack pointer register. The contents of the H register are exchanged with the next stack location (SP+1); however, the contents of the stack pointer register are not altered. Example: XTHL MYcsvtu Notes
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Data Transfer (Copy) Operations Output data from accumulator to a port with 8-bit
address OUT 8-bit port address The contents of the accumulator are copied into the I/O port specified by the operand. Example: OUT F8H
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Data Transfer (Copy) Operations Input data to accumulator from a port with 8-bit
address IN 8-bit port address The contents of the input port designated in the operand are read and loaded into the accumulator. Example: IN 8CH
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Arithmetic instructions Add register or memory to accumulator ADD R – The contents of the operand (register or memory) are M
added to the contents of the accumulator and the result is stored in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers. All flags are modified to reflect the result of the addition. Example: ADD B or ADD M MYcsvtu Notes
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Arithmetic instructions Add register to accumulator with carry ADC R The contents of the operand (register or memory) and
M the Carry flag are added to the contents of the accumulator and the result is stored in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers. All flags are modified to reflect the result of the addition. Example: ADC B or ADC M MYcsvtu Notes
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Arithmetic instructions Add immediate to accumulator
ADI 8-bit data The 8-bit data (operand) is added to the contents of the
accumulator and the result is stored in the accumulator. All flags are modified to reflect the result of the addition. Example: ADI 45H
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Arithmetic instructions Add immediate to accumulator with carry
ACI 8-bit data The 8-bit data (operand) and the Carry flag are added
to the contents of the accumulator and the result is stored in the accumulator. All flags are modified to reflect the result of the addition. Example: ACI 45H
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Arithmetic instructions Add register pair to H and L registers
DAD Reg. pair The 16-bit contents of the specified register pair are
added to the contents of the HL register and the sum is stored in the HL register. The contents of the source register pair are not altered. If the result is larger than 16 bits, the CY flag is set. No other flags are affected. Example: DAD H MYcsvtu Notes
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Arithmetic instructions Subtract register or memory from accumulator
SUB R The contents of the operand (register or memory ) are
M subtracted from the contents of the accumulator, and the result is stored in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers. All flags are modified to reflect the result of the subtraction. Example: SUB B or SUB M MYcsvtu Notes
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Arithmetic instructions Subtract source and borrow from accumulator
SBB R The contents of the operand (register or memory ) and
M the Borrow flag are subtracted from the contents of the accumulator and the result is placed in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers. All flags are modified to reflect the result of the subtraction. Example: SBB B or SBB M MYcsvtu Notes
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Arithmetic instructions Subtract immediate from accumulator
SUI 8-bit data The 8-bit data (operand) is subtracted from the contents
of the accumulator and the result is stored in the accumulator. All flags are modified to reflect the result of the subtraction. Example: SUI 45H
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Arithmetic instructions Subtract immediate from accumulator with borrow
SBI 8-bit data The 8-bit data (operand) and the Borrow flag are
subtracted from the contents of the accumulator and the result is stored in the accumulator. All flags are modified to reflect the result of the subtraction. Example: SBI 45H
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Arithmetic instructions Increment register or memory by 1
INR R The contents of the designated register or
memory) are M incremented by 1 and the result is stored in the same place. If the operand is a memory location, its location is specified by the contents of the HL registers. Example: INR B or INR M
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Arithmetic instructions Increment register pair by 1
INX R The contents of the designated register pair are
incremented by 1 and the result is stored in the same place. Example: INX H
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Arithmetic instructions Decrement register or memory by 1
DCR R The contents of the designated register or memory are
M decremented by 1 and the result is stored in the same place. If the operand is a memory location, its location is specified by the contents of the HL registers. Example: DCR B or DCR M
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Arithmetic instructions Decrement register pair by 1 DCX R The contents of the designated register pair are
decremented by 1 and the result is stored in the same place. Example: DCX H
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Arithmetic instructions Decimal adjust accumulator DAA none The contents of the accumulator are
changed from a binary value to two 4-bit binary coded decimal (BCD) digits. This is the only instruction that uses the auxiliary flag to perform the binary to BCD conversion, and the conversion procedure is described below. S, Z, AC, P, CY flags are altered to reflect the results of the operation.
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Arithmetic instructions Decimal adjust accumulator If the value of the low-order 4-bits in the accumulator is
greater than 9 or if AC flag is set, the instruction adds 6 to the low-order four bits. If the value of the high-order 4-bits in the accumulator is greater than 9 or if the Carry flag is set, the instruction adds 6 to the high-order four bits. Example: DAA
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Branching operations Jump unconditionally
JMP 16-bit address The program sequence is
transferred to the memory location specified by the 16bit address given in the operand. Example: JMP 2034H or JMP XYZ
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Branching operations Jump conditionally
Operand: 16-bit address The program sequence is transferred to the memory
location specified by the 16-bit address given in the operand based on the specified flag of the PSW as described below. Example: JZ 2034H or JZ XYZ
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Branching operations JC Jump on Carry CY = 1
JNC Jump on no Carry CY = 0 JP Jump on positive S = 0 JM Jump on minus S = 1 JZ Jump on zero Z = 1 JNZ Jump on no zero Z = 0 JPE Jump on parity even P = 1 JPO Jump on parity odd P = 0 MYcsvtu Notes
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Subroutine Unconditional subroutine call CALL 16-bit address The program sequence is transferred to the memory
location specified by the 16-bit address given in the operand. Before the transfer, the address of the next instruction after CALL (the contents of the program counter) is pushed onto the stack. Example: CALL 2034H or CALL XYZ MYcsvtu Notes
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Subroutine Call conditionally Operand: 16-bit address The program sequence is transferred to the memory
location specified by the 16-bit address given in the operand based on the specified flag of the PSW as described below. Before the transfer, the address of the next instruction after the call (the contents of the program counter) is pushed onto the stack. Example: CZ 2034H or CZ XYZ MYcsvtu Notes
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Subroutine CC Call on Carry CY = 1 CNC Call on no Carry CY = 0 CP Call on positive S = 0 CM Call on minus S = 1 CZ Call on zero Z = 1 CNZ Call on no zero Z = 0 CPE Call on parity even P = 1 CPO Call on parity odd P = 0 MYcsvtu Notes
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Subroutine Return from subroutine unconditionally RET none The program sequence is transferred from the
subroutine to the calling program. The two bytes from the top of the stack are copied into the program counter, and program execution begins at the new address. Example: RET MYcsvtu Notes
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Subroutine Return from subroutine conditionally
Operand: none The program sequence is transferred from the
subroutine to the calling program based on the specified flag of the PSW as described below. The two bytes from the top of the stack are copied into the program counter, and program execution begins at the new address. Example: RZ MYcsvtu Notes
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Subroutine RC Return on Carry CY = 1
RNC Return on no Carry CY = 0 RP Return on positive S = 0 RM Return on minus S = 1 RZ Return on zero Z = 1 RNZ Return on no zero Z = 0 RPE Return on parity even P = 1 RPO Return on parity odd P = 0 MYcsvtu Notes
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Other instructions Load program counter with HL contents
PCHL none The contents of registers H and L are copied into the
program counter. The contents of H are placed as the high-order byte and the contents of L as the low-order byte. Example: PCHL
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Other instructions Restart RST 0-7 The RST instruction is equivalent to a 1-byte
call instruction to one of eight memory locations depending upon the number. The instructions are generally used in conjunction with interrupts and inserted using external hardware. However these can be used as software instructions in a program to transfer program execution to one of the eight locations. The addresses are: MYcsvtu Notes
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Restart
Instruction Restart Address RST 0 0000H RST 1 0008H RST 2 0010H RST 3 0018H RST 4 0020H RST 5 0028H RST 6 0030H RST 7 0038H
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Restart The 8085 has four additional interrupts and these
interrupts generate RST instructions internally and thus do not require any external hardware. These instructions and their Restart addresses are: Interrupt Restart Address TRAP 0024H RST 5.5 002CH RST 6.5 0034H RST 7.5 003CH MYcsvtu Notes
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Logical instructions Compare register or memory with accumulator CMP R The contents of the operand (register or memory) are M compared with the contents of the accumulator. Both contents are preserved .
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Logical instructions The result of the comparison is shown by setting the
flags of the PSW as follows: if (A) < (reg/mem): carry flag is set if (A) = (reg/mem): zero flag is set if (A) > (reg/mem): carry and zero flags are reset Example: CMP B or CMP M
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Logical instructions Compare immediate with accumulator CPI 8-bit data The second byte (8-bit data) is compared with the
contents of the accumulator. The values being compared remain unchanged.
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Logical instructions The result of the comparison is shown by setting the
flags of the PSW as follows: if (A) < data: carry flag is set if (A) = data: zero flag is set if (A) > data: carry and zero flags are reset Example: CPI 89H
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Logical instructions Logical AND register or memory with accumulator ANA R The contents of the accumulator are logically ANDed
with M the contents of the operand (register or memory), and the result is placed in the accumulator. If the operand is a memory location, its address is specified by the contents of HL registers. S, Z, P are modified to reflect the result of the operation. CY is reset.AC is set. Example: ANA B or ANA M MYcsvtu Notes
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Logical instructions Logical AND immediate with accumulator
ANI 8-bit data The contents of the accumulator are logically ANDed
with the 8-bit data (operand) and the result is placed in the accumulator. S, Z, P are modified to reflect the result of the operation. CY is reset. AC is set. Example: ANI 86H MYcsvtu Notes
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Logical instructions Exclusive OR register or memory with accumulator XRA R The contents of the accumulator are Exclusive ORed
with M the contents of the operand (register or memory), and the result is placed in the accumulator. If the operand is a memory location, its address is specified by the contents of HL registers. S, Z, P are modified to reflect the result of the operation. CY and AC are reset. Example: XRA B or XRA M MYcsvtu Notes
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Logical instructions Exclusive OR immediate with accumulator XRI 8-bit data The contents of the accumulator are Exclusive ORed
with the 8-bit data (operand) and the result is placed in the accumulator. S, Z, P are modified to reflect the result of the operation. CY and AC are reset. Example: XRI 86H
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Logical instructions Logical OR register or memory with accumulator ORA R The contents of the accumulator are logically ORed with
M the contents of the operand (register or memory), and the result is placed in the accumulator. If the operand is a memory location, its address is specified by the contents of HL registers. S, Z, P are modified to reflect the result of the operation. CY and AC are reset. Example: ORA B or ORA M MYcsvtu Notes
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Logical instructions Logical OR immediate with accumulator ORI 8-bit data The contents of the accumulator are logically ORed with
the 8-bit data (operand) and the result is placed in the accumulator. S, Z, P are modified to reflect the result of the operation. CY and AC are reset. Example: ORI 86H
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Logical instructions Rotate accumulator left RLC none Each binary bit of the accumulator is rotated left by one
position. Bit D7 is placed in the position of D0 as well as in the Carry flag. CY is modified according to bit D7. S, Z, P,AC are not affected. Example: RLC
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Logical instructions Rotate accumulator right
RRC none Each binary bit of the accumulator is rotated right by
one position. Bit D0 is placed in the position of D7 as well as in the Carry flag. CY is modified according to bit D0. S, Z, P,AC are not affected. Example: RRC MYcsvtu Notes
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Logical instructions Rotate accumulator left through carry
RAL none Each binary bit of the accumulator is rotated left by one
position through the Carry flag. Bit D7 is placed in the Carry flag, and the Carry flag is placed in the least significant position D0. CY is modified according to bit D7. S, Z, P, AC are not affected. Example: RAL MYcsvtu Notes
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Logical instructions Rotate accumulator right through carry
RAR none Each binary bit of the accumulator is rotated right by
one position through the Carry flag. Bit D0 is placed in the Carry flag, and the Carry flag is placed in the most significant position D7. CY is modified according to bit D0. S, Z, P, AC are not affected. Example: RAR MYcsvtu Notes
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Logical instructions
Complement accumulator CMA none The contents of the accumulator are complemented. No flags are affected. Example: CMA
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Logical instructions Complement carry
CMC none The Carry flag is complemented. No other flags are affected. Example: CMC
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Logical instructions Set Carry
STC none The Carry flag is set to 1. No other flags are
affected. Example: STC
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Machine control instructions
No operation NOP none No operation is performed. The instruction is fetched and decoded. However no operation is executed. Example: NOP
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Machine control instructions Halt and enter wait state
HLT none The CPU finishes executing the current instruction and
halts any further execution. An interrupt or reset is necessary to exit from the halt state. Example: HLT
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Machine control instructions Disable interrupts
DI none The interrupt enable flip-flop is reset and all the
interrupts except the TRAP are disabled. No flags are affected. Example: DI
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Machine control instructions Enable interrupts
EI none The interrupt enable flip-flop is set and all interrupts are
enabled. No flags are affected. After a system reset or the acknowledgement of an interrupt, the interrupt enable flip flop is reset, thus disabling the interrupts. This instruction is necessary to enable the interrupts (except TRAP). Example: EI MYcsvtu Notes
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Machine control instructions Read interrupt mask
RIM none This is a multipurpose instruction used to read the
status of interrupts 7.5, 6.5, 5.5 and read serial data input bit. The instruction loads eight bits in the accumulator with the following interpretations. Example: RIM
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Machine control instructions Set interrupt mask
SIM none This is a multipurpose instruction and used to
implement the 8085 interrupts 7.5, 6.5, 5.5, and serial data output. The instruction interprets the accumulator contents as follows. Example: SIM
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Stack The Stack Pointer The stack on an 8080/8085 can be located anywhere in
RAM memory, pointed to by the stack pointer SP.
Every time something is pushed on to the stack, the SP
pointer is decremented, so the stack is growing down in memory.
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Stack Stack operations are always performed with registers
pairs. A register pair is referenced by the name of the MSB register: B, D or H. The only exception is PSW, which in fact is the LSB register of the AF pair
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Stack A push on the stack, whether it comes from the PUSH
instruction, a subroutine call, or interrupt has the following sequence:
Decrement SP by 1 Save most significant byte of register pair Decrement SP by 1 Save least significant byte of register pair Naturally a pop from the stack has just the opposite effect:
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Stack Load least significant byte of register pair
Increment SP by 1 Load most significant byte of register pair Increment SP by 1
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Stack Push register pair onto stack PUSH Reg. pair The contents of the register pair designated in the
operand are copied onto the stack in the following sequence. The stack pointer register is decremented and the contents of the high order register (B, D, H, A) are copied into that location. The stack pointer register is decremented again and the contents of the low-order register (C, E, L, flags) are copied to that location. Example: PUSH B or PUSH A MYcsvtu Notes
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Stack Pop off stack to register pair POP Reg. pair The contents of the memory location pointed out by the
stack pointer register are copied to the low-order register (C, E, L, status flags) of the operand. The stack pointer is incremented by 1 and the contents of that memory location are copied to the high-order register (B, D, H, A) of the operand. The stack pointer register is again incremented by 1. Example: POP H or POP A MYcsvtu Notes
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The 8085 Addressing Modes The instructions MOV B, A or MVI A, 82H are to copy
data from a source into a destination. In these instructions the source can be a register, an input port, or an 8-bit number (00H to FFH). Similarly, a destination can be a register or an output port. The sources and destination are operands. The various formats for specifying operands are called the ADDRESSING MODES. MYcsvtu Notes
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The 8085 Addressing Modes For 8085, they are:
Immediate addressing. Register addressing. Direct addressing. Indirect addressing. Implicit addressing
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The 8085 Addressing Modes Immediate addressing
Data is present in the instruction. Load the immediate
data to the destination provided. Example: MVI R, data Register addressing Data is provided through the registers. Example: MOV Rd, Rs MYcsvtu Notes
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The 8085 Addressing Modes Direct addressing
Used to accept data from outside devices to store in the
accumulator or send the data stored in the accumulator to the outside device. Accept the data from the port 00H and store them into the accumulator or Send the data from the accumulator to the port 01H. Example: IN 00H or OUT 01H
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The 8085 Addressing Modes Indirect Addressing
This means that the Effective Address is calculated by
the processor and the contents of the address (and the one following) is used to form a second address. The second address is where the data is stored. Note that this requires several memory accesses; two accesses to retrieve the 16-bit address and a further access (or accesses) to retrieve the data which is to be loaded into the register. MYcsvtu Notes
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8085 Assembler Directives Assembler directives are instructions to the assembler
concerning the program being assembled. They are not translated into machine code or assigned any memory locations in the object file. ORG (origin) org 20 The next block of instructions or data should be stored
in memory locations starting at 2010. Either hex or decimal numbers are acceptable. MYcsvtu Notes
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8085 Assembler Directives END
end start end of assembly. A HLT instruction may suggest the end of a program,
but does not necessarily mean it is the end of assembly. "start" is the label at the beginning of the program*.
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8085 Assembler Directives EQU
(equate) lookup equ 2 The value of the term, lookup, is equal to 2. lookup's value may be referred by name in the program. Similar to a constant statement.
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8085 Assembler Directives inbuf equ 2099
The value of the term, inbuf, is 2099. This may be the memory location used as an input
buffer.
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8085 Assembler Directives DB
(define byte) data: db 34 or data: db 34 db A2,db 93 Initializes an area byte by byte. Assembled bytes of data are stored in successive
memory locations until all values are stored. The label is optional and may be used as the memory location of the beginning of the data. MYcsvtu Notes
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8085 Assembler Directives DW (define word) long: dw 2050 Initializes an area two bytes at a time. DS (define storage) table: ds 10 Reserves a specified number of memory locations.In
this example,10 memory locations are reserved for "table". The label may be used as the memory location of the beginning of the block of memory. MYcsvtu Notes
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Instruction Format An instruction is a command to the microprocessor to
perform a given task on a specified data.
Each instruction has two parts: one is task to be
performed, called the operation code (opcode), and the second is the data to be operated on, called the operand.
The operand (or data) can be specified in various
ways.It may include 8-bit (or 16-bit ) data, an internal register, a memory location, or 8-bit (or 16-bit) address.
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Instruction Format In some instructions, the operand is implicit. Instruction word size The 8085 instruction set is classified into the following
three groups according to word size: One-word or 1-byte instructions Two-word or 2-byte instructions Three-word or 3-byte instructions
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Instruction Format One-Byte Instructions A 1-byte instruction includes the op code and operand
in the same byte. Operand (s) are internal register and are coded into the instruction. For example: Copy the contents of the accumulator in the register C. MOV C,A 0100 1111 4FH
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Instruction Format Add the contents of register B to the contents of the
accumulator. ADD B 1000 0000 80H
Invert (compliment) each bit in the accumulator. CMA 0010 1111 2FH
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Instruction Format MOV rd, rs rd
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