Microprocesor 8086
Short Description
a detailed info of microprocessor intel 8086...
Description
Subject Code : 06EC62 No. of Lecture Hrs/Week : 04 Total no. of Lecture Hrs. : 52
Microprocessor- 8086 MICROPROCESSOR
IA Marks : 25 Exam Hours : 03 Exam Marks : 100
PART - A UNIT - 1 8086 PROCESSORS: Historical background, The microprocessor-based personal computer system, 8086 CPU Architecture, Machine language instructions, Instruction execution timing, The 8088 7 Hours UNIT - 2 INSTRUCTION SET OF 8086: Assembler instruction format, data transfer and arithmetic, branch type, loop, NOP & HALT, flag manipulation, logical and shift and rotate instructions. Illustration of these instructions with example programs, Directives and operators 7 Hours UNIT - 3 BYTE AND STRING MANIPULATION: String instructions, REP Prefix, Table translation, Number format conversions, Procedures, Macros, Programming using keyboard and video display 6 Hours UNIT - 4 8086 INTERRUPTS: 8086 Interrupts and interrupt responses, Hardware interrupt applications, Software interrupt applications, Interrupt examples 6 Hours PART - B UNIT - 5 8086 INTERFACING: Interfacing microprocessor to keyboard (keyboard types, keyboard circuit connections and interfacing, software keyboard interfacing, keyboard interfacing with hardware), Interfacing to alphanumeric displays (interfacing LED displays to microcomputer), Interfacing a microcomputer to a stepper motor 6 Hours UNIT - 6 8086 BASED MULTIPROCESSING SYSTEMS: Coprocessor configurations, The 8087 numeric data processor: data types, processor architecture, instruction set and examples 6 Hours UNIT - 7 SYSTEM BUS STRUCTURE: Basic 8086 configurations: minimum mode, maximum mode, Bus Interface: peripheral component interconnect (PCI) bus, the parallel printer interface (LPT), the universal serial bus (USB) 7 Hours UNIT - 8 80386, 80486 AND PENTIUM PROCESSORS: Introduction to the 80386 microprocessor, Special 80386 registers, Introduction to the 80486 microprocessor, Introduction to the Pentium microprocessor. 7 Hours TEXT BOOKS: 1. Microcomputer systems-The 8086 / 8088 Family – Y.C. Liu and G. A. Gibson, 2E PHI -2003 2. The Intel Microprocessor, Architecture, Programming and Interfacing-Barry B. Brey, 6e, Pearson Education / PHI, 2003 REFERENCE BOOKS: 1. Microprocessor and Interfacing- Programming & Hardware, Douglas hall, 2e TMH, 1991 2. Advanced Microprocessors and Peripherals - A.K. Ray and K.M. Bhurchandi, TMH, 2001 3. 8088 and 8086 Microprocessors - Programming, Interfacing, Software, Hardware & Applications - Triebel and Avtar Singh,4e, Pearson Education, 2003.
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Microprocessor- 8086 Unit - I
8086- PROCESSORS In December 1970, Gilbert Hyatt filed a patent application entitled “Single Chip Integrated Circuit Computer Architecture”, the first basic patent on the microprocessor. The microprocessor was invented in the year 1971 in the Intel labs. The first processor was a 4 bit processor and was called 4004.The following table gives chronologically the microprocessor revolution. Microprocess Year of
Word
Memory
ors
Length
Addressi
Introduct ion
Pins
Clock
Remarks
ng
4004
1971
4 bits
1KB
16
750KHz
Intel’s 1st P
8008
1972
8 bits
16KB
18
800KHz
Mark-8 used this; 1st computer for the home.
8080
1973
8 bits
64KB
40
2 MHz
8085
1976
8 bits
64KB
40
3-6 MHz
8086
1978
16 bits
1 MB
40
5-10 MHz
8088
1980
8/16 bits
1MB
40
5-8MHz
80186
1982
16 bits
1 MB
68
5-8MHz
80286
1982
16 bits
16 MB
68
60-
real,
12.5MHz
4GBv 80386DX 80386SX
1985 1988
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32 bits 16/32
4GB real,
132
64TBv
PGA
16MB
100
6000trs, Altair1st PC Popular IBM PC, Intel became one of fortune 500 companies. PC/XT More a Microcontroller PC/AT, 15 million PC’s sold in 6 years
20-33MHz
2,75,000 transistors
20MHz
32b int 16b ext Page 2
Microprocessor- 8086
bits
real,
64TBv 80486DX
Pentium
1989
1993
32 bits
64 bits
4 GB real,
168
25-66MHz
64TBv
PGA
4 GB, 16
237
60-200
KB cache
PGA
MHz
64Gb, 256K/512 K L2 Cache 64Gb
387 PGA
150MHz
242
400MHz
Pentium Pro
1995
64 bits
Pentium II
1997
64 bits
Pentium II Xeon
1998
64 bits
512k/1M/ 2M L2 cache
528 pins LGA
400MHz
Pentium III Xeon
1999
64 bits
370 PGA
1GHz
Pentium 4
2000
64 bits
16 k L1 data + 16 k L1 instr; 512 kB/1 MB/2 MB L2 514,864 KB
423 PGA
1.3 - 2GHz
Xeon
2001
64 bits
Itanium
2001
64 bits
Itanium 2
2002
64 bits
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8 MB iL3 cache 2MB/ 4MB L3 cache 1.5 – 9MB L3 cache
3.33 GHz 418 pins FCP GA 611 pins FCP GA
800 MHz
200 MHz
Flaot pt cop, Command line to point and click 2 intr. At a time, Process real world data like sound, hand written and photo images. Speedy CAD
Capture, edit & share digital photos via Internet Workstations thriving on business applications e-commerce applications
1.5 GHz, Professional quality movies, rendering 3D graphics. Choice of operating system Enabling ecommerce security transactions Business applications
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Microprocessor- 8086
Centrino mobile
2003
64 bits
Pentium 4 processor extreme Centrino M (mobile)
2003
64 bits
2004
64 bits
2 MB L2 cache
423 pins PGA
3.80 GHz
Mobile specific, increased battery life. Hyper threading technology, games 90nm,2MB L2 cache400MHz power-system optimized system bus
Apart from Intel, Motorola, Zylog Corporation, Fairchild and National (Hitachi, Japan) are some of the other microprocessor manufacturers. Microprocessors are used in all modern appliances, which are Intelligent, meaning that they are capable of different modes of working. For example an automatic washing machine has different wash options, one for woolen and the other for nylon etc., Also in a printing Industry right from type setting to page lay out to color photo scanning and printing and cutting and folding are also taken care of by microprocessors. The applications of microprocessors can be sub divided into three categories. The first and most important one is the computer applications. The second one is the control application (micro controllers, embedded controllers etc.) and the third is in Communication (DSP processors, Cell phones etc.). The basis of working of all the microprocessors is binary arithmetic and Boolean logic. The number system used is Hexadecimal (base 16) and the character code used is ASCII. Many assemblers are available to interface the machine code savvy processor to English language like programs of the users.(CP/M, MASM, TASM etc.). For Games we have joysticks, electronic guns and touch screens. Nowadays laptop and palmtop computers are proliferating and in future nano computing, bio computing, molecular and optical computing also are contemplated.
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Microprocessor- 8086
Microprocessor Based Personal Computer System
DATA BUS INPUT DEVICE I/O PORTS
CONTROL BUS
CENTRAL PROCESSING UNIT (CPU)
CONTROL BUS
MEMORY (RAM AND ROM)
OUTPUT DEVICE ADDRESS BUS
Different Components of Computers •
Microprocessor – 8086, 8088, 80186, 80188, 80286, 80386, 80486, Pentium, Pentium Pro, Pentium II, Pentium III, Pentium IV
•
Memory System – DRAM, SRAM, Cache, ROM, Flash Memory, EEPROM, SDRAM, RAMBUS
•
I/O System – Printer, Serial communications, Floppy Disk Drive, Hard Disk Drive, Mouse, CD-ROM drive, Plotter, Keyboard, Monitor, Scanner, DVD, Pen Drive
Summary of Simple Microcomputer Bus Operation 1. A microcomputer fetches each program instruction in sequence, decodes the instruction, and executes it. 2. The CPU in a microcomputer fetches instructions or reads data from memory by sending out an address on the address bus and a Memory Read signal on the control bus. The memory outputs the addressed instruction or data word to the CPU on the data bus. 3. The CPU writes a data word to memory by sending out an address on the address bus, sending out the data word on the data bus, and sending a Memory write signal to memory on the control bus. 4. To read data from a port, the CPU sends out the port address on the address bus and sends an I/O Read signal to the port device on the control bus. Data from the port comes into the CPU on the data bus. 5. To write data to a port, the CPU sends out the port address on the address bus, sends out the data to be written to the port on the data bus, and sends an I/O Write signal to the port device on the control bus. MANOJKUMAR S.B
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Microprocessor- 8086
8086 Internal Block diagram (Intel Corp.)
The block diagram of 8086 is as shown. This can be subdivided into two parts, namely the Bus Interface Unit and Execution Unit. The Bus Interface Unit consists of segment registers, adder to generate 20 bit address and instruction prefetch queue. Once this address is sent out of BIU, the instruction and data bytes are fetched from memory and they fill a First In First Out 6 byte queue. Execution Unit: The execution unit consists of scratch pad registers such as 16-bit AX, BX, CX and DX and pointers like SP (Stack Pointer), BP (Base Pointer) and finally index registers such as source index and destination index registers. The 16-bit scratch pad registers can be split into two 8-bit registers. For example, AX can be split into AH and AL registers. The segment registers and their default offsets are given below.
MANOJKUMAR S.B
Segment Register
Default Offset
CS
IP (Instruction Pointer)
DS
SI, DI
SS
SP, BP
ES
DI Page 6
Microprocessor- 8086
The Arithmetic and Logic Unit adjacent to these registers perform all the operations. The results of these operations can affect the condition flags. Different registers and their operations are listed below: Register
Operations
AX
Word multiply, Word divide, word I/O
AL
Byte Multiply, Byte Divide, Byte I/O, translate, Decimal Arithmetic
AH
Byte Multiply, Byte Divide
BX
Translate
CX
String Operations, Loops
CL
Variable Shift and Rotate
DX
Word Multiply, word Divide, Indirect I/O 8086/8088 MPU
IP
Instruction Pointer
CS
Code Segment Register
DS
Data Segment Register
SS
Stack Segment Register
ES
Extra Segment Register
AX
AH
AL
BX
BE
BL
CX
CE
CL
DX
DH
DL
SP
Stack Pointer Register
BP
Break Pointer Register
SI
Source Index Register
DI
Destination Index Register
SR
Status Register
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MEMORY 00000016
Code Segment (64Kb)
Data Segment (64Kb)
Stack Segment (64Kb)
Extra Segment (64Kb) FFFFF16
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Microprocessor- 8086
Generation of 20-bit Physical Address: LOGICAL ADDRESS SEGMENT REGISTER
0000
ADDER
20 BIT PHYSICAL MEMORY ADDRESS 8086 flag register format BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
U
U
U
U
0F
DF
IF
TF
SF
ZF
U
AF
U
PF
U
CF
U= UNDEFINED
(a) (b) (c) (d) (e) (f) (g) (h) (i)
(a) (b) (c) (d) (e) (f) (g) (h) (i)
: CARRY FLAG – SET BY CARRY OUT OF MSB : PARITY FLAG – SET IF RESULT HAS EVEN PARITY : AUXILIARY CARRY FLAG FOR BCD : ZERO FLAG – SET IF RESULT = 0 : SIGN FLAG = MSB OF RESULT : SINGLE STEP TRAP FLAG : INTERRUPT ENABLE FLAG : STRING DIRECTION FLAG : OVERFLOW FLAG
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Microprocessor- 8086
There are three internal buses, namely A bus, B bus and C bus, which interconnect the various blocks inside 8086.The execution of instruction in 8086 is as follows: The microprocessor unit (MPU) sends out a 20-bit physical address to the memory and fetches the first instruction of a program from the memory. Subsequent addresses are sent out and the queue is filled upto 6 bytes. The instructions are decoded and further data (if necessary) are fetched from memory. After the execution of the instruction, the results may go back to memory or to the output peripheral devices as the case may be.
Real mode memory addressing The segment registers have contents of 16-bits. Hence, 216 = 64Kb of memory can be addressed by segment registers. Normally, the segment base register contains three zeroes, so that each segment can start from say E0000 to EFFFF. The segments namely code segment, data segment, stack segment and extra segment for a particular program can be contiguous, separate or in case of small programs overlapping even. i.e., for example, code segment is supposed to have 64Kb and in case of small programs data segment may be within the code segment. Fig: One way four 64-Kbyte segment might be positioned within the 1-Mbyte address space FFFFFH
PHYSICAL ADDRESS
7FFFFH
MEMORY HIGHEST ADDRESS TOP OF EXTRA SEGMENT
64K 70000H
EXTRA SEGMENT BASE ES=7000H
5FFFFH
TOP OF STACK SEGMENT 64K
50000H
STACK SEGMENT BASE SS = 5000H
4489FH
TOP OF CODE SEGMENT 64K
348A0H
CODE SEGMENT BASE CS=348AH
2FFFFH
TOP OF DATA SEGMENT 64K
of an 8086
20000H
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BOTTOM OF DATA SEGMENT
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Microprocessor- 8086
Fig: Addition of IP to CS to produce the physical address of the code byte
4489FH
PHYSICAL ADDRESS
MEMORY TOP OF CODE SEGMENT
38AB4H
CODE BYTE
IP=4214H 348A0H
START OF CODE SEGMENT CS=348AH
(a) Diagram CS IP + PHYSICAL ADDRESS
3 4 8 A 0 4 2 1 4 3 8 A B 4
HARDWIRED ZERO
(b) Computation Segment Over Ride Prefix SOP is used when a particular offset register is not used with its default base segment register, but with a different base register. This is a byte put before the OPCODE byte. 0
0
SR
Segment Register
00
ES
01
CS
10
SS
11
DS
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1
S
R
1
1
0
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Microprocessor- 8086
Here SR is the new base register. To use DS as the new register 3EH should be prefix. Operand Register
Default
With over ride prefix
IP (Code address)
CS
Never
SP(Stack address)
SS
Never
BP(Stack Address)
SS
BP+DS or ES or CS
SI or DI(not including Strings)
DS
ES, SS or CS
SI (Implicit source Address for
DS
”
ES
Never
strings) DI (Implicit Destination Address for strings) Examples: MOV AX, DS: [BP], LODS ES: DATA1 S4
S3
Indications
0
0
Alternate data
0
1
Stack
1
0
Code or none
1
1
Data
Bus High Enable / Status
BHE
A0
Indications
0
0
Whole word
0
1
Upper byte from or to odd address
1
0
Lower byte from or to even address
1
1
None
Segmentation: The 8086 microprocessor has 20 bit address pins. These are capable of addressing 220 = 1Mega Byte memory. To generate this 20 bit physical address from 2 sixteen bit registers, the following procedure is adopted. MANOJKUMAR S.B
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Microprocessor- 8086
The 20 bit address is generated from two 16-bit registers. The first 16-bit register is called the segment base register. These are code segment registers to hold programs, data segment register to keep data, stack segment register for stack operations and extra segment register to keep strings of data. The contents of the segment registers are shifted left four times with zeroes (0’s) filling on the right hand side. This is similar to multiplying four hex numbers by the base 16. This multiplication process takes place in the adder and thus a 20 bit number is generated. This is called the base address. To this a 16-bit offset is added to generate the 20-bit physical address. Segmentation helps in the following way. The program is stored in code segment area. The data is stored in data segment area. In many cases the program is optimized and kept unaltered for the specific application. Normally the data is variable. So in order to test the program with a different set of data, one need not change the program but only have to alter the data. Same is the case with stack and extra segments also, which are only different type of data storage facilities. Generally, the program does not know the exact physical address of an instruction. The assembler, a software which converts the Assembly Language Program (MOV, ADD etc.) into machine code (3EH, 4CH etc) takes care of address generation and location. Sr. No 1. 2. 3.
4.
5.
8088 Its has only eight data lines. Therefore, it has AD0 – AD7 and A8 –A15 signals. As data bus is 8-bit wide, it does not have BHE signal. It has 4 byte instruction queue. Due to 8-bit data bus instruction fetching is slow and 4 bytes are sufficient for queue. Its pin number 34 is SSO. It acts as S0 in the minimum mode. In maximum mode, SSO pin is always high.
80086 It has sixteen data lines. Therefore it has AD0 – AD15 signals. It has BHE signal to access higher byte. It has 6 byte instrucyion queue.
Its pin number 34 is BHE/S7. During T1(first clock cycle) BHE should be used to enable data on to the most significant byte of the data bus. During T2, T3 and T4 status of this pin is logic 0. In maximum mode, 8087 monitors this pin to identify the CPU as a 8088 or a 8086, and accordingly sets its own queue length to 4 or 6 bytes. In minimum mode its pin 28 is In minimum mode its pin 28 is assigned to signal assigned to signal IO/M M/IO
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Microprocessor- 8086
Addressing Modes Addressing modes of 8086 When 8086 executes an instruction, it performs the specified function on data. These data are called its operands and may be part of the instruction, reside in one of the internal registers of the microprocessor, stored at an address in memory or held at an I/O port, to access these different types of operands, the 8086 is provided with various addressing modes (Data Addressing Modes). Data Addressing Modes of 8086 The 8086 has 12 addressing modes. The various 8086 addressing modes can be classified into five groups. A. Addressing modes for accessing immediate and register data (register and immediate modes). B. Addressing modes for accessing data in memory (memory modes) C. Addressing modes for accessing I/O ports (I/O modes) D. Relative addressing mode E. Implied addressing mode
8086 ADDRESSING MODES
A. Immediate addressing mode: In this mode, 8 or 16 bit data can be specified as part of the instruction. OP Code Example 1 : MOV CL, 03 H Moves the 8 bit data 03 H into CL
Immediate Operand
Example 2 :
MOV DX, 0525 H Moves the 16 bit data 0525 H into DX In the above two examples, the source operand is in immediate mode and the destination operand is in register mode. A constant such as “VALUE” can be defined by the assembler EQUATE directive such as VALUE EQU 35H Example : MOV BH, VALUE Used to load 35 H into BH B. Register addressing mode : The operand to be accessed is specified as residing in an internal register of 8086. Fig. below shows internal registers, any one can be used as a source or destination operand, however only the data registers can be accessed as either a byte or word. MANOJKUMAR S.B
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Register Accumulator Base Count Data Stack pointer Base pointer Source index Destination index Code Segment Data Segment Stack Segment Extra Segment
Microprocessor- 8086 Byte (Reg 8) AL, AH BL, BH CL, CH DL, DH -
Operand sizes
Word (Reg 16) Ax Bx Cx Dx SP BP SI DI CS DS SS ES
Example 1 : MOV DX (Destination Register) , CX (Source Register) Which moves 16 bit content of CS into DX. Example 2 :
MOV CL, DL Moves 8 bit contents of DL into CL
MOV BX, CH is an illegal instruction. * The register sizes must be the same. C. Direct addressing mode : The instruction Opcode is followed by an affective address, this effective address is directly used as the 16 bit offset of the storage location of the operand from the location specified by the current value in the selected segment register. The default segment is always DS. The 20 bit physical address of the operand in memory is normally obtained as PA = DS : EA But by using a segment override prefix (SOP) in the instruction, any of the four segment registers can be referenced, PA =
CS DS : Direct Address SS ES The Execution Unit (EU) has direct access to all registers and data for register and immediate operands. However the EU cannot directly access the memory operands. It must use the BIU, in order to access memory operands. In the direct addressing mode, the 16 bit effective address (EA) is taken directly from the displacement field of the instruction. MANOJKUMAR S.B
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Microprocessor- 8086
Example 1 : MOV CX, START If the 16 bit value assigned to the offset START by the programmer using an assembler pseudo instruction such as DW is 0040 and [DS] = 3050. Then BIU generates the 20 bit physical address 30540 H. The content of 30540 is moved to CL The content of 30541 is moved to CH Example 2 : MOV CH, START If [DS] = 3050 and START = 0040 8 bit content of memory location 30540 is moved to CH. Example 3 : MOV START, BX With [DS] = 3050, the value of START is 0040. Physical address : 30540 MOV instruction moves (BL) and (BH) to locations 30540 and 30541 respectively. Register indirect addressing mode : The EA is specified in either pointer (BX) register or an index (SI or DI) register. The 20 bit physical address is computed using DS and EA. Example : MOV [DI], BX register indirect If [DS] = 5004, [DI] = 0020, [Bx] = 2456 PA=50060. The content of BX(2456) is moved to memory locations 50060 H and 50061 H. CS PA = DS BX SS = SI ES DI Based addressing mode: PA =
CS DS SS ES
:
BX or BP
+ displacement
when memory is accessed PA is computed from BX and DS when the stack is accessed PA is computed from BP and SS. Example : MOV AL, START [BX] or MOV AL, [START + BX] based mode EA : [START] + [BX] PA : [DS] + [EA] The 8 bit content of this memory location is moved to AL.
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Indexed addressing mode: CS PA = DS SS : ES Example
Microprocessor- 8086 SI or DI
+ 8 or 16bit displacement
:
MOV BH, START [SI] PA : [SART] + [SI] + [DS] The content of this memory is moved into BH. Based Indexed addressing mode: CS PA = DS BX SI SS : or + or + 8 or 16bit displacement ES BP DI Example : MOV ALPHA [SI] [BX], CL If [BX] = 0200, ALPHA – 08, [SI] = 1000 H and [DS] = 3000 Physical address (PA) = 31208 8 bit content of CL is moved to 31208 memory address. String addressing mode: The string instructions automatically assume SI to point to the first byte or word of the source operand and DI to point to the first byte or word of the destination operand. The contents of SI and DI are automatically incremented (by clearing DF to 0 by CLD instruction) to point to the next byte or word. Example : MOV S BYTE If [DF] = 0, [DS] = 2000 H, [SI] = 0500, [ES] = 4000, [DI] = 0300 Source address : 20500, assume it contains 38 PA : [DS] + [SI] Destination address : [ES] + [DI] = 40300, assume it contains 45 After executing MOV S BYTE, [40300] = 38 [SI] = 0501 incremented [DI] = 0301 C. I/O mode (direct) : Port number is an 8 bit immediate operand. Example : OUT 05 H, AL Outputs [AL] to 8 bit port 05 H I/O mode (indirect): The port number is taken from DX. MANOJKUMAR S.B
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Microprocessor- 8086
Example 1 :
INAL, DX If [DX] = 5040 8 bit content by port 5040 is moved into AL. Example 2 : IN AX, DX Inputs 8 bit content of ports 5040 and 5041 into AL and AH respectively. D. Relative addressing mode: Example : JNC START If CY=O, then PC is loaded with current PC contents plus 8 bit signed value of START, otherwise the next instruction is executed. E. Implied addressing mode: Instruction using this mode have no operands. Example : CLC which clears carry flag to zero.
SINGLE INDEX
DOUBLE INDEX
BX OR Encoded in the instruction
BP OR
BX
SI
OR
OR
BP
DI
+
EU
SI OR DI
Explicit in the instruction
+
DISPLACEMENT CS
+
0000 OR
Assumed unless over ridden by prefix
DS
0000 OR
SS
+
OR ES
BIU
0000 0000
+
PHYSICAL ADDRESS
Fig.3.1 : Summary of 8086 Addressing Modes MANOJKUMAR S.B
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Microprocessor- 8086
Special functions of general-purpose registers: AX & DX registers: In 8 bit multiplication, one of the operands must be in AL. The other operand can be a byte in memory location or in another 8 bit register. The resulting 16 bit product is stored in AX, with AH storing the MS byte. In 16 bit multiplication, one of the operands must be in AX. The other operand can be a word in memory location or in another 16 bit register. The resulting 32 bit product is stored in DX and AX, with DX storing the MS word and AX storing the LS word. BX register : In instructions where we need to specify in a general purpose register the 16 bit effective address of a memory location, the register BX is used (register indirect). CX register : In Loop Instructions, CX register will be always used as the implied counter. In I/O instructions, the 8086 receives into or sends out data from AX or AL depending as a word or byte operation. In these instructions the port address, if greater than FFH has to be given as the contents of DX register. Ex : IN AL, DX DX register will have 16 bit address of the I/P device Physical Address (PA) generation : Generally Physical Address (20 Bit) = Segment Base Address (SBA) + Effective Address (EA) Code Segment : Physical Address (PA) = CS Base Address + Instruction Pointer (IP) Data Segment (DS) PA = DS Base Address + EA can be in BX or SI or DI Stack Segment (SS) PA + SS Base Address + EA can be SP or BP Extra Segment (ES) PA = ES Base Address + EA in DI
Instruction Format :
The 8086 instruction sizes vary from one to six bytes. The OP code occupies six bytes and it defines the operation to be carried out by the instruction. Register Direct bit (D) occupies one bit. It defines whether the register operand in byte 2 is the source or destination operand. D=1 Specifies that the register operand is the destination operand. D=0 indicates that the register is a source operand. Data size bit (W) defines whether the operation to be performed is an 8 bit or 16 bit data W=0 indicates 8 bit operation W=1 indicates 16 bit operation MANOJKUMAR S.B
Byte 3
Byte 4
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7
2
1
Opcode
0 D
7 W
Byte 1
Microprocessor- 8086
6
5
MOD
4
3
2
REG
1 0
R/M
Low Disp/ DATA
High Disp/ DATA
OR
Byte 2 DIRECT ADDRESS LOW BYTE
DIRECT ADDRESS HIGH BYTE
Register Operand/Register to use EA Calculation Register Operand/Extension of opcode Register mode/Memory mode with displacement length Word/byte operation Direction is to register/from register Operation code
The second byte of the instruction usually identifies whether one of the operands is in memory or whether both are registers. This byte contains 3 fields. These are the mode (MOD) field, the register (REG) field and the Register/Memory (R/M) field. MOD (2 bits) 00 01 10 11
Interpretation Memory mode with no displacement follows except for 16 bit displacement when R/M=110 Memory mode with 8 bit displacement Memory mode with 16 bit displacement Register mode (no displacement)
Register field occupies 3 bits. It defines the register for the first operand which is specified as source or destination by the D bit. REG W=0 W=1 000 AL AX 001 CL CX 010 DL DX 011 BL BX 100 AH SP 101 CH BP 110 DH SI 111 BH DI The R/M field occupies 3 bits. The R/M field along with the MOD field defines the second operand as shown below. MANOJKUMAR S.B
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Microprocessor- 8086
MOD 11 R/M 000 001 010 011 100 101 110 111
W=0 AL CL DL BL AH CH DH BH
W=1 AX CX DX BX SP BP SI DI
Effective Address Calculation R/M 000 001 010 011 100 101 110 111
MOD=00 (BX) + (SI) (BX)+(DI) (BP)+(SI) (BP)+(DI) (SI) (DI) Direct address (BX)
MOD 01 (BX)+(SI)+D8 (BX)+(DI)+D8 (BP)+(SI)+D8 (BP)+(DI)+D8 (SI) + D8 (DI) + D8 (BP) + D8 (BX) + D8
MOD 10 (BX)+(SI)+D16 (BX)+(DI)+D16 (BP)+(SI)+D16 (BP)+(DI)+D10 (SI) + D16 (DI) + D16 (BP) + D16 (BX) + D16
In the above, encoding of the R/M field depends on how the mode field is set. If MOD=11 (register to register mode), this R/M identifies the second register operand. MOD selects memory mode, then R/M indicates how the effective address of the memory operand is to be calculated. Bytes 3 through 6 of an instruction are optional fields that normally contain the displacement value of a memory operand and / or the actual value of an immediate constant operand. Example 1 : MOV CH, BL This instruction transfers 8 bit content of BL
Into CH
The 6 bit Opcode for this instruction is 1000102 D bit indicates whether the register specified by the REG field of byte 2 is a source or destination operand. D=0 indicates BL is a source operand. W=0 byte operation In byte 2, since the second operand is a register MOD field is 112. The R/M field = 101 (CH) Register (REG) field = 011 (BL) Hence the machine code for MOV CH, BL is 10001000 11 011 101 Byte 1 Byte2 = 88DD16 MANOJKUMAR S.B
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Microprocessor- 8086
Example 2 : SUB Bx, (DI) This instruction subtracts the 16 bit content of memory location addressed by DI and DS from Bx. The 6 bit Opcode for SUB is 0010102. D=1 so that REG field of byte 2 is the destination operand. W=1 indicates 16 bit operation. MOD = 00 REG = 011 R/M = 101 The machine code is 0010 1011 0001 1101 2 B 1 D 2B1D16 MOD / R/M
Memory Mode (EA Calculation) 00 01 10 (BX)+(SI) (BX)+(SI)+d8 (BX)+(SI)+d16 (BX) + (DI) (BX)+(DI)+d8 (BX)+(DI)+d16 (BP)+(SI) (BP)+(SI)+d8 (BP)+(SI)+d16 (BP)+(DI) (BP)+(DI)+d8 (BP)+(DI)+d16 (SI) (SI) + d8 (SI) + d16 (DI) (DI) + d8 (DI) + d16 d16 (BP) + d8 (BP) + d16 (BX) (BX) + d8 (BX) + d16
000 001 010 011 100 101 110 111
Register Mode W=0 W=1 AL AX CL CX DL DX BL BX AH SP CH BP DH SI BH DI
Summary of all Addressing Modes Example 3 : Code for MOV 1234 (BP), DX Here we have specify DX using REG field, the D bit must be 0, indicating the DX is the source register. The REG field must be 010 to indicate DX register. The W bit must be 1 to indicate it is a word operation. 1234 [BP] is specified using MOD value of 10 and R/M value of 110 and a displacement of 1234H. The 4 byte code for this instruction would be 89 96 34 12H. Opcode
D
W
MOD
REG
R/M
LB displacement
HB displacement
100010
0
1
10
010
110
34H
12H
Example 4 : Code for MOV DS : 2345 [BP], DX Here we have to specify DX using REG field. The D bit must be o, indicating that Dx is the source register. The REG field must be 010 to indicate DX register. The w bit must be 1 to indicate it is a word operation. 2345 [BP] is specified with MOD=10 and R/M = 110 and displacement = 2345 H. Whenever BP is used to generate the Effective Address (EA), the default segment would be SS. In this example, we want the segment register to be DS, we have to provide the segment override prefix byte (SOP byte) to start with. The SOP byte is 001 SR 110, where SR value is provided as per table shown below.
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Microprocessor- 8086
SR Segment register 00 ES 01 CS 10 SS 11 DS To specify DS register, the SOP byte would be 001 11 110 = 3E H. Thus the 5 byte code for this instruction would be 3E 89 96 45 23 H. SOP
Opcode
D
W
MOD
REG
R/M
LB disp.
HD disp.
3EH
1000 10
0
1
10
010
110
45
23
Suppose we want to code MOV SS : 2345 (BP), DX. This generates only a 4 byte code, without SOP byte, as SS is already the default segment register in this case. Example 5 : Give the instruction template and generate code for the instruction ADD OFABE [BX], [DI], DX (code for ADD instruction is 000000) ADD OFABE [BX] [DI], DX Here we have to specify DX using REG field. The bit D is 0, indicating that DX is the source register. The REG field must be 010 to indicate DX register. The w must be 1 to indicate it is a word operation. FABE (BX + DI) is specified using MOD value of 10 and R/M value of 001 (from the summary table). The 4 byte code for this instruction would be Opcode D W MOD REG R/M 16 bit disp. =01 91 BE FAH 000000 0 1 10 010 001 BEH FAH Example 6 : Give the instruction template and generate the code for the instruction MOV AX, [BX] (Code for MOV instruction is 100010) AX destination register with D=1 and code for AX is 000 [BX] is specified using 00 Mode and R/M value 111 It is a word operation Opcode 100010
D 1
W 1
Mod 00
REG 000
R/M 111
=8B 07H
Questions : 1. 2. 3. 4. 5. 6. 7. 8.
Write a note on segment registers. List the rules for segmentation. What are the advantages of using segmentation? What do you mean by index registers? What is the function of SI and DI registers? Explain the addressing modes of 8086 with the help of examples. What do you mean by segment override prefix? Write a short notes on i) Instruction formats ii) Instruction execution timing
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Microprocessor- 8086 Unit - 2
INSTRUCTION SET OF 8086 The instructions of 8086 are classified into SIX groups. They are: 1.
DATA TRANSFER INSTRUCTIONS
2.
ARITHMETIC INSTRUCTIONS
3.
BIT MANIPULATION INSTRUCTIONS
4.
STRING INSTRUCTIONS
5.
PROGRAM EXECUTION TRANSFER INSTRUCTIONS
6.
PROCESS CONTROL INSTRUCTIONS
1.DATA TRANSFER INSTRUCTIONS The DATA TRANSFER INSTRUCTIONS are those, which transfers the DATA from any one source to any one destination. The data’s may be of any type. They are again classified into four groups. They are: GENERAL – PURPOSE BYTE OR WORD TRANSFER INSTRUCTIONS
SIMPLE INPUT AND OUTPUT PORT TRANSFER INSTRUCTION
MOV PUSH POP XCHG XLAT
SPECIAL ADDRESS TRANSFER INSTRUCTION
FLAG TRANSFER INSTRUCTIONS
LEA LDS LES
LAHF SAHF PUSHF POPF
IN OUT
2.ARITHMETIC INSTRUCTIONS These instructions are those which are useful to perform Arithmetic calculations, such as addition, subtraction, multiplication and division. They are again classified into four groups. They are: ADDITION INSTRUCTIONS
SUBTRACTION INSTRUCTIONS
MULTIPLICATION INSTRUCTIONS
DIVISION INSTRUCTIONS
ADD ADC INC AAA DAA
SUB SBB DEC NEG CMP AAS DAS
MUL IMUL AAM
DIV IDIV AAD CBW CWD
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Microprocessor- 8086
3.BIT MANIPULATION INSTRUCTIONS
These instructions are used to perform Bit wise operations. LOGICAL INSTRUCTIONS
SHIFT INSTRUCTIONS
ROTATE INSTRUCTIONS
NOT AND OR XOR TEST
SHL / SAL SHR SAR
ROL ROR RCL RCR
4. STRING INSTRUCTIONS The string instructions function easily on blocks of memory. They are user friendly instructions, which help for easy program writing and execution. They can speed up the manipulating code. They are useful in array handling, tables and records. STRING INSTRUCTIONS REP REPE / REPZ REPNE / REPNZ MOVS / MOVSB / MOVSW COMPS / COMPSB / COMPSW SCAS / SCASB / SCASW LODS / LODSB / LODSW STOS / STOSB / STOSW
5.PROGRAM EXECUTION TRANSFER INSTRUCTIONS These instructions transfer the program control from one address to other address. (Not in a sequence). They are again classified into four groups. They are: UNCONDITIONAL TRANSFER INSTRUCTIONS CALL RET JMP
MANOJKUMAR S.B
CONDITIONAL TRANSFER INSTRUCTIONS JA / JNBE JAE / JNB JB / JNAE JBE / JNA JC JE / JZ JG / JNLE JGE / JNL JL / JNGE
JLE / JNG JNC JNE / JNZ JNO JNP / JPO JNS JO
ITERATION CONTROL INSTRUCTIONS
INTERRUPT INSTRUCTIONS
LOOP LOOPE / LOOPZ LOOPNE / LOOPNZ JCXZ
INT INTO IRET
JP / JPE JS
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Microprocessor- 8086
6.PROCESS CONTROL INSTRUCTIONS
These instructions are used to change the process of the Microprocessor. They change the process with the stored information. They are again classified into Two groups. They are: FLAG SET / CLEAR INSTRUCTIONS
EXTERNAL HARDWARE SYNCHRONIZATION INSTRUCTIONS
STC CLC CMC STD CLD STI CLI
HLT WAIT ESC LOCK NOP
Addition: There are two instructions ADD and ADC Register Addition: ADD AL,BL AL=AL+BL ADD CX,DI CX=CX+DI ADD CL,10H CL=CL+10 ADD [BX],AL the contents of AL are added with the contents of a memory location addressed by BX and the result is stored in the same memory location Example ADD AL,BL AL=10H BL=30H the result AL=40H ADD AX,[SI+2] the word content of the data segment memory location addressed by sum of SI+2 is added with AX and the result is stored in AX Example AX=1234H SI=2000 SI+2=2002 and let the word stored in memory location 2002 be 1122H The result AX=2356H ADD BYTE PTR [DI],3 –3 is added to the byte contents of the data segment memory location addressed by DI Example DI=2000 and the contents of that memory location is 11H The contents of address 2000 will be 14H after the execution of this instruction The contents of the flag register change after the addition operation. The flags affected are SIGN,CARRY,ZERO, AUX CARRY,PARITY,OVERFLOW MANOJKUMAR S.B
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Microprocessor- 8086
The INTR,TRAP and other flags not affected.
Immediate Addition An 8 bit immediate data is added. Example MOV AL,10H ADD AL,30H The result AL=40H
Memory to Register addition Example MOV AX,0 ADD AX,DI ADD AX,DI+1 Let DI=2000 the contents of this memory location is 22H After first add AX will have 22+0=22H Then DI+1=2001 let the contents be 11H
The result will be 33H Array addition The offset address of the array is moved to the SI or DI register Example MOV AL,0 MOV SI,OFFSET of Array ADD AL,[SI] ADD AL,[SI+2] ADD AL,[SI+4] Array
Offset addr
2000
10H
2001 2002 2003 2004
11H 22H 33H 44H
After first add the contents AL will be 0+10=10H After the second add instruction AL will be 10+22=32H After the third add instruction AL will be 32+44=76H MANOJKUMAR S.B
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Microprocessor- 8086 Increment addition
INC adds a 1 to a register or a memory location used for memory increments Example INC AX This instruction adds one to the contents ox AX let Ax=1234H the result will be AX=1235H INC BYTE PTR [DI] This instruction adds one to the byte contents of the data segment location addressed by DI Addition with carry
ADC adds the bit in carry flag to the operand data. Example
ADC AL,BH AL=AL+BH+CARRY ADC CX,AX CX=CX+AX+CARRY ADC BX,[BP+2] the word contents of the stack segment memory location addressed by BP+2 is added to BX with carry and the result is stored in BX. Subtraction Many forms of subtraction appears to use with any addressing mode 8 16 and 32 bit data SUB SBB subtract with borrow Register Subtraction: SUB AL,BL AL=AL-BL SUB CL,10H CL=CL-10 The carry flag holds the borrow. Decrement
A 1 is subtracted from the register or the memory location. Example
DEC AX DEC BYTE PTR [DI] DEC CL
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Microprocessor- 8086
DEC BL Subtracts 1 to from a register or a memory location CMP
This changes only the flag the destination operand never changes This instruction is usually followed by conditional jump instructions and tests the condition against the flags Multiplication The multiplication is performed on bytes words or double words and can be a signed integer or unsigned integer MUL: unsigned IMUL: signed Flags CARRY,OVERFLOW 8 Bit multiplication Example MOV BL,05H MOV AL,10H MUL BL The multiplicand is in AL The multiplier is in BL (even a memory location can be used) 8 Bit multiplication Example IMUL BYTE PTR [BX] AL is multiplied by the byte contents of the data segment memory location addressed by BX the signed product is placed in AX For signed multiplication the product is in true binary form if positive and in two’s complement form if negative Example AL 00000010 BL 10000100 AL contains +2 and BL contains -4 IMUL BL The product is -8 The product is in two’s complement form stored in AX AX 11111000 Division DIV,IDIV The dividend is always a double width dividend that is divided by the operand An 8 bit division devides a 16 bit number by a 8 bit number MANOJKUMAR S.B
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Microprocessor- 8086
Errors: Divide by zero,devide overflow
AX register stores the dividend that is divided by contents of any 8 bit register or memory location. the Quotient(result) moves to AL and AH has the remainder. For signed division the remainder always assumes sign of dividend and is an integer AX=0010H equivalent to +16 BL=FDH equivalent to -3 DIV BL AL=05H and AH=-1 11111111H AX=1111111100000101H AX=0010H equivalent to +16 BL=FDH equivalent to -3 DIV BL AL=-5 11111011 and AH=1 AX=0000000111111011H BCD Arithmetic: The microprocessor allows manipulation of BCD and ASCII data BCD used in Cash registers and ASCII used by many programs There are two instructions DAA decimal adjust after addition DAS decimal adjust after subtraction Both instructions correct the result. The BCD number is stored as packed form 2 digits/byte and if unpacked form means 1 digit/byte it functions with AL only. DAA decimal adjust after addition The result is in AL The Logic of this instruction If lower nibble>9 or AF=1 add 06 After adding 06 if upper nibble>9 or CF=1 add 60 DAA instruction follows ADD or ADC Example1 ADD AL,CL DAA Let AL=53 and CL=29 AL=53+29 AL=7C AL=7C+06 (as C>9) AL=82 Example 2 MANOJKUMAR S.B
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Microprocessor- 8086
Let AL=73 CL=29 AL=9C AL=9C+06 (as C>9) AL=A2 AL=A2+60=02 and CF=1 The instruction affects AF,CF,PF and ZF Example3 MOV DX,1234H MOV BX,3099H MOV AL,BL ADD AL,DL DAA MOV AL,BH ADC AL,DH DAA MOV CH,AL BL=99H DL=34H 99+34=CD AL=CD+6(D>9) AL=D3 AL=D3+60(D>9) AL=33 and CF=1 BH=30 DH=12 AL=30+12+CF AL=43 DAA does not do anything The result is placed in CX=4333 DAS instruction follows subtraction The result is in AL Logic of this instruction
If lower nibble>9 or AF=1 subtract 06 After subtracting 06 if upper nibble>9 or CF=1 add 60 The instruction affects AF,CF,PF and ZF Example1 SUB AL,BH DAS Let AL=75 BH=46 AL=75-46=2F AF=1
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AL=2F-6(F>9) AL=29
Microprocessor- 8086
Example 2 SUB AL,CH DAS AL=38 CH=61 AL=38-61=D7 CF=1(borrow) AL=D7-60(D>9) AL=77 CF=1(borrow) Example 3 MOV DX,1234H MOV BX,3099H MOV AL,BL SUB AL,DL DAS MOV CL,AL MOV AL,BH SBB AL,DH DAS MOV CH,AL AL=99-34=65 DAS will not have affect AL=30-12=1E AL=1E-06(E>9) AL=18 The result is 1865 placed in CX ASCII Arithmetic Functions with ASCII coded numbers The numbers range from 30-39H for 0-9 AAA AAD AAM AAS use AX as source and destination AAA Example add 31H and 39H the result is 6AH it should have been 10 decimal which is 31H and 30H AAA is used to correct the answer Converts resulting contents of AL to unpacked decimal digits
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Microprocessor- 8086
AAA instruction examines the lower 4 bits of AL for valid BCD numbers and checks AF=0 sets the 4 high order bits to 0 AH cleared before addition If lower digit of AL is between 0-9 and AF=1 06 is added The upper 4 digits are cleared and incremented by 1 If the lower value of the lower nibble is greater than 9 then increment AL by 06 AH by 1 AF and CF set The higher 4 bits of AL are cleared to 0 AH modified To get the exact sum add 3030H to AX AAS Correct result in AL after subtracting two unpacked ASCII operands The result is in unpacked decimal format If the lower 4 bits of AL are>9 or if AF=1 then AL=AL-6 and AH=AH-1 CF and AF set otherwise CF and AF set to 0 no correction
result the upper nibble of AL is 00 and the lower nibble may be any number from 0-9 AAM Follows multiplication instruction after multiplying two unpacked BCD numbers Converts the product available in AL into unpacked BCD Lower byte of result is in AL and upper in AH Example let the product is 5D in AL D>9 so add 6 =13H LSD of 13H is lower unpacked byte Increment AH, AH=5+1=6 upper unpacked byte After execution AH=06 and AL=03 MOV AL,5 MOV CL,5 MUL CL AAM Accomplishes conversion by dividing AX by 10 Benefit of AAM –converts from binary to unpacked BCD use of AAM for conversion XOR DX,DX MOV CX,100 DIV CX AAM ADD AX,3030H XCHG AX,DX AAM ADD AX,3030H MANOJKUMAR S.B
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Microprocessor- 8086
AAD Appears before division requires AX to contain two digit unpacked BCD number(not ASCII) before executing After adjusting AX with AAD it is divided by an unpacked BCD number to generate a single digit result in AL with remainder in AH Example .MODEL .CODE .STARTUP MOV AL,48H MOV AH,0 AAM ADD AX,3030H MOV DL,AH MOV AH,2 PUSH AX INT 21H POP AX MOV DL,AL INT 21H .EXIT END Logic instructions AND OR Exclusive OR NOT TEST The above instructions perform bitwise operation and the src and destination could be register or memory location. Their function is same as logic opeartions JUMP Group of Instructions Introduction: •
In almost any meaningful program, we need to alter the sequential flow of execution.
•
Examples: Instruction at reset CS:IP: At rest, 8086 begins execution at the address FFFF:0000H (absolute address of FFFF0H). There are only 16 bytes from this location to the end of the memory space (FFFFH)! It is unlikely that any meaningful program can be written within this space. Thus the instruction at this reset location is usually a “long jump”
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Microprocessor- 8086
instruction that transfers control to some suitable lower address based on the available memory. A Sorting Program: A comparison-based sorting program would need to swap or not swap two elements based on the outcome of the comparison of the two elements. This would mean that we need an instruction to “conditionally jump” to some other location in the program. Any number of such examples can be given to illustrate the need for instructions that alter the linear flow of control, either unconditionally or conditionally. •
Unconditional and Conditional Jump Instructions allow such a control over the execution flow.
Unconditional Jump: •
No testing of any flags is involved in deciding whether a jump is to be executed or not.
•
Control transfer occurs always.
•
This is illustrated in the following figure:
Unconditional Jump: Example Before:
After:
CS=FFFF; IP=0000
CS=F000; IP=8000
FFFF0
F0 00 80 00 EA
Unconditionally Jump here
F8000
01 00 B8
Target Location
The instructions used for such unconditional jumps are discussed in detail later. Conditional Jump: •
Values of one or more flags are used in deciding whether a jump is to be executed or not.
•
Thus, a jump may or may not occur depending on the values of such flag bits
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Microprocessor- 8086
This idea is illustrated in the following figure:
Conditional JUMP: Example CMP AX,BX JE LAB1 MOV BX,1 … … LAB1: MOV BX,0 … …
Test the Z flag Target location Test fails i.e Z=0 No jump; Execution continues with the next sequential instruction. Control is transferred here only if Z = 1. A conditional Jump.
The instructions used for such conditional jumps are discussed in detail later. Unconditional Jump Instructions: •
Unconditionally transfer control to an instruction located else where.
•
3 different instructions are available for such unconditional jumps.
•
All have similar behavior; but differ in where the target instruction is allowed to be and consequently, the instruction lengths also differ. And that is the main advantage.
•
The 3 forms are: Short Jump: Target location must be within -128 to +127 bytes from the address following the Jump instruction, i.e current IP. In this case, there is no change in the CS value. Only IP is changed Near Jump: Target location must be within -32768 to +32767 bytes from the address following the Jump instruction, i.e current IP. In this case also, there is no change in the CS value. Only IP is changed Far Jump: Target location can be any where in the memory space. In this case, CS as well as IP is changed.
Intra-Segment Jump Instructions: •
Both Short Jump and Near Jump are called intra-segment jumps also because in both the cases, there is no change in the CS value and only IP is changed. In other words, the jump is to a location that is within the same code segment.
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•
Microprocessor- 8086
For these jumps, the target IP value is not specified as absolute value. Instead, displacement (relative distance) from the current IP is specified.
•
Thus both are relative jumps. (Called Relative Program Memory Addressing in earlier sessions)
•
Jump can be forward (to a higher address) or backwards (to a lower address).
•
So, displacement must be a signed number (can be positive or negative).
•
Short and Near Jumps differ in the way the displacement is specified.
Short Jump Instruction: •
Specifies one byte displacement. It is sign-extended to 16 bits and added to current IP to get new IP.
•
Displacement can be -128 to +127
•
This instruction occupies 2 bytes; the first byte specifies the opcode and the second byte specifies the relative displacement as a signed 8-bit quantity. The format is shown below:
Displacement
Opcode EB
8-Bit Signed Value
A short jump instruction with positive relative displacement is illustrated in the following figure:
Short Jump Instruction 1001C
Jmp Target
CS = 1000 H ; IP = 0002 H (Address following the JMP instruction) Displacement = 1A H = 0001 1010 Sign Extend = 001A H New IP = 0002 + 001A = 001C H Branch to 1000:001C
10002 10001 10000
MANOJKUMAR S.B
1A EB
(+ve displacement; Forward Jump)
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Microprocessor- 8086
A similar situation but with a negative relative displacement is illustrated in the following figure:
Short Jump Instruction 10012 10011 10010
10005 10004 10003
•
F2 EB
CS = 1000 H ; IP = 0012 H (Address following the JMP instruction) Displacement = F2 H = 1111 0010 Sign Extend = FFF2 H New IP = 0012 + FFF2 = 0004 H (ignoring the carry out) Branch to 1000:0004
Jmp Target
(-ve displacement; Backward Jump)
In a typical Assembly Language Program, we use labels for branch targets and the Assembler will automatically compute the displacement.
•
We can force Short Jump to be assembled using the SHORT directive.
•
Anyway, most Assemblers choose the short form if possible (that is, if the displacement is in the range of -128 to +127)
•
A program illustrating the Short Jump instruction is shown below: XOR BX, BX ST1: MOV AX, 1 ADD AX, BX JMP SHORT NXT5 ; assume that the forward displacement 1A H is true.
•
Interpreted as Signed integers using 2’s Complement system, 0FE H = -2 in Decimal and 1A H = 170 Decimal. Thus 0FE H > 1A H is false!
•
Thus, we have one set of conditional jump instructions that are to be used if the numbers are to be interpreted as
Unsigned Integers and another set of conditional jump
instructions that are to be used if the numbers are to be interpreted as Signed Integers. •
After comparison of Unsigned integers:
Mnemonic
Condition
JA
Z=0 and C=0
Jump if above
JAE
C=0
Jump if above or equal
JB
C=1
Jump if below
JBE
Z=1 or C=1
Jump if below or equal
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Operation
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•
Microprocessor- 8086
After comparison of Signed integers:
Mnemonic
Condition
Operation
JG
Z=0 and S=O
Jump if greater than
JGE
S=O
Jump if greater or equal
JL
S< >O
Jump if less than
JLE
Z=1 or S< >O
Jump if less or equal
(Both S and O Flags are required to test the condition when comparing signed numbers!) •
After comparison of Signed or Unsigned integers:
Mnemonic
Condition
Operation
JE or JZ
Z=1
Jump if equal or Jump if Zero
JNE or JNZ
Z=0
Jump if not equal or Jump if not Zero
•
Alternative, less often used mnemonics also exist.
JA same as JNBE JG same as JNLE JAE same as JNB JGE same as JNL JB same as JNAE JL same as JNGE JBE same as JNA JLE same as JNG •
Other Conditional Jump Instructions:
Mnemonic
Condition
Operation
JC
C=1
Jump if carry set
JNC
C=0
Jump if no carry
JO
O=1
Jump if overflow
JNO
O=0
Jump if no overflow
JS
S=1
Jump if sign is set
JNS
S=0
Jump if no sign
•
Some more Conditional Jump Instructions:
Mnemonic JP or JPE MANOJKUMAR S.B
Condition P=1
Operation Jump if parity set or Jump if parity is even Page 43
JNP or JPO
P=0
JCXZ
CX = 0
Microprocessor- 8086
Jump if no parity or Jump if parity is odd Jump if CX = 0
(Note that the last instruction, JCXZ is some what different from the rest in the sense that it tests the contents of CX register rather than flags. This instruction, generally used in loops, is illustrated in later sessions. Programs illustrating other conditional jump instructions are also discussed in later sessions.) LOOP Instruction: •
Program loops are quite common. Most of the counting loops have a typical structure that is shown below: MOV CX, 10H ; Initialize the count that determines the number of ; times the loop is to be executed. Start1: Instructions constituting the loop body DEC CX
; Decrement counter
JNZ Start1 ; Repeat if not over
If the pair of instructions that test whether the loop body is to be executed again or not, that is the instructions, DEC CX and JNZ Start1, could be combined in to one instruction, we would get more elegant and clearer program.
The LOOP instruction does so combine the above pair of instructions.
Thus the single instruction: LOOP LAB1 is equivalent in effect to the two instructions: DEC CX JNZ LAB1
Conditional LOOP Instructions: •
These instructions are similar to LOOP instruction except that equality (Z flag) is also tested. This allows a loop to be controlled by a count as well as a comparison test (like in the case of String instructions).
•
There are two such instructions.
•
LOOPE (Loop While Equal) or LOOPZ Exit the loop if the condition is not equal or if CX decrements to 0.
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•
Microprocessor- 8086
LOOPNE (Loop While Not Equal) or LOOPNZ
Exit the loop if the condition is equal or if CX decrements to 0. ESC Instruction •
This instruction is related to 8087 Numeric Data Coprocessor. Details of 8087 are discussed in later sessions. Briefly, 8087 provides support for floating point operations and works as a coprocessor to 8086. It
•
–
Shares Pin bus with 8086.
–
Implements floating point arithmetic
–
and Has its own instruction set
The program has instructions for 8086 as well as 8087. How does 8087 know the instruction is for itself? The solution to this problem is the ESC instruction.
•
ESC indicates that it is 8087 instruction. Opcode has 11011 as the higher-order 5 bits. Thus ESC is never used by itself.
•
Generated by Assembler automatically when 8087 mnemonic is used! Consequently, ESC is never coded directly by the programmer. WAIT Instruction
•
Monitors the TEST/ pin of 8086.
•
At the time of executing this instruction, if TEST/ pin is LOW , there is no effect; execution simply continues with the next instruction. However, if TEST/ is HIGH , then 8086 waits in an “idle” state until TEST/ returns to LOW.
•
TEST/ is sampled during leading edge of CLK in each clock cycle during “waiting”.
•
This instruction is generally used in conjunction with 8087.
•
8086 and 8087 can execute in parallel (concurrently)
•
WAIT instruction allows synchronization between the concurrently executing 8086 and 8087.
•
When 8086 needs the “result” from 8087, it executes the WAIT instruction.
•
TEST/ pin of 8086 is connected to the BUSY pin of 8087.
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•
Microprocessor- 8086
When 8087 is busy executing its instruction, it sets its BUSY pin = HIGH. Thus TEST/ of 8086 will also be HIGH. This forces 8086 to “wait” for the completion of 8087 activity.
•
When 8087 is not executing its instruction, its BUSY pin = LOW and thus the TEST/ of 8086 will also be LOW. This allows 8086 to continue its execution.
•
In this manner, synchronization between 8086 and 8087 is achieved.
•
More on this topic in the session on 8087. NOP Instruction
•
As the name implies, it is a no operation instruction!
•
Takes a short time to execute; otherwise no effect.
•
Used in early days to provide for manual code patches. Some NOP instructions would be written every 100 bytes or so. When code was to be patched, the space occupied by the NOP instructions was used. However, this is irrelevant in modern times because the program development usually is based on Assemblers nad manual coding is no more common.
•
Another use for this instruction is that it could be used for producing short time delays if delay accuracy is not of concern. HLT Instruction
•
As the name implies, it “halts” the program; the processor enters the “HALT” state.
•
An interrupt or a hardware reset will force the 8086 out of the “HALT” state.
•
May be used when the program has to wait for an interrupt to occur; but rarely used so in practice.
•
In the early days, this instruction was used in the trainer kits as the last instruction of a user program. It is no more used in this fashion. In fact, presently it is rarely used for any other purpose either!
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Microprocessor- 8086 LOCK Prefix
•
LOCK can be prefix of an instruction.
•
When such an instruction is executed, the LOCK/ pin of 8086 is activated (forced LOW). Now, another bus master can not gain control of the bus until the end of the “bus lock”. Thus the Lock prefixed instruction executes as an indivisible instruction even if it has several memory cycles. (Without the LOCK prefix, the bus could be taken over by another bus master after a memory cycle, even if the current instruction is not completed!)
•
This feature is useful for implementing indivisible “read – modify-write” kind of operations that are necessary in multi-processor systems.
•
Example: LOCK: XCHG AL, SEM1 The instruction is executed without the possibility of another bus master intervening. Instruction shown above can be used in implementing semaphores in a multiprocessor system.
Shift instructions They manipulate binary numbers Used to control I/O Devices. Shift operation moves the number either to left or right within memory location or a register. There are four instructions.There are two types of shift (1) arithmetic and (2) logical. The shift left operation is equivalent to multiply operation and shift right is divide operation. The data is shifted to left or right only by one position. Shift left operation Logical left: The contents of the register or memory location are shifted left by one position the MSB bit moves to Carry flag bit and a zero is added to the LSB position Example SHL AX,1 AX=0000 1111 0000 1111 and Carry=1 After the execution of the instruction AX=0001 1110 0001 1110 and Carry =0 Example MOV CL,3 SHL DX,CL The contents of the DX register are shifted left by three postions Arithmetical Left: It is same as logical left shift. MANOJKUMAR S.B
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Microprocessor- 8086
Logical right: The contents of the register or memory location are shifted right by one position the LSB bit moves to Carry flag bit and a zero is added to the MSB position Example SHR AX,1 AX=0000 1111 0000 1111 and Carry=0 Result AX=0000 0111 1000 0111 and carry=1 Arithmetic right: The contents of the register or memory location are shifted right by one position the LSB bit moves to Carry flag bit and the sign bit is copied through the MSB position Example SAL AX,1 AX=1000 0000 0000 1111 and carry=0 Result AX=1100 0000 0000 0111 and carry=1 Example SAR SI,3 SI= 1010 1100 1010 0101 C=0 After first shift SI= 1101 0110 0101 0010 C=1 second shift SI=1110 1011 0010 1001 C=0 third shift SI= 1111 0101 1001 0100 C=1 All condition flags are affected Rotation instructions There are four rotate instructions. Rotate left: The contents of the memory location or the register are rotated left by the no of positions indicated in the instruction through the carry or without the carry. ROL BL,4 Let BL=0001 0110 C=0 After first rotate After second rotate After third rotate After fourth rotate
MANOJKUMAR S.B
C= 0 C=0 C=0 C=1
BL= 0010 1100 BL= 0101 1000 BL= 1011 0000 BL= 0110 0000
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Microprocessor- 8086
Rotate right
The contents of the memory location or the register are rotated right by the no of positions indicated in the instruction through the carry or without the carry. Assembly Language programming
Assembler: is a program that accepts an assembly language program as input and converts it into an object module and prepares for loading the program into memory for execution. Loader (linker) further converts the object module prepared by the assembler into executable form, by linking it with other object modules and library modules. The final executable map of the assembly language program is prepared by the loader at the time of loading into the primary memory for actual execution. The assembler prepares the relocation and linkages information (subroutine, ISR) for loader. The operating system that actually has the control of the memory, which is to be allotted to the program for execution, passes the memory address at which the program is to be loaded for execution and the map of the available memory to the loader. Based on this information and the information generated by the assembler, the loader generates an executable map of the program and further physically loads it into the memory and transfers control to for execution. Thus the basic task of an assembler is to generate the object module and prepare the loading and linking information.
Procedure for assembling a program
Assembling a program proceeds statement by statement sequentially. The first phase of assembling is to analyze the program to be converted. This phase is called Pass1 defines and records the symbols, pseudo operands and directives. It also analyses the segments used by the program types and labels and their memory requirements. The second phase looks for the addresses and data assigned to the labels. It also finds out codes of the instructions from the instruction machine, code database and the program data. It processes the pseudo operands and directives. It is the task of the assembler designer to select the suitable strings for using them as directives, pseudo operands or reserved words and decides syntax.
Directives
Also called as pseudo operations that control the assembly process. They indicate how an operand or section of a program to be processed by the assembler. They generate and store information in the memory.
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Microprocessor- 8086
Assembler Memory models
Each model defines the way that a program is stored in the memory system. Tiny: data fits into one segment written in .COM format Small: has two segments data and memory. There are several other models too.
Directive for string data in a memory segment DB DW DD DQ Example
define byte define word define double word define 10 bytes Data1 DB Data2 DW
10H,11H,12H 1234H
SEGMENT: statement to indicate the start of the program and its symbolic name. Example Name SEGMENT Variable_name DB ……. Variable_name DW ……. Name ENDS Data Data
SEGMENT Data1 Data2 ENDS
DB DW
……. …….
Code SEGMENT START: MOV AX,BX … … … Code ENDS Similarly the stack segment is also declared.
For small models
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.DATA … … ENDS The ENDS directive indicates the end of the segment. Page 50
Microprocessor- 8086
Memory is reserved for use in the future by using a ? as an operand for DB DW or DD directive. The assembler sets aside a location and does not initialize it to any specific value (usually stores a zero). The DUP (duplicate) directive creates an array and stores a zero. Example Data1 DB 5 DUP(?) This reserves 5 bytes of memory for a array data1 and initializes each location with 05H
ALIGN: memory array is stored in word boundaries. Example ALIGN 2 means storing from an even address Address 0 Address 1 Address 2
XX YY XX
The data XX is aligned to the even address. ASSUME, EQU, ORG ASSUME tells the assembler what names have been chosen for Code, Data Extra and Stack segments. Informs the assembler that the register CS is to be initialized with the address allotted by the loader to the label CODE and DS is similarly initialized with the address of label DATA. Example ASSUME CS: Name of code segment ASSUME DS: Name of the data segment ASSUME CS: Code1, DS: Data1
EQU: Equates a numeric, ASCII(American Standard Code for Information Interchange) or label to another label. Example Data SEGMENT Num1 EQU 50H Num2 EQU 66H Data ENDS Numeric value 50H and 66H are assigned to Num1 and Num2
ORG: Changes the starting offset address of the data in the data segment Example ORG 100H 100 data1 DB 10H it can be used for code too. PROC & ENDP: indicate the start and end of the procedure. They require a label to indicate the name of the procedure. NEAR: the procedure resides in the same code segment. (Local)
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Microprocessor- 8086
FAR: resides at any location in the memory. Example Add PROC NEAR ADD AX,BX MOV CX,AX RET Add ENDP
PROC directive stores the contents of the register in the stack. EXTRN, PUBLIC informs the assembler that the names of procedures and labels declared after this directive have been already defined in some other assembly language modules. Example If you want to call a Factorial procedure of Module1 from Module2 it must be declared as PUBLIC in Module1. Example A sample for full segment definition Data
Data
Example
SEGMENT Num1 DB 10H Num2 DB 20H Num3 EQU 30H ENDS
ASSUME CS:Code,DS:Data Code SEGMENT START: MOV AX,Data MOV DS,AX MOV AX,Num1 MOV CX,Num2 ADD AX,CX Code ENDS A sample for small model . MODEL SMALL .Data
.Code
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Num1 DB 10H Num2 DB 20H Num3 EQU 30H HERE: MOV MOV MOV MOV ADD
AX,@Data DS,AX AX,Num1 CX,Num2 AX,CX Page 52
Microprocessor- 8086
UNIT - 3 BYTE AND STRING MANIPULATION String instructions REP it is a prefix used with instruction REPE/REPZ REPNE/REPNZ These are used with CMPS and SCAS instructions These instructions are used in the program as prefix. CMPS Compare string byte or string word Only Flags affected Zero flag set if strings match otherwise reset DS:SI and ES:DI are used to point to the two strings SCAS Scans the string of bytes or words for an operand byte or word specified in register AL or AX When match found the ZF=1 otherwise it is reset LODS Load string byte or string word Loads the AL/AX register by the contents of a string pointed by DS:SI No flag affected STOS Stores contents of AL/AX register to a location in a string pointed by ES:DI No flag affected Strings and String Handling Instructions : The 8086 microprocessor is equipped with special instructions to handle string operations. By string we mean a series of data words or bytes that reside in consecutive memory locations. The string instructions of the 8086 permit a programmer to implement operations such as to move data from one block of memory to a block elsewhere in memory. A second type of operation that is easily performed is to scan a string and data elements stored in memory looking for a specific value. Other examples are to compare the elements and two strings together in order to determine whether they are the same or different. Move String : MOV SB, MOV SW: An element of the string specified by the source index (SI) register with respect to the current data segment (DS) register is moved to the location specified by the destination index (DI) register with respect to the current extra segment (ES) register. The move can be performed on a byte (MOV SB) or a word (MOV SW) of data. After the move is complete, the contents of both SI & DI are automatically incremented or decremented by 1 for a byte move and by 2 for a word move. Address pointers SI and DI increment or decrement depends on how the direction flag DF is set. MANOJKUMAR S.B
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Microprocessor- 8086
Example : Block move program using the move string instruction MOV AX, DATA SEG ADDR MOV DS, AX MOV ES, AX MOV SI, BLK 1 ADDR MOV DI, BLK 2 ADDR MOV CK, N CDF ; DF=0 NEXT :
MOV SB LOOP NEXT HLT
Load and store strings : (LOD SB/LOD SW and STO SB/STO SW) LOD SB: Loads a byte from a string in memory into AL. The address in SI is used relative to DS to determine the address of the memory location of the string element. (AL) [(DS) + (SI)] (SI) (SI) + 1 LOD SW : The word string element at the physical address derived from DS and SI is to be loaded into AX. SI is automatically incremented by 2. (AX) [(DS) + (SI)] (SI) (SI) + 2 STO SB : Stores a byte from AL into a string location in memory. This time the contents of ES and DI are used to form the address of the storage location in memory [(ES) + (DI)] (AL) (DI) (DI) + 1 STO SW : [(ES) + (DI)] (AX) (DI) (DI) + 2 Mnemonic Meaning Move MOV SB String Byte MOV SW
Move String Word
LOD SB / LOD SW
Load String
STOSB/ STOSW
Store String
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Format MOV SB MOV SW LOD SB/ LOD SW STOSB/ STOSW
Operation ((ES)+(DI))((DS)+(SI)) (SI)(SI) 1 (DI) 1 ((ES)+(DI))((DS)+(SI)) ((ES)+(DI)+1)(DS)+(SI)+1) (SI) (SI) 2 (DI) (DI) 2
Flags affected None
None
(AL) or (AX) ((DS)+(SI)) (SI)(SI) 1 or 2
None
((ES)+(DI))(AL) or (AX) (DI) (DI) 71 or 2
None
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Example :
AGAIN : NEXT :
Microprocessor- 8086
Clearing a block of memory with a STOSB operation. MOV AX, 0 MOV DS, AX MOV ES, AX MOV DI, A000 MOV CX, OF CDF STO SB LOOP NE AGAIN
Clear A000 to A00F to 0016 Repeat String : REP The basic string operations must be repeated to process arrays of data. This is done by inserting a repeat prefix before the instruction that is to be repeated. Prefix REP causes the basic string operation to be repeated until the contents of register CX become equal to zero. Each time the instruction is executed, it causes CX to be tested for zero, if CX is found to be nonzero it is decremented by 1 and the basic string operation is repeated. Example : Clearing a block of memory by repeating STOSB MOV AX, 0 MOV ES, AX MOV DI, A000 MOV CX, OF CDF REP STOSB NEXT: The prefixes REPE and REPZ stand for same function. They are meant for use with the CMPS and SCAS instructions. With REPE/REPZ the basic compare or scan operation can be repeated as long as both the contents of CX are not equal to zero and zero flag is 1. REPNE and REPNZ works similarly to REPE/REPZ except that now the operation is repeated as long as CX0 and ZF=0. Comparison or scanning is to be performed as long as the string elements are unequal (ZF=0) and the end of the string is not yet found (CX0). Prefix REP REPE/ REPZ REPNE/REPNZ
MANOJKUMAR S.B
MOVS STOS CMPS SCAS CMPS SCAS
Used with
Meaning Repeat while not end of string CX0 CX0 & ZF=1 CX0 & ZF=0
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Example :
Microprocessor- 8086
CLD ; DF =0 MOV AX, DATA SEGMENT ADDR MOV DS, AX MOV AX, EXTRA SEGMENT ADDR MOV ES, AX MOV CX, 20 MOV SI, OFFSET MASTER MOV DI, OFFSET COPY REP MOVSB
Moves a block of 32 consecutive bytes from the block of memory locations starting at offset address MASTER with respect to the current data segment (DS) to a block of locations starting at offset address copy with respect to the current extra segment (ES). Auto Indexing for String Instructions : SI & DI addresses are either automatically incremented or decremented based on the setting of the direction flag DF. When CLD (Clear Direction Flag) is executed DF=0 permits auto increment by 1. When STD (Set Direction Flag) is executed DF=1 permits auto decrement by 1. Mnemonic CLD STD
Meaning Clear DF Set DF
Format CLD STD
Operation (DF) 0 (DF) 1
Flags affected DF DF
1. LDS Instruction: LDS register, memory (Loads register and DS with words from memory) This instruction copies a word from two memory locations into the register specified in the instruction. It then copies a word from the next two memory locations into the DS register. LDS is useful for pointing SI and DS at the start of the string before using one of the string instructions. LDS affects no flags. Example 1 :LDS BX [1234] Copy contents of memory at displacement 1234 in DS to BL. Contents of 1235H to BH. Copy contents at displacement of 1236H and 1237H is DS to DS register. Example 2 : LDS, SI String – Pointer (SI) [String Pointer] (DS) [String Pointer +2] DS, SI now points at start and desired string 2.
LEA Instruction : Load Effective Address (LEA register, source) This instruction determines the offset of the variable or memory location named as the source and puts this offset in the indicated 16 bit register. LEA will not affect the flags. Examples : MANOJKUMAR S.B
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LEA BX, PRICES ;Load BX with offset and PRICES in DS LEA BP, SS : STACK TOP ;Load BP with offset of stack-top in SS LEA CX, [BX] [DI] ;Loads CX with EA : (BX) + (DI) 3.
LES instruction : LES register, memory Example 1: LES BX, [789A H] (BX) [789A] in DS (ES) [789C] in DS Example 2 : LES DI, [BX] (DI) [BX] in DS (ES) [BX+2] in DS Modular Programming Concepts: •
Modular Programming is essential for conquering complexity inherent in the development of large, industry-strength software systems.
•
The basic idea is the classical “Divide & Conquer” approach. Program is composed from several smaller modules. Modules could be developed by separate teams concurrently. The modules are only assembled producing .OBJ modules (Object modules). Each module is produced from a separate Assembly Language program.
•
The .OBJ modules so produced are combined using a LINK program.
•
The ML command of MASM typically used for smaller programs actually consists of the two distinct steps of assembling to produce the object file and then Linking the object module to produce the .EXE file.
•
Here, the two steps are separated.
•
This idea is illustrated in the following figure:
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Microprocessor- 8086
Concepts - 2 ASM File #1
Assembler
ASM File #2
Assembler
.OBJ file .OBJ file
Linker ASM File #n
Assembler
.EXE
.OBJ file
A further concept that is extremely useful is that of a Library of Object Modules. Frequently used procedures could be assembled in to object modules and these object modules are placed in a Library file that is linked into the application. Note that only the required object modules are pulled from the Library to be linked in to the final application. The concept of a Library is explored in detail later. This idea is illustrated in the following figure:
Concepts - 3 ASM File
Assembler
ASM File
Assembler
.OBJ file .OBJ file
Linker
.EXE
Library of Assembled Modules (.OBJ files)
Assembler Features Required to Support Modular Programming: To appreciate the features required to support Modular Programming, consider the following development scenario: MANOJKUMAR S.B
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•
Microprocessor- 8086
In Module A , we defined
BUF1 DB 10 DUP (?) •
In Module B , we wish to access BUF1, say as in MOV DX, OFFSET BUF1
•
BUF1 is not defined in Module B. Thus, when assembling Module B, we will get the assembly error of “Undefined Symbol”. Note that the symbol is actually defined in Module A. But, the two modules are assembled independently!
•
Problem: How to make the BUF1, defined in Module A, accessible to Module B?
•
Solution: •
Declare BUF1 as public in Module A (Interpretation: Defined in this module, may be used in other modules.)
•
Declare BUF1 as external in Module B (Interpretation: Used in this module, but defined in some other module.)
BUF1 becomes a global symbol.
Its use is resolved by a Linker program.
What happens if BUF1 is declared as external in one module; but Linker does not find its definition in any of the modules being linked together? This will be a Link Error, something like: “Globally Unresolved Symbol”
•
Properly used, Public and External facilities allow modules to communicate with each other, which is essential for Modular Programming.
PUBLIC and EXTRN Directives: The following example illustrates the use of Public and External directives to achieve communication among independently assembled modules. PROG1.ASM, defines two symbols BUF1 and BUF2 and declares them as PUBLIC. It also defines a Far Procedure called RDKEY and declares this also as PUBLIC. Such a declaration allows these symbols to be accessed from other modules. Thus, BUF1, BUF2 and RDKEY can be accessed from other modules. File 1: PROG1.ASM .MODEL SMALL .DATA MANOJKUMAR S.B
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PUBLIC
Microprocessor- 8086 BUF1
PUBLIC
BUF2
BUF1 DB
10 DUP (?)
BUF2 DW
10 DUP (?)
.CODE .STARTUP PUBLIC RDKEY PROC
RDKEY FAR
MOV AH, 1 INT 21H RDKEY
ENDP END
In another program PROG2.ASM, we make use of the symbols BUF1, BUF2 and RDKEY. We declare them as EXTRN. Such a declaration indicates that the definitions for these symbols are not in this module; how ever this is not to be treated as an error. These symbols are expected to be defined in other modules which will be specified during LINK time. Further, note that the type of the EXTRN data items must be declared for proper assembly. Similarly, the FAR / NEAR nature of an EXTRN procedure also must be declared for the Assembler to generate correct code. File 2: PROG2.ASM .MODEL
SMALL
.DATA EXTRN
BUF1:BYTE
EXTRN
BUF2:WORD
.CODE EXTRN
RDKEY:FAR
.STARTUP MOV DX, OFFSET BUF1 MOV CX, 10 L1:
CALL RDKEY STOSB
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LOOP L1
Microprocessor- 8086
MOV BUF2, AX .EXIT END •
We now have 2 Files: PROG1.ASM and PROG2.ASM
•
These can be assembled and Linked by the following command ML PROG1.ASM PROG2.ASM
•
Another way that more clearly illustrates the Modular Programming approach is as follows :
Only assemble (not link) the two programs separately, getting the two .OBJ files.
Run LINK utility and specify the two .OBJ files as inputs.
Experiment in the Laboratory.
LIBRARIES: •
Frequently used procedures for a given application domain may be placed in a “Library File” as .OBJ files.
•
The Library file can be specified at LINK time.
•
Only the required .OBJ files are extracted from the Library File and linked in to the program.
•
Thus, Libraries provide a powerful reuse mechanism.
LIB Command: The LIB command provides the following facilities: •
Create a new Library file
•
Add .OBJ file to a Library file.
•
Delete .OBJ file from a Library file.
•
Replace an existing .OBJ file in the Library with another .OBJ file with the same name (equivalent to Delete followed by Add)
•
The LIB command is used as follows: LIB library file name
If the named Library file does not exist, the system prompts whether to create? Type Y
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Microprocessor- 8086
It prompts for operation (operation could be specified on command line also). The Operation can be:
+ (add) ; - (remove) ; -+ (replace)
Examples Create a Library file called MYIO1.LIB and add the module PROG1 to the library: >LIB MYIO1.LIB Copyright messages etc from the utility Library file does not exist. Create? Y Operations: +PROG1 List File: MYIO1 To the Library file called MYIO1.LIB add the module PROG2: > LIB MYIO1.LIB Copyright messages etc from the utility Operations: +PROG2 > To the Library file called MYIO1.LIB add the module PROG3: >LIB MYIO1.LIB Copyright messages etc from the utility Operations: +PROG3 >
Alternatively, the 3 modules could be added to the Library file as shown below: >LIB MYIO1.LIB Copyright messages etc from the utility Library file does not exist. Create? Y Operations: PROG1 + PROG2 + PROG3 List File: MYIO1 > From the Library file called MYIO1.LIB, remove the module PROG2: > LIB MYIO1.LIB Copyright messages etc from the utility Operations: -PROG2 MANOJKUMAR S.B
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> •
•
Microprocessor- 8086
List file shows:
Sizes and names of the files in the Library
Public labels available in the Library
Once we create Library files, we can use them to link the required modules in to the application program by specifying the Library files to the Linker. With ML or with LINK, specify the Library files required in response to the prompt Libraries [.lib]:
•
Library files have .lib as the default extension. Procedures
•
Procedure or a subroutine or a function is a key concept for modular programming, the essential way to conquer complexity. It is an application of the general divide-andconquer strategy. This idea is used in high-level language programs as well as in assembly language programs.
•
A procedure is a reusable set of instructions that has a name.
•
Only one copy of the procedure is stored in the memory; and it can be “called” as many times as needed.
•
As only one copy is stored, it saves memory; but has execution time overhead for the “call” and “return” operations.
•
Macros to be studied later are faster but consume more space.
•
“CALL” transfers control to the procedure like with a jump; but unlike a jump, procedure has a “RETURN” instruction which returns control to the instruction following the CALL instruction! In order to implement such a return, the necessary information is stored on a stack, before transferring control to the procedure.
•
Further, nested procedures calls are possible. In other words, Procedure A can call Procedure B which in turn calls Procedure C. After completing Procedure C, control returns to Procedure B and after completing Procedure B, control returns to Procedure A. Logically, such a nesting of calls can be to any level, though in practice Assemblers impose implementation-dependent limits on the nesting depth.
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•
Microprocessor- 8086
It is also possible for a Procedure to call itself (a recursive procedure). Of course, to avoid infinite regress, the procedure would have an alternative that would not involve recursion. Examples of recursive procedures are described in later sessions.
•
These ideas are illustrated in the following figures:
Procedure JMP
CALL
RETURN
Nesting of Procedures CALL
CALL
CALL
RETURN
RETURN RETURN
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•
Microprocessor- 8086
From the above figure we see that return addresses are known in one order and are used for implementing “return” in exactly the reverse order. Thus a Stack would be the most convenient data structure for storing return addresses
Coding Procedure and Procedure - Related Instructions: •
Call can be to a procedure in the same code segment. In such a case, we specify only IP as relative distance or indirectly as actual value. This is known as NEAR CALL.
•
Call can be to a procedure in a different code segment. I such a case, we need to specify both IP and CS (directly or indirectly). This is known as a FAR CALL
•
In ALP, procedure starts with PROC directive and ends with ENDP directive.
•
Each directive appears with the name of the procedure.
•
PROC directive is followed by the type of procedure: NEAR or FAR.
•
NEAR or FAR can be followed by USES statement.
•
USES statement allows specification of registers which are automatically pushed on to the stack and popped from the stack within the procedure.
Near CALL Instruction: •
Similar to Near Jump except that current IP is saved on the stack before transferring control to the new IP with CS remaining the same.
•
Displacement is specified as 16 – Bit signed integer. Target range is thus -32768 to +32767 and consequently, target can be any where in the current code segment
•
This Instruction is 3 – Byte long and the format is as shown below:
opcode E8
Displacement Low Byte
High Byte
The operation of this instruction is illustrated in the following figure:
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Microprocessor- 8086
Near CALL Instruction 1201D Near Procedure
10003 10002 10001 10000
CS = 1000 H ; IP = 0003 H (Address following the CALL instruction) Displacement = 201A H New IP = 0003 + 201A = 201D H Push current IP (0003) on to stack & Branch to 1000:201D
20 1A E9
The saving of the return address is illustrated in the following figure:
Near CALL Instruction: Saving Return Address AFFFF AFFFE AFFFD
00 03
Saving IP: Before CALL: SS = A000 H ; SP = A000 H IP = 0003
10006 10005 10004
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Microprocessor- 8086
In ALP, NEAR indicates near procedure. The following program fragment illustrates the coding and using of a near procedure: ST1
PROC NEAR USES BX MOV AX, 1 ADD AX, BX RET
ST1
ENDP …
…
…
CALL ST1 FAR CALL Instruction: •
FAR CALL is like FAR JMP in the sense that it can call a procedure available any where in the code space.
•
In this case, the target address is directly specified as new CS:IP.
•
Both current IP and CS are saved on the stack and then control is transferred to the new CS:IP
•
The instruction is 5 – Byte long. The first byte specifies the opcode, the next two bytes specify the new IP value and the next two bytes specify the new CS value. The format is shown below:
opcode E8
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IP Low Byte
CS High Byte
Low Byte
High Byte
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Microprocessor- 8086
The operation of the Far Call instruction is illustrated in the following figure:
FAR CALL Instruction 20014 20013 20012
10 00 00
Before Far CALL: CS = 2000 H ; IP = 0015 H (Address following the CALL instruction)
20011 20010
04 9A
After the Far CALL: New CS:IP = 1000:0004 H
10005 10004 10003
•
Save IP & CS on stack and Branch to 10004 H
Far Procedure
Example: SUM1 PROC FAR …
…
…
…
…
…
SUM1 ENDP Now, a CALL to SUM1 is assembled as FAR CALL. CALL with Register Operands: •
As with JMP, 16-Bit register may be used as the operand for the CALL instruction. (Indirect CALL)
•
Again, as with JMP, contents of the register are transferred directly into IP (no concept of relative displacement).
•
This is always a Near CALL.
•
Example: Assume BX = 0080H. Now the execution of the instruction: CALL BX calls the procedure at 0080H in the current code segment (Near Call).
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Indirect CALL Using Index: •
Microprocessor- 8086
Like the corresponding JMP instruction, this instruction uses [] form of addressing to directly access a table of CALL addresses.
•
FAR PTR directive indicates a far CALL ( the table is assumed to contain double words giving CS, IP values)
•
Otherwise a near CALL is indicated. ( the table is assumed to contain words giving IP values)
•
This form is called Indirect Memory CALL also.
•
Example: CALL TABLE[SI] Fetch the word, using indexed addressing, at the offset of TABLE[SI] from the current code segment and CALL the near procedure at that address.
•
Example: CALL FAR PTR [SI] Fetch the double word, using indexed addressing, at the offset of [SI] from the current code segment and CALL the far procedure at that address.
Return from Procedure: •
We use a RET instruction to “return” from the called procedure.
•
The control returns to the instruction following the CALL instruction in the calling program. Corresponding to the two varieties of CALL instructions (near & far), two forms of RET instructions (near & far) exist.
•
Near RET instruction pops a 16-Bit word from the stack and places it in the IP.
•
Far RET instruction pops two 16-Bit words from the stack and places them in IP & CS.
•
In ALP, RET is written within the procedure, before the ENDP directive and the Assembler will automatically select the proper RET instruction!
•
Another form: RET immediate value Example: RET 6 In this case, after popping return address from the stack, the specified number (in this case, 6) is added to SP, effectively removing some (in this case 3) words from the stack! These words could have been pushed on to stack before calling. This is the scheme followed by compilers. Examples are discussed in later sessions.
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Microprocessor- 8086 Macros
Macros provide several powerful mechanisms useful for the development of generic programs. •
A Macro is a group of instructions with a name.
•
When a macro is invoked, the associated set of instructions is inserted in place in to the source, replacing the macro name. This “macro expansion” is done by a Macro Preprocessor and it happens before assembly. Thus the actual Assembler sees the “expanded” source!
•
We could consider the macro as shorthand for a piece of text; somewhat like a new pseudo-code instruction.
Macros and Procedures:
Macros are similar to procedures in some respects, yet are quite different in many other respects.
Procedure:
Only one copy exists in memory. Thus memory consumed is less.
“Called” when required;
Execution time overhead is present because of the call and return instructions.
Macro:
When a macro is “invoked”, the corresponding text is “inserted” in to the source. Thus multiple copies exist in the memory leading to greater space requirements.
However, there is no execution overhead because there are no additional call and return instructions. The code is in-place.
These concepts are illustrated in the following figure:
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Microprocessor- 8086
CALL
Macro invoked
MACRO
Inserted in place
RETURN
MACRO Definition: A macro has a name. The body of the macro is defined between a pair of directives, MACRO and ENDM. Two macros are defined in the example given below. Examples of Macro Definitions: ; Definition of a Macro named PA2C PA2C
MACRO PUSH AX PUSH BX PUSH CX ENDM
; Another Macro named POPA2C is defined here POPA2C
MACRO POP CX POP BX POP AX ENDM
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Examples of Macro usage:
Microprocessor- 8086
The following examples illustrate the use of macros. We first show the source with macro invocation and then show how the expanded source looks. Program with macro invocations: PA2C MOV CX, DA1 MOV BX, DA2 ADD AX, BX ADD AX, CX MOV DA2, AX POPA2C When the Macro Preprocessor expands the macros in the above source, the expanded source looks as shown below: PUSH AX PUSH BX PUSH CX MOV CX, DA1 MOV BX, DA2 ADD AX, BX ADD AX, CX MOV DA2, AX POP CX POP BX POP AX Note how the macro name is replaced by the associated set of instructions. Thus, macro name does not appear in the expanded source code. In other words, the actual Assembler does not “see” the macros. What gets assembled is the expanded source. This process is illustrated in the following figure:
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Microprocessor- 8086
MACROS (continued) Macro Preproc essor
.ASM file with Macros
Assemble & Link
.ASM file with Macros Expanded
.EXE file
MACROS with Parameters: Macros have several other interesting and powerful capabilities. One of these is the definition and use of macros with parameters. A macro can be defined with parameters. These are dummy parameters. When the macro is invoked, we provide the actual parameters. During the macro expansion, the dummy parameters are replaced by the corresponding actual parameters. The association between the dummy and actual parameters is positional. Thus the first actual parameter is associated with the first dummy parameter, the second actual parameter with the second dummy one and so on. This is illustrated in the following example where a Macro named COPY is defined with two parameters called A and B. Example: COPY MACRO
A,B
PUSH AX MOV AX, B MOV A, AX POP
AX
ENDM MANOJKUMAR S.B
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Microprocessor- 8086
The macro is invoked in the following code with actual parameters as VAR1 and VAR2. Thus during the macro expansion, the parameter A is replaced by VAR1 and the parameter B is replaced by VAR2. COPY
VAR1, VAR2
The expanded code is: PUSH AX MOV AX, VAR2 MOV VAR1, AX POP
AX
Local Variables in a Macro: •
Assume that a macro definition includes a label RD1 as in the following example: READ MACRO PUSH RD1: MOV
A DX AH, 06
MOV
DL, 0FFH
INT
21H
JE
RD1
MOV
A, AL
POP
DX
;; No key, try again
ENDM •
If READ macro is invoked more than once, as in READ VAR1 READ VAR2 assembly error results!
•
The problem is that the label RD1 appears in the expansion of READ VAR1 as well as in the expansion of READ VAR2. Hence, the label RD1 appears in both the expansions. In other words, the Assembler sees the label RD1 at two different places and this results in the “Multiple Definition” error!
•
SOLUTION: Define RD1 as a local variable in the macro.
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READ MACRO
Microprocessor- 8086 A
LOCAL
RD1
PUSH
DX
RD1: MOV
AH, 06
MOV
DL, 0FFH
INT
21H
JE
RD1
MOV
A, AL
POP
DX
;; No key, try again
ENDM •
Now, in each invocation of READ, the label RD1 will be replaced, automatically, with a unique label of the form ??xxxx ; where xxxx is a unique number generated by Assembler. This eliminates the problem of multiple definitions in the expanded source.
•
With the use of local variable as illustrated above, READ
VAR1
gets expanded as: PUSH ??0000: MOV
DX AH, 06
MOV
DL, 0FFH
INT
21H
JE
??0000 ;; No key, try again
MOV
VAR1, AL
POP
DX
Subsequently, if we write READ
VAR2
it gets expanded as: PUSH ??0001: MOV
DX AH, 06
MOV
DL, 0FFH
INT
21H
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Microprocessor- 8086
JE
??0001 ;; No key, try again
MOV
VAR2, AL
POP
DX
Note how each invocation of the READ macro gets expanded with a new and unique label, generated automatically by the Assembler, in place of the local variable RD1. Further, note that LOCAL directive must immediately follow the MACRO directive. Another feature to note is that Comments in Macros are preceded by ;; (two semicolons) , and not as usual by ; (a single semicolon). File of Macros: •
We can place all the required Macros in a file of its own and then include the file into the source.
•
Example: Suppose the Macros are placed in D:\MYAPP\MYMAC.MAC In the source file, we write INCLUDE D:\MYAPP\MYMAC.MAC
Advanced Features: •
Conditional Assembly
•
REPEAT , WHILE, and FOR statements in MACROS
Conditional Assembly: •
A set of statements enclosed by IF and ENDIF are assembled if the condition stated with IF is true; otherwise, the statements are not assembled; no code is generated.
•
This is an Assembly time feature; not run-time behavior!
•
Allows development of generic programs. From such a generic program, we can produce specific source programs for specific application contexts.
•
Example: Assume that our generic program has the following statements: IF WIDT WIDE
DB
72
DB
80
ELSE WIDE ENDIF Now the assembly language program that is generated depends on the value of WIDT. Assume the block is preceded by MANOJKUMAR S.B
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Microprocessor- 8086
WIDT EQU 1
Then the assembled code is: WIDE DB
72
It is important to note that the Assembler sees a source file that has only the above statement.
Another case: WIDT EQU 0 IF WIDT WIDE DB 72 ELSE WIDE DB 80 ENDIF
What gets assembled is: WIDE DB
80
There are several other directives that can be used for Conditional Assembly as listed below: IF
If the expression is true
IFB
If the argument is blank
IFNB
If the argument is not blank
IFDEF
If the label has been defined
IFNDEF
If the label has not been defined
IFIDN
If argument 1 equals argument 2
IFDIF
If argument 1 does not equal argument 2
With each of the above constructs, the code that follows gets assembled only if the stated condition is true. REPEAT Statement: This statement allows a block of code to be repeated the specified number of times. This avoids repetitive typing and is much more elegant than Editor-level Copy-and-Paste operation. Example: REPEAT 3 INT 21H MANOJKUMAR S.B
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INC
DL
Microprocessor- 8086
ENDM The generated code would be 3 repetitions of the block of 2 statements enclosed within REPEAT and ENDM as shown below: INT 21H INC DL INT 21H INC DL INT 21H INC DL WHILE Statement: This statement allows a block of code to be repeated while the condition specified with the WHILE is true. Example: Consider the following code SQ LABEL BYTE SEED = 1 RES = SEED * SEED WHILE RES LE 9 DB
RES
SEED = SEED + 1 RES = SEED * SEED ENDM Note that SEED and the arithmetic statements involving SEED and RES are all Assembly time actions. Apart from the initial label SQ, the only statement to actually get repeated is DB RES. The logic is follows: Initially the label SQ is generated. SEED is initialized to 1 and RES is computed as 1 * 1 = 1. Now RES LE 9 is true as the value of RES is 1 which is less than 9. So the code DB 1 is generated. The next statement within the scope of WHILE, “SEED = SEED + 1” is executed making SEED assume the value of 2. The next statement within the scope of WHILE is RES = SEED * SEED. This is also executed and RES assumes the value of 4. This completes one pass of execution of the WHILE block. So, the condition associated MANOJKUMAR S.B
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Microprocessor- 8086
with WHILE is again evaluated. This is again TRUE as 4 is less than 9. So again DB 9 is generated. Reasoning as before, we see that DB 9 is also generated. However, in the next pass SEED is 4 and RES is 16. So the condition RES LE 9 evaluates to FALSE and WHILE loop is exited! Thus the generated code is: SQ
DB
01
DB
04
DB
09
FOR Statement: This is very similar to the FOR of languages like PERL. With the FOR statement, a control variable and a list of values are specified. The control variable is successively assigned values from the specified list and for each such value, the following block of statements is repeated. Example: DISP MACRO CHR:VARARG MOV AH, 2 FOR ARG, MOV DL, ARG INT
21H
ENDM ENDM The outer Macro has one parameter which is specified as sequence of characters of variable length. The inner FOR statement has two enclosed statements which will be repeated for each value in the list . Thus in the following illustration, DISP is invoked with 3 characters as parameters. The two statements within FOR scope are thus repeated 3 times with ARG successively assuming the 3 characters. Thus, the statement DISP ‘S’,’B’,’M’ gets expanded as MOV
AH, 2
MOV
DL,’S’
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Microprocessor- 8086
INT
21H
MOV
DL, ’B’
INT
21H
MOV
DL, ’M’
INT
21H
Summary: •
Modular programming techniques simplify the software development process by exploiting the classical divide and conquer approach.
•
MACROS have very powerful features.
•
Used properly, they can reduce effort required to develop large and complex programs. Further, Macros make it easy to develop Generic Programs which can be easily adapted for specific applications.
•
Expertise with Modular programming techniques and Macros is essential for developing industry-strength large scale software in Assembly Language.
Table translation, Number format conversions Introduction: •
Often Data available in one format needs to be converted in to some other format. Examples:
•
ASCII to Binary
Binary to ASCII
BCD to 7-Segment Code … … …
Data Conversion may be based on
Algorithm
Look –Up Table
Converting from Binary to ASCII: In many contexts, for example, when displaying a number on the screen, we must produce a sequence of ASCII characters representing the number to be displayed. Thus the given number must be converted to a string of equivalent ASCII characters. MANOJKUMAR S.B
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•
Microprocessor- 8086
Example: Binary number: 0100 0011 = 43H = 67 D
To display this on the screen, we need to convert this binary number in to Two ASCII characters, ‘6’ and ‘7’. ASCII code for character ‘6’ is 36H and ASCII code for character ‘7’ is 37H. So, we need to produce 36H and 37H as output given 43H as input. •
Another Example: Binary number: 0000 0010 0100 0011 = 0243H = 579 D To display this on the screen, we need Three ASCII characters, ‘5’, ‘7’ and ‘9’. ASCII code for character ‘5’ is 35H, ASCII code for character ‘7’ is 37H, and ASCII code for character ‘9’ is 39H So, we need to produce 35H, 37H and 39H as output given 0243H as input
Binary to ASCII Algorithm: Example: Binary number: 0000 0010 0100 0011 = 579 D • Divide 579 by 10 ; Quotient = 57 ; Remainder = 9 , Save 9 •
Divide 57 by 10;
Quotient = 5 ; Remainder = 7 , Save 7
•
Divide 5 by 10;
Quotient = 0 ; Remainder = 5 , Save 5
•
Quotient = 0 Conversion Complete.
•
Remainders saved in the order of 9, 7, and 5.
•
Retrieve remainders in the order of 5, 7, and 9. (As the order of retrieval is the reverse of the order of producing these digits, the most convenient technique is to Save & Retrieve the digits using Stack)
•
While retrieving, add 30H to convert the digit to ASCII code and then display it (or print it, or save it…)
•
Thus the algorithm is: While the number is not equal to 0 Divide the number by 10; Push the remainder digit on the stack; Set number
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