Micro Processor 8086

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NOTES ON

8086 MICRO PROCESSOR FOR

ELECTRICAL ENGG. BRANCH, PTU (JALANDHAR).

PREPARED BY: MANISH KUMAR E.E. (2006-2010 BATCH) SUSCET, TANGORI, MOHALI, PUNJAB.

8086 Micro Processor

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COMPARISON OF 8085 AND 8086 PARAMETER Size Address bus Instruction queue Pipelining Multiprocessor support I / Os Coprocessor interface Arithmetic support Check speed External hardware Operating modes Cost Memory segmentation

8085 8 bit MP 16 bits Does not have instruction queue Does not support Does not support

8086 16 bit MP 20 bits It has a 6 byte instruction queue

2^8 = 256 Does not have any

2^16 = 65,536 I/Os It has coprocessor interface

Only supports integer arithmetic Operates on 3 MHz or 5 MHz Requires less external hardware It supports single operating modes Cost is low Memory spaces are not segmented

Supports both integer and real arithmetic Operates on 5 MHz, 8 MHz, 10 MHz or 12 MHz Requires more external hardware

Supports pipelined architecture Supports multiprocessing

Supports two operating modes i.e. minimum and maximum mode Cost is high The memory space is segmented

FEATURES OF INTEL 8086 • • • • • • • • • • • • •

Direct addressing capability of 1 MB of memory because 20 address lines. Can process data in the bit, byte, word or block formats multiplexed address/data bus. Operates on high clock speed. 8 and 16 bit signed and unsigned arithmetic in binary or decimal including multiply and divide operation. Technology used is N channel, depletion load, silicon gate technology (HMOS - 111). Capable of operating in the single processor or multiprocessor configuration. It operates on +5 V supply. Powerful instruction sets. Provides 256 types of vectored interrupts. It generates 16 bit I/O address. So it can access 64 K I/O devices port. Operates in both minimum and maximum mode. It has 6 byte instruction queue. It supports 24 operand addressing modes.

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8086 INTERNAL ARCHITECTURE.

1. Execution Unit (EU): Control circuitry: used for directing the internal operations. Decoder: translates the instructions into a set of actions. ALU i.e. arithmetic & logical unit: for mathematical and logical operation. Flag Registers: It is 16 bit registers each corresponding to a flip – flop. It indicates some condition produced by the execution of an instruction.

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a) Conditional Flags: i) ii) iii) iv) v) vi)

The Carry Flag (CF): set when there is a carry or a borrow. The Parity Flag (PF): set when result has even parity i.e. even numbers of 1’s. Auxiliary Carry (AF): Carry out or borrow out from low nibble to high nibble or high nibble to low nibble respectively; then it is set. The Zero Flag (ZF): Set when the result of the operation is zero. Sign Flag (SF): set when high order bit of the result is 1. Overflow Flag (OF): set when arithmetic overflow occurs.

b) Control Flags i) ii) iii)

Trap Flag (TF): If set then processor is in single step debugging mode. Interrupt Flag (IF): If set, CPU recognizes external and internal interrupt request. Direction Flag (DF): Used for string instructions. a. DF = 1, the string instruction decrements the pointer. b. DF = 0, the string instruction increments the pointer.

General purpose registers: It has eight general purpose registers. It can be used for temporary storage of 8 bit of data. 8 Bit registers are
AH, AL, BH, BL, CH, CL, DH, DL. These 8 bit registers can be combined to form 4 registers of 16 bit each. Thus there are altogether eight 16 bit registers
AX, BX, CX, DX, SI, DI, SP, BP. The combination of eight 8 bit register to form 16 bit register, is as follows: AX: AH & AL > accumulator. BX: BH & BL > base register. CX: CH & CL > count register. DX: DH & DL > data register. i) ii) iii)

Accumulator: It is used in mathematical operations. Stores the result of arithmetic operations and also the operand for calculation. Base register: It is used fro indirect addressing of the memory location where the data is stored. Count register: It is used by string instruction, loop instruction and shift and rotate instruction, to determine the number of times they will be repeated.

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Data register: It is used together with AX for the word – size MUL & DIU operations. It also stores data.

Pointer and Index registers: i) Source Index register (SI): holds the offset of a data word in the data segment. ii) Base Pointer register (BP): holds the 16 bit offset relative to the stack segment register. iii) Destination Index register (DI): holds the 16 bit offset of a data word in the extra segment register. iv) Stack Pointer register (SP): it is a 16 bit register used to hold 16 bit offset relative the stack segment register. 2. The Bus Interfacing Unit: Instruction que: It is based on FIFO principle i.e. first in first out. While decoding and executing an instruction BIU fetches upto 6 instruction bytes for the next instruction and stores it in the Que register. Pipe lining: It is the process of fetching the next instruction when the present instruction is being executed. Advantages:
eliminates the waiting time of EU and speed up the processing.
BIU obtains two instructions byte per fetch. Segment registers: Code segment reg. (CS) Stack segment reg. (SS) Extra segment reg. (ES) Data segment reg. (DS) i) ii) iii)

Code Segment: BIU fetches the instruction code bytes. Stack Segment: Holds the upper 16 bits of the starting address of the stack area. Data Segment & Extra Segment: These are used to point to the segment of the memory, where data is residing.

Instruction Pointer registers: It holds the 16 bit addresses or offset of the next code byte within the code segment.

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MEMORY SEGMENTATION It means segmenting memory into number of bytes. This memory can be thought of as a vast collection of bytes; which are organized in an efficient manner. Advantages of Segmentation: • Provides a powerful memory management mechanism. • Supports modular software design i.e. programs can be partitioned into modules that operate independently of one another. • Implement object oriented programs. • Allows two processes to easily store data. • Allows the use of 16 bit registers. • Possibility of increasing memory size of code, data or stack segments beyond 64 K Byte. • Possibility to separate memory areas for stack, code and data.

ADDRESSING MODES OF 8086

1. Register Addressing mode Data is in the register. Instruction specifies the particular register. 2. Immediate operand Addressing mode Specifies the source operand within the instruction. 3. Memory Addressing mode Specifies the memory. i. Direct memory addressing mode: addresses direct to the memory location where data is stored.

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Register Indirect Addressing mode: address of the memory is taken directly from one of the base register or index register specified by the instruction. Based Addressing mode: physical address is obtained by adding the contents of based register with segment register. Indexed Addressing mode: physical address is generated by adding the contents of index register SI or DI with the segment register. Based Index Addressing mode: EA is sumk of base register and index register, both specified in the instruction.

4. Relative Addressing mode i. Register relative add. Mode: effective addressing is sum of an 8 or 16 bit displacement and the contents of base register or an index register. ii. Relative Based Addressing mode: EA is sum of 8/16 bit displacement to the contents of BX. Segment registers used are DS and SS. iii. Relative Indexed Addressing mode: EA is sum of an 8/16 bit displacement to the contents of index register SI or DI. iv. Relative Based Indexed Addressing mode: generates EA which is the sum of BX, an index register and a displacement. 5. String Addressing mode SI points to the first byte or word of the source string and by default DS is assumed segment register. DI will point to the first byte or word of the destination string and ES is assumed to be by default segment register. 6. I/O Addressing mode i. Memory Mapped I/O: memory operand addressing mode is used to access port. ii. I/O Mapped I/O: supports two addressing modes. a. Direct Port Addressing Mode: allows fixed access to ports numbered 0 - 255. b. Indirect Port Addressing Mode: port number is taken from register DX. 7. Implied Addressing mode All those instructions that do not have operands come under implied addressing mode.

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OPERATING MODE OF 8086 PIN DIAGRAM

Pins common to maximum & minimum mode:  Clock: from external clock generator to synchronize its internal operations.  Multiplexed Address/Data lines (AD0 – AD15)  Read (RD): an active low pin. If low, 8086 reads data from memory and ports.  Reset: fetches next instruction from the physical address FFFFOH  Interrupt inputs: has two interrupts; non maskable interrupts (NMI) and maskable interrupt (INTR). Applying signal to any of them will prevent 8086 from executing the current program and go to execute a program called interrupt service routine (ISR).  Address / Status bus: S3, S4, S5 and S6 holds the status information about the processor.

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 Bus High Enable (BHE)/Status S7: BHE used to enable data onto the most significant half of the data bus i.e. D8 – D15.  Ready: It is an input pin. Useful while working with slower memory or I/O devices. It slows down the MP due to the slow devices.  Test: It is an input pin. If signal is low, execution of WAIT instruction continues.  Mode Selection Input (MN/MX): It is to select minimum or maximum mode for micro processor operation. MINIMUM MODE:

 M/IO (memory / IO output line): access of memory or I/O port  WRITE (WR): an O/P pin. For write operation on memory.  INTA (Interrupt Acknowledge): It is an output pin. Shows the acceptance of the interrupt request.

10  ALE (Address Latch Enable): It is a active high output line. Used to enable address lines.  DT/R (Data Transmit/Recieve): Decides the direction of flow of data.  DEN (Data Enable): Enables the line for data transmit.  HOLD & HLDA: Used for DMA (direct memory access) READ CYCLE:

WRITE CYCLE

11 MAXIMUM MODE

Works with multi processors or CPU’s.  QSO, QS1 (Que status): O/P pins, provides the status of que. Keeps external tracking of the instruction que.  So, S1, S2 (Status lines): provides status information about 8086.  LOCK: indicates to other MP that theyshould not gain the control of the system bus.  RQ/GTo, RQ/GT1 (Request/Grant): provides control to DMA controller.

MP releases the bes and

12 READ CYCLE :

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LOGIC ANALYZER

Only two bus signal lines can be observed at a time. Logic Analyzer allows to make measurements on 16 to 64 signals lines at once. Operations of Logic Analyzer: It detects and displays 1’s and 0’s with the help of COMPARATOR. The reference input of the comparator is set for the logic threshold of the devices in the system being looked at. Logic Analyzer takes a snap shot of the logic levels on the data inputs each time it receives a clock pulse. The samples are stored in an Internal Ram. These samples represents a sequence of address output or data words (which ever stored) by the 8-86. for precise timing with an analyzer, we use a clock signal from an internal, crystal controlled oscillator. A trigger signal tells the analyzer when to stop taking samples and display the samples stored in the RAM. Word recognizer is used to produce a trigger signal. It compares the binary word on the I/P signal lines with a word you set with switches or a keyboard. When the two words match, the word recognizer sends out a trigger signal.

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STEPS TO TROUBLESHOOT A MICRO PROCESSOR 1.

Identify the Symptoms Make the list of symptoms that is find or described the customer. Whether the symptom is present at the moment the power is turned ON or the system operates for a while before the symptoms show up.

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Make a Careful Visual and Tactile Inspection Check whether the system has become hot. Whether IC’s are firmly seated in their sockets. Make inspection for broken wires and bent points.

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Check the Power Supply Check whether the power cable broken in middle or not. Carefully check the socket and plugs and replace for the broken part.

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Do a Signal Roll Call Check for the key signals around the CPU of Micro Computer. Check for the clock signal at right frequency. And check all other signals.

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Systematically Substitute Socketed IC’s Never remove or place any IC with the power ON. Always substitute the IC’s firmly on the sockets or on the board. Look for the broken or bent pins or loose connection.

ASSEMBLER DIRECTIVES Assembly language supports a number of statements that enables to control the way in which a program assembles and lists. These are called Assembler Directives. They set only during the assembly of program and generates no machine executable code. 1. Segment and Ends directive Used to identify a group of data items or a group of instructions that you want to be put together in a particular segment. 2. Assume Directive It tells the assembler which logical segment to use for each of these physical segments; code segment, data segment, stack segment & extra segment; at a given time.

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3. EQU directive It assigns names to be used in a program. 4. DB, DW and DD directive. It assigns name to the variables in a program.
DB directive: after a name specifies that data is of type data.
DW: specifies that data is of type word.
DD: specifies that data is of type double word. 5. DUP directive It can be used to initialize several locations and to assign value to these locations.

DIFFERENCE PROCEDURES

BETWEEN

S.NO. PROCEDURE 1 It resembles a call function of high level language. The processor branches to the procedure on call proc, instruction and returns back to the caller program after executing the procedure. 2 Since the assembler stores the instructions of procedure only once in the memory, the program consumes less space in memory. 3

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MACROS

AND

MACRO When the assembler comes across the instruction “CALL MACRO”, it replaces thic instructions placed in the corresponding macro Since the assembler replaces all “CALL MACRO” instructions in the macro, the program consumes more space in the memory. Since the processor branches to Macro does not require any another memory location and returns latency period. back, it consumes some time to store and fetch back the return address. Hence it has a latency period. Procedures are to be used for repetitive Macros are to be used for task, if the task is very large (i.e. it has repetitive task, if the task is many instruction). small (i.e. it has less number of instruction).

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INSTRUCTION SETS OF 8086
Data Transfer Instructions
Arithmetic Instructions
Bit Manipulation Instructions
Processor Control Instructions
String Instructions
Program Execution Transfer Instructions DATA TRANSFER INSTRUCTIONS: # MOV [ MOV destination, source ] Eg: MOV BX, 592FH It transfers the word or a byte of data from source to a destination. Destination: register or memory location. Source: register, memory location or immediate number. Note: They can’t both be memory locations simultaneously. # PUSH [ PUSH source ] It decrements the stack pointer by two and copies a word from some source to the location in the stack where the SP ( Stack Pointer) points. Eg: PUSH CX PUSH BX PUSH NEXT [BX] # POP [POP destination ] It copies a word from the stack location pointed by the stack pointer to a destination and increment it by two. Eg: POP CX POP BX POP NEXT [BX] # XCHG [ XCHG destination,source] It exchanges the contents of a register with the contents of another register or the contents of a register with the contents of memory location. Eg: XCHG BX,CX XCHG AL, SUM[BX]

17 # XLAT [ Translate Byte in AL] It replaces a byte in AL register with a byte from a look up table in the memory. # IN [ Input a Byte or Word from Port ] It copies data from a port to the accumulator. i. Direct Addressing Mode Execution: 8 bit address of the port is a part of the instruction. ii.

Indirect Addressing Mode Execution Address of the port is referred from DX register.

# OUT [ Output a Byte or Word to a Port ] i.

Direct Addressing Mode: 8 bit address of the port is given in the instruction.

ii.

Indirect Addressing Mode: Referred from the DX register.

ARITHMETIC INSTRUCTIONS: A) Addition Instructions # ADD/DC ( ADC means ADD with carry ) [ ADD destination, source ] [ ADC destination, source ] eg:

ADD AL,0F0H ADC DL, CL

#INC [ Increment Destination ] Adds 1 to the specifies destination. Destination = register or memory location. # AAA [ASCII Adjust for Addition ] # DAA [ Decimal Adjust Accumulator ]

18 BIT MANIPULATION INSTRUCTIONS: # NOT [ NOT destination ] Inverts each bit of a byte or a word. # OR [ OR destination, source ] # AND [ AND destination, source ] # XOR [ XOR destination, source ] # TEST [ TEST destination, source] AND’s the contents of a source byte or word with the contents of the specified destination word. SHIFT INSTRUCTIONS: # SAL/SHL [ SAL/SHL destination, count ] Shifts each bit in the specified destination to the left and 0 is stored at LSB position. # SHR [ SHR destination, count ] Shifts each bit in the specified destination to the right and 0 is stored at MSB. LSB shifted to carry flag. # SAR [ SAR destination, count ] Shifts each bit in the specified destination source number of bits positions to the right. ROTATE INSTRUCTIONS: # ROL [ ROL desination, count ] Rotates all bits in the specified byte or word to the left some number of bit position. # ROR [ ROR destination, count ] Rotates all of the bits ina specified byte or word to the left some number of bit positions.

19 # RCL [ RCL destination, count ] Rotates all of the bits in a specified word or byte some number of bit positions to the left along with the carry flag. # RCR [ RCR destination, count ] With carry flag.

INTERRUPTS IN 8086 Any program in 8086 can be interrupted by some external signal or by a special instruction in the program. When an Interrupt is implied, the Micro Processor stops the execution of its current program and calls the procedure which service the interrupt. An instruction at the end of the interrupt of interrupt service procedure, returns execution to the interrupted program. These interrupts can come from any of these three sources. One source is an EXTERNAL signal applied to the non-maskable interrupt input pin or to the interrupt input pin. This is termed as Hardware Interrupt. The second source is execution of the interrupt instruction, INT; which is referred as software interrupt. The third source of interrupt is some error condition produced in the 8086 by the execution of an instruction; like for example ‘divide by zero’ interrupt. Series of action in response to an interrupt: a) b) c) d) e) f)

It decrements the stack pointer by 2 and pushes the flag register on the stack. I disables the INTR interrupt input by clearing the interrupt flag in the flag register. It resets the trap flag in the register. It decrements stack pointer by 2 and pushes the current code segment register contents on the stack. It decrements stack pointer by 2 and pushes the current current instruction pointer contents on the stack. It does an indirect far jump at the start of the procedure by loading the CS and IP values for the start of the interrupt service routine(ISR).

20 Maskable and Non – Maskable Interrupts: a) Maskable Interrupts: The interrupts which can be masked i.e. disabled are called so. The micro processor can ignore or delay a maskable interrupt if it is performing some critical task and do not want to be interrupted. b) Non – Maskable Interrupts: The interrupts which cannot be disabled or masked are called non maskable interrupts. DIFFERENTIATE NON MASKABLE AND MASKABLE INTERRUPTS S.NO. NON MASKABLE 1 It cannot be masked off or made pending 2 This interrupt does not disable non maskable interrupts. 3 It is used for emergency purpose. 4 Higher priority. 5 Response time is low.

MASKABLE It van be masked off made pending This interrupt disables all the non maskable interrupts. It is used to interface peripherals. Lower priority. Response time is high.

COMPARE HARDWARE AND SOFTWARE INTERRUPT S.NO. SOFTWARE INTERRUPT 1 It is synchronous event. 2 This interrupt is requested by executing instruction. 3 It cannot be ignored or masked. 4 It has the highest priority among all interrupts. 5 It does not affect on interrupt control logic.

HARDWARE INTERRUPT It is an asynchronous event. This interrupt is requested by external device. It can be masked. The priority is lower than that of software interrupt. It affects on interrupt control logic.

21 Types of Interrupts: There are five basic types of interrupts available in 8086 Micro Processor. These are as follows: Type 0. [ Divide by Zero interrupt ] The 8086 is automatically interrupted whenever a division by zero is attempted. It is non – maskable interrupt and is implemented as a part of execution of the divide instruction. Type 1. [ Single Step Interrupt ] When we use a single step features in some monitor programs and debugger programs, micro - processor executes on instruction and stops. During this we can examine the contents of memory locations and registers. The micro - processor then waits for further directions. When trap flag is set by an instruction, the 8086 goes inot the single step mode and will automatically do a type 1 interrupt. Type 2 [ Non – Maskable interrupt ] This interrupt is initiated when NMI pin of 8086 receives a low to high transition. It normally used for catastrophic failures such as apower failure. Whenever there is failure of ac power to the system, it is detected by some external circuitry and an interrupt signal is sent the NMI input of 8086. Type 3. [ Break Point Interrupt] This interrupt is used for break point and is non maskable. The user inserts the one byte instruction INT3 into a program by replacing an instruction. Break points are useful for debugging a program. Type 4. [ Overflow Interrupt ] This interrupt occurs if the overflow flag (OF) is set and the INTO i.e., Interrupt on overflow instruction is executed. INTERRUPT VECTOR TABLE It is a predefined memory area, used for storing address of interrupt service routine. Its address range is from 00000H to 003ffH, which is equivalent to 1024 bytes of memory. Interrupt Vector
A four byte number 256 in numbers and all are different. Its sequence is termed as Interrupt Vector Table. Contains two bytes of segment address (CS) and 2 bytes of offset address (IP)

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General layout of interrupt vector table: Type 0 to 4: Predefined Interrupts. Type 5 to 31: Reserved. Type 32 to 255: User Defined.

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PROGRAMMED DATA TRANSFER SCHEME Programmed data schemes are controlled by the CPU, data are transferred from an I/O device to the CPU (or to the memory through the CPU) or vice – versa under the control of program which are in the memory. These programs are executed by the CPU when when an I/O device is ready to transfer data. It is classified as follows: 1.

Synchronous data transfer scheme Synchronous means at the same time. In this scheme every event (i.e. sending of data and receiving of clock) is performed at a fixed time.it is useful when I/O devices and CPU matches in speed.

2.

Asynchronous data transfer scheme This scheme is used when the CPU and I/O devices do not match in speed. In this scheme the data are not transferred on a predetermined timing pattern. First MP checks the status of the I/O device continuously until I/O device becomes ready to transfer data. This scheme is also called handshaking mode of data transfer.

3.

Interrupt driven data transfer Here the MP initiates an I/O device to get ready, and then instead of remaining in a program loop of to keep on checking its status, it executes its main program. On becoming ready, the I/O device sends a signal to a special input line called an interrupt line (INTR in 8085) to the MP; to which MP responds immediately by halting all its current execution and gets ready to transfer the data.

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DMA data transfer scheme Direct memory Access is an I/O technique commonly used for high speed data transfer. Here, the MP releases the control of the buses to a device called DMA controller. This device manages the data transfer between the memory and the peripheral under the control. It is used to transfer from mass storage devices and for high speed printers. a) Burst mode of DMA data transfer In this scheme, I/O device withdraws the DMA request only after all the data bytes have been transferred. b) Cycle Stealing technique It allows the DMA controller to transfer one word at a time after which it returns control of the buses to the CPU.

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MEMORY AND I/O INTERFACING MEMORY INTERFACING: Generalized block schematic of memory chip

Note : (1) Vpp and PGM pin is only for PROM; not for RAM (2) WR pin is for RAM. 1) Address lines Number of address lines depends upon size of the memory. 2) Data bus Data bus depends upon, data bits of memory. Standard memory data bits available are 1, 4 and 8. 3) CS [ Chip select ] or CE [ Chip enable ] This signal is active LOW. This acts as master enable pin, for read write operation. Unless and until the pin is active, no operation will be performed. 4) WR [ Write Signal ] This signal is active LOW. Whenever we want to write into memory. 5) RD / OE [ Read / Output enable ]

25 This pin is also active LOW. Used whenever we want to read a location from the memory. 6) Vpp [ Programming pin ] Normally available in EPROM. Whenever you want to program EPROM, apply 12.5 / 21V / 25V to this pin. Then and then only, one can program the IC. 7) PGM [ Program ] Whenever we program the chip, PGM = 0. Whenever we verify the operation, PGM = 1. ADDRESS DECODING TECHNIQUES The 8086 Microprocessor provides a 20 bit memory address that allows upto 1 MB of main memory. Out of these several address lines are unused, but these extra lines determine the range of addresses the memory interface occupies. Address decoder circuit, examines these extra address lines and enables the memory for a specific range of addresses. Depending upon number of lines used for decoder, we get: 1. FULL DECODING [ Absolute Decoding ] 2. PARTIAL DECODING [ Linear Decoding ] 3. BLOCK DECODING These are discussed along with comparison as follows: S.NO. FULL DECODING 1 Also referred to as absolute decoding. 2 All address lines are considered. 3 No shadowing or warp around effect. 4 5

PARTIAL DECODING Also referred to as linear decoding. Few address line(s) are ignored. Shadow or wrap around, of interfaced device will be present. More hardware Decoder hardware is required for decoding simple. the number of bits. Flexible size(s) of the Flexible size(s) of the memory(s) may be memory may be interfaced. interfaced.

BLOCK DECODING No alternative name. Normally all address lines are considered. Shadowing or wrap around normally not allowed. Decoder hardware is simple. Fixed BLOCKS of memory is present.

INPUT OUTPUT INTERFACING In microprocessor based system, we accept data from external device through input device and transfer data from microprocessor to external device through output device.

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I/O interfacing techniques: It is of two types: a) I/O mapped I/O For 62K IO addresses of 8086. 8086 offers two ways of addressing the IO. These are as follows:
Direct addressing.
Indirect addressing. b) Memory mapped I/O Here instead of using IOR and IOW, we use MEMR and MEMW. Address line Ao to A19 should be considered for address decoding. IO should be enabled when M/IO = 1.

27 S.NO. I/O MAPPED I/O 1. I/O devices are treated as I/O and memory as memory. 2 Device address is 8/16 bits. 3 Control signals used for I/O are IOR and IOW. 4 Special instructions are available such as IN and OUT. 5 6

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Data transfer is possible between accumulator and I/O only. The total devices which can be connected will be 1 MB memory and maximum 65,535 input, so hardware will be less. Decoding 8/16 bits of address is only required, so hardware will be less. The arithmetic and logical operations are not possible with direct data from I/O device.

MEMORY MAPPED I/O Both the devices i.e. I/O and the memory are treated as memory. Device address is 20 bits. Control signals used for I/O are MEMR and MEMW. All memory related instructions can be used to communicate with IO. Data transfer is possible between any register and I/O. The total devices will be only 1 MB as it is shared between memory and I/O. Decoding of 20 bits of address is required, so hardware will be more. The arithmetic and logical operations can be performed on direct data from I/O device.

Types of I/O Devices: This classification is based on how they are used: 1) Non – Programmable I/O devices: Their operation is controlled through hardware. Their operating mode cannot be changed without modifying hardware. It does not provide control and status registers. 2) Programmable I/O devices: These are software controlled devices whose operating mode can be changed without modifying hardware. It provides control and status registers. Their operating modes are changed by writing appropriate command word into the controller register.