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An Operational Amplifier for a CMOS VLSI Design by Marc Bernier, Consultant Middleboro, MA Recent advances in Very Large Scale Integration (VLSI) technologies have made possible the realization of complete systems on a single chip. Since complete systems often include analog devices as well as digital devices, there has been a reemergence of interest in Metal-Oxide Semiconductor (MOS) analog circuits. Examples of these types of integrated circuits include: Digital-to-Analog Converters, Analog-to-Digital Converters, Voltage-Controlled Oscillators, Analog Input/Output Pads, and amplifiers. All these devices can be based on a simple element in MOS design, the MOSFET transistor. CMOS VLSI Design Complementary Metal-Oxide-Semiconductor (CMOS) technology is circuit implementation using both pMOS and nMOS transistors on the same silicon chip. CMOS designs typically offer high gain and speed at low power consumption. In addition, CMOS scales well to smaller devices without drastic changes in performance. The effect of device dimensions on FET operation becomes clearer in the design calculations below.

Several design parameters affect MOS device performance, including the following: doping (level of semiconducting impurities added) of the substrate, doping of the source, doping of the drain, oxide thickness, channel width, and channel length. In practice, all but two of these parameters are often determined by the manufacturing process and are out of the designer's control. The two remaining parameters are channel width, w, and channel length, L, as shown in the drawing. CMOS design becomes a simple process of connecting together "rectangles" (transistors) of varying dimensions. Typical topography for such a circuit is included at the end of this article.

Additionally, certain device characteristics will not change when the transistor is scaled. Thus, for a preliminary design, a width-to-length ratio, or "aspect ratio" can be used in place of the two dimensions. Performance factors such as current handling, noise, and actual circuit size are affected by a transistor's dimension, so specific transistor size is an important consideration in later design stages. Transistors designed in this way can be arranged into larger devices that can be addressed as a single unit on a chip.

Operational Amplifier Design Using Mathcad One of the most common analog circuit elements is the operational amplifier. It will compare two inputs (V+ an V- in the schematic on the next page) and amplify their difference. This device is commonly used to amplify small signals, to add/subtract voltages, and in active filtering. It must have high gain, low current draw (high

input/output impedance), and should function over a variety of frequencies. This article considers the design of such a device using Mathcad.

The op-amp will meet or exceed the following specifications: 1) open loop gain of at least 1000 2) total current drain < 20 μΑ 3) gain-bandwidth product > 10 6

The "garden-variety" operational amplifier circuit shown at left was used as a basis for this design. The maroon transistors (with circles on the gates) are p-type, and the purple transistors (no circles) are n-type.

Transistor 2 functions as a constant current source, and transistors 1, 3, and 8 function as two current mirror 'pairs'. The network consisting of transistors 4, 5, 6, and 7 is the differential amplifier, and transistor 9 is an output amplifier stage (a very simple one!). Some constants and parameters required for the calculation are listed below. These will be used along with the specifications above to design the size of the transistors required for this circuit.

Specified by overall VLSI circuit requirements: Vdd := 5 ⋅ volt

Supply voltage

Specified by doping levels: Channel length modulation for n-type and p-type devices λ n := 2.752 ⋅ 10

−3

−1

⋅ volt

λ p := 1.427 ⋅ 10

−2

−1

⋅ volt

Intrinsic transconductance for n-type and p-type devices − 5 amp

Kn := 5.518 ⋅ 10

⋅

2

− 5 amp

Kp := 2.226 ⋅ 10

volt

⋅

2

volt

Specified by doping levels and oxide thickness: Threshold voltage for n-type and p-type devices Vtn := .77⋅ volt

Vtp := −.77⋅ volt

The parameters λ, K, and Vt are determined by the manufacturing process. First, transistor 1's aspect ratio is calculated. It will be a function of the required voltage drop across the transistor to make sure it is operating above the threshold voltage, Vt. A minimal gate-to-source voltage of Vtp +Vsafety is used to insure the device would turn on despite any variations in processing. It's important to make the voltage as small as possible, since the output voltage in the circuit should not be clipped by the supply voltage. Since the current consumption is limited to 20 μA, a somewhat arbitrary current of 5 μA is drained through this leg.

μA := 10

−6

⋅ amp

Vsafety := −0.5⋅ volt

Vgs1 := Vtp + Vsafety

Ids1 := 5 ⋅ 10

−6

⋅ amp

The formula for AR 1 is derived from the following formula [1]:

Ids =

1 2

⋅ K⋅ AR⋅ ( Vgs − Vt)

AR1 :=

2 ⋅ Ids1 Kp⋅ ( Vgs1 − Vtp)

AR1 = 1.797

2

Since Vgs1 has been fixed, Vgs2 is also fixed, since they both carry the same current. Transistor 2's aspect ratio can be calculated: Vgs2 := −( Vdd + Vgs1)

AR2 :=

2 ⋅ Ids1 Kp⋅ ( Vgs2 − Vtp)

AR2 = 0.051

2

Vgs2 = −3.73 volt

The difference amplifier can now be designed, starting at the first current mirror (transistors 1 and 3). Like Vgs1 , a minimal Vgs3 is desired for the same reason. The current through transistor 3 is to be half of Ids1 .

Vgs3 := Vgs1

Idsd :=

1 2

⋅ Ids1

AR3 :=

2 ⋅ Idsd Kp⋅ ( Vgs3 − Vtp)

2

AR3 = 0.898

Note that AR3 is exactly half that of AR1 . This is because the following equation applies: AR1 AR3

=

Ids1 Idsd

and Idsd was chosen to be one half of the current in the first leg.

The derivation of this formula isn't shown here, although it is relatively easy. The name 'current mirror' is quite fitting. Now the differential amplifier can be designed.

To obtain a balanced output, transistors 4 and 6 should be matched, as well as transistors 5 and 7. Because of this balancing, the current flowing through transistors 4 and 5 is the same as the current flowing through transistors 5 and 7 (almost no current is drained through the gates of transistors 5 and 7). Like transistor 1, transistor 5's (and 7's) Vgs is to be as small as possible.

2⋅ Vgs5 := Vtn − Vsafety

AR5 :=

Idsd 2

Kn⋅ ( Vgs5 − Vtn)

2

AR5 = 0.181

Some additional parameters must be determined to calculate the high-frequency characteristics. The drain conductance and transconductance parameters are needed for ac small signal analysis.

AR7 := AR5

g d3 := λ p⋅ Idsd

g d3 = 3.567 × 10

g m3 :=

g m3 = 1 × 10

2 ⋅ Idsd⋅ Kp⋅ AR3

g d5 := λ n⋅

Idsd

−5

−8

−9

(drain conductance)

(transconductance)

mho

g d5 = 3.44 × 10

2

mho

mho mho ≡

g m5 :=

2⋅

g d4 := λ p⋅

Idsd

⋅ Kn⋅ AR5

2

g m5 = 5 × 10

Idsd

−6

ohm

mho

g d4 = 1.784 × 10

2

1

−8

mho

Like Vgs1 , Vgs4 should be as small as possible while still turning on the transistor:

2⋅ Vgs4 := Vtp + Vsafety

AR4 :=

Idsd 2

Kp⋅ ( Vgs4 − Vtp)

2

AR4 = 0.449

which allows calculation of gm4 :

g m4 :=

2⋅

Idsd 2

⋅ Kp⋅ AR4

g m4 = 5 × 10

−6

mho

The drain conductances and transconductances that have been calculated enter into the following equation for the gain of the differential amplifier. The derivation of this equation (omitted) is somewhat lengthy. In a nutshell, an ac circuit analysis is performed on the differential amplifier using the appropriate small signal models for the transistors [2]. Some reasonable approximations (such as gm4 + gd4 ≈ gm4 ) were made to greatly simplify the equation. The differential stage gain is given by

Ad :=

1

⋅

g m4

Ad = 117.495

2 g d4 + g d5

This is the gain of the differential amplifier stage. Thus, a gain of 10 or so is needed at the output amplifier stage. Now for the output stage: as with the differential amplifier, the current is set to half of the mirror's Ids : Vgs8 := Vtp + Vsafety

AR8 :=

Ids8 :=

2 ⋅ Ids8 Kp⋅ ( Vgs8 − Vtp)

2

1 2

⋅ Ids1

AR8 = 0.898

g d8 := λ p⋅ Ids8

g d8 = 3.567 × 10

−8

mho

At several points in this design, it was mentioned that certain Vgs 's should be as small as possible. The reason for this is apparent at the output stage: Vout cannot be above Vdd-Vgs8 or below Vgs9 . Vout will be clipped if such a situation does occur. Because Vgs1 =Vgs3 =Vgs8 , these voltages also reflect this consideration. Similarly, Vgs5 and Vgs7 are limited to prevent clipping at the output of the differential amplifier.

Vgs9 := Vtn − Vsafety −9

g d9 := λ n⋅ Ids8

AR9 :=

g d9 = 6.88 × 10

2 ⋅ Ids8 Kn⋅ ( Vgs9 − Vtn)

g m9 :=

2 ⋅ Ids8⋅ Kn⋅ AR9

2

mho

AR9 = 0.362

g m9 = 1 × 10

−5

mho

The equation for the gain of the output stage is shown below:

Ao := −

g m9 g d9 + g d8

Ao = 235

Thus, the total open-loop gain for the amplifier is:

Av := Ad⋅ Ao

Av = 27610

Required gain is > 1000.

It would appear that the amplifier was over-engineered by a factor of 10. The circuit was simulated (with CAzM) and an open-loop gain of 2680 was determined. Two reasons could account for the design/simulation difference. First, to determine the open-loop gain, an ac voltage is applied to the inputs in the simulation. This ac voltage is biased with a dc voltage determined by the simulation's transfer characteristic curve of the circuit (i.e., Vin versus Vout ). The determination of the bias voltage is, at best, an inaccurate procedure. Unfortunately, a small change in the bias voltage greatly affects the open-loop gain, so the optimal open-loop gain may not have been found. Second, the simulation takes into account all sorts of parasitic capacitances not included here, which all affect the gain adversely.

The final part of the design calls for selection of a compensation capacitor, C. The capacitor acts simply as a low pass filter to ensure that the op-amp will be stable. Stability is indicated by the condition where the gain of the circuit vs. frequency crosses unity before the phase crosses 0°. A little trial-and-error with the simulator found a value of .1 pF that fit the requirement rather well.

C := .1⋅ 10 Hz :=

1 sec

− 12

⋅ farad

Rout( s) :=

1 s :=

s⋅ C + g d9 + g d3

3 .10

10

3

2⋅ π

⋅ Hz ,

10

4

2⋅ π

7

⋅ Hz ..

10

2⋅ π

7

⋅ Hz

Use the marker on the graph to help find a guess for the 3 dB point:

sg

2 .10

7

Rout( s ) 1 .10

7

5

sg ≡ 1 ⋅ 10 ⋅ sec 0 100

1 .10

3

1 .10

1 .10

4

1 .10

5

6

−1

1 .10

7

s

The dc output impedance is:

(

Rout 0 ⋅ sec

) = 2.35 × 107 ohm

−1

The -3db point is found by the following root finding equation, using the guess value on the previous page:

(

s3dB := root⎛⎜ Rout( sg) − Rout 0 ⋅ sec

⎝

)⋅ 1

−1

2

, sg⎞⎟

⎠

So the -3db point occurs at the frequency 5

s3dB = 1.763 × 10 sec

−1

Finally, the Gain-Bandwidth product can be determined: 9

GBW := Av⋅ s3dB

GBW = 4.867 × 10 sec

−1

The above information along with the simulation results give the following specifications:

Current drain: Power consumption: Bias Voltage: Open-Loop Gain: Bandwidth: Gain-bandwidth product:

Simulated 10 μamp 50 μwatt 2.5001 volt 2680 2.2 kHz 3 MHz

Calculated 10 mamp 50 mwatt 2.5 volt 27610 1.8 MHz 4.9 GHz

Specified < 20 μΑ < 100 μwatt 2.5 volt >1000 >1 kHz > 1 GHz

On the following page is a schematic of the op-amp layout. Note that transistor 9 has been split in half. Two transistors in parallel with identical lengths, L, and different widths, W1 and W2, are equivalent to one transistor with the same length, L , but with a width of W1+W2 (similar property to parallel capacitors). This property makes design a bit easier, because very wide transistors can be made into two or three not-so-wide transistors which fit more

economically into the circuit topology. The transistors aspect ratios in this layout are not consistent with this design, as this layout is after a design 'evolution' involving a switched-capacitor circuit (so put the ruler away!).

Blue Red Brown Green

Metal Layer PolySilicon Layer p-type Diffusion (source/drain for p-type transistor) n-type Diffusion (source/drain for n-type transistor)

Magenta Purple

A contact between two layers. A capacitor - actually made of layers of PolySilicon and Metal (the "plates"), separated by a layer of oxide (the "dielectric").

Conclusion Hopefully this design example has demonstrated some of the aspects that go into an analog CMOS VLSI design. Although simulators are frequently used to test designs, the actual design is commonly done by hand. Mathcad is an ideal tool for this type of design, as changes in parameters give instantaneous results. As an example, and a place to start your own exploration of this problem, try changing the safety voltage on page 5 and examine its effect on the aspect ratios and the gain of the op-amp.

References 1. Haskard, Malcom R., and May, Ian C. (1988), Analog VLSI Design nMOS and CMOS, Prentice Hall of Australia Pty Ltd, Englewood Cliffs, New Jersey, p.16. 2. Ibid, p. 19.

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Several design parameters affect MOS device performance, including the following: doping (level of semiconducting impurities added) of the substrate, doping of the source, doping of the drain, oxide thickness, channel width, and channel length. In practice, all but two of these parameters are often determined by the manufacturing process and are out of the designer's control. The two remaining parameters are channel width, w, and channel length, L, as shown in the drawing. CMOS design becomes a simple process of connecting together "rectangles" (transistors) of varying dimensions. Typical topography for such a circuit is included at the end of this article.

Additionally, certain device characteristics will not change when the transistor is scaled. Thus, for a preliminary design, a width-to-length ratio, or "aspect ratio" can be used in place of the two dimensions. Performance factors such as current handling, noise, and actual circuit size are affected by a transistor's dimension, so specific transistor size is an important consideration in later design stages. Transistors designed in this way can be arranged into larger devices that can be addressed as a single unit on a chip.

Operational Amplifier Design Using Mathcad One of the most common analog circuit elements is the operational amplifier. It will compare two inputs (V+ an V- in the schematic on the next page) and amplify their difference. This device is commonly used to amplify small signals, to add/subtract voltages, and in active filtering. It must have high gain, low current draw (high

input/output impedance), and should function over a variety of frequencies. This article considers the design of such a device using Mathcad.

The op-amp will meet or exceed the following specifications: 1) open loop gain of at least 1000 2) total current drain < 20 μΑ 3) gain-bandwidth product > 10 6

The "garden-variety" operational amplifier circuit shown at left was used as a basis for this design. The maroon transistors (with circles on the gates) are p-type, and the purple transistors (no circles) are n-type.

Transistor 2 functions as a constant current source, and transistors 1, 3, and 8 function as two current mirror 'pairs'. The network consisting of transistors 4, 5, 6, and 7 is the differential amplifier, and transistor 9 is an output amplifier stage (a very simple one!). Some constants and parameters required for the calculation are listed below. These will be used along with the specifications above to design the size of the transistors required for this circuit.

Specified by overall VLSI circuit requirements: Vdd := 5 ⋅ volt

Supply voltage

Specified by doping levels: Channel length modulation for n-type and p-type devices λ n := 2.752 ⋅ 10

−3

−1

⋅ volt

λ p := 1.427 ⋅ 10

−2

−1

⋅ volt

Intrinsic transconductance for n-type and p-type devices − 5 amp

Kn := 5.518 ⋅ 10

⋅

2

− 5 amp

Kp := 2.226 ⋅ 10

volt

⋅

2

volt

Specified by doping levels and oxide thickness: Threshold voltage for n-type and p-type devices Vtn := .77⋅ volt

Vtp := −.77⋅ volt

The parameters λ, K, and Vt are determined by the manufacturing process. First, transistor 1's aspect ratio is calculated. It will be a function of the required voltage drop across the transistor to make sure it is operating above the threshold voltage, Vt. A minimal gate-to-source voltage of Vtp +Vsafety is used to insure the device would turn on despite any variations in processing. It's important to make the voltage as small as possible, since the output voltage in the circuit should not be clipped by the supply voltage. Since the current consumption is limited to 20 μA, a somewhat arbitrary current of 5 μA is drained through this leg.

μA := 10

−6

⋅ amp

Vsafety := −0.5⋅ volt

Vgs1 := Vtp + Vsafety

Ids1 := 5 ⋅ 10

−6

⋅ amp

The formula for AR 1 is derived from the following formula [1]:

Ids =

1 2

⋅ K⋅ AR⋅ ( Vgs − Vt)

AR1 :=

2 ⋅ Ids1 Kp⋅ ( Vgs1 − Vtp)

AR1 = 1.797

2

Since Vgs1 has been fixed, Vgs2 is also fixed, since they both carry the same current. Transistor 2's aspect ratio can be calculated: Vgs2 := −( Vdd + Vgs1)

AR2 :=

2 ⋅ Ids1 Kp⋅ ( Vgs2 − Vtp)

AR2 = 0.051

2

Vgs2 = −3.73 volt

The difference amplifier can now be designed, starting at the first current mirror (transistors 1 and 3). Like Vgs1 , a minimal Vgs3 is desired for the same reason. The current through transistor 3 is to be half of Ids1 .

Vgs3 := Vgs1

Idsd :=

1 2

⋅ Ids1

AR3 :=

2 ⋅ Idsd Kp⋅ ( Vgs3 − Vtp)

2

AR3 = 0.898

Note that AR3 is exactly half that of AR1 . This is because the following equation applies: AR1 AR3

=

Ids1 Idsd

and Idsd was chosen to be one half of the current in the first leg.

The derivation of this formula isn't shown here, although it is relatively easy. The name 'current mirror' is quite fitting. Now the differential amplifier can be designed.

To obtain a balanced output, transistors 4 and 6 should be matched, as well as transistors 5 and 7. Because of this balancing, the current flowing through transistors 4 and 5 is the same as the current flowing through transistors 5 and 7 (almost no current is drained through the gates of transistors 5 and 7). Like transistor 1, transistor 5's (and 7's) Vgs is to be as small as possible.

2⋅ Vgs5 := Vtn − Vsafety

AR5 :=

Idsd 2

Kn⋅ ( Vgs5 − Vtn)

2

AR5 = 0.181

Some additional parameters must be determined to calculate the high-frequency characteristics. The drain conductance and transconductance parameters are needed for ac small signal analysis.

AR7 := AR5

g d3 := λ p⋅ Idsd

g d3 = 3.567 × 10

g m3 :=

g m3 = 1 × 10

2 ⋅ Idsd⋅ Kp⋅ AR3

g d5 := λ n⋅

Idsd

−5

−8

−9

(drain conductance)

(transconductance)

mho

g d5 = 3.44 × 10

2

mho

mho mho ≡

g m5 :=

2⋅

g d4 := λ p⋅

Idsd

⋅ Kn⋅ AR5

2

g m5 = 5 × 10

Idsd

−6

ohm

mho

g d4 = 1.784 × 10

2

1

−8

mho

Like Vgs1 , Vgs4 should be as small as possible while still turning on the transistor:

2⋅ Vgs4 := Vtp + Vsafety

AR4 :=

Idsd 2

Kp⋅ ( Vgs4 − Vtp)

2

AR4 = 0.449

which allows calculation of gm4 :

g m4 :=

2⋅

Idsd 2

⋅ Kp⋅ AR4

g m4 = 5 × 10

−6

mho

The drain conductances and transconductances that have been calculated enter into the following equation for the gain of the differential amplifier. The derivation of this equation (omitted) is somewhat lengthy. In a nutshell, an ac circuit analysis is performed on the differential amplifier using the appropriate small signal models for the transistors [2]. Some reasonable approximations (such as gm4 + gd4 ≈ gm4 ) were made to greatly simplify the equation. The differential stage gain is given by

Ad :=

1

⋅

g m4

Ad = 117.495

2 g d4 + g d5

This is the gain of the differential amplifier stage. Thus, a gain of 10 or so is needed at the output amplifier stage. Now for the output stage: as with the differential amplifier, the current is set to half of the mirror's Ids : Vgs8 := Vtp + Vsafety

AR8 :=

Ids8 :=

2 ⋅ Ids8 Kp⋅ ( Vgs8 − Vtp)

2

1 2

⋅ Ids1

AR8 = 0.898

g d8 := λ p⋅ Ids8

g d8 = 3.567 × 10

−8

mho

At several points in this design, it was mentioned that certain Vgs 's should be as small as possible. The reason for this is apparent at the output stage: Vout cannot be above Vdd-Vgs8 or below Vgs9 . Vout will be clipped if such a situation does occur. Because Vgs1 =Vgs3 =Vgs8 , these voltages also reflect this consideration. Similarly, Vgs5 and Vgs7 are limited to prevent clipping at the output of the differential amplifier.

Vgs9 := Vtn − Vsafety −9

g d9 := λ n⋅ Ids8

AR9 :=

g d9 = 6.88 × 10

2 ⋅ Ids8 Kn⋅ ( Vgs9 − Vtn)

g m9 :=

2 ⋅ Ids8⋅ Kn⋅ AR9

2

mho

AR9 = 0.362

g m9 = 1 × 10

−5

mho

The equation for the gain of the output stage is shown below:

Ao := −

g m9 g d9 + g d8

Ao = 235

Thus, the total open-loop gain for the amplifier is:

Av := Ad⋅ Ao

Av = 27610

Required gain is > 1000.

It would appear that the amplifier was over-engineered by a factor of 10. The circuit was simulated (with CAzM) and an open-loop gain of 2680 was determined. Two reasons could account for the design/simulation difference. First, to determine the open-loop gain, an ac voltage is applied to the inputs in the simulation. This ac voltage is biased with a dc voltage determined by the simulation's transfer characteristic curve of the circuit (i.e., Vin versus Vout ). The determination of the bias voltage is, at best, an inaccurate procedure. Unfortunately, a small change in the bias voltage greatly affects the open-loop gain, so the optimal open-loop gain may not have been found. Second, the simulation takes into account all sorts of parasitic capacitances not included here, which all affect the gain adversely.

The final part of the design calls for selection of a compensation capacitor, C. The capacitor acts simply as a low pass filter to ensure that the op-amp will be stable. Stability is indicated by the condition where the gain of the circuit vs. frequency crosses unity before the phase crosses 0°. A little trial-and-error with the simulator found a value of .1 pF that fit the requirement rather well.

C := .1⋅ 10 Hz :=

1 sec

− 12

⋅ farad

Rout( s) :=

1 s :=

s⋅ C + g d9 + g d3

3 .10

10

3

2⋅ π

⋅ Hz ,

10

4

2⋅ π

7

⋅ Hz ..

10

2⋅ π

7

⋅ Hz

Use the marker on the graph to help find a guess for the 3 dB point:

sg

2 .10

7

Rout( s ) 1 .10

7

5

sg ≡ 1 ⋅ 10 ⋅ sec 0 100

1 .10

3

1 .10

1 .10

4

1 .10

5

6

−1

1 .10

7

s

The dc output impedance is:

(

Rout 0 ⋅ sec

) = 2.35 × 107 ohm

−1

The -3db point is found by the following root finding equation, using the guess value on the previous page:

(

s3dB := root⎛⎜ Rout( sg) − Rout 0 ⋅ sec

⎝

)⋅ 1

−1

2

, sg⎞⎟

⎠

So the -3db point occurs at the frequency 5

s3dB = 1.763 × 10 sec

−1

Finally, the Gain-Bandwidth product can be determined: 9

GBW := Av⋅ s3dB

GBW = 4.867 × 10 sec

−1

The above information along with the simulation results give the following specifications:

Current drain: Power consumption: Bias Voltage: Open-Loop Gain: Bandwidth: Gain-bandwidth product:

Simulated 10 μamp 50 μwatt 2.5001 volt 2680 2.2 kHz 3 MHz

Calculated 10 mamp 50 mwatt 2.5 volt 27610 1.8 MHz 4.9 GHz

Specified < 20 μΑ < 100 μwatt 2.5 volt >1000 >1 kHz > 1 GHz

On the following page is a schematic of the op-amp layout. Note that transistor 9 has been split in half. Two transistors in parallel with identical lengths, L, and different widths, W1 and W2, are equivalent to one transistor with the same length, L , but with a width of W1+W2 (similar property to parallel capacitors). This property makes design a bit easier, because very wide transistors can be made into two or three not-so-wide transistors which fit more

economically into the circuit topology. The transistors aspect ratios in this layout are not consistent with this design, as this layout is after a design 'evolution' involving a switched-capacitor circuit (so put the ruler away!).

Blue Red Brown Green

Metal Layer PolySilicon Layer p-type Diffusion (source/drain for p-type transistor) n-type Diffusion (source/drain for n-type transistor)

Magenta Purple

A contact between two layers. A capacitor - actually made of layers of PolySilicon and Metal (the "plates"), separated by a layer of oxide (the "dielectric").

Conclusion Hopefully this design example has demonstrated some of the aspects that go into an analog CMOS VLSI design. Although simulators are frequently used to test designs, the actual design is commonly done by hand. Mathcad is an ideal tool for this type of design, as changes in parameters give instantaneous results. As an example, and a place to start your own exploration of this problem, try changing the safety voltage on page 5 and examine its effect on the aspect ratios and the gain of the op-amp.

References 1. Haskard, Malcom R., and May, Ian C. (1988), Analog VLSI Design nMOS and CMOS, Prentice Hall of Australia Pty Ltd, Englewood Cliffs, New Jersey, p.16. 2. Ibid, p. 19.

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