Low Power Vlsi

LOW POWER VLSI By, K.Venkataramana reddy 07c31a0458

Why worry about power? --Heat Dissipation Microprocessor power Consumption

Why we go to Low Power.. PORTABILITY: Enhanced run-time, Reduced weight, Reduced volume, Low cost operation High Performance: Low-cost cooling, Low-cost packaging, Low-cost operation RELIABILITY:  Avoid thermal problems  Avoid scaling related problems

Speed/Power performance for  available Technologies

Where Does Power Go In CMOS • Dynamic Power Consumption : Charging and Discharging Capacitors • Short Circuit Currents : Short circuit path between supply rails during switching • Leakage: Leakage diodes and transistors

Ptotal = PDYN + PSC + PLeakage =CLVDDF+VDDIPEAK{(Tr  +

Tf )/2}F+VDD ILEAK

Dynamic Power Consumption

L

2 dd

Energy/transition = C * V

Dynamic Power Consumption • Power = Energy / Transition * transition rate 2 = C * V * f  L dd • So, power is proportional to V dd , f ,CL • Power dissipation is data dependent Function of switching activity

Reducing Vdd • Power P is proportional to square of V • VDD has decreased in modern processes  – High VDD would damage modern tiny transistors  – Lower VDD saves power 

• VDD = 5, 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, … • Further decreasing may cause affect to Threshold voltage • Relatively independent of logic function and style. • Power Delay Product Improves with lowering Vdd. • By reducing Vdd Noise margin will be affected

Noise Margin

• NML = VIL - VOL • NMH = VOH - VIH

Power Consumption is Data Dependent Ex: Static 2 i/p NOR Gate

 A B Y

 A

B

Y

0

0

1

0

1

0

1

0

0

1

1

0

P(A=1) = ½ P(B=1) = ½ Then P(out=1) = ¼ P(out=0) = 1-P(out=1) =1-1/4 = ¾

P(0->1) = P(out=1).P(out=0) = ¾ * ¼ = 3/16

Transition Probability of 2-input NOR Gate  A B Y

Transition Probabilities for Basic Gates

P0 -> 1  AND OR

(1-Pa * Pb) Pa Pb (1-Pa)(1-Pb)(1-(1-Pa)(1-Pb))

EXOR (1-(Pa + Pb - 2Pa * Pb)) (Pa + Pb 2Pa * Pb)

Switching Activity for Static CMOS P0 -> 1 = P0 * P1

How about Dynamic Circuits..? Clk

 Power

Mp

Out In1 In2

CL PDN

In3 Clk

is only dissipated when out=0

Me

 Ceff

= P(out=0) * C L

Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1)

2 input NOR gate  A

B

Y

0

0

1

0

1

0

1

0

0

1

1

0

P(A=1) = ½ P(B=1) = ½ P(out=0) = ¾ Ceff = ¾ * CL  Switching

activity is always Higher in Dynamic Circuits

Transition Probabilities For  Dynamic GATES

P0 -> 1  AND

(1-Pa * Pb)

OR

(1-Pa)(1-Pb)

EXOR (1-(Pa + Pb - 2Pa * Pb)) Switching Activity for Precharged Dynamic Gates

Glitching… • Glitching refers to spurious and unwanted transitions that occur before a node settle down to its final steady-state value. • Glitching often arises when paths with unbalanced propagation delay converges at the same point in the circuit. • The dissipation caused by the spurious transitions can reach up to 25% of the total dissipation for some circuits.

Glitching in Static CMOS

 Each

gate has Unit delay  Input A, B, C arrive at same time.  No glitching in dynamic circuits

How to Cope With Glitching..?

Short Circuit Currents • Short circuit currents are encountered only in static design. • In static CMOS circuits the flow current from VDD to GND during Switching when both NMOS and PMOS conducting Simultaneously. • Such path never exists in a dynamic circuits.

Short Circuit Currents Vdd

Vin

Vout

V out 

 NMOS off  PMOS res

       5   .         2

CL

 NMOS s at PMOS res

       2

 NMOS sat

       5   .         1

0.15

PMOS sat

       1      )      A     m      (      D      D      V      I

 NMOS res

0.10

0.05

0.0

PMOS sat

       5   .         0 

1.0

2.0 3.0 Vin (V)

4.0

5.0

0.5

1

1.5

2

 NMOS re s PMOS off 

2.5

V in

Impact of rise/fall time on ShortCircuit Currents V DD

V in

V DD

V out 

V in

C L

Large Capacitive Load 

The input through the transient region before the output start to change

V out  C L

Small capacitive Load 

Output fall time is Substantially smaller than the input rise time

Short-Circuit energy as a function of slope ratio • Short-Circuit energy dissipation (normalized with respect to zero i/p rise time energy) for a static CMOS. • The power dissipation due to short circuit currents is minimized by matching the rise/fall times of the input and output signals. • Short-Circuit reduced by lower the Supply Voltage.

Leakage Vd d

Vout

Drain Junction Leakage Sub-Threshold Current

Sub-Threshold current Dominant factor 

Static Power Consumption Vd d



Dominates over dynamic consumption



Not a function of Switching Frequency.



Reduce switching activity



Reduce physical capacitance

Istat Vo ut

Vin =5V

CL

Pstat = P(In=1) .Vdd . Istat

System-Level optimization : Power  Management

• In event-driven application, large amounts of  power are wasted while the system is in idlemode. • The power consumption can be reduced significantly by using power management scheme to shunt down idle component.

Conclusion • Thus the low power can be achieved by decreasing Vdd to certain level. •  As leakage current cannot be reduced, the short circuit currents are eliminated by dynamic circuits. • The power dissipation due to short circuit currents is minimized by matching the rise/fall times of the input and output signals • Glitching makes power to dissipate so it is reduced by cope process

References • Digital Integrated Circuits –JAN M.RABAEY • Encyclopedia of computer science and technology,1995. • VLSI Design Techniques for Analog and Digital Circuits –Randall L.Geiger, Phillip E.Allen. • Basic VLSI Design A.PUCKNELL. • Low-Power CMOS Design “IEEE journal of solid state circuit -pages 472-484,Aprill 1992”.

THANK 

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