Low Power Design in VLSI

May 4, 2018 | Author: prathap13 | Category: Field Effect Transistor, Capacitor, Mosfet, Cmos, P–N Junction
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Low Power Design in VLSI

Evolution in Power Dissipation:

Why worry about power? Hea eatt Dis issi sipa pati tion on microprocessor power dissipation source source : arpa-e arpa-esto sto DEC 21164

Computers Defined by Watts not MIPS: Watt Watt Wire Wirele less ss Sensor Networks

Base Stations Wireless Internet Internet

PDAs, Cameras, Cellphones, Laptops, GPS, Set-tops, 0.1-10 Watt Clients


MegaWatt Data Centers

Why Low Power ?

• Growth of battery-powered systems • Users need for:  – Mobility  – Portability  – Reliability • Cost • Environmental Environmental effects

IC Design Space:

Power Impacts on System Design: • Energy consumed per task determines battery life  – Second order effect is that higher current draws decrease effective battery energy capacity • Current draw causes IR drops in power supply voltage  – Requires more power/ground pins to reduce resistance R  – Requires thick&wide on-chip metal wires or dedicated metal layers • Switching current (dI/dT) causes inductive power supply voltage bounce LdI/dT  – Requires more pins/shorter pins to reduce inductance L  – Requires on-chip/on-package decoupling capacitance to help bypass pins during switching transients • Power dissipated as heat, higher temps reduce speed and reliability  – Requires more expensive packaging and cooling systems

Facts ... Moore´s Law

- doubling transistors every 18 months 

• Power Power is prop proport ortion ional al to to die area and frequency ! • In the same same technology technology a new new architect architecture ure has 2-3X 2-3X in Die Area • Changing Changing techn technology ology implies implies 2X frequency frequency SCALING TECHNOLOGY ... • Decreasin Decreasing g voltage voltage

( 0.7 scaling scaling factor factor )

• Decreasing Decreasing of die area

( 0.5 scaling scaling factor factor )

• Increasin Increasing g C per unit area

43% !!!

This implies implies that that the power power density density increase increase of 40% 40% every generation !!! Temperature is a function of power density and determinates the type of  cooling system needed. VARIABLES 

PEAK POWER ( worst case ) Today´s packages can sustain a power dissipation over 100W for up to 100msec >>> cheaper package if peaks are reduced 

ENERGY SP SPENT ( for a workload ) More correlated to battery life

Low Power Strategies: • OS level evel : • Soft Softwa ware re lev level el :


( Compiler Compiler technol technology ogy for low power, power, in instruct struction ion scheduling scheduling )

• Archit Architect ecture ure level level : PIPELINING, REDUNDANCY, DATA ENCODING ( ISA, architec architectural tural design, design, memory memory hierarchy, hierarchy, HW  extensions, etc )

• Circui Circuit/l t/logi ogic c level level : LOGIC STYLES, TRANSISTOR SIZING, ENERGY RECOVERY

( Logic families, conditional clocking, adiabatic circuits, asynch asynchron ronous ous design design )

• Techno Technolog logy y level level : Threshold reduction, multi-threshold devices, etc 

Power Consumption Estimation: 30



  n   o    i    t   a   m    i    t 15   s   e   r   o   r   r    E

power consumption



0 Arch


Circ uit

Levels of abstraction

Lay out

Due to the relative high error rate in the architectural estimation ( no vision of the total area, circuit types, technology, block activity, etc )


Accu Accura rate te pow power er eva evalu luat atio ion n is done done at at lat late e desi design gn pha phase ses s

Need Needs s of of goo good d fee feedb dbac ack k bet betwe ween en all all the the desi design gn phas phases es - Correlation between power estimation from low level to high  level 


- Critical path based power consumption analysis 

( CIRCUIT TYPES, TECHNOLOGY, ACTIVITY FACTOR ) - Thermal images based correlation analysis 


Architectural Power Evaluation: Archit Architec ectur tural al desig design n partiti partition on • Powe Powerr con consu sump mpti tion on eval evalua uati tion on at bloc block k lev level el - Power density density of blocks blocks

( SPICE simulation simulation,, statistica statisticall input set, technology and circuit types definition )

- Activity of blocks and sub-blocks 

( running benchmarks )

- Area ( fee feedba dback ck from from VLSI VLSI design design,, circui circuits ts and techno technolog logy  y  defined )

• Try Try do defin define e scal scalin ing g fact factor ors s that that allo allow w to rem remap ap the the architectural power simulator when technology, area and circuit types change • Try Try to to red reduc uce e the the erro errorr est estim imat atio ion n at at hig high h lev level el

Power Dissipation in CMOS: Short-Circuit Current

Diode Leakage Current Capacitor  Charging Current


Subthreshold Leakage Current

Primary Components: • Capacitor Charging (85-90% of active power)  – Energy is ½ CV2 per transition • Short-Circuit Current (10-15% of active power)  – When both p and n transistors turn on during signal transition • Subthreshold Leakage (dominates when inactive)  – Transistors don’t turn off completely • Diode Leakage (negligible)  – Parasitic source and drain diodes leak to substrate

Sources of Power Dissipation:

• Dyna Dynam mic powe powerr diss dissip ipat atio ions ns:: whenever the logic level changes at different points in the circuit because of the change in the input signals the dynamic power dissipation occurs.

 – Switch Switching ing power power dissip dissipati ation. on.  – Short Short-ci -circu rcuit it power power diss dissipa ipatio tion. n.

• Stat tatic powe ower dis dissi sipa pati tion ons: s: this is a type of dissipation, which does not have any effect of level change in the input and output. output .

 – Leak Leakag age e powe power. r.

Switching Power Dissipation: • Caus Caused ed by the the cha charg rgin ing g and and disch dischar argi ging ng of the the node capacitance.

Figure 1: Switching power  dissipation [1].

Switching Power Dissipation (Contd.): • Ps/w= 0.5 * α * CL* Vdd2 * f clk  – CL physic physical al capacit capacitanc ance, e, Vdd supply voltage, f clk clock frequency.


switching activity,

 – CL(i) = Σ j CIN j + Cwire + Cpar(i)  – CIN the gate input capacitanc capacitance, e, Cwire the parasitic interconnect and Cpar  diffusion capacitances of each gate[I].

• Depends on: – Supply vo voltage  – Phys Physic ical al Capa Capaci cita tanc nce e  – Switc witchi hing ng act activ ivit ity y

Short circuit power dissipation: • Caus Caused ed by by simu simulta ltane neou ous s cond conduc ucti tion on of of n and and p bloc blocks ks..

Figure 2: Short circuit current

Short circuit power dissipation


where here k = (kn = kp), the trans conductance of the transistor, τ

= (trise = tfall), the input/output transition time, V DD = supply voltage,

f = clock clock freque frequency ncy,, and VT = (VTn = |VTp|), the threshold voltage of  MOSFET.

• Depends on : – –  – – –  –

The The input ramp Load The The tran transi sist stor or size size of the the gate gate Supply vo voltage Frequency Thre Thresh shol old d volt voltag age. e.

Leakage power dissipation: • Six Six shor shortt-cha chann nnel el leaka leakage ge mech mechan anis isms ms are are there:  – I1 Reverse-bias p-n junction leakage  – I2 Sub threshold leakage  – I3 Oxide tunneling current  – I4 Gate current due to hot-carrier injection  – I5 GIDL (Gate Induced Drain Leakage)  – I6 Channel punch through current • I1 and I2 are the dominant leakage mechanisms

Leakage power dissipation (contd.)

Figure 3: Summary of leakage current mechanism [2]

PN Junction reverse bias current: • The The rev rever erse se bias biasin ing g of of p-n p-n jun junct ctio ion n cau cause se reverse bias current  – Caused Caused by diffus diffusion/d ion/drift rift of minority minority carrier carrier near near the the edge of the depletion region.

where V bias = the reverse bias voltage across the p-n junction, J s = the reverse saturation current density and A = the junction area.

Sub Threshold Leakage Current: • Caus Caused ed when when the the gat gate e vol volta tage ge is belo below w Vth.

Fig 4: Sub threshold current[2] 

Fig 5: Subthreshol Subthreshold d leakage leakage in a negative-  negative-  channel metal–oxide–semiconductor   (NMOS) transistor.[2] 

Contribution of Different Power  Dissipation:

Fig 6: Contribution of different powers[1]

Fig 7:Static power increases with shrinking device geometries [7].

Degrees of Freedom

• The The thr three ee degr degree ees s of of fre freed edom om are: are:  – Supp Supply ly Vol Volta tage ge  – Swit Switch chin ing g Activ Activit ity y  – Physi Physica call capaci capacitan tance ce

Reducing Power: • Switching power activity*½ CV2*frequency  – (Ignoring short-circuit and leakage currents) • Reduce activity  – Clock and function gating  – Reduce spurious logic glitches • Reduce switched capacitance C  – Different logic styles (logic, pass transistor, dynamic)  – Careful transistor sizing  – Tighter layout  – Segmented structures • Reduce supply voltage V Quadratic savings savings in energy energy per transitio transition n – BIG effect effect  – Quadratic  – But circuit delay is reduced • Reduce frequency  – Doesn’t save energy just reduces rate at which it is consumed  – Some saving in battery life from reduction in current draw

Supply Voltage Scaling • Swit Switch chin ing g and and shor shortt cir circu cuit it powe powerr are are proportional to the square of the supply voltage. • But But the the del delay ay is is pro propo port rtio iona nall to to the the supp supply ly voltage. So, the decrease in supply voltage will results in slower system.

• Thre Thresh shol old d volt voltag age e can can be be scal scaled ed dow down n to get get the same performance, but it may increase the concern about the leakage current and noise margin.

Supply Voltage Scaling (contd.)

Fig 8: Scaling supply and threshold voltages [4]

Fig 9: Scaling of threshold voltage on leakage power and delay[4]

Switching Activity Reduction • Two components:  – f: The The average average periodicit periodicity y of of data data arriva arrivals ls  –


how many transitions each arrival will generate.

• Ther There e will will be no net net bene benefi fits ts by by Redu Reduci cing ng f. •

can be reduced by algorithmic optimization, by architecture optimization, by proper choice of  logic topology and by logic-level optimization.


Physical capacitance reduction • Physi Physica call cap capac acita itanc nce e in in a cir circu cuit it con consi sists sts of thr three ee components:  – The The out outpu putt nod node e cap capac acit itan ance ce (C L).  – The The inp input ut capa capaci cita tanc nce e (C in ) of the driven gates.  – The total total interc interconn onnect ect capaci capacitan tance ce (C int ).

• Smal Smalle lerr the the size size of a dev devic ice, e, smal smalle lerr is is C L. • The The gate gate area area of each each tran transis sisto torr det deter ermi mine nes s C in. • C int  is determine by width and thickness of the metal/oxide layers with which the interconnect line is made of, and capacitances between layers around the interconnect lines.

Issues • Technology Sc Scaling  – Capaci Capacitan tance ce per per node node reduces reduces by 30% 30%  – Elec Electr tric ical al node nodes s incr increa ease se by 2X  – Die Die siz size e gro grows ws by 14% 14% (Mo (Moor ore’ e’s s Law) Law)  – Supply Supply voltag voltage e redu reduces ces by 15%  – And frequen frequency cy incre increase ases s by 2X 2X This will increase the active power by 2.7X

Issues (contd.) • To meet eet fre frequ quen ency cy dem demand Vt will be scaled, resulting high leakage power.

*Source: Intel Fig 10:Total 10:Total power power consump consumption tion of a micropro microprocesso cessorr following following Moore’s Moore’s Law

Ultra Low Power System Design: • Powe Powerr mini minim mizat izatio ion n appr approa oach ches es:: • Run at mini minimum mum allowa allowable ble voltag voltage e • Minimi Minimize ze effect effective ive switc switchin hing g capacit capacitanc ance e

Process • Progr rogre ess in SOI and and bul bulk k sil silic icon on  – (a) 0.5V 0.5V opera operation tion of ICs ICs using using SOI SOI techno technology logy  – (b) 0.9V 0.9V opera operation tion of of bulk silicon silicon memory, memory, logic, logic, and and processors

• Incr Increa easi sing ng dens densit itie ies s and and clock clock fre frequ quen enci cies es have have pushed the power up even with reduce power  supply

Choice of Logic Style

Choice of Logic Style

• Powe Powerr-de dela lay y prod produc uctt impr improv oves es as as volt voltag age e decr decrea ease ses s •


Power Consumption is Data Dependent • Exam xample ple : Sta Static tic 2 Inpu Inputt NO NOR Gat Gate e Assume : P(A=1) = ½ P(B=1) = ½ Then : P(Out=1) = ¼ P(0→ P(0→1) = P(Out=0).P(Out=1) P(Out=0).P(Out=1) =3/4 * 1/4 = 3/16 CEFF = 3/16 * CL

Transition Probability of 2-input NOR Gate

as a function of input probabilities

Switching Activity (α) : Example

Glitc litchi hing ng in Sta Stati tic c CMO CMOS

At the Datapath Level… Irregular


Balancing Operations

Carry Ripple

Data Representation

Low Power Design Consideration (cont’) (Binary v.s. Gray Encoding)

Resource Sharing Can Increase Activity

(Separate Bus Structure)

Resource Sharing Can Increase Activity (cont’d)

Operating at the Lowest Possible Voltage • Desir Desire e to oper operate ate at lowe lowest st possi possibl ble e spe speed eds s (using low supply voltages) • Use Use Arc Archi hite tectu cture re opti optimi miza zati tion on to to comp compen ensa sate te for  for  slower operation

Approach : Trade-off AREA for lower  POWER

Reducing Vdd

Lowering Vdd Increases Delay

• Concept of Dynamic Voltage Scaling (DVS)

Architecture Trade-offs : Reference Data Path

Parallel Data Path

Paralelna implementacija dela datapath :

Pipelined Data Path

Protočna implementacija:

Paralelno-protočna implementacija:

A Simple Data Path : Summary

Computational Complexity of DCT Algorithms

Power Down Techniques • Concept of Dynamic Frequency Scaling (DFS)

Energy-efficient Software Coding • Pote Potent ntia iall for for powe powerr redu reduct ctio ion n via via soft softwa ware re modification is relatively unexploited. • Code Code size size and and algo algori rith thmi mic c effi effici cien ency cy can can significantly affect energy dissipation • Pip Pipelin elinin ing g at at soft softwa ware re leve levell- VLIW LIW cod codin ing g sty style le • Examples -

Powe Powerr Hung Hunger er – Cloc Clock k Net Netwo work rk (Always Ticking) • H-Tr H-Tree ee – desi design gn defi defici cien enci cies es base based d on on Elm Elmor ore e del delay ay model • PLL PLL – ever every y des desig igne nerr (di (digi gita tall or or ana analo log) g) shou should ld have have the knowledge of PLL • Multi Multipl ple e freq freque uenc ncie ies s in chi chips ps/s /sys yste tems ms – by PLL PLL • Low Low mai main n fre frequ quen ency cy,, But But • Jitter and Noise, Noise, Gain Gain and and Bandwidth Bandwidth,, Pull-in Pull-in and Lock Time, Stability … • Local time zone • Self-Timed • Asyn Asynch chro rono nous us => Use Use Gat Gated ed Cloc Clocks ks,, Sle Sleep ep Mode Mode

Power Analysis in the Design Flow

Human Wearable Computing Power  • Wear Weara able ble comp comput utin ing g – emb embeddi edding ng comp comput ute er  into clothing or creating a form that can be used like clothing • Curr Curren entt comp comput utin ing g is limi limite ted d by batte battery ry cap capac acity ity,, output current, and electrical outlet for  recharging

Conclusions •

High-speed design is a requirement for many applications

Low-power design is also a requirement for IC designers.

A new way of THINKING to simultaneously achieve both!!!

Low power impacts in the cost, size, weight, performance, and reliability.

Variable Vdd and and Vt Vt is a tre trend nd

CAD tools high level power estimation and management

Don’t just just work on VLSI, VLSI, pay pay attention attention to MEMS MEMS – lot of problems and potential is great.

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