Logic Circuits Final Exam

School of EECE LOGIC CIRCUITS & SWITCHING THEORY I

FINAL EXAMINATION

Q1 SY 2009 - 2010

NOTE: CHEATING IN ANY FORM WILL NULLIFY YOUR EXAM AND WILL BE A GROUND FOR AN AUTOMATIC GRADE OF 5.00. MULTIPLE CHOICE: Select the most appropriate answer from the given choices. 1. It is a system by which certain data or information is represented in numerical pattern. a. number system c. analog system b. digital system d. system representation 2. A datapath, when combined with the control unit, forms a component referred to as ______. a. memory unit c. output unit b. input unit d. central processing unit 3. The equivalent of the decimal number 41.6875 in the binary numbering system is _________ a. 101011.1101 c. 101001.1011 b. 101010.0011 d. 101011.0111 4. The binary number 101100 01101011.11110010, when converted to hexadecimal is ______ a. C D 7 A . 2 F c. B 1 A 2 . 2 F b. 1 C 6 C . F 2 d. 2 C 6 B . F 2 5. What is the decimal equivalent of the largest binary integer that can be obtained with 16 bits ? a. 65536 c. 32768 b. 32767 d. 65535 6. Each of the following 4 numbers has a different base. Which of the four numbers have the same value in decimal ? (a) 20225 a. b & d b. c & d

(b) 120113

(c) 33124

(d) 19A12 c. a & d d. b & c

7. Given two decimal numbers 694 and 835. Their sum in BCD is ________ a. 00111111001001 c. 0001010100101001 b. 01011111001001 d. none of these 8. The result of subtracting 654253758 from 740152368 is ___________ a. 6367541 c. 6267641 b. 6367641 d. 6367541 9. The Boolean expression (X+Y+Z)’ = X’Y’Z’ is an example of which Law/Theorem? a. Commutative Law c. Idempotent Law b. Involution Law d. DeMorgan’s Theorem

“Knowledge is of no value unless you put it into practice.” - Heber J. Grant

10. The Boolean expression (X’)’ is an example of which Law/Theorem? a. Commutative Law c. Idempotent Law b. Involution Law d. DeMorgan’s Theorem 11. The Boolean expression X + Y = Y + X is an example of which Law/Theorem? a. Commutative Law c. Idempotent Law b. Involution Law d. DeMorgan’s Theorem 12. This is the basic mathematics needed for the study of the logic design of digital systems. a. Combinational Design c. Boolean Algebra b. Sequential Design d. Quine-McCluskey Technique 13. This has one or more inputs and one or more outputs which take on discrete values. a. digital system c. finite state machine b. switching circuit d. algorithmic state machine 14. This part of the design of digital system involves determining how to interconnect basic logic building blocks to perform a specific function a. block diagram c. iterative design b. system design d. logic design Questions 15 to 17 refer to the logic gate symbols shown below.

A.

B.

C.

D.

E.

F.

15. What type of logic gate is gate A? a. NOT gate b. AND gate

c. XOR gate d. OR gate

16. What type of logic gate is gate C? a. NOT gate b. AND gate

c. XOR gate d. OR gate

17. What type of logic gate is gate F? a. NOT gate b. NAND gate

c. XOR gate d. XNOR gate

18. What logical reason/s can you give why NAND and NOR gates are considered universal gates? a. they can appear anywhere in the circuit c. they can imitate function of other gates b. they can produce universal operation d. they cannot be partial 19. A race condition happens in an R-S latch when the inputs are ______ a. both zero c. both one b. either zero or one d. indeterminate 20. This is the time needed by a gate in processing its input signals before the output signal can be generated a. setup time c. hold time b. propagation delay time d. threshold time “Knowledge is of no value unless you put it into practice.” - Heber J. Grant

21. Which of the following circuits function like an inverter or NOT gate?

a)

c)

b)

d)

22. What code is used in labeling the cells of a K-map? a. gray code c. excess-3 code b. binary code d. two-out-of-five code 23. What will happen if the function v(w+x+y)z would be implemented using NOR gates? a. Not possible using NOR gates c. Six NOR gates will be used b. given function must be implemented d. none of these using OR and NAND gates

For Questions 24 to 28, refer to the circuit diagram shown below.

A

T

B T C D

T

1 2

T

4

T

5

3

24. What is the expression for T1? a. A + B b. A  B

c. AB d. (A  B)’

25. What is the expression for T2? a. BC b. (C  B)’

c. (BC)’ d. (C  B)

26. What is the expression for T3? a. CD b. (C  D)

c. (CD)’ d. C + D

27. What is the expression for T4? a. ( A  B )( BC ) c. ( A  B )( B  C ) AB  ( B  C )is of no value unless you  Cpractice.” ) b. “Knowledge d. AB putit( Binto - Heber J. Grant

28. What is the expression for T5? a. ( B  C )  CD b. ( B  C )  CD

c. ( BC )(C  D) d. ( B  C )(C  D )

29. The simplest expression (in sum-of-products form) for the function F(A,B,C,D,E) = ∑m (1,3,5,7,8,12,15,18,19,22,23,24,27,28,31) is a. ABE + CD’E + AB’D+ADE+BD’E’ b. A’B’E + CDE + AB’D + ADE + BD’E’

c. ABE + CD’E + AB’D+A’DE+BD’E’ d. A’B’E + CD’E + AB’D+ADE+BD’E’

30. Use the K-map to find the minimum sum of products of F(A,B,C,D) = ∏M (0,2,4,6,8,10,12,14) a. F = D b. F = D’

c. F = A’D d. none of these

31. Simplify the Expression (wx + yz)(w’y’+xz’) using Boolean Algebra: a. w’x’y’ b. wxz’

c. wx’z d. w’xz

32. Given the function F(a,b,c,d) = ∏M(1,3,5,9,12,14,15) determine its canonical form. a. F = M1 + M3 + M5 + M9 + M12 + M14 + M15 b. F = m1 + m3 + m5 + m9 + m12 + m14 + m15

c. F = m1m3m5m9m12m14m15 d. F = M1M3M5M9M12M14M15

33. A multiplexer is also called _________ a. Data controller b. Data manipulator

c. Data selector d. Data converter

For questions 34 to 40, refer to the behavior of the synchronous sequential circuit below. Assume that the states are identified as the combination ABC.

X Y D

Q

A

T

Q

J

Q

K

B Q

Q

C Q

CP 34. What is the next state for an input of 0 if the current state is 000?

“Knowledge is of no value unless you put it into practice.” - Heber J. Grant

a. 010 b. 011

c. 110 d. none of these

35. What is the next state for an input of 1 if the current state is 001? a. 100 b. 010

c. 101 d. none of these

36. What is the next state for an input of 0 if the current state is 010? a. 000 c. 100 b. 001 d. none of these 37. What is the next state for an input of 1 if the current state is 011? a. 100 c. 110 b. 101 d. none of these 38. What is the next state for an input of 0 if the current state is 100? a. 100 c. 111 b. 101 d. none of these 39. What is the next state for an input of 1 if the current state is 101? a. 000 c. 110 b. 001 d. none of these 40. What is the next state for an input of 0 if the current state is 110? a. 100 c. 110 b. 101 d. none of these

For questions 41 to 44, refer to the given J-K flip-flop excitation table below. Line 1 2 3 4

Q(t) 0 0 1 1

Q(t + 1) 0 1 0 1

J

K

41. In line 1 of the given table, what should be the value of K if J = 0? a. 0 c. X b. 1 d. undefined 42. In line 2 of the given table, what should be the value of K if J = 1? a. 0 c. X b. 1 d. undefined 43. In line 3 of the given table, what should be the value of J if K = 0? a. 0 c. X b. 1 d. undefined 44. In line 4 of the given table, what should be the value of J if K = 1? a. 0 c. X b. 1 d. undefined

“Knowledge is of no value unless you put it into practice.” - Heber J. Grant

For questions 45 to 48, refer to the given 4-bit register below.

THE CONTENT OF A 4-BIT REGISTER IS INITIALLY 1001 (Q 3Q2Q1Q0). THE SHIFT REGISTER IS SHIFTED 8 TIMES TO THE LEFT WITH THE SEQUENCE 00101011 AS THE SERIAL INPUT. THE RIGHTMOST BIT OF THE SEQUENCE IS APPLIED FIRST. 45. What should be the content of the register after the arrival of the 3rd initiating clock? a. 1101 b. 1110

c. 0111 d. 1011

46. What should be the content of the register after the arrival of the 5th initiating clock? a. 1101 b. 0101

c. 1010 d. 0100

47. What should be the content of the register after the arrival of the 7th initiating clock? a. 1101 b. 0101

c. 1010 d. 0100

48. What should be the content of the register after the arrival of the 8th initiating clock? a. 0010 c. 1010 b. 0101 d. 0100 49. The master-slave is a pulse-triggered flip-flop and is indicated as such with a right angle symbol called a ______________ a. dynamic input indicator c. postponed output indicator b. static pulse indicator d. none of these 50. The functional relationships between the inputs, outputs, and flip-flop states of a sequential circuit can be enumerated in a _______________ a. truth table c. logic function b. excitation table d. none of these

“Knowledge is of no value unless you put it into practice.” - Heber J. Grant