lna1matlab

ABabcdfghiejkl Stanford University

Design of a CMOS Low-Noise Amplifier

Pablo Moreno Galbis and Mohammad Hekmat

EE314 Project Report Professor H. Rategh, Winter 2006

Contents 1 Specifications and Achieved Results

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2 SPICE Netlist

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3 Design Methodology 3.1 Topology . . . . . . . . . . . . . . . 3.2 S-Parameter Analysis . . . . . . . . 3.3 Optimal Noise Design Methodology . 3.4 Biasing . . . . . . . . . . . . . . . .

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4 Designed circuit 4.1 Initial Design . . . . . . . . 4.2 Noise Optimized 2.5V LNA 4.3 Noise Optimized 1.5V LNA 4.4 Final Design . . . . . . . .

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5 Conclusion

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A MATLAB Optimization Code

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B EE314 Technology Characterization Plots

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1

1

Specifications and Achieved Results

Low noise amplifiers (LNA) are a key component in wireless systems. The main purpose of using an LNA is to increase the power of the signal coming from the antenna while introducing little noise by the LNA itself, mitigating in this way the effect of the noise introduced by subsequent stages. In this project, an LNA for CDMA/WCDMA applications covering simultaneously Korean PCS (1.83GHz-1.86GHz), US PCS (1.931.99GHz) and WCDMA receive band (2.11-2.17GHz) has been designed. The complete set of specifications and the achieved results in the final design are summarized in Table 1.

PDC S11 S21 IIP3 NF VDD Total capacitance Total resistance No. of pins

Specification ≤ 13mW ≤ −10dB ≥ 10dB ≥ −5dBm Minimize ≤ 2.5V ≤ 200pF ≤ 200kΩ ≤ 12

Achieved 12.99mW ≤ −10dB ≥ 11.4dB 12.75dBm 0.8–1.1dB 1.5V 195fF 111kΩ 12

Table 1: Required specifications and performance summary of the LNA.

The designed LNA does not use any off-chip components and all required inductances are implemented using the parasitic inductance of bondwires and package pins. The schematic view of the LNA is depicted in Figure 1. The bonding diagram is also shown in Figure 2.

2

VDD = 1.5V

9mm

3mm

586µA Ld 1kΩ

Rref Output

110kΩ

11 /5 0.25 Q1s

170 /85 0.25

8.076mA

RBias Q1

Lg

2mm

3

170 /85 0.25

Input Cmmcap

1mm

195fF

1mm Ls

4mm 4mm

VSS

6mm 6mm 8mm

5mm

Figure 1: Schematic view of the LNA (The number next to each transistor is

W L

/nf ).

Figure 2: Bonding diagram of the chip in the package

4

2

SPICE Netlist

The SPICE netlist of the design is as follows:1 .subckt lna in outo supo ss .param length =0.25u .param width1 =170u .param width2 =170u .param width3 =11u .param ref =1000 .param bias =110k ****************************************** ***** Devices ***************************** ******* Transistors ********************** Xmn1 d1 g1 s1 s1 nnmos w=’width1’ l=’length’ nf=85 Xmn2 out sup d1 s1 nnmos w=’width2’ l=’length’ nf=85 Xmn3 g3 g3 s1 s1 nnmos w=’width3’ l=’length’ nf=5 ******* Inductors ************************ Xg in g1 s1 pin np=1 nb=1 lb=5m Xs1 ss s1 s1 pin np=1 nb=1 lb=1m Xs2 ss s1 s1 pin np=1 nb=1 lb=1m Xs3 ss s1 s1 pin np=1 nb=1 lb=4m Xs4 ss s1 s1 pin np=1 nb=1 lb=4m Xs5 ss s1 s1 pin np=1 nb=1 lb=6m Xs6 ss s1 s1 pin np=1 nb=1 lb=6m Xs7 ss s1 s1 pin np=2 nb=2 lb=8m Xvdd supo sup s1 pin np=1 nb=1 lb=3m Xd supo out s1 pin np=1 nb=1 lb=9m Xout outo out s1 pin np=1 nb=1 lb=2m ******* Capacitors *********************** Xgs g1 s1 s1 mmcap Cm=195f ******* Resistors ************************ Rref sup g3 R=’ref’ Rbias g3 g1 R=’bias’ .ends

1 the

model descriptions for the pad, bondwire, pin, MM capacitor and noisy MOS device are omitted for brevity.

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3 3.1

Design Methodology Topology

Given the specifications for the LNA in this project, a great variety of circuit topologies can be chosen to meet the requirements; however, an inductively degenerated topology was adopted in this design, which proves to have superior performance as compared to its common-gate and resistively terminated counterparts [1]. Furthermore, this topology allows for control over the real part of the input impedance (thereby achieving power match), while it avoids introducing extra noise and losses which can happen in case of using a shunt input resistor; therefore, it provides simultaneous input matching and minimum noise figure, making it an optimal choice for this project. Another design consideration is whether to choose single-ended or differential architecture. The single ended configuration provides a lower noise figure for in the differential topology both branches contribute to the noise at the output. Additionally, since the current in each transistor in the differential circuit is half that of the single-ended topology, the transit frequency of the device would be smaller for the differential circuit, which degrades the noise figure of the circuit. Nevertheless, the differential topology can provide an increased output dynamic range, and a better tolerance to common-mode interferences in the circuit. Furthermore, the effect of the parasitic inductance of the ground pin is significantly mitigated due to the differential nature of the circuit. This is not however, a significant issue in this design because the parasitic inductance of the ground pin has been used as part of the input matching network. Finally, a cascode configuration was used in the signal path to increase the isolation between the input and the output, which makes it possible to optimize independently the values of the input and the output matching circuits. The disadvantage of cascode is the additional headroom requirement, which limits the output swing and the minimum supply voltage. Even though, swing is not an important issue in this LNA, lowering the supply voltage allows larger currents for the specified power budget and as will be discussed in the optimization part, this provides a better noise performance. However, in this case it was preferred to reduce the interaction between the input and the output tanks, in order to be able to achieve the S-parameter requirements.

3.2

S-Parameter Analysis

As the first step in the design procedure the dependence of S-parameters on properties of passive and active components should be studied. The transconductance of the cascode stage (to the first order) is the same as that of the single transistor stage. This transconductance will be multiplied by the quality factor of the input RLC tank (Qin ) formed by Lg , Cgs , and Ls ; therefore, the effective transconductance of the cascode stage, Gm , is given by [2]: Gm = gm1 Qin =

gm1 ωT = ω0 Cgs (Rs + ωT Ls ) 2ω0 Rs

(1)

where body effect has been neglected and the input is also assumed to be matched to Rs at the frequency of interest. |S21 |2 is defined as the ratio of the power delivered to the load divided by the available power at the source; therefore, after a little math crunching it can be written in terms of Gm as: |S21 |2 =

Io2 RL Vs2 4Rs

=

(Gm Vs )2 RL Vs2 4Rs

=

ωT
2 ωT
2 4RL Rs = 2ω0 Rs ω0

(2)

As a result, |S21 | in the ideal case depends only on ωT of the transistor. Given the requirement of this project (|S21 | > 10dB), the minimum required ωT can be calculated as: |S21 | > 10dB =⇒ ωT > 100.5 ω0 =⇒ fT,min ' 7GHz

(3)

It should be noted that the derivations in this part assumed ideal matching at both the input and the output at the frequency of interest; however, in reality perfect matching across the whole bandwidth will 6

not be achievable; therefore, in practice the required fT to meet the specifications would be larger than 7GHz. Since S11 is defined as the reflection coefficient at the input of the circuit: S11 =

Zin − Zs Zin + Zs

therefore, to satisfy S11 requirement the following equation should hold: Zin − Zs < √1 =⇒ 26Ω < Zin < 96Ω |S11 | < −10dB =⇒ Zin + Zs 10

(4)

(5)

hence, S11 is a function of the input impedance, which in an inductively degenerated LNA is given by: Zin |f0 = ωT Ls

(6)

It should be noted that once fT of the device is known all other component values can be readily calculated. First, from fT , gm /Id can be found, which in turn gives the transconductance of the device.2 From gm /Id , the current density of the device can also be found which then yields the total width of the transistor. Ls is also related to fT by Equation 6 and the relationship between Lg and other component values is: ω0 = p

1 (Lg + Ls )Cgg

(7)

where Cgg represents the total gate capacitance.3 From this equation Lg can be calculated and the design would be complete.4 As a final note, once again it should be emphasized that all derivations in this part assume ideal components and perfect matching at all frequencies, which is not a realistic assumption in the actual design. Nevertheless, these first-order results give an intuition on how major components affect the performance of the circuit and have been used as a starting point for the design procedure.

3.3

Optimal Noise Design Methodology

The derivation of the complete noise figure equation (taking into account the effect of all existing parasitics in the circuit) would be quite cumbersome, and the obtained results would not give an insight into how to choose design parameters such as the width and the biasing of the transistor. However, in a simplified approach (which neglects the noise contribution of the cascode device and assumes perfect matching conditions at the input) the noise factor of the circuit can be shown to be given by the following equation [2, 3]: F =1+ where

Rg γ ω0
2 + χgm Rs Rs α ωT

χ

=

1 + 2|c|QL

QL

=

1 Rs Cgg ω0

s

(8)

δα2 δα2 + (1 + Q2L ) 5γ 5γ

In Equation 8 the second term shows the noise due to the gate resistance, which can be minimized by careful layout techniques, e.g., by increasing the number of fingers in the design one can effectively reduce this resistance. Therefore, the only term which is of our concern and should be optimized is the third one. Note that once the optimal QL is determined, all other parameters such as gm and ωT will be readily calculated PDC is always assumed that the whole available current is to be used in this project; therefore, Id = Id,max = V DD gg can be replaced with Cgs ; however, to have a better estimate of the capacitance of the series RLC and considering the effect of Cgd , in all equations and simulations Cgg has been used. 4 L is also found by a similar procedure. d 2 It 3C

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4.5

Actual α Constant α

4 3.5

NF (dB)

3 2.5 2 1.5 1 0.5 0

2

4

6

8

10

QL

Figure 3: NF as a function of QL for VDD =2.5V.

as discussed in Section 3.2 In order to obtain some intuition on how to choose the optimal value of QL , two cases have been considered in this project. First, if QL is assumed to be small, the current density of the device would also be small (remember that both QL and current density are inversely proportional to W), which corresponds to a large gm /Id . As a result, the transistor will have a poor fT , which based on Equation 8 results in a large NF. On the other hand, if a large QL is assumed to increase current density and thus fT , again from Equation 8, it is apparent that even though fT increases with QL , at the same time χ may increase with a higher rate, which can degrade the overall noise factor. Consequently, an increase in noise factor is expected both at high and low values of QL . From another perspective, by choosing a small QL , the transconductance of the device will increase which can aggravate channel thermal noise, so at low values of QL , thermal noise in the channel dominates the overall noise factor. On the other hand, at large QL , the effect of gate induced noise is more pronounced because the gate-induced noise will be amplified by QL of the input series RLC circuit and appear at the output; therefore, the higher the QL , the larger the contribution to the noise at the output. Based on the preceding discussion, there exist an optimal QL for which a minimum is expected to be observed in the noise factor curves plotted as a function of QL . A MATLAB script has been used to calculate noise factor as a function of QL . The results of MATLAB code are shown in Figure 3 using EE314 technology and assuming a 2.5V power supply and a constant α (dashed line). This code performs the following steps: for each value of QL the corresponding Cgg is found. From HSpice simulation plots, it is straightforward to find the width of the transistor to obtain a particular Cgg . As mentioned before, since the whole current budget is assumed to be used, the current density could be calculated based on Imax and W. Once the current density is calculated, fT can be found from the characterization plots. Finally, λ, δ, and α were assumed to be 0.8, 1.6, and 0.5, respectively.5 As can be seen in Figure 3 (dashed line), an optimal QL exists which leads to minimum noise factor; however, the resulting plot shows a relatively flat response across a wide range of QL , which implies that in general increasing the width does not degrade noise factor substantially. It should be noted that in our calculations up to this point, the variation of α with QL has been neglected. However, α is a strong function of the width of the transistor (assuming constant Id ) and cannot be simply assumed a constant. In order to achieve a more realistic estimate of α, gd0 and gm were plotted as a function of QL as shown in Figure 4. 5 c was assumed to be 0 (even though it is not true) because the correlation between channel thermal noise and gate induced noise is ignored in the provided model files.

8

10 g d0 g

9

m

Transconductance (mS)

8 7 6 5 4 3 2 1 0 −0.5

0

0.5

1

V

ov

1.5

2

2.5

(V)

Figure 4: gm and gd0 as a function of the gate overdrive voltages.

As can be seen, α is a strong function of QL and increases significantly as the width of the device decreases. The new noise factor plot is depicted in Figure 3 (solid line). As observed, with taking the variations of α into account, the noise factor increases for higher values of QL as compared to our previous assumption of constant α. As a final note, it was mentioned that by choosing the optimal QL , the transit frequency of the device will be determined; therefore, the value fT is primarily enforced by the noise factor; whereas, in previous sections it was calculated based on S21 requirement. This is not however, an important issue in our design because it has been observed that the optimal QL occurs at such high current densities that fT requirements will be satisfied automatically. Obviously, in case that S21 requirement imposed a limitation on a design, achieving minimum noise factor should be traded for gain.

3.4

Biasing

The design flow for the signal path requires certain current levels in the devices. In this project, a current mirror with a reference current was chosen as bias circuitry [3]. Since PMOS devices are not available in this project, a purely NMOS current mirror had to be used for biasing the circuit. The chosen biasing topology establishes a reference current determined by the value of Rref , while Rbias is chosen to be big enough so that the loading effect of the bias circuit on the signal path is negligible. In this case, a simple design has been chosen; however, if the temperature stability is critical for the design, a constant-gm supply can be used.

4

Designed circuit

The final design presented in this project was obtained after a handful of iterations, three of which are briefly discussed in the following sections. The performance of each design is analyzed as well as the techniques used to enhance the performance in particular noise figure optimization techniques.

4.1

Initial Design

The first LNA was designed using a 2.5V supply voltage. As discussed before, the required S21 mandates an fT somewhat larger than 7GHz, which leads to a transistor width around 200µm. For the required transit frequency, the value of Ls to obtain an input resistance of 50Ω is 1.4nH, which is hard to obtain with the

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parasitic inductances present in the bondwires and the pins.6 In this case, the solution taken was to use four bondwires in parallel; however, in order to avoid the mutual coupling effects between the bondwires, they were implemented as orthogonal connections by putting each of them at one side of the chip. This arrangement results an equivalent inductance value of 1.38nH, which is close to the required one. The value of Lg required to establish the resonance of the input RLC tank at the center frequency is around 11nH, which can be easily attained using the parasitic inductances of the pin and an 8mm long bondwire. The drain-bulk capacitance of the cascode transistor is relatively small, so a very large inductance Ld is required at the output to resonate at the operating frequency. This value is approximately 30nH, so it was decided to design an spiral inductor to satisfy it. It should be noted that, while a 30nH spiral inductor may seem to be impractical, the effect of parasitic capacitance of the spiral inductor (which significantly changes the total capacitance at the output) should be taken into account. A MATLAB script was written to optimize this design obtaining the required inductance value accounting for the capacitance value added by the inductor itself, while minimizing the series resistance. The required inductance value goes down to approximately 10nH when the added capacitance is taken into account, and using 6 turns, with a davg =190µm, and ρ = 0.6 provides the minimum series resistance. This design met S-parameter specifications with a little modifications. However, the noise figure values were totally unacceptable. The minimum and maximum values of noise figure were 1.9dB and 2.8dB, respectively. These high noise figures can be attributed to the combination of two factors. First, the non-optimal width selection for the transistor, as the decision was purely based on the required gain and not on the noise figure. Second the noise introduced by the resistance of the spiral inductor in the RLC output tank significantly degrades the noise figure.

4.2

Noise Optimized 2.5V LNA

The next step was to design an optimized 2.5V supply LNA following the previously presented design methodology. Firstly, as explained, a sweep in QL was performed, calculating the noise figure for each value. As shown in Figure 5 it was observed that the optimum QL is 3.4, which corresponds to a theoretical noise figure of 1dB. This QL corresponds to a width of approximately 180µm, and an fT of 11GHz. This transit frequency provides a theoretical gain of approximately 15dB, so it should not be limiting our S21 . In fact, the main problem with this design is precisely the opposite. The large value of fT imposes an Ls value of 0.71nH, which is hard to obtain due to the high values of the parasitic inductances of bondwires. The same solution with 4 bondwires in orthogonal directions that was used in the previous design was repeated here. The correspondent value is 1.38nH, which is much higher than the required one, but it is good enough to meet the S11 specifications; however, since the source degeneration impedance is higher than what was assumed before, lower S21 is to be expected in this part. The Lg value required to establish the resonance of the input RLC tank at the operating frequency is around 14nH, while the maximum value of achievable inductance with bondwires is 13nH, this implies that the resonance frequency will not be exactly at 2GHz, but a little higher. The main objective of this design was to minimize the noise figure. For this reason it was decided to implement Ld inductor using the parasitic inductances of the bondwire and the pin. The maximum value of the inductance that can be obtained with this procedure is not enough to fix the resonance frequency of the output RLC tank at the operating frequency. However, the output RLC tank has a very low quality factor due to the fact the load resistance is very low (50Ω); therefore, the tank will have a very wide bandwidth, and it will be possible to obtain the required S21 without much difficulty. After a few modifications in SPICE, this design met all the specifications, and the noise figures were much reduced compared to the previous design. The minimum noise figure was 0.92dB while the maximum value was 1.38dB.

4.3

Noise Optimized 1.5V LNA

The power specification establishes a maximum current for a given voltage supply. Reducing the voltage supply allows for increasing the maximum current, therefore, for each QL (which corresponds to a single 6 Note

that the minimum length of the bondwire is 1mm, which along with the 3nH inductance of the package pin leads to a minimum inductance of 4nH for a single pin and bondwire.

10

3.5

Actual α Constant α

NF (dB)

3

2.5

2

1.5

1 0

2

4

6

8

10

QL

Figure 5: Noise figure as a function of QL for VDD = 2.5V .

width) a higher current density will be obtained. A higher current density implies a lower gm /Id , which provides a higher fT , and therefore a lower noise figure. Figure 6 shows the theoretical noise figures versus QL when a 1.5V supply is used. The minimum noise figure is obtained for QL,opt = 3.5, and the theoretical noise figure is 0.8 dB. The QL,opt corresponds to a width of 177µm, which, as expected, is very similar to the one obtained in the previous design. Thanks to the extra available current the transient frequency is 14.1 GHz, that is almost 30% higher, and consequently, the noise figure is lower. However, for the same reason the required Ls becomes smaller too. In this case the required Ls goes down to 0.56nH, which is far away from any value that can be achieved with the parasitics present in the circuit. To minimize the value of the source inductance, 8 pins were used in parallel. However, the obtained value is still around 1nH, which is twice as much as the required value. For this reason, the transistor was made a bit wider (W = 180µm) so as to meet S11 specification. The noise figure in the circuit varies from 0.85dB to 1.24dB, which is in close agreement with the theoretical prediction. Note that by reducing the supply voltage the noise figure of the amplifier reduces by 0.15dB with no degradation in other specifications. The limit to the voltage decrease is in the linearity specifications. If the supply voltage is further reduced, at a certain point the input transistor will enter in the linear region due to its increased overdrive voltage, severely degrading the linearity of the amplifier.

4.4

Final Design

In previous designs, the value of QL determined the width of the amplifier through the value of the Cgs capacitor. Since the width of the device also determined the gm /Id and thus gm and gd0 , it is evident that α = gm /gd0 was also determined once the width is chosen. As a result, the values of α and the Cgs could not be set independently; however, if a capacitor CMMCAP is added between the gate and the source of the transistor, an additional degree of freedom is gained that allows for changing the value of the total Cgs capacitance, which fixes QL and also the equivalent fT of the transistor, while the current density of the device can be changed independently determining gm /Id and hence α. Making those parameters independent from each other enables an additional noise optimization step. From the theoretical noise figure calculation, it is apparent that the noise figure depends on terms that contain either α or α1 , therefore there exists an optimum value of α that minimizes the noise. On the other hand the noise figure also depends on gm ; therefore, now gm can be decreased without degrading the input

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3.5

Actual α Constant α

3

NF (dB)

2.5

2

1.5

1

0.5 0

2

4

6

8

10

QL

Figure 6: Noise figure as a function of QL for VDD = 1.5V .

power match.7 By using this capacitor it is possible to reduce the width of the transistor changing gd0 and approaching to the optimum value of α, and at the same time, preserve the power match to meet S11 specification because the equivalent fT does not change. Using this finding in this technique, a new optimum configuration for the LNA has been found, obtaining sub 1dB noise figures values at the resonance frequency. The idea of adding a capacitor in parallel with gate-source capacitance of the device to improve the noise figure is further discussed in [4]. Simulation results of the final design are presented in Figures 7-9. As can be seen, the final design achieves a noise figure of less than 1.1dB across the frequency band of interest, while meeting all other specifications. The simulated IIP3 of the circuit is 12.75dBm. 14

12

f=1.8GHz

f=2.2GHz

S21=11.4dB

S21=11.6dB

S21 (dB)

10

8

6

4

2

0 1.4

1.6

1.8

2

2.2

2.4

Frequency (GHz)

Figure 7: S21 of the final design. 7 Note

that in this case there is a tradeoff between the gain and the noise.

12

2.6

2.8

0

S11 (dB)

−5

−10

S11=−22.6dB

−15 f=1.8GHz

f=2.2GHz

S11=−10.0dB −20

−25 1.4

1.6

1.8

2

2.2

2.4

2.6

2.8

Frequency (GHz)

Figure 8: S11 of the final design.

1.8 1.7 1.6

NF (dB)

1.5 1.4 1.3 1.2 1.1 1

f=1.8GHz NF=0.81dB

NF=1.10dB f=2.2GHz

0.9 0.8 1.5

2

Frequency (GHz)

Figure 9: Noise figure of the final design.

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2.5

5

Conclusion

An LNA achieving a noise figure less than 1.1dB across the frequency band of 1.8–2.2GHz was designed using a design methodology which finds the optimal dimensions of the transistor to minimize noise figure. An optimization procedure was introduced, which gives a relatively accurate estimate of the noise figure based on technology characterization plots. Even though, the theoretical calculations of the noise figure come from a much simplified noise model, they constitute a good starting point for the dimension selection. The created MATLAB script calculates the noise figure for different values of QL , making it possible to estimate the optimum dimensions of the transistor. An additional noise figure enhancement technique was applied to the design by adding a capacitor to mitigate the effect of gate-induced noise. Using this method allows the designer to choose different values of α without degrading the input power match, making it possible to find a new minimum value for the noise figure. The tradeoffs involved in using this technique were also discussed. The final design was achieved after four iterations, performance of which are summarized in Table 2 Design # 1 LNA with 2.5V supply 2 Noise optimized LNA with 2.5V supply 3 Noise optimized LNA with 1.5V supply 4 Final design

NF ≤ 2.83dB ≤ 1.38dB ≤ 1.25dB ≤ 1.10dB

Table 2: Comparison of the NF in different iterations of the design.

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References [1] D. K. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE J. Solid-State Circuits, vol. 32, pp. 745–759, May 1997. [2] H. Rategh, Radio-frequency integrated circuit design (EE314) lecture notes. Stanford University, Winter 2006. [3] T. H. Lee, The Design of CMOS Radio Frequency Integrated Circuits, 2nd ed. Press, 2004.

Cambridge University

[4] P. Andreani and H. Sjoland, “ Noise optimization of an inductively degenerated CMOS low noise amplifier,” IEEE Trans. Circuits Syst. II, vol. 48, pp. 835–841, Sept. 2001.

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A % % % % % %

MATLAB Optimization Code

EE314, Winter 2006 Midterm Project Design of a CMOS LNA. Authors: Mohammad Hekmat and Pablo Moreno Galbis Created on Feb. 26, 2006. Last modified: Mar. 10, 2006.

% This file plots the noise figure as a function of Q_L to find the % optimum Q_L (or equivalently width) of the device from noise performance % perspective. clear all; read_data3;

% Reading technology characterization plots

% Defining parameters R_s = 50; w_0 = 2*pi*2e9; V_dd = 1.5; P_max = 13e-3; I_max = 0.9*(P_max/V_dd);

% % % % % %

Source impedance = 50ohms Center frequency = 2GHz V_dd P_max= 13mW Assuming that 90% of current is to be used in the main transistor

c =0; gamma = 0.8; delta = 2 * gamma; Q_L

= 0.5:0.1:10;

%Finding reequired Cgg C_gg = 1./(Q_L .* R_s .* w_0); %Finding required width W = interp1(cgg3, W3, C_gg); % Assuming that we are willing to spend as much current as possible, i.e. % I_max, we have: IdW=I_max./W

% This is the largest allowed current density which gives % us the smallest possible gm_Id hence the largest f_T

% Finding gm_Id gm_Id = interp1(idw1(:,1), gmid1(:,1), IdW); % Finding f_T f_T = interp1(gmid1(300:1600,1),ft1(300:1600,1), gm_Id); w_T = 2 * pi * f_T; % Finding g_m and g_d0 gm = gm_Id * I_max; vgs = interp1(gmid1(300:1600,1),vgs1(300:1600,1), gm_Id); g_d0= interp2(W2M,vgs2,gd02,W,vgs); alpha=gm./g_d0;

16

% Noise figure equations X = 1 + 2.*abs(c).*Q_L.*sqrt(delta .* alpha.^2./(5.*gamma)), ... + (delta .* alpha.^2/(5.*gamma)) .* (1+Q_L.^2); F = 1 + (gamma./alpha).* X .* gm .* R_s .* (w_0./w_T).^2; % Plotting the results figure(1) set(gca, ’fontsize’,14) plot(Q_L, 10*log10(F), ’-b’,’linewidth’,3); xlabel(’Q_L’, ’fontsize’, 18) ylabel(’NF (dB) ’, ’fontsize’, 18) % Extracting optimal design parameters [fmin, n]=min(10*log10(F)); C_gg_opt = 1./(Q_L(n) .* R_s .* w_0); W_opt = interp1(cgg3, W3, C_gg_opt); IdW_opt = I_max./W_opt; gm_Id_opt = interp1(idw1(:,1), gmid1(:,1), IdW_opt); f_T_opt = interp1(gmid1(300:1600,1),ft1(300:1600,1), gm_Id_opt); gm_opt = gm_Id_opt * I_max;

17

EE314 Technology Characterization Plots

30

25

gm/id (1/V)

20

15

10

5

0 −0.5

0

0.5

1

1.5

2

2.5

20

25

30

Vov (V)

20 18 16 14 12 10

T

f (GHz)

B

8 6 4 2 0 0

5

10

15

g /i (1/V) m d

18

3

10

2

10

1

id/w (µA/µm)

10

0

10

−1

10

−2

10

−3

10

−4

10

−5

10

0

5

10

15

20

25

30

20

25

30

g /i (1/V) m d

32 30 28 26

g r

m o

24 22 20 18 16 14 12 0

5

10

15

g /i (1/V) m d

19

3 Cgg Cgs

Capacitance (pF)

2.5

2

1.5

1

0.5

0 0

200

400

600

800

1000

W (µm)

10 9

g d0 g m

Transconductance (mS)

8 7 6 5 4 3 2 1 0 −0.5

0

0.5

1

Vov (V)

20

1.5

2

2.5