Lecture4 - VHDL - Simple Testbenches

Lecture 4

Simple Testbenches

Testbench Defined • Testbench = VHDL entity that applies stimuli (drives the inputs) t the Desi!n "nder Test (D"T) and (ptinally) verifies e#pected utputs$ • The results can be vie%ed in a %avefrm %ind% r %ritten t a file$ • Since Testbench is %ritten in VHDL& it is nt restricted t a sin!le simulatin tl (prtability)$ • The same Testbench can be easily adapted t test different implementatins (i$e$ different architectures) f the same desi!n$

Testbench Defined • Testbench = VHDL entity that applies stimuli (drives the inputs) t the Desi!n "nder Test (D"T) and (ptinally) verifies e#pected utputs$ • The results can be vie%ed in a %avefrm %ind% r %ritten t a file$ • Since Testbench is %ritten in VHDL& it is nt restricted t a sin!le simulatin tl (prtability)$ • The same Testbench can be easily adapted t test different implementatins (i$e$ different architectures) f the same desi!n$

Testbench

Processes Generating 

Design Under Test (DUT)

Stimuli 

Observed Outputs

ssible surces f e#pected results used fr cmparisn Testbench VHDL Design

actual results % &

Representative Inputs

Manual Calculations or 

Reference Software Implementation (C !ava Matlab "

e#pecte$ results

Testbench The same testbench can be used t test multiple implementatins f the same circuit (multiple architectures) testbench

desi!n entity

 *rchitecture +  *rchitecture 2

$$$$

 *rchitecture ,

Testbench *natmy ENTITY my_entity_tb IS

--TB entity has no ports END my_entity_tb;

 ARCHITECTURE behavioral OF tb IS

--Local signals and constants COMPONENT TestComp PORT (

--All Design Under Test component declarations );

END COMPONENT;

----------------------------------------------------BEGIN

DUTTestComp

PORT MAP(

-- !nstantiations o" DUTs

); test#e$%ence

PROCESS

-- !np%t stim%li END PROCESS;

END behavioral;

Testbench fr /01' (+) LIBRARY ieee USE ieee.std_logic_116.!ll E"#I#Y #r'3tb IS E"$ #r'3tb AR%&I#E%#URE behaviral O' #r'3tb IS  5mpnent declaratin f the tested unit %O()O"E"# *or+ )OR#(  * 6 I" STD3L0785 9 6 I" STD3L0785 5 6 I" STD3L0785 1esult 6 OU# STD3L0785 ) E"$ %O()O"E"#  Stimulus si!nals  si!nals mapped t the input and i nut prts f tested entity SI,"AL test3vectr6 STD3L07853V:5T01(2 $O-"#O ;) SI,"AL test3result 6 STD3L0785

Testbench fr /01' (2) BE,I" ""T 6 #r' )OR# (A) (  * = test3vectr(2)& 9 = test3vectr(+)& 5 = test3vectr(;)& 1esult = test3result) )  Testin!6 )RO%ESS BE,I" test3vectr >= ?;;;? -AI# 'OR +; ns test3vectr >= ?;;+? -AI# 'OR +; ns test3vectr >= ?;+;? -AI# 'OR +; ns test3vectr >= ?;++? -AI# 'OR +; ns test3vectr >= ?+;;? -AI# 'OR +; ns test3vectr >= ?+;+? -AI# 'OR +; ns test3vectr >= ?++;? -AI# 'OR +; ns test3vectr >= ?+++? -AI# 'OR +; ns E"$ )RO%ESS E"$ behaviral

VHDL Desi!n Styles &$L $esign St/les

d!t!0lo Concurrent statements

structur!l Components and  interconnects

beh!vior!l Sequential statements

• #estbenches

Ghat is a 105:SSI •  * prcess is a seAuence f instructins referred t as seAuential statements$ The Bey%rd 105:SS

•  * prcess can be !iven a uniAue name usin! an ptinal L*9:L • This is fll%ed by the Bey%rd 105:SS • The Bey%rd 9:78, is used t indicate the start f the prcess •  *ll statements %ithin the prcess are e#ecuted S:C":,T8*LL$ Hence& rder f statements is imprtant$ •  * prcess must end %ith the Bey%rds :,D 105:SS$

Testin!6 105:SS 9:78, test3vectr>=E;;F G*8T 01 +; ns test3vectr>=E;+F G*8T 01 +; ns test3vectr>=E+;F G*8T 01 +; ns test3vectr>=E++F G*8T 01 +; ns :,D 105:SS

:#ecutin f statements in a 105:SS

•

The e#ecutin f statements cntinues seAuentially till the last statement in the prcess$ •  *fter e#ecutin f the last statement& the cntrl is a!ain passed t the be!innin! f the prcess$

Testin!6 105:SS 9:78, test3vectr>=E;;F G*8T 01 +; ns test3vectr>=E;+F G*8T 01 +; ns test3vectr>=E+;F G*8T 01 +; ns test3vectr>=E++F G*8T 01 +; ns :,D 105:SS   n       i    t   u   c   e   #   e    f      r   e    d   r    0

r!ram cntrl is passed t the first statement after 9:78,

105:SS %ith a G*8T Statement •

•

•

The last statement in the 105:SS is a G*8T instead f G*8T 01 +; ns$ This %ill cause the 105:SS t suspend indefinitely %hen the G*8T statement is e#ecuted$ This frm f G*8T can be used in a prcess included in a testbench %hen all pssible cmbinatins f inputs have been tested r a nnperidical si!nal has t be !enerated$

r!ram e#ecutin stps here

Testin!6 105:SS 9:78, test3vectr>=E;;F G*8T 01 +; ns test3vectr>=E;+F G*8T 01 +; ns test3vectr>=E+;F G*8T 01 +; ns test3vectr>=E++F -AI#2 :,D 105:SS   n       i    t   u   c   e   #   e    f      r   e    d   r    0

G*8T 01 vs$ G*8T G*8T 016 %avefrm %ill Beep repeatin! itself frever  '



)

*

'



)

*

+

G*8T 6 %avefrm %ill Beep its state after the last %ait instructin$

+

Speci0/ing ti3e in &$L

Time values (physical literals)  :#amples . ns + min min +;$- us +;$- fs

,umeric value

Space

"nit f time (dimensin)

"nits f time Unit

$e0inition

B!se Unit fs

femtsecnds (+;4+) secnds)

$erived Units ps

picsecnds (+;4+2 secnds)

ns

n!noseconds 41567 seconds8

us

micrsecnds (+;4- secnds)

ms

milisecnds (+;4' secnds)

sec

secnds

min

minutes (-; secnds)

hr

hurs ('-;; secnds)

Si3ple #estbenches

7eneratin! selected values f ne input S87,*L test3vectr 6 STD3L07853V:5T01(2 d%nt ;) 9:78,   $$$$$$$ testin!6 105:SS 9:78, test_vector 9: ;555;2 -AI# 'OR 15 ns2 test_vector 9: ;551;2 -AI# 'OR 15 ns2 test_vector 9: ;515;2 -AI# 'OR 15 ns2 test_vector 9: ;511;2 -AI# 'OR 15 ns2 test_vector 9: ;155;2 -AI# 'OR 15 ns2 :,D 105:SS

 $$$$$$$$ :,D behaviral

7eneratin! all values f ne input S87,*L test3vectr 6 STD3L07853V:5T01(' d%nt ;)1_periodD2 cl>1 9: 1C2 -AI# 'OR cl>1_periodD2 :,D 105:SS cl> 9: not cl> !0ter cl>_periodD2   $$$$$$$ :,D behaviral

7eneratin! netime si!nals& such as resets 50,ST*,T reset+3%idth 6 T8M: 6= +;; ns 50,ST*,T reset23%idth 6 T8M: 6= +; ns S87,*L reset+ 6 STD3L0785 S87,*L reset2 6 STD3L0785 = K+ G*8T 01 +;; ns reset >= K; test_vector 9:;555;2

 

G*8T :,D 105:SS !eneratr26 105:SS G*8T 01 2;; ns test_vector 9:;551;2 G*8T 01 -;; ns test_vector 9:;511;2 :,D 105:SS $$$$$$$

:,D behaviral

Asserts F Reports

 *ssert  *ssert is a nons/nthesiG!ble statement %hse purpse is t %rite ut messa!es n the screen %hen prblems are fund durin! simulatin$ Dependin! n the severit/ o0 the proble3& The simulatr is instructed t cntinue simulatin r halt$

 *ssert  synta#  *SS:1T cnditin N1:01T ?messa!e? NS:V:18T severity3level O #he 3ess!ge is ritten hen the condition is 'ALSE. Severity3level can be6 "ote? -!rning? Error 4de0!ult8? or '!ilure.

 *ssert  :#amples assert initial3value >= ma#3value reprt ?initial value t lar!e? severity errr assert pacBet3len!th P= ; reprt ?empty net%rB pacBet received? severity %arnin! assert false reprt ?8nitialiQatin cmplete? severity nte

1eprt  synta# 1:01T ?messa!e? NS:V:18T severity3level O #he 3ess!ge is !l!/s ritten. Severity3level can be6 "ote 4de0!ult8? -!rning? Error? or '!ilure.

1eprt  :#amples

reprt ?8nitialiQatin cmplete? reprt ?5urrent time = ? R timeima!e(n%) reprt ?8ncrrect branch? severity errr